Two-dimensional semiconductor field effect transistor based on high-k gate dielectric and manufacturing method thereof

Abstract

The invention discloses a manufacturing method of a two-dimensional semiconductor field effect transistor based on a high-k gate dielectric integration technology capable of eliminating a buffer layer. The manufacturing method comprises the following steps: depositing a back gate electrode and a back gate dielectric on a substrate in sequence; transferring the channel layer to the back gate medium; sequentially forming a buffer layer, a source electrode, a drain electrode, a top gate dielectric layer formed by a high-k dielectric material and a top gate electrode on the channel layer; and annealing treatment is carried out in a vacuum environment, and the buffer layer sublimates, so that Van der Waals interfaces are formed between the channel layer and the top gate dielectric layer and between the channel layer and the source electrode as well as between the channel layer and the drain electrode. According to the high-k gate dielectric integration technology based on the erasable buffer layer, the erasable buffer layer after vacuum annealing is utilized, damage to a two-dimensional material is avoided, a high-quality high-k gate dielectric is deposited, interface regulation and control between a channel layer and a top gate dielectric are achieved, and the equivalent oxide thickness is reduced; and good contact between the channel layer and source and drain metal is realized, the contact resistance of the transistor is reduced, and the electrical performance of the transistor is improved.

Description

Technical Field

[0001] At least one embodiment of the present invention relates to a semiconductor device, and more particularly to a two-dimensional semiconductor field effect transistor based on a high-k gate dielectric layer integration technology capable of eliminating a buffer layer, and a method for manufacturing the same. Background Art

[0002] Silicon-based technology has always been the cornerstone of complementary metal oxide semiconductor (CMOS) field effect transistor (FET) devices and the main driving force for the rapid growth of information technology. According to the predictions of Moore's Law, modern electronics continues to achieve higher speeds and greater capacity through device miniaturization, which enhances computing performance and reduces costs. However, in recent years, the further reduction of silicon-based CMOS FET size has been limited by quantum effects, especially short channel effects and inevitable heat dissipation problems, and the advancement of process nodes faces huge challenges.

[0003] In this context, researchers are eager to explore new channel materials and new device architectures that go beyond the limitations of traditional silicon-based technology to achieve low-power, high-performance logic devices. Therefore, two-dimensional (2D) materials composed of a single layer or a few layers of atoms or molecules, such as graphene, boron nitride, and transition metal dihalide compounds (TMDCs), have opened up new possibilities due to their atomic-level thickness, no dangling bonds on the surface, and extraordinary optical and electrical properties, and have attracted widespread attention from researchers.

[0004] TMDCs such as MoS2, MoSe2, WSe2 or WS2 have high mobility close to that of semiconductor silicon, and most of their energy gaps are above 1eV. They are natural semiconductors, so using these materials to develop high-performance field-effect transistors is a very important direction. Transistors based on two-dimensional materials also show the potential to surpass silicon in terms of miniaturization. However, to ensure the excellent device performance of two-dimensional field effect transistors (2D FETs), it is essential to prepare suitable high-k gate dielectrics. However, the deposition energy of high-k gate dielectrics is high, and it is inevitable that the two-dimensional material layer will be damaged during the deposition process. Summary of the invention

[0005] In view of this, the present invention provides a two-dimensional semiconductor field effect transistor and a manufacturing method thereof based on a high-k gate dielectric layer integration technology that can eliminate a buffer layer, so as to prepare a high-k gate dielectric layer on the channel layer while avoiding damage to the two-dimensional material of the channel layer.

[0006] As one aspect of the present invention, the present invention provides a method for manufacturing a two-dimensional semiconductor field effect transistor based on a high-k gate dielectric layer integration technology that can eliminate a buffer layer, comprising: depositing a back gate electrode and a back gate dielectric layer on a substrate in sequence; transferring a channel layer onto the back gate dielectric layer; forming a buffer layer, a source, a drain, a top gate dielectric layer formed of a high-k dielectric material, and a top gate electrode in sequence on the channel layer; and performing annealing in a vacuum environment after forming the top gate electrode so that the buffer layer sublimates under heating conditions, so that the channel layer and the top gate dielectric layer form a van der Waals interface, and so that the channel layer forms a van der Waals interface with the source and the drain.

[0007] As another aspect of the present invention, the present invention provides a two-dimensional semiconductor field effect transistor obtained by the above-mentioned manufacturing method.

[0008] According to the method for manufacturing a two-dimensional semiconductor field effect transistor based on the high-k gate dielectric layer integration technology that can eliminate the buffer layer provided by the above-mentioned embodiment of the present invention, a buffer layer that can be removed by annealing is deposited on the channel layer, so that a high-k gate dielectric layer can be deposited on the two-dimensional material layer without damaging the two-dimensional material. This can avoid the problem of poor film formation quality of the top gate dielectric layer due to stress and strain generated between the two-dimensional material layer and the top gate dielectric layer, thereby improving the gate control capability of the two-dimensional semiconductor field effect transistor, and can also avoid damage to the two-dimensional material lattice caused by the top gate dielectric layer, thereby improving the electrical performance of the two-dimensional semiconductor field effect transistor, such as improving the mobility of the device, reducing the subthreshold swing and avoiding hysteresis.

[0009] According to the method for manufacturing a two-dimensional semiconductor field effect transistor based on a high-k gate dielectric layer integration technology that can eliminate a buffer layer provided in the above-mentioned embodiment of the present invention, a buffer layer that can be removed by annealing is deposited on the channel layer, which can enable the two-dimensional material to have good contact with the source metal and the drain metal, thereby reducing the contact resistance of the two-dimensional semiconductor field effect transistor, increasing the on-state current, and further improving the electrical performance of the device.

[0010] According to the method for manufacturing a two-dimensional semiconductor field effect transistor based on the high-k gate dielectric layer integration technology that can eliminate the buffer layer provided by the above-mentioned embodiment of the present invention, a high-k gate dielectric layer is deposited on the two-dimensional material layer, so that a good van der Waals interface contact is formed between the channel layer and the top gate dielectric layer, and between the channel layer and the source / drain. The equivalent oxide thickness of the top gate dielectric layer can be miniaturized, the gate control capability of the transistor can be improved, the leakage current can be reduced, and the switching ratio and mobility of the device can be improved, thereby realizing a high-performance and high-breakdown field device.

[0011] According to the method for manufacturing a two-dimensional semiconductor field effect transistor based on a high-k gate dielectric layer integration technology that can eliminate a buffer layer provided in the above-mentioned embodiment of the present invention, since the buffer layer can be removed after annealing, there is no need for material matching and compatibility between the buffer layer and the top gate dielectric layer, making the manufacturing method highly scalable. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 A flowchart of a method for manufacturing a two-dimensional semiconductor field effect transistor based on a high-k gate dielectric capable of eliminating a buffer layer according to an embodiment of the present invention;

[0013] Figure 2A A schematic diagram of a two-dimensional semiconductor field effect transistor based on a high-k gate dielectric capable of eliminating a buffer layer before annealing according to an embodiment of the present invention;

[0014] Figure 2B A schematic diagram of a two-dimensional semiconductor field effect transistor based on a high-k gate dielectric capable of eliminating a buffer layer after annealing according to an embodiment of the present invention; and

[0015] Figure 3 4 is a process flow chart of a dual-gate two-dimensional semiconductor field effect transistor according to an embodiment of the present invention.

[0016] [Description of Reference Numerals]

[0017] 1- substrate;

[0018] 11-silicon layer;

[0019] 12-silicon dioxide layer;

[0020] 2- back gate electrode;

[0021] 3-back gate dielectric layer;

[0022] 4-channel layer;

[0023] 5- buffer layer;

[0024] 6- Source;

[0025] 7-drain;

[0026] 8-top gate dielectric layer;

[0027] 9- top gate electrode;

[0028] 1'-Si / SiO2 substrate;

[0029] 2'-TiN back gate electrode layer;

[0030] 3'-HfO2 back gate dielectric layer;

[0031] 4'-WSe2 two-dimensional material layer;

[0032] 5'-first photoresist layer;

[0033] 6'-WSe2 channel layer;

[0034] 7'-Se buffer layer;

[0035] 8'-second photoresist layer;

[0036] 9'-Ni, Pd first metal layer;

[0037] 10'-Ni, Pd source;

[0038] 11'-Ni, Pd drain;

[0039] 12'-high-k gate dielectric HfO2 top gate dielectric layer;

[0040] 13'-third photoresist layer;

[0041] 14'-TiN second metal layer;

[0042] 15'-TiN top gate electrode. DETAILED DESCRIPTION

[0043] In order to make the purpose, technical scheme and advantages of the present invention more clear, the present invention is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings. However, the present invention can be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, providing these embodiments will make the invention thorough and complete and fully convey the scope of the present invention to those skilled in the art. In the accompanying drawings, for clarity, the sizes and relative sizes of layers and regions may be exaggerated, and the same reference numerals throughout represent the same elements.

[0044] The terms used herein are only for describing specific embodiments and are not intended to limit the present invention. The terms "comprise", "include", etc. used herein indicate the existence of the features, steps, operations and / or components, but do not exclude the existence or addition of one or more other features, steps, operations or components.

[0045] It should be noted that high-k dielectric materials refer to dielectric materials with a dielectric constant greater than that of SiO2 (3.9 to 4.2). The importance of high-k gate dielectrics to 2D FETs is reflected in the following points: (1) high dielectric constant and stronger charge binding ability, which can reduce the leakage current of field effect transistor devices; (2) good thermal stability, which is beneficial to improving device performance and extending device life; (3) having a large band gap and high barrier height, which can reduce the tunneling current of the device; (4) low defect state density and low fixed charge density, which effectively reduce interface scattering during carrier transport and improve carrier mobility. It should be noted that fixed charge refers to the charge that permanently exists at the interface or volume in a semiconductor device.

[0046] The inert basal plane of two-dimensional semiconductors has no chemical pendant bonds and cannot provide enough nucleation sites for the deposition of high-k dielectrics, which inhibits the nucleation and growth ability of high-k dielectrics prepared using standard atomic layer deposition (ALD) processes. If the dielectric is directly deposited on the surface of 2D channel materials by atomic layer deposition and other methods, the dielectric film quality is poor, mostly in the shape of islands or needles. At the same time, the high-k dielectric will seriously damage the 2D channel material, and there will be a large number of impurities and defects at the formed interface, which will seriously affect the carrier mobility, subthreshold swing and other performance of the device, and cause obvious hysteresis effects. Therefore, it is necessary to find a method to deposit high-k dielectrics on the surface of two-dimensional channel materials.

[0047] The scheme of integrating a large area of ​​high-k gate dielectric layer on a two-dimensional semiconductor channel can be mainly divided into four methods:

[0048] (1) Surface treatment method, for example, using ultraviolet ozone to treat the two-dimensional semiconductor MoS2 to form a sacrificial oxygen layer on the surface, thereby generating reaction sites on the inert substrate, and using ALD deposition to obtain a uniform, pinhole-free Al2O3 dielectric. The disadvantage of this method is that the surface of the two-dimensional material is first treated to form nucleation sites, but this treatment will produce a large number of defects on the surface of the nanoscale two-dimensional material, which will affect the performance of the logic device.

[0049] (2) Improved atomic layer deposition, which is largely related to surface treatment, as it involves steps such as precursor selection and modification or plasma precursors to drive the functionalization of the surface of the two-dimensional material to form nucleation sites and ultimately nucleation. For example, the precursor tetramethylaluminum (TMA) is first pulsed into the chamber, and then the Al2O3 dielectric is deposited using a water vapor-based ALD process or an O2 plasma-based PEALD process. The disadvantages of this method are the same as those of the surface treatment method.

[0050] (3) Thin film transfer method or conversion method. The thin film transfer method is a physical operation that requires manual mechanical transfer. Common dielectric films that are transferred include h-BN, MoO3, GaS, CaF2, etc. The conversion method is a chemical reaction. For example, the two-dimensional semiconductor Bi2O2Se is partially converted into a Bi2SeO5 dielectric film with an equivalent oxide thickness (EOT) of about 0.9nm through an oxidation reaction. The disadvantage of the thin film transfer method is that it requires manual operation and has high requirements for the experimental environment and experimental operation; the disadvantage of the conversion method is that the types of materials that can be used to generate dielectric films through chemical reactions are relatively small, and the scalability is poor.

[0051] (4) Buffer layer / seed layer growth method. For example, 3,4,9,10-perylene-tetracarboxylic dianhydride (PTCDA) is grown as a seed layer on a two-dimensional material using a thermal evaporation deposition method, and then a high-k dielectric layer HfO2 with good contact and no defects with PTCDA is deposited using atomic layer deposition technology (ALD). The disadvantages of this method are: the seed layer (usually with a low dielectric constant) will remain permanently in the dielectric structure, which will affect the dielectric capability and gate control capability of the device; it is necessary to find a suitable gate dielectric layer that is compatible with the seed layer, and the scalability is poor.

[0052] In view of this, the present invention provides a two-dimensional semiconductor field effect transistor and a manufacturing method thereof based on a high-k gate dielectric layer integration technology that can eliminate a buffer layer, so as to deposit a high-k gate dielectric layer on a two-dimensional material of a channel layer, so that the channel layer and the high-k gate dielectric layer form a good van der Waals interface contact, and can reduce the damage to the two-dimensional material layer caused by depositing the high-k gate dielectric layer on the two-dimensional material.

[0053] Figure 1 The present invention is a flow chart of a method for manufacturing a two-dimensional semiconductor field effect transistor based on a high-k gate dielectric capable of eliminating a buffer layer according to an embodiment of the present invention.

[0054] Figure 2A Schematic diagram of a two-dimensional semiconductor field effect transistor based on a high-k gate dielectric capable of eliminating a buffer layer before annealing according to an embodiment of the present invention.

[0055] Figure 2B Schematic diagram of a two-dimensional semiconductor field effect transistor based on a high-k gate dielectric capable of eliminating a buffer layer after annealing according to an embodiment of the present invention.

[0056] According to an exemplary embodiment of the present invention, the present invention provides a method for manufacturing a two-dimensional semiconductor field effect transistor based on a high-k gate dielectric capable of eliminating a buffer layer, referring to Figure 1 , Figure 2A and Figure 2B As shown, it includes: step S01 to step S04.

[0057] Step S01 : depositing a back gate electrode 2 and a back gate dielectric layer 3 on a substrate 1 in sequence.

[0058] According to an embodiment of the present invention, the substrate 1 includes a silicon layer 11 and a silicon dioxide layer 12 formed on the silicon layer 11 .

[0059] Step S02 , transferring the channel layer 4 onto the back gate dielectric layer 3 .

[0060] According to an embodiment of the present invention, the two-dimensional material layer is transferred to the surface of the back gate dielectric layer 3 , and the two-dimensional material layer is subjected to photolithography, development, and etching to form the channel layer 4 .

[0061] According to an embodiment of the present invention, the two-dimensional material forming the channel layer 4 includes one of MoS 2 , MoSe 2 , WSe 2 , WS 2 , graphene and black phosphorus.

[0062] Step S03 , forming a buffer layer 5 , a source electrode 6 , a drain electrode 7 , a top gate dielectric layer 8 formed of a high-k dielectric material, and a top gate electrode 9 in sequence on the channel layer 4 .

[0063] According to an embodiment of the present invention, forming a buffer layer 5, a source 6, a drain 7, a top gate dielectric layer 8 and a top gate electrode 9 in sequence on the channel layer 4 includes: depositing a buffer layer 5 on the channel layer 4; forming a source 6 and a drain 7 on the buffer layer 5, the source 6 and the drain 7 partially overlapping with the channel layer 4 in a direction perpendicular to the substrate 1; depositing a top gate dielectric layer 8 on the source 6, the drain 7 and the buffer layer 5, and forming a top gate electrode 9 on the top gate dielectric layer 8.

[0064] According to an embodiment of the present invention, the buffer layer 5 is a material with low deposition energy, and the buffer layer 5 can be removed by sublimation after being heated in a high vacuum environment. For example, the material of the buffer layer 5 is selenium.

[0065] It should be noted that the deposition energy of the buffer layer 5 is lower than the deposition energy of the top gate dielectric layer 8. Directly depositing the buffer layer 5 on the channel layer 4 avoids directly depositing a high-k gate dielectric layer on the channel layer 4, which can reduce damage to the two-dimensional material of the channel layer.

[0066] According to the embodiment of the present invention, a source electrode pattern and a drain electrode pattern are defined on the buffer layer 5, and after metal is deposited, a source electrode 6 and a drain electrode 7 are formed.

[0067] According to an embodiment of the present invention, after depositing the top gate dielectric layer 8 on the source 6, the drain 7 and the buffer layer 5, a photoresist is spin-coated on the top gate electrode layer 8, the photoresist is exposed and developed in a developer to form a photoresist pattern of the top gate electrode, a metal layer is deposited on the photoresist pattern, and then a top gate electrode 9 is formed by stripping the photoresist.

[0068] According to an embodiment of the present invention, the material of the top gate dielectric layer 8 is a high-k dielectric material; wherein the dielectric constant of the high-k dielectric material is higher than the dielectric constant of SiO 2 .

[0069] According to an embodiment of the present invention, the material of the top gate dielectric layer 8 is HfO 2 .

[0070] Step S04 , after forming the top gate electrode 9 , annealing treatment is performed in a vacuum environment to allow the buffer layer 5 to sublime under heating conditions, so that the channel layer 4 forms a van der Waals interface with the top gate dielectric layer 8 , and the channel layer 4 forms a van der Waals interface with the source 6 and the drain 7 .

[0071] According to an embodiment of the present invention, the annealing temperature of the annealing treatment is 150°C to 250°C, for example, the annealing temperature can be 150°C, 180°C, 200°C, 220°C, 250°C; the annealing time is 4h to 6h, for example, the annealing time can be 4h, 4.5h, 5h, 5.5h, 6h; the vacuum environment is 10 -7 torr~10 -9 torr, for example, in a vacuum environment it can be 10 -9 torr, 10 -8 torr, 10 - 7 torr.

[0072] According to an exemplary embodiment of the present invention, the present invention provides a two-dimensional semiconductor field effect transistor obtained by the above-mentioned manufacturing method, referring to Figure 2B As shown, it includes: a substrate 1, including a silicon layer 11 and a silicon dioxide layer 12; a back gate electrode 2, formed on the substrate 1; a back gate dielectric layer 3, formed on the back gate electrode 2; a channel layer 4, formed on the back gate dielectric layer 3; a source 6 and a drain 7, formed at both ends of the channel layer 4, and the source 6 and the drain 7 partially overlap with the channel layer 4 in a direction perpendicular to the substrate 1; a top gate dielectric layer 8 formed of a high-k dielectric material, formed on the source 6, the channel layer 4 and the drain 7; a top gate electrode 9, formed on a partial area of ​​the top gate dielectric layer 8; wherein the top gate dielectric layer 8 forms a van der Waals interface with the channel layer 4, and the source 6 and the drain 7 form a van der Waals interface with the channel layer 4.

[0073] According to the method for manufacturing a two-dimensional semiconductor field effect transistor based on a high-k gate dielectric with an eliminable buffer layer provided in the above-mentioned embodiment of the present invention, a buffer layer that can be removed by annealing is deposited on the channel layer, so that a high-quality high-k gate dielectric layer is deposited on the two-dimensional material layer without damaging the two-dimensional material. This can avoid the problem of poor film formation quality of the top gate dielectric layer due to stress and strain generated between the two-dimensional material layer and the top gate dielectric layer, thereby improving the gate control capability of the field effect transistor; it can also avoid damage to the two-dimensional material lattice by the top gate dielectric layer, thereby improving the electrical performance of the field effect transistor, such as improving the mobility of the device, reducing the subthreshold swing and avoiding hysteresis.

[0074] According to the method for manufacturing a two-dimensional semiconductor field effect transistor based on a high-k gate dielectric layer integration technology that can eliminate a buffer layer provided in the above-mentioned embodiment of the present invention, a buffer layer that can be removed by annealing is deposited on the channel layer, which can enable the two-dimensional material to have good contact with the source metal and the drain metal, thereby reducing the contact resistance of the field effect transistor, increasing the on-state current, and further improving the electrical performance of the device.

[0075] According to the method for manufacturing a two-dimensional semiconductor field effect transistor based on the high-k gate dielectric layer integration technology that can eliminate the buffer layer provided by the above-mentioned embodiment of the present invention, a high-k gate dielectric layer is deposited on the two-dimensional material layer, so that a good van der Waals interface contact is formed between the channel layer and the top gate dielectric layer, and between the channel layer and the source / drain. The equivalent oxide thickness of the top gate dielectric layer can be miniaturized, the gate control capability of the transistor can be improved, the leakage current can be reduced, and the switching ratio and mobility of the device can be improved, thereby realizing a high-performance and high-breakdown field device.

[0076] According to the method for manufacturing a two-dimensional semiconductor field effect transistor based on a high-k gate dielectric layer integration technology that can eliminate a buffer layer provided in the above-mentioned embodiment of the present invention, since the buffer layer can be removed after annealing, there is no need for material matching and compatibility between the buffer layer and the top gate dielectric layer, making the manufacturing method highly scalable.

[0077] According to the method for manufacturing a two-dimensional semiconductor field effect transistor based on a high-k gate dielectric layer integration technology that can eliminate a buffer layer provided by the above-mentioned embodiment of the present invention, the deposition process of the buffer layer matches the traditional metal deposition process, does not increase the difficulty of the manufacturing process, and can be applied to large-scale production.

[0078] According to the method for manufacturing a two-dimensional semiconductor field effect transistor based on a high-k gate dielectric layer integration technology that can eliminate a buffer layer provided in the above-mentioned embodiment of the present invention, after the buffer layer is removed, no residual impurities will affect the flatness of the interface and the dielectric properties of the top gate dielectric layer, thereby improving the life and stability of the device.

[0079] The structure of the designed dual-gate two-dimensional semiconductor field effect transistor and its manufacturing method are schematically described below. It should be noted that the example description is only a specific embodiment of the present invention and cannot limit the protection scope of the present invention.

[0080] Example 1

[0081] It should be noted that the double-gate two-dimensional semiconductor field effect transistor is fabricated by taking HfO2 as the gate dielectric and two-dimensional WSe2 as the channel material as an example. Figure 3 As shown in Figures (a) to (r) in the figure, the method for manufacturing a dual-gate two-dimensional semiconductor field effect transistor includes: steps S11 to S19.

[0082] In step S11, Si / SiO2 material is used as a substrate, and the Si / SiO2 substrate 1' is pretreated. The pretreatment process includes: ultrasonically cleaning the Si / SiO2 substrate 1' with acetone and isopropanol for 15 minutes, and drying it in an oven at 70° C. The Si wafer is heavily doped with p-type and has low resistance (<0.005Ω·cm), and SiO2 is a natural oxide layer with a thickness of about 300nm.

[0083] It should be noted that the Si wafer may also be heavily n-doped, and the thickness of the SiO2 layer may be 1-300 nm.

[0084] In step S12, TiN (back gate electrode layer) 2' and HfO2 film (back gate dielectric layer) 3' are sequentially deposited on the Si / SiO2 substrate 1'.

[0085] In step S13, the WSe2 two-dimensional material layer 4' grown on the sapphire substrate is transferred onto the HfO2 film (back gate dielectric layer) 3' by a wet transfer method.

[0086] In step S14, a first photoresist layer 5' is spin-coated on the WSe2 two-dimensional material layer 4', a channel pattern is defined by photolithography exposure and development, and the channel material WSe2 not protected by the photoresist is removed by dry etching, and then a de-resist treatment is performed to obtain a WSe2 channel layer 6'.

[0087] In step S15, a Se buffer layer 7' is grown on the surface of the WSe2 channel layer 6' by thermal evaporation deposition, wherein the Se buffer layer 7' protects the surface 6' of the two-dimensional material WSe2.

[0088] In step S16, a second photoresist layer 8' is formed on the Se buffer layer 7' to define source electrode patterns and drain electrode patterns, and Ni and Pd (first metal layer) 9' are deposited and stripped to form source 10' and drain 11'.

[0089] In step S17, a top gate dielectric layer (high-k gate dielectric HfO2) 12' is deposited on the Se buffer layer 7', the source 10', and the drain 11' by electron beam evaporation, wherein high-energy atoms generated by electron beam evaporation are deposited on the Se buffer layer 7' without damaging the two-dimensional material of the WSe2 channel layer 6'.

[0090] In step S18, a top gate electrode pattern is defined on the top gate dielectric layer 12' using the third photoresist layer 13', and TiN (second metal layer) 14' is deposited, and then a stripping process is performed to form a top gate electrode 15'.

[0091] In step S19, after forming the top gate electrode 15', the two-dimensional semiconductor field effect transistor manufactured as above is subjected to annealing treatment to remove the Se buffer layer 7' which is easy to sublime, thereby completing the preparation of the dual-gate two-dimensional semiconductor field effect transistor device.

[0092] The electrical performance of the dual-gate two-dimensional semiconductor field effect transistor device manufactured as described above was tested, and the electrical performance tested included carrier mobility, on-state and off-state current, subthreshold swing, hysteresis, etc. The test equipment was a semi-automatic electrical probe station and a semiconductor analyzer, and the test process was carried out in a nitrogen atmosphere to prevent the performance degradation of the material in the device from being affected by air.

[0093] It should be noted that the formula for the carrier mobility of a two-dimensional semiconductor field effect transistor is as follows:

[0094]

[0095] Where L is the channel length, W is the channel width, and C ox Represents dielectric capacitance.

[0096] Example 2

[0097] Using the above-mentioned two-dimensional semiconductor field-effect transistor, NMOS and PMOS inverters based on 2D WSe2 are prepared, the voltage transfer characteristic curve of the inverter is tested, and its performance such as noise tolerance, gain and operating logic level is evaluated.

[0098] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A method for manufacturing a two-dimensional semiconductor field effect transistor based on a high-k gate dielectric, characterized in that: include: A back gate electrode (2) and a back gate dielectric layer (3) are sequentially deposited on a substrate (1); Transferring the channel layer (4) onto the back gate dielectric layer (3); A buffer layer (5), a source electrode (6), a drain electrode (7), a top gate dielectric layer (8) formed of a high-k dielectric material, and a top gate electrode (9) are sequentially formed on the channel layer (4); and After forming the top gate electrode (9), an annealing treatment is performed in a vacuum environment so that the buffer layer (5) sublimates under heating conditions, so that the channel layer (4) forms a van der Waals interface with the top gate dielectric layer (8), and so that the channel layer (4) forms a van der Waals interface with the source electrode (6) and the drain electrode (7).

2. The method according to claim 1, characterized in that: A buffer layer (5), a source electrode (6), a drain electrode (7), a top gate dielectric layer (8) formed of a high-k dielectric material, and a top gate electrode (9) are sequentially formed on the channel layer (4), comprising: Depositing a buffer layer (5) on the channel layer (4); A source electrode (6) and a drain electrode (7) are formed on the buffer layer (5), wherein the source electrode (6) and the drain electrode (7) partially overlap with the channel layer (4) in a direction perpendicular to the substrate (1); A top gate dielectric layer (8) formed of a high-k dielectric material is deposited on the source (6), the drain (7) and the buffer layer (5), and a top gate electrode (9) is formed on the top gate dielectric layer (8).

3. The method according to claim 1, characterized in that: Transferring the channel layer (4) onto the back gate dielectric layer (3) comprises: The two-dimensional material layer is transferred to the surface of the back gate dielectric layer (3), and the two-dimensional material layer is subjected to photolithography, development and etching to form the channel layer (4).

4. The method according to claim 3, characterized in that: The two-dimensional material layer includes one of MoS2, MoSe2, WSe2, WS2, graphene and black phosphorus.

5. The method according to claim 1, characterized in that: The deposition energy of the buffer layer (5) is lower than the deposition energy of the top gate dielectric layer (8), and the binding energy of the buffer layer (5) is lower than the binding energy of the top gate dielectric layer (8), The buffer layer (5) is easy to sublime under vacuum conditions, and the sublimation temperature of the buffer layer (5) under vacuum conditions is 150° C. to 250° C.; Preferably, the material of the buffer layer (5) includes selenium.

6. The method according to claim 1, characterized in that: The material of the top gate dielectric layer (8) is a high-k dielectric material; Among them, the dielectric constant of the high-k dielectric material is higher than the dielectric constant of SiO2.

7. The manufacturing method according to claim 6, characterized in that: The material of the top gate dielectric layer (8) is HfO2.

8. The manufacturing method according to claim 1, characterized in that: The substrate (1) comprises a silicon layer and a silicon dioxide layer formed on the silicon layer.

9. The manufacturing method according to claim 1, characterized in that: The annealing temperature of the annealing treatment is 150℃~250℃, the annealing time is 4h~6h, and the vacuum environment is 10 -7 torr~10 -9 torr.

10. A two-dimensional semiconductor field effect transistor obtained by the manufacturing method according to any one of claims 1 to 9.

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