A method of manufacturing a semiconductor device

Abstract

This invention discloses a method for manufacturing a semiconductor device, relating to the field of semiconductor technology, for simultaneously improving the carrier mobility of NMOS and PMOS transistors, both of which have a gate-around-the-loop (GOP) transistor structure. The manufacturing method includes: forming a first GOP transistor on a first well region of a substrate, and forming a second GOP transistor on a second well region of the substrate. The crystal orientation of a first channel region of the first GOP transistor is perpendicular to the crystal orientation of a second channel region of the second GOP transistor. Forming the first GOP transistor on the first well region includes: forming a first stacked structure on the first well region. The first stacked structure includes a pre-formed layer and alternating first and second material layers formed on the pre-formed layer. The second material layer is the topmost layer in the first stacked structure. Each first material layer is laterally thinned so that the width of the remaining portion of each first material layer is equal to the width of the first channel region.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a semiconductor device. Background Technology

[0002] Gate-around transistors (GMT-A) have advantages over planar transistors and fin field-effect transistors, such as higher gate control capability. Therefore, when both NMOS and PMOS transistors in a CMOS device are gate-around transistors, the operating performance of the CMOS device can be improved.

[0003] However, when the device structures of the aforementioned NMOS and PMOS transistors are both existing gate-around transistors, it will lead to poor performance of the CMOS device including the NMOS and PMOS transistors. Summary of the Invention

[0004] The purpose of this invention is to provide a method for manufacturing a semiconductor device, which improves the carrier mobility of both the NMOS transistor and the PMOS transistor in a CMOS device, thereby enhancing the conductivity of the CMOS device, when both the NMOS transistor and the PMOS transistor in the CMOS device have a gate-around transistor structure.

[0005] To achieve the above objectives, the present invention provides a method for manufacturing a semiconductor device, the method comprising:

[0006] A substrate is provided. The substrate has a first well region and a second well region.

[0007] A first ring-gate transistor is formed on a first well region, and a second ring-gate transistor is formed on a second well region. The first ring-gate transistor and the second ring-gate transistor have opposite conductivity types. The first ring-gate transistor includes a first channel and a first gate stack surrounding the periphery of the first channel region. The second ring-gate transistor includes a second channel and a second gate stack surrounding the periphery of the second channel region. The crystal orientation of the first channel region is perpendicular to the crystal orientation of the second channel region. Forming the first ring-gate transistor on the first well region includes:

[0008] A first stacked structure is formed on the first well region. Along the thickness direction of the substrate, the first stacked structure includes a pre-formed layer and a first material layer and a second material layer alternately formed on the pre-formed layer. The second material layer is the topmost layer in the first stacked structure, and the length of the first stacked structure is equal to the length of the first channel region.

[0009] The first material layer comprising the first stacked structure is subjected to lateral thinning so that the width of the remaining portion of each first material layer comprising the first stacked structure is equal to the width of the first channel region.

[0010] Compared with the prior art, in the semiconductor device manufacturing method provided by the present invention, the first ring-gate transistor and the second ring-gate transistor formed on the substrate have opposite conductivity types, that is, one of the first ring-gate transistor and the second ring-gate transistor can be an NMOS transistor and the other is a PMOS transistor. In other words, the device structure of both the NMOS transistor and the PMOS transistor can be a ring-gate transistor, thereby simultaneously improving the gate control capability of both NMOS transistors and PMOS transistors and suppressing short-channel effects. Furthermore, the crystal orientation of the first channel region of the first ring-gate transistor is perpendicular to the crystal orientation of the second channel region of the second ring-gate transistor. Based on this, in practical applications, taking a first gate ring transistor as a PMOS transistor and a second gate ring transistor as an NMOS gate ring transistor as examples, if the first channel region of the first gate ring transistor has a

[110] crystal orientation and the second channel region of the second gate ring transistor has a

[100] crystal orientation, then compared with the prior art where both NMOS and PMOS transistors use gate ring transistors with a

[100] crystal orientation for the channel, the semiconductor device manufacturing method provided by this invention can simultaneously improve the carrier mobility of both NMOS and PMOS transistors, thereby enhancing the conductivity of the manufactured semiconductor device. Furthermore, the semiconductor device manufacturing method provided by this invention obtains the first channel region by performing lateral thinning on each first material layer included in the first stacked structure, without the need for additional photolithography and sidewall transfer processes, reducing the manufacturing difficulty of the semiconductor device and facilitating the acquisition of the aforementioned semiconductor device. Meanwhile, compared to laterally thinning the first fin structure used to manufacture the first channel region, laterally thinning only each first material layer with a length equal to the first channel region helps prevent bending or breakage of the first channel region after lateral thinning. Furthermore, during the lateral thinning process, the top and bottom of each first material layer are in contact with the corresponding second material layer and pre-formed layer. Under the protection of these two film layers, the top and bottom of the portion of each first material layer in the first stacked structure used to form the first channel region can be prevented from being unaffected by the lateral thinning process, thus improving the yield of the semiconductor device. Attached Figure Description

[0011] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0012] Figure 1 A flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0013] Figure 2Parts (1) and (2) are schematic diagrams of two structures after alternatingly forming a first material forming layer and a second material forming layer on a substrate in an embodiment of the present invention;

[0014] Figure 3 Parts (1) and (2) are schematic diagrams of two structures in the embodiments of the present invention: forming a pre-formed layer on a substrate and alternately forming a first material forming layer and a second material forming layer on the pre-formed layer.

[0015] Figure 4 This is a schematic diagram of the structure after the first fin and the second fin are formed on the substrate in an embodiment of the present invention;

[0016] Figure 5 Parts (1) and (2) are respectively a three-dimensional view of the first structure after shallow trench isolation is formed in the embodiment of the present invention and a cross-sectional view of the first structure along the B-B' direction;

[0017] Figure 6 Parts (1) and (2) are, respectively, a three-dimensional view of the second structure after shallow trench isolation is formed in the embodiment of the present invention and a cross-sectional view of the second structure along the B-B' direction;

[0018] Figure 7 Parts (1) and (2) are respectively a three-dimensional view of the third structure after shallow trench isolation is formed in the embodiment of the present invention and a cross-sectional view of the third structure along the B-B' direction;

[0019] Figure 8 This is a cross-sectional view of a structure along the B-B' direction after the sacrificial fence and sidewalls are formed in an embodiment of the present invention;

[0020] Figure 9 This is a cross-sectional view of the first structure along the A-A' direction after the sacrificial fence and sidewalls are formed in an embodiment of the present invention;

[0021] Figure 10 This is a cross-sectional view of the second structure along the A-A' direction after the sacrificial fence and sidewalls are formed in an embodiment of the present invention;

[0022] Figure 11 This is a cross-sectional view of the third structure along the A-A' direction after the sacrificial fence and sidewall are formed in an embodiment of the present invention;

[0023] Figure 12 Parts (1) and (2) are cross-sectional views of a structure formed in the first stacked structure and the second stacked structure in the embodiment of the present invention after the source region and the drain region are formed, along the B-B' direction;

[0024] Figure 13 This is a schematic diagram of the structure after the dielectric layer is formed in an embodiment of the present invention;

[0025] Figure 14This is a schematic diagram of a structure along the A-A' direction after selective oxidation treatment of each first material layer in the first stacked structure under the masking effect of the mask layer in an embodiment of the present invention.

[0026] Figure 15 This is a cross-sectional view of a structure along the A-A' direction after the first material layer of the first stacked structure is laterally thinned in an embodiment of the present invention.

[0027] Figure 16 Parts (1), (2) and (3) are cross-sectional views of three structures along the A-A' direction after the formation of the first channel region in the embodiment of the present invention;

[0028] Figure 17 This is a cross-sectional view of a structure along the A-A' direction after the formation of the first ring gate transistor in an embodiment of the present invention;

[0029] Figure 18 This is a cross-sectional view of a structure along the A-A' direction after removing the mask layer covering the second well region in an embodiment of the present invention;

[0030] Figure 19 Parts (1), (2) and (3) are cross-sectional views of three structures along the A-A' direction after the formation of the second channel region in the embodiment of the present invention;

[0031] Figure 20 This is a cross-sectional view of a structure along the A-A' direction after the semiconductor device has been formed in an embodiment of the present invention;

[0032] Figure 21 This is a cross-sectional view of a structure along the A-A' direction after the second channel region is formed under the masking effect of the cover layer in an embodiment of the present invention;

[0033] Figure 22 This is a cross-sectional view of a structure along the A-A' direction after the second ring gate transistor is formed under the masking effect of the capping layer in an embodiment of the present invention.

[0034] Reference numerals: 11 is the substrate, 111 is the first well region, 112 is the second well region, 12 is the first material forming layer, 121 is the first material layer, 13 is the second material forming layer, 131 is the second material layer, 14 is the strain buffer layer, 15 is the first fin, 151 is the first fin structure, 1511 is the first stacked structure, 16 is the second fin, 161 is the second fin structure, 1611 is the second stacked structure, 17 is the shallow trench isolation, 18 is the source forming region, 19 is the drain forming region, 20 is the transition region, 21 is the sacrificial gate, 2 2 is a sidewall, 23 is a preformed layer, 231 is a first preformed portion, 232 is a second preformed portion, 24 is a first source region, 25 is a first drain region, 26 is a second source region, 27 is a second drain region, 28 is a dielectric layer, 29 is a mask layer, 30 is an oxide layer, 31 is a first channel, 311 is a first channel region, 32 is a first gate stack, 321 is a first gate dielectric layer, 322 is a first gate, 33 is a second channel, 331 is a second channel region, 34 is a second gate stack, 341 is a second gate dielectric layer, and 342 is a second gate. Detailed Implementation

[0035] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0036] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0037] In the context of this disclosure, when a layer / element is referred to as being "on top of" another layer / element, the layer / element may be directly on top of the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "on top of" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element. To make the technical problems, technical solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0038] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0039] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0040] Gate-around transistors (GMT-A) have advantages over planar transistors and fin field-effect transistors, such as higher gate control capability. Therefore, when both NMOS and PMOS transistors in a CMOS device are gate-around transistors, the operating performance of the CMOS device can be improved.

[0041] However, the crystal orientation of the channel in existing gate-around transistors is typically

[100] . In this case, the channel of the gate-around transistor is conducive to the transport of electrons but not to the transport of holes. Based on this, since the channel carriers of NMOS transistors are electrons and the channel carriers of PMOS transistors are holes, when a gate-around transistor with a

[100] oriented channel is applied to the above-mentioned CMOS device, the gate-around transistor is only conducive to improving the electron mobility of NMOS transistors but not to the hole mobility of PMOS transistors, resulting in poor performance of the CMOS device using the above-mentioned gate-around transistor structure.

[0042] To address the aforementioned technical problems, embodiments of the present invention provide a method for manufacturing a semiconductor device. In this method, the first gate-ring transistor and the second gate-ring transistor formed on the substrate have opposite conductivity types. Furthermore, the crystal orientation of the first channel region of the first gate-ring transistor is perpendicular to the crystal orientation of the second channel region of the second gate-ring transistor, thereby simultaneously improving the carrier mobility of both NMOS and PMOS transistors and enhancing the conductivity of the manufactured semiconductor device. In addition, this manufacturing method obtains the first channel region by laterally thinning each first material layer included in the first stacked structure, eliminating the need for additional photolithography and sidewall transfer processes, thus reducing the manufacturing difficulty of the semiconductor device and facilitating the production of the aforementioned semiconductor device.

[0043] like Figure 1 As shown, this embodiment of the invention provides a method for manufacturing a semiconductor device. The following will describe a method based on... Figures 2 to 22 The illustrated perspective and cross-sectional views describe the manufacturing process. Specifically, the method for manufacturing this semiconductor device includes:

[0044] First, a substrate is provided. The substrate has a first well region and a second well region. Specifically, the substrate can be any semiconductor substrate such as a silicon substrate or a silicon-on-insulator substrate. The specific location, number, and doping type of the first well region of the substrate can be set according to the requirements of the formation location, number, and conductivity type of the first gate ring transistor in the actual application scenario, and are not specifically limited here.

[0045] For example, in a semiconductor device comprising a first gate-around transistor and a second gate-around transistor, wherein the first gate-around transistor is a PMOS transistor and the second gate-around transistor is an NMOS transistor, the substrate has a first well region and a second well region. Furthermore, the first well region is an N-well region and the second well region is a P-well region.

[0046] like Figures 2 to 22 As shown, a first ring-gate transistor is formed on a first well region 111, and a second ring-gate transistor is formed on a second well region 112. The first ring-gate transistor and the second ring-gate transistor have opposite conductivity types. The first ring-gate transistor includes a first channel 31 and a first gate stack 32 surrounding the outer periphery of the first channel region 311 in the first channel 31. The second ring-gate transistor includes a second channel 33 and a second gate stack 34 surrounding the outer periphery of the second channel region 331 in the second channel 33. The crystal orientation of the first channel region 311 is perpendicular to the crystal orientation of the second channel region 331. The formation of the first ring-gate transistor on the first well region 111 includes: Figures 2 to 12 As shown, a first stacked structure 1511 is formed on the first well region 111. Along the thickness direction of the substrate 11, the first stacked structure 1511 includes a pre-formed layer 23, and a first material layer 121 and a second material layer 131 alternately formed on the pre-formed layer 23. The second material layer 131 is the topmost layer in the first stacked structure 1511, and the length of the first stacked structure 1511 is equal to the length of the first channel region 311. Figure 14 and Figure 15 As shown, each first material layer 121 of the first stacked structure 1511 is subjected to lateral thinning so that the width of the remaining portion of each first material layer 121 of the first stacked structure 1511 is equal to the width w of the first channel region.

[0047] Specifically, the conductivity types of the first and second gate-ring transistors can be set according to the actual application scenario. For example, the first gate-ring transistor can be a PMOS transistor. In this case, the second gate-ring transistor is an NMOS transistor. Another example: the first gate-ring transistor can be an NMOS transistor. In this case, the second gate-ring transistor is a PMOS transistor. Furthermore, as mentioned above, the crystal orientation of the channel included in the gate-ring transistor affects the carrier transport mobility in the channel. Therefore, the crystal orientation of the first and second channel regions can be determined according to the conductivity types of the first and second gate-ring transistors to simultaneously improve the carrier mobility of both transistors and enhance the conductivity performance of the semiconductor device. For example, the first gate-ring transistor is a PMOS transistor, and the crystal orientation of the first channel region is

[110] . And the second gate-ring transistor is an NMOS transistor, and the crystal orientation of the second channel region is

[100] . At this time, since the channel with

[110] crystal orientation is conducive to improving the hole mobility and the channel with

[100] crystal orientation is conducive to improving the electron mobility, the hole mobility in the PMOS transistor and the electron carrier mobility in the NMOS transistor can be improved simultaneously under the above conditions.

[0048] For the aforementioned first and second trench regions, the materials of the first and second trench regions can be set according to the actual application scenario. It should be understood that since the first material layer included in the first stacked structure is a film layer used to manufacture the first trench region, the material of the first material layer is the same as the material of the first trench region. Furthermore, as... Figure 15 and Figure 16 As shown, the first channel region 311 will be released subsequently by at least removing the second material layer 131 located on the first well region 111. Therefore, the material of the second material layer 131 is different from that of the first material layer 121. Figures 14 to 22As shown, the first channel region 311 and the second channel region 331 can be fabricated by alternatingly forming a first material layer 121 and a second material layer 131 on the first and second well regions, respectively, thereby improving the manufacturing efficiency of semiconductor devices while reducing manufacturing costs. In the above case, the material of the second material layer 131 can be set with reference to the materials of the first material layer 121 and the second channel region 331. For example, the material of the first material layer 121 can be Si. 1-x Ge x Where 0 ≤ x ≤ 1. The second material layer 131 is made of Si. 1-y Ge y Where 0 ≤ y ≤ 1 and |xy| ≥ 0.2. Specifically, the difference in Ge content between the first material layer 121 and the second material layer 131 can be set according to actual needs, and is not specifically limited here. For example, the materials of the first material layer 121 and the second material layer 131 can be Si or Si2O2, respectively. 0.25 Ge 0.75 For example, the materials of the first material layer 121 and the second material layer 131 can be Si, respectively. 0.8 Ge 0.2 or Si 0.5 Ge 0.5 wait.

[0049] Furthermore, the number of nanowire or sheet layers in the first and second channel regions can be set according to the actual application scenario, and no specific limitation is made here. Specifically, for example... Figure 19 As shown, the number of nanowires or sheets in the first channel region 311 and the second channel region 331 can be the same or different. As mentioned above, since the first material layer 121 included in the first stacked structure 1511 is a film layer used to manufacture the first channel region 311, the number of the first material layer 121 included in the first stacked structure 1511 is equal to the number of nanowires or sheets in the first channel region 311. Furthermore, when the first channel region 311 and the second channel region 331 are manufactured by alternatingly forming the first material layer 121 and the second material layer 131, respectively, the number of the second material layer 131 is equal to the number of nanowires or sheets in the second channel region 331. Among them, except for the pre-formed layer 23, the bottom film layer in the first stacked structure 1511 can be either the first material layer 121 or the second material layer 131. Because the topmost film layer in the first stacked structure 1511 is the second material layer 131, and the first material layer 121 and the second material layer 131 are arranged alternately, the bottommost film layer affects the number of first material layer 121 and second material layer 131, and thus affects the number of nanowires or sheets in the first channel region 311 and the second channel region 331. For example: Figure 2 and Figure 3 Part (1) of the text, and Figures 9 to 11 As shown, the number of layers in the first material layer 121 is equal to the number of layers in the second material layer 131. The bottommost first material layer 121 is in contact with the pre-formed layer 23. For example: Figure 2 and Figure 3 As shown in section (2), the number of layers in the first material layer is one less than the number of layers in the second material layer. The second material layer, located at the bottom, is in contact with the pre-formed layer. Based on this, the bottom layer of the first stacked structure, excluding the pre-formed layer, can be determined as either the first material layer or the second material layer, depending on the number of nanowire or sheet layers in the first and second channel regions. For example, when the number of nanowire or sheet layers in the first and second channel regions is equal, the bottom first material layer is in contact with the pre-formed layer. As another example, when the number of nanowire or sheet layers in the first channel region is one less than the number of nanowire or sheet layers in the second channel region, the bottom second material layer is in contact with the pre-formed layer.

[0050] The thicknesses of the first and second material layers can be equal or unequal. For example, such as... Figures 9 to 22 As shown, the thickness of the first material layer 121 can be greater than the thickness of the second material layer 131. In this case, it is convenient to obtain the first channel region 311 with crystal orientation

[110] by performing a lateral thinning process on each of the thicker first material layers 121 included in the first stacked structure 1511, which is beneficial to improve the hole mobility of the PMOS transistor when the first ring gate transistor is a PMOS transistor. Furthermore, when the first channel region 311 and the second channel region 331 are fabricated by alternatingly forming the first material layer 121 and the second material layer 131, the thickness of the first material layer 121 being greater than the thickness of the second material layer 131 allows for lateral thinning so that the width w of the first channel region 311 and the height of the second channel region 331, as well as the height of the first channel region 311 and the width of the second channel region 331, do not differ significantly. This reduces the difference between the cross-sectional areas of the first channel region 311 and the second channel region 331, thereby facilitating a further improvement in the carrier mobility of the first gate-around transistor while simultaneously improving the carrier mobility of both the first and second gate-around transistors. Specifically, the thicknesses of the first material layer 121 and the second material layer 131 can be set according to actual needs. For example, the thickness of the first material layer 121 can be 10nm to 60nm. For example, the thickness of the second material layer 131 can be 5nm to 20nm. Furthermore, the difference between the width of the first material layer 121 and the width of the second material layer 131 after the lateral thinning process can be determined based on the crystal orientation of the first channel region 311 and the second channel region 331, without specific limitations here.

[0051] For the pre-formed layer included in the first stacked structure, the material of the pre-formed layer is at least different from the material of the first or second material layer in contact with the pre-formed layer, and its specific material can be set according to actual needs. The pre-formed layer can be a single-layer structure or a stacked structure composed of at least two film layers, and the specific structure of the pre-formed layer can be set according to the actual application scenario. Specifically, such as... Figures 9 to 11 As shown, the preformed layer 23 may include a first preformed portion 231 and / or a second preformed portion 232. The first preformed portion 231 is made of Si. The second preformed portion 232 is made of Si. 1-z Ge z Where 0 < z ≤ 1. When the preforming layer 23 includes a first preforming portion 231 and a second preforming portion 232, the second preforming portion 232 is located on the first preforming portion 231. For details on whether the preforming portion specifically includes only the first preforming portion 231, only the second preforming portion 232, or both, please refer to the detailed explanation of the manufacturing process below.

[0052] For the first gate stack and the second gate stack, as Figure 20 As shown, the first gate stack 32 includes at least a first gate dielectric layer 321 and a first gate 322 sequentially formed around the outer periphery of the first channel region 311. The first gate dielectric layer 321 may also be formed on the portion of the substrate 11 located in the first gate formation region. The second gate stack 34 includes at least a second gate dielectric layer 341 and a second gate 342 sequentially formed around the outer periphery of the second channel region 331. The second gate dielectric layer 341 may also be formed on the portion of the substrate 11 located in the second gate formation region. The materials of the first gate dielectric layer 321 and the second gate dielectric layer 341 can be the same or different. Specifically, they can be insulating materials with low dielectric constants, such as silicon oxide or silicon nitride, or insulating materials with high dielectric constants, such as HfO2, ZrO2, TiO2, or Al2O3. The materials of the first gate 322 and the second gate 342 can be the same or different. Specifically, they can be conductive materials such as doped polysilicon, TiN, TaN, or TiSiN.

[0053] In some cases, such as Figures 12 to 22As shown, the first gate-ring transistor further includes a first source region 24, a first drain region 25, a sidewall 22, and a dielectric layer 28. A first channel 31 is formed between the first source region 24 and the first drain region 25. The first source region 24 and the first drain region 25 can be made of semiconductor materials such as silicon, silicon germanium, or germanium. The dielectric layer 28 included in the first gate-ring transistor covers the first well region 111, and its top is flush with the top of the first gate stack 32. The sidewall 22 included in the first gate-ring transistor is formed between the dielectric layer 28 and the first gate stack 32. The dielectric layer 28 and the sidewall 22 can be made of insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride. It should be noted that the first channel 31 also includes a third channel region located below the sidewall 22. The first channel region 311 is located before and in contact with the two third channel regions.

[0054] In some cases, such as Figures 12 to 22 As shown, the second gate-ring transistor further includes a second source region 26, a second drain region 27, a sidewall 22, and a dielectric layer 28. A second channel 33 is formed between the second source region 26 and the second drain region 27. The dielectric layer 28 of the second gate-ring transistor covers the second well region 112, and its top is flush with the top of the second gate stack 34. The sidewall 22 of the second gate-ring transistor is formed before the dielectric layer 28 and the second gate stack 34. The materials of the second source region 26, the second drain region 27, the sidewall 22, and the dielectric layer 28 of the second gate-ring transistor can be set with reference to the materials of the first source region 24, the first drain region 25, the sidewall 22, and the dielectric layer 28 of the first gate-ring transistor described above, and will not be repeated here.

[0055] In practical applications, the order in which the first and second gate-ring transistors are formed can be set according to the specific application scenario. For example, the first gate-ring transistor can be formed on the first well region, and then the second gate-ring transistor can be formed on the second well region. Alternatively, the second gate-ring transistor can be formed on the second well region first, and then the first gate-ring transistor can be formed on the first well region. Furthermore, a first stacked structure for manufacturing the first channel region can be formed on the first well region, while a second stacked structure for manufacturing the second channel region is formed on the second well region, with the composition of the second stacked structure being the same as the first stacked structure. In this case, the first channel region and the second channel region can be manufactured by alternately forming the first material layer and the second material layer, respectively.

[0056] In one example, such as Figures 2 to 12As shown above, when a first stacked structure 1511 is formed on the first well region 111 and a second stacked structure 1611 is formed on the second well region 112 simultaneously, after providing a substrate 11 and before performing lateral thinning on each first material layer 121 located on the first well region 111, forming a first gate ring transistor on the first well region 111 and a second gate ring transistor on the second well region 112 includes the following steps:

[0057] like Figures 2 to 7 As shown, a first fin structure 151 and a second fin structure 161 with identical structures are formed on a substrate 11. The first fin structure 151 is located on a first well region 111. The second fin structure 161 is located on a second well region 112. Both the first fin structure 151 and the second fin structure 161 have a source formation region 18, a drain formation region 19, and a transition region 20 located between the source formation region 18 and the drain formation region 19.

[0058] In practical applications, such as Figure 2 As shown, a first material forming layer 12 for manufacturing a first material layer and a second material forming layer 13 for manufacturing a second material layer can be alternately formed directly on the substrate 11 using processes such as epitaxial growth. Information regarding the material and thickness of the first material forming layer 12 and the second material forming layer 13 can be found above and will not be repeated here. Alternatively, as... Figure 3 As shown, after providing the substrate 11, a strain buffer layer 14 can be formed on the substrate 11 using processes such as epitaxial growth. This provides stress to the subsequently formed first material forming layer 12 and second material forming layer 13, thereby generating strain in the first channel region and second channel region formed based on the first material forming layer 12 and second material forming layer 13. This further improves the carrier mobility of the first gate ring transistor and the second gate ring transistor, enhancing the driving performance of the semiconductor device. Specifically, the strain buffer layer 14 is a film layer used to form the second pre-formed portion 232. Therefore, the material and thickness of the strain buffer layer 14 can be set with reference to information such as the material and thickness of the second pre-formed portion 232. Figure 4 As shown, photolithography and dry etching processes can then be used to etch the alternating first and second material formation layers, as well as the substrate 11 and / or strain buffer layer, from top to bottom, to form the first fin 15 on the first well region 111 and the second fin 16 on the second well region 112. Depending on whether a strain buffer layer is formed and the thickness of the strain buffer layer, the etching process can be divided into three types: The first type: ... Figure 4As shown, if the aforementioned strain buffer layer is not formed, then the first material forming layer, the second material forming layer, and the substrate 11 need to be etched. Secondly, if a strain buffer layer with a large thickness is formed, then the first material forming layer, the second material forming layer, and the strain buffer layer need to be etched. Thirdly, if a strain buffer layer with a small thickness is formed, then the first material forming layer, the second material forming layer, the strain buffer layer, and the substrate 11 need to be etched. Figures 5 to 7 As shown, shallow trench isolation 17 can be formed on the portion of the substrate 11 or strain buffer layer exposed outside the first and second fins using processes such as deposition, chemical mechanical polishing, and etching. The portions of the first and second fins exposed outside the shallow trench isolation 17 are respectively the first fin structure 151 and the second fin structure 161. The thickness of the shallow trench isolation 17 is less than or equal to the total thickness of the substrate 11 and / or the strain buffer layer etched, to facilitate subsequent removal of the pre-formed layer located on the first well region 111 and / or the second well region 112, releasing the second material layer (or the first material layer).

[0059] It should be noted that the identical structure of the first fin structure and the second fin structure means that the membrane layers, the material of each membrane layer, and the number of membrane layers are all the same in both structures. The length extension directions of the first fin structure and the second fin structure can be the same or different.

[0060] like Figures 8 to 11 As shown, a sacrificial gate 21 and sidewalls 22 are formed covering the transition region 20 of the first fin structure and the outer periphery of the transition region 20 of the second fin structure. The sidewalls 22 are formed on at least both sides of the sacrificial gate 21 along its width. The portion of the first fin structure covered by the sacrificial gate 21 is a first stacked structure 1511. The portion of the second fin structure covered by the sacrificial gate 21 is a second stacked structure 1611.

[0061] Specifically, the length extension direction of the sacrificial gate can be any direction parallel to the substrate surface and different from the length extension directions of both the first fin structure and the second fin structure. Preferably, when the length extension directions of the first fin structure and the second fin structure are the same, the length extension direction of the sacrificial gate is perpendicular to the length extension directions of both the first fin structure and the second fin structure.

[0062] In practical applications, processes such as chemical vapor deposition (CVD) can be used to deposit the gate material for forming the sacrificial gate onto the existing structure. Then, processes such as dry etching can be used to etch the gate material, retaining the portion of the gate material covering the transition region of the first fin structure and the outer periphery of the transition region of the second fin structure, thus obtaining the sacrificial gate. The gate material can be an amorphous silicon, polycrystalline silicon, or other easily removable materials. Figure 8As shown, after forming the sacrificial gate 21, a sidewall 22 can be formed at least on the sidewall of the sacrificial gate 21 using the method described above. The material of the sidewall 22 can be referred to the previous text. The thickness of the sidewall 22 can be set according to actual needs.

[0063] It should be noted that, as Figure 5 and Figure 9 As shown, if the aforementioned strain buffer layer is not formed, the portion of the substrate 11 that is etched and surrounded by the sacrificial gate 21 constitutes the pre-formed layer 23. In this case, if the substrate 11 is a silicon-based substrate, the pre-formed layer 23 only includes the first pre-formed portion 231. Figure 6 and Figure 10 As shown, if a strain buffer layer with a relatively large thickness is formed, the portion of the strain buffer layer that is etched and surrounded by the sacrificial gate 21 is the pre-formed layer 23. In this case, the pre-formed layer 23 only includes the second pre-formed portion 232. Figure 7 and Figure 11 As shown, if a strain buffer layer with a small thickness is formed, the preformed layer 23 includes a portion of the strain buffer layer that is etched and surrounded by the sacrificial gate 21 (this portion is the second preformed portion 232) and a portion of the substrate 11 that is etched and surrounded by the sacrificial gate 21 (this portion is a preformed portion 231).

[0064] like Figure 12 As shown, the source formation region and drain formation region of the first fin structure are processed to form the first source region 24 and the first drain region 25 of the first ring gate transistor; and the source formation region and drain formation region of the second fin structure are processed to form the second source region 26 and the second drain region 27 of the second ring gate transistor.

[0065] In practical applications, the formation order of the first source region and the first drain region, as well as the second source region and the second drain region, can be set according to the actual application scenario, and no specific limitation is made here. For example, under the masking effect of the first capping layer, the portion of the first fin structure located in the source formation region and the drain formation region can be removed first using a dry etching process or a wet etching process. The first capping layer is located on the second well region. Figure 12 As shown in part (1), a first source region 24 is epitaxially formed at least in the source formation region located on the first well region 111, and a first drain region 25 is epitaxially formed at least in the drain formation region using processes such as epitaxial growth. Alternatively, ion implantation can be performed directly on the portions of the first fin structure located in the source formation region and the drain formation region, so that the source formation region located on the first well region corresponds to the formation of the first source region, and the drain formation region located on the first well region corresponds to the formation of the first drain region. Then, the first capping layer is removed. Under the masking effect of the second capping layer located on the first well region, the second source region and the second drain region can be formed in the manner described above.

[0066] In some cases, such as Figure 13 As shown, when the manufactured semiconductor device also includes a dielectric layer 28, the dielectric layer 28 can be formed over the formed structure by deposition, chemical mechanical polishing, and etching processes after forming the first source region, the first drain region, the second source region, and the second drain region. The top of the dielectric layer 28 is flush with the top of the sacrificial gate 21.

[0067] The sacrificial gate can then be removed using dry etching or wet etching processes. Specifically, the portions of the sacrificial gate located in the first and second well regions can be removed simultaneously, or the portions of the sacrificial gate located in the first and second well regions can be removed separately in different steps.

[0068] It should be noted that the above structure can be formed in various ways. How the structure is formed is not the main feature of this invention; therefore, it is only briefly described in this specification to enable those skilled in the art to easily implement the invention. Those skilled in the art can certainly conceive of other ways to manufacture the above structure.

[0069] It is understandable that after removing the portion of the sacrificial gate located on the first and second well regions, both the first and second stacked structures are exposed. Based on this, as... Figures 14 to 17 As shown, a first channel region 311 can be formed based on the first stacking structure 1511, and a first gate stack 32 can be formed on the outer periphery of the first channel region 311. Figures 18 to 20 As shown, a second channel region 331 is then formed based on the second stacking structure 1611, and a second gate stack 34 is formed around the second channel region 331. Alternatively, as... Figure 21 , Figure 22 and Figure 20 As shown, the semiconductor device can be formed in the reverse order of the above process. Alternatively, after forming a first channel region based on a first stacked structure and a second channel region based on a second stacked structure, a first gate stack can be formed on the outer periphery of the first channel region, and a second gate stack can be formed on the outer periphery of the second channel region. In this case, the order in which the first and second channel regions are formed, as well as the order in which the first and second gate stacks are formed, can be set according to actual needs and are not specifically limited here.

[0070] The following example illustrates the formation of the four structures described above, using the sequential formation of the first channel region and the first gate stack as an example, followed by the sequential formation of the second channel region and the second gate stack:

[0071] In practical applications, under the protection of the pre-formed layer and the second material layer, an etchant that has an etching effect on the first material layer can be used to directly perform lateral thinning on each of the first material layers included in the first stacked structure. Alternatively, as... Figure 14 and Figure 15 As shown, a quasi-atomic layer etching process can also be used to perform lateral thinning of each first material layer 121 included in the first stacked structure 1511.

[0072] For example, the lateral thinning process of each first material layer in the first stacked structure using a quasi-atomic layer etching process may include the following steps: Figure 14 As shown, under the masking effect of the mask layer 29, each of the first material layers 121 included in the first stacked structure 1511 undergoes selective oxidation treatment, thereby laterally thinning each of the first material layers 121 included in the first stacked structure 1511 to a fixed thickness, and forming an oxide layer 30 on the sidewall of the remaining portion of each of the first material layers 121 included in the first stacked structure 1511. The mask layer 29 covers the second well region 112. The oxide layer is then removed. Figure 15 As shown, repeat the above operation until the width of the remaining portion of each first material layer included in the first stack structure 1511 is equal to the width w of the first channel region 311.

[0073] Specifically, the material of the aforementioned mask layer can be set according to actual needs. For example, the mask layer can be a photoresist mask layer, a spin-coated carbon mask layer, or an advanced patterning mask layer. Under the masking effect of the aforementioned mask layer, solutions with strong oxidizing properties, such as nitric acid or hydrogen peroxide, can be used to selectively oxidize each of the first material layers included in the first stacked structure. The concentration of the aforementioned strong oxidizing solution can be set according to the actual application scenario. For example, when the strong oxidizing solution is a nitric acid solution, the mass fraction of nitric acid can be 20% to 70%. When the strong oxidizing solution is a hydrogen peroxide solution, the mass fraction of hydrogen peroxide can be 20% to 40%. Then, HF solution or buffered oxide etching solution can be used to remove the oxide layer. The number of repetitions of the above operation can be determined according to the thickness of the oxide layer formed each time, as well as the width w of the first material layer and the first channel region, and is not specifically limited here. In addition, it should be noted that during the above selective oxidation process, the thickness of each oxidation will saturate after a certain period of time. In other words, after the selective oxidation time is greater than or equal to the saturation time, the formed oxide layer can isolate the remaining part of each first material layer included in the first stack structure from the strong oxidizing solution, preventing that part from continuing to react. Thus, the thickness of each lateral thinning can be precisely controlled without precisely controlling the etching time, ensuring that the width of the first channel region meets the working requirements, and further improving the yield of the first ring gate transistor.

[0074] It is worth noting that the semiconductor device manufacturing method provided in this embodiment of the invention obtains the first channel region by performing lateral thinning on each first material layer of the first stacked structure whose length is equal to that of the first channel region. This eliminates the need for additional photolithography and sidewall transfer processes, reducing the manufacturing difficulty of the semiconductor device and facilitating the production of the aforementioned semiconductor device. Furthermore, compared to performing lateral thinning on the first fin structure used to manufacture the first channel region, performing lateral thinning only on each first material layer whose length is equal to that of the first channel region helps prevent bending or breakage of the first channel region after lateral thinning, thereby improving the yield of the semiconductor device.

[0075] It should be noted that since the second material layer, or the second material layer and the pre-formed layer in the first stacked structure, will be removed in subsequent operations, whether the first material layer of the first stacked structure is directly etched by an etchant or the first material layer is laterally thinned by a quasi-atomic layer etching process, the etchant or strong oxidizing solution used to treat the first material layer of the first stacked structure can be used to treat only the first material layer, or it can be used to treat the second material layer and the pre-formed layer of the first stacked structure. As long as the etching rate of the etchant and strong oxidizing solution on the second material layer and the pre-formed layer is less than or equal to the etching rate on the first material layer, the top and bottom of the portion of the first material layer forming the first channel region can be protected by the second material layer and the pre-formed layer. This can expand the range of materials that can be selected for the second material layer and the pre-formed layer while reducing the difficulty of the lateral thinning process.

[0076] like Figure 16 and Figure 17 As shown, after performing lateral thinning on each first material layer 121 of the first stacked structure 1511, forming the first ring gate transistor on the first well region 111 further includes the step of: Figure 16 As shown, at least the second material layer located on the first well region 111 is selectively removed, such that the remaining portion of the first material layer located on the first well region 111 and after lateral thinning forms the portion of the first channel 31 located within the first channel region 311. Figure 17 As shown, a first gate stack 32 is formed at least on the outer periphery of the first channel region 311.

[0077] Specifically, in the first stacked structure, the first material layer and the second material layer are formed alternately. Therefore, to release the first channel region, at least the second material layer located on the first well region needs to be removed. Whether or not the pre-formed layer located on the first well region needs to be removed depends on whether the film layer in contact with the pre-formed layer is the first material layer or the second material layer. If the bottommost first material layer is in contact with the pre-formed layer, such as... Figure 16As shown in part (1), it is also necessary to remove the pre-formed layer located on the first well region 111 to release the first material layer located at the bottom layer after lateral thinning. If the second material layer located at the bottom layer is in contact with the pre-formed layer, such as Figure 16 As shown in parts (2) and (3), the pre-formed layer located on the first well region 111 can be removed, or it can be left unremoved. Specifically, under the masking effect of the mask layer 29, the second material layer, or the second material layer and the pre-formed layer, located on the first well region 111 can be removed using a dry or wet etching process. Then, as... Figure 17 As shown, the first gate stack 32 can be formed using processes such as atomic layer deposition. After forming the first ring gate transistor, the mask layer needs to be removed to facilitate the subsequent formation of the second ring gate transistor.

[0078] like Figures 18 to 20 As shown, after forming the first ring gate transistor on the first well region 111, forming the second ring gate transistor on the second well region 112 further includes the following steps: Figure 18 and Figure 19 As shown, at least the first material layer located on the second well region 112 is selectively removed, such that the second material layer located on the second well region 112 forms the portion of the second channel 33 located within the second channel region 331. Figure 20 As shown, a second gate stack 34 is formed at least on the outer periphery of the second channel region 331.

[0079] Specifically, as mentioned above, in the second stacked structure, the first material layer and the second material layer are formed alternately. Therefore, to release the second channel region, at least the first material layer located on the second well region needs to be removed. Whether or not the pre-formed layer located on the second well region needs to be removed depends on whether the film layer in contact with the pre-formed layer is the first material layer or the second material layer. If the bottommost first material layer is in contact with the pre-formed layer, such as... Figure 19 As shown in parts (1) and (2), the pre-formed layer located on the second well region 112 can be removed, or it can be left unremoved. If the bottommost second material layer is in contact with the pre-formed layer, such as Figure 19 As shown in section (3), it is also necessary to remove the pre-formed layer located on the second well region 112 to release the second material layer located at the bottom layer on the second well region 112. Specifically, the second material layer located on the second well region 112, or the second material layer and the pre-formed layer, can be removed using a dry or wet etching process. Then, as... Figure 20 As shown, the second gate stack 34 can be formed using processes such as atomic layer deposition.

[0080] It should be noted that, except for forming the second ring-gate transistor after forming the first ring-gate transistor, such as... Figure 21 and Figure 22As shown, after removing the sacrificial gate, and before performing lateral thinning on each of the first material layers 121 included in the first stacked structure 1511, the second stacked structure 1611 can be processed to form a second channel region 331, and a second gate stack 34 can be formed on the outer periphery of the second channel region 331. Alternatively, as described above, after forming the first channel region based on the first stacked structure and the second channel region based on the second stacked structure, a first gate stack can be formed on the outer periphery of the first channel region, and a second gate stack can be formed on the outer periphery of the second channel region. The specific formation processes corresponding to the above situations can be referred to above, and will not be repeated here.

[0081] As can be seen from the above, in the semiconductor device manufacturing method provided by the embodiments of the present invention, the first ring-gate transistor and the second ring-gate transistor formed on the substrate have opposite conductivity types, that is, one of the first ring-gate transistor and the second ring-gate transistor can be an NMOS transistor and the other is a PMOS transistor. In other words, the device structure of both the NMOS transistor and the PMOS transistor can be a ring-gate transistor, thereby simultaneously improving the gate control capability of both NMOS transistors and PMOS transistors and suppressing short-channel effects. Furthermore, the crystal orientation of the first channel region of the first ring-gate transistor is perpendicular to the crystal orientation of the second channel region of the second ring-gate transistor. Based on this, in practical applications, taking the first ring gate transistor as a PMOS transistor and the second ring gate transistor as an NMOS ring gate transistor as an example, if the first channel region of the first ring gate transistor has a

[110] crystal orientation and the second channel region of the second ring gate transistor has a

[100] crystal orientation, then compared with the prior art where both NMOS transistors and PMOS transistors use ring gate transistors with a

[100] crystal orientation for the channel, the semiconductor device manufacturing method provided by the present invention can simultaneously improve the carrier mobility of NMOS transistors and PMOS transistors, and improve the conductivity of the manufactured semiconductor device.

[0082] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0083] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, include: A substrate is provided; the substrate has a first well region and a second well region; A first ring-gate transistor is formed on the first well region, and a second ring-gate transistor is formed on the second well region; the first ring-gate transistor and the second ring-gate transistor have opposite conductivity types; the first ring-gate transistor includes a first channel and a first gate stack surrounding the periphery of the first channel region, the first gate stack surrounding the periphery of each nanowire or sheet included in the first channel region; the second ring-gate transistor includes a second channel and a second gate stack surrounding the periphery of the second channel region, the second gate stack surrounding the periphery of each nanowire or sheet included in the second channel region; the crystal orientation of the first channel region is perpendicular to the crystal orientation of the second channel region, and the materials of the first channel and the second channel are different; wherein, forming the first ring-gate transistor on the first well region includes: in the first well region A first stacked structure is formed on the substrate; along the thickness direction of the substrate, the first stacked structure includes a pre-formed layer and alternating first and second material layers formed on the pre-formed layer; the top layer of the first stacked structure is the second material layer, and the length of the first stacked structure is equal to the length of the first channel region; each of the first material layers included in the first stacked structure is laterally thinned such that the width of the remaining portion of each of the first material layers included in the first stacked structure is equal to the width of the first channel region; at least the second material layer located on the first well region is selectively removed such that the remaining portion of the first material layer located on the first well region and after the lateral thinning process forms the portion of the first channel located within the first channel region; the first gate stack is formed at least on the outer periphery of the first channel region; The process of forming a first gate-around transistor on the first well region and a second gate-around transistor on the second well region includes: forming a first fin structure and a second fin structure with identical structures on the substrate; the first fin structure is located on the first well region; the second fin structure is located on the second well region; both the first fin structure and the second fin structure have a source formation region, a drain formation region, and a transition region located between the source formation region and the drain formation region; forming a sacrificial gate and sidewalls covering the outer periphery of the transition regions of the first fin structure and the second fin structure; the sidewalls are formed at least on both sides of the sacrificial gate along the width direction; the portion of the first fin structure covered by the sacrificial gate is the first stacked structure; the portion of the second fin structure covered by the sacrificial gate is the second stacked structure; processing the source formation region and the drain formation region of the first fin structure to form a first source region and a first drain region included in the first gate-around transistor; and processing the source formation region and the drain formation region of the second fin structure to form a second source region and a second drain region included in the second gate-around transistor; and removing the sacrificial gate; The step of removing the sacrificial gate, or forming the second ring gate transistor on the second well region after forming the first ring gate transistor on the first well region, further includes: at least selectively removing the first material layer located on the second well region, such that the second material layer located on the second well region forms the portion of the second channel located within the second channel region; and forming the second gate stack at least on the outer periphery of the second channel region.

2. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The first ring gate transistor is a PMOS transistor, and the crystal orientation of the first channel region is [110] crystal orientation; The second ring gate transistor is an NMOS transistor, and the crystal orientation of the second channel region is [100].

3. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The number of layers in the first material layer is equal to the number of layers in the second material layer; the first material layer, which is the bottommost layer, is in contact with the pre-formed layer; or, The first material layer has one less layer than the second material layer; the second material layer, which is the bottommost layer, is in contact with the preformed layer.

4. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The thickness of the first material layer is greater than the thickness of the second material layer; and / or, The thickness of the first material layer is 10 nm to 60 nm; and / or, The thickness of the second material layer is 5nm~20nm.

5. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The first material layer is made of Si. 1-x Ge x ; Where 0 ≤ x ≤ 1; The second material layer is made of Si. 1-y Ge y Where 0≤y≤1 and |xy|≥0.

2.

6. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The preformed layer includes a first preformed portion and / or a second preformed portion; the first preformed portion is made of Si; the second preformed portion is made of Si. 1-z Ge z Where 0 < z ≤ 1; In the case where the preformed layer includes the first preformed portion and the second preformed portion, the second preformed portion is located on the first preformed portion.

7. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The first material layer comprising the first stacked structure is subjected to the lateral thinning process using a quasi-atomic layer etching process.

8. The method for manufacturing a semiconductor device according to claim 7, characterized in that, The lateral thinning process performed on each of the first material layers in the first stacked structure using a quasi-atomic layer etching process includes: Under the masking effect of the mask layer, each of the first material layers included in the first stacked structure is selectively oxidized to reduce the thickness of each of the first material layers included in the first stacked structure laterally to a fixed thickness, and an oxide layer is formed on the sidewall of the remaining portion of each of the first material layers included in the first stacked structure; the mask layer covers the second well region. Remove the oxide layer; Repeat the above operation until the width of the remaining portion of the first material layer in each of the first stacked structures is equal to the width of the first channel region.

9. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The second material layer, located at the bottom layer, is in contact with the pre-formed layer; The selective removal of the first material layer located on the second well region is: selectively removing the pre-formed layer located on the second well region and the first material layer located on the second well region.

10. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The first material layer, located at the bottom layer, is in contact with the pre-formed layer; The selective removal of the second material layer located on the first well region is: selectively removing the pre-formed layer located on the first well region and the second material layer located on the first well region.

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