Heterojunction HEMT device based on AlN buffer layer on AlN substrate and preparation method

Abstract

The invention discloses a heterojunction HEMT (High Electron Mobility Transistor) device based on an AlN buffer layer on an AlN substrate and a preparation method, and mainly solves the problems of high dislocation density, large electric leakage, poor heat conductivity, serious current collapse and low channel two-dimensional electron gas concentration of the buffer layer of the existing similar device. The device comprises a substrate, a buffer layer, a channel layer, a barrier layer and a cap layer from bottom to top, a drain electrode and a source electrode are arranged on the two sides of the cap layer, a gate electrode is arranged in the middle of the cap layer, a passivation layer covers the top of the device, and the substrate is an AlN single crystal substrate; the buffer layer adopts an AlN thin film with the thickness of 60 nm to 400 nm; the barrier layer is one or a combination of more of AlGaN, InAlN, AlN, AlScN and Si doped AlGaN; and the passivation layer is one or a combination of more of air, SiO2, Al2O3 and SiNx. The high-power microwave radio frequency device has the advantages of low on resistance, high reverse voltage resistance, high output power, small grid electric leakage and higher grid control capability, and can be used as a high-power microwave radio frequency device.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and in particular relates to a novel heterogeneous high electron mobility transistor (HEMT) and a preparation method thereof, which can be used as a high-power microwave radio frequency device. Background Art

[0002] The demand for millimeter-wave power amplifiers for next-generation cellular communication networks and radar applications continues to grow. As a wide-bandgap semiconductor material, GaN is considered to be the preferred platform for future millimeter-wave solid-state power amplification due to its wide bandgap, high breakdown electric field, high electron saturation velocity, radiation resistance, strong polarization effect, and high-concentration two-dimensional electron gas generated at the heterojunction interface.

[0003] At present, AlGaN / GaN high electron mobility transistors (HEMTs) have become the mainstream in high-frequency and high-power applications, showing their unique advantages. In order to further optimize the performance of its devices, improve its power and frequency characteristics, and obtain RF devices with higher current and higher power, it is necessary to optimize the materials, device structure and process, minimize the device parasitic parameters, and improve the device RF performance. In terms of materials, it is necessary to use a new heterojunction structure to reduce the surface resistance of the material, and at the same time optimize the substrate and buffer layer structure to improve the device's withstand voltage.

[0004] Traditional heterojunction structures are mainly based on heteroepitaxial GaN and heterojunction structures on substrates such as SiC, Si, and sapphire. Due to the large lattice mismatch between the substrate and GaN, there is a high density of dislocations in the epitaxial layer. In order to avoid high dislocations in the heteroepitaxial layer, a GaN buffer layer with a thickness of about 1um needs to be introduced between the substrate and the heterostructure. Figure 1 The traditional SiC substrate AlGaN / GaN heterostructure is given. It includes substrate 1, GaN buffer layer 2, intrinsic GaN layer 3, AlGaN barrier layer 4, GaN cap layer 5 and passivation layer 6 from top to bottom. This structure is difficult to obtain high-concentration two-dimensional electron gas due to the use of conventional heterojunctions. At the same time, due to the high dislocation density of the GaN buffer layer, the buffer layer is prone to leakage under high-voltage conditions, which cannot meet the needs of high-frequency, high-power microwave radio frequency applications. In addition, the thick GaN buffer layer has poor thermal conductivity, resulting in poor heat dissipation and causing current collapse effect.

[0005] The patent document with application number CN202222280818.6 discloses "a hybrid gate GaN-based high electron mobility transistor", which includes SiC substrate, AlIn nucleation layer, GaN buffer layer, GaN channel layer, AlGaN barrier layer, and passivation layer from bottom to top. A groove is etched on the upper surface of the AlGaN barrier layer, and a P cap layer is arranged in the groove. The P cap layer protrudes from the upper surface of the AlGaN barrier layer and is lower than the upper surface of the passivation layer. The Al component in the AlGaN barrier layer gradually changes from 0.3 to 0.24 from the passivation layer to the GaN channel layer. This structure has the following disadvantages: 1. The barrier layer needs to be etched, which will introduce etching damage, deteriorate the surface and interface states, and cause reliability problems such as premature breakdown, and cannot meet high power requirements; 2. An additional P-GaN cap layer needs to be grown, which increases the growth difficulty and preparation cost; 3. The control conditions of the AlGaN barrier layer with a gradient Al component are strict, and the preparation yield is low;

[0006] Patent document with application number CN201810771532.3 discloses "a method for isolating GaN devices based on InGaN insertion layer", which sets an InGaN insertion layer between the isolation regions of the GaN epitaxial wafer. The InGaN insertion layer is located outside the AlGaN layer, and polarized negative charges are induced in the heterojunction between the InGaN insertion layer and the AlGaN barrier layer to achieve isolation of different device regions. The isolation passivation layers of different device regions are made of SiN prepared by PECVD, LPCVD, ALD or Sputter deposition. x , SiO2, SiNO, Al2O3, AIN or one or more. This structure needs to grow a layer of SiO2 as an InGaN growth barrier layer first, and then remove the barrier layer above InGaN by etching. After InGaN grows, the AlGaN barrier layer SiO2 barrier layer needs to be removed. Multiple etchings introduce etching damage, which will cause the surface state of the barrier layer to deteriorate. At the same time, since this structure does not use full ALD passivation, the passivation layer is not dense and the device leakage is large. Summary of the invention

[0007] The purpose of the present invention is to address the deficiencies of the above-mentioned prior art and propose a high electron mobility transistor based on an AlN substrate and an AlN buffer layer and a method for manufacturing the same, so as to reduce leakage and etching damage of the buffer layer, improve the density of the passivation layer, and increase the concentration of the two-dimensional electron gas of the heterojunction, thereby enhancing the reverse withstand voltage of the high electron mobility transistor, improving the power output density of the device and the radio frequency device, and meeting the application requirements of GaN-based high electron mobility transistors in high power, high frequency and high efficiency.

[0008] The technical solutions for achieving the purpose of the present invention include the following:

[0009] 1. A heterojunction HEMT device based on an AlN buffer layer on an AlN substrate, which comprises, from bottom to top, a substrate 1, a buffer layer 2, a channel layer 3, a barrier layer 4, and a cap layer 5, with a drain electrode 6 and a source electrode 7 on both sides of the cap layer 5, a gate electrode 8 in the middle of the cap layer 5, and a passivation layer 9 covering the top of the device, characterized in that:

[0010] The substrate 1 is an AlN single crystal substrate;

[0011] The buffer layer 2 is an AlN film with a thickness of 60nm-400nm;

[0012] The barrier layer 4 is one or a combination of AlGaN, InAlN, AlN, AlScN and Si-doped AlGaN;

[0013] The passivation layer 9 is composed of air, SiO2, Al2O3, SiN x 、SiN X One or a combination of .

[0014] Furthermore, the channel layer 3 is made of GaN or Al with a thickness of 50nm-200nm. x Ga (1-x) N, the Al x Ga (1-x) The Al component in N is 20-60%; the cap layer 5 is made of GaN with a thickness of 2nm-10nm or SiN with a thickness of 3nm-5nm; the source electrode 6 and the drain electrode 7 are ohmic contacts, and the electrode metal is a Ti / Al / Ni / Au stacked combination with thicknesses of 22 / 140 / 45 / 55nm respectively.

[0015] Furthermore, the gate electrode 8 is a T-shaped structure that is wide at the top and narrow at the bottom. The gate foot length of the part in contact with the cap layer 5 is 50nm-250nm and the width is 10um-300um. It is in Schottky contact with the cap layer 5. The electrode metal adopts Ni / Au metal stack with thicknesses of 40 / 400nm respectively.

[0016] 2. A method for preparing a heterojunction HEMT device based on an AlN buffer layer on an AlN substrate, characterized in that it comprises the following steps:

[0017] 1) Selecting an AlN single crystal substrate 1, and epitaxially growing a 60nm-400nm AlN thin film buffer layer 2 on the surface thereof by a metal organic compound vapor deposition process MOCVD;

[0018] 2) A 50nm-200nm thick GaN or AlGaN channel layer 3, a 5nm-20nm thick AlGaN or 1nm-5nm thick AlN barrier layer 4, a 2nm-10nm thick GaN or 3nm-

[0019] 5nm SiN cap layer 5;

[0020] 3) performing photolithography on the mesa region of the epitaxial wafer, and using an inductively coupled plasma ICP dry etching process to completely remove the cap layer 5, the barrier layer 4, and the channel layer 3 in the area between the mesas, and etching to the AlN buffer layer 2 to form mesa isolation;

[0021] 4) Photolithography of the source and drain regions is performed on the table, and Ti / Al / Ni / Au metal stacks are evaporated in the source and drain regions using electron beam evaporation equipment, followed by metal annealing to form source electrodes 6 and drain electrodes 7;

[0022] 5) Electron beam lithography is performed on the gate region between the source and drain regions to obtain a plurality of gate metal patterns, and a Ni / Au metal stack is deposited on the surface of the gate metal pattern using an electron beam evaporation device to form a gate electrode 8;

[0023] 6) Photolithography is performed on the source, drain and gate electrode plate areas, and 800nm ​​to 1um Au or alloy is deposited using electron beam evaporation equipment to thicken the electrodes;

[0024] 7) Using an atomic layer deposition (ALD) device to deposit 40nm-50nm thick SiO2 on the surface of the sample after the source and drain electrodes are made, or firstly using ALD to deposit 10nm-20nm of Al2O3, and then using a plasma enhanced chemical vapor deposition (PECVD) process to deposit 50nm-100nm thick SiN, to complete the production of the passivation layer 9;

[0025] 7) The passivation layer 9 on the source and drain electrodes is removed by RIE etching process to expose the source and drain electrodes, and metal interconnection lines are prepared on the source and drain electrodes to complete the device manufacturing.

[0026] Compared with the prior art, the present invention has the following advantages:

[0027] 1. The present invention adopts AlN single crystal substrate and AlN buffer layer, which effectively avoids high-density defects introduced by lattice mismatch during epitaxy, fundamentally reduces device leakage current, and improves device breakdown voltage;

[0028] 2. The present invention adopts an AlN single crystal substrate and an AlN buffer layer, and adopts a thinner AlN buffer layer to replace the original thicker GaN buffer layer, thereby reducing the overall thermal resistance of the device and improving the heat dissipation capacity of the device;

[0029] 3. The present invention adopts an AlN single crystal substrate and an AlN buffer layer, and adopts a thinner AlN buffer layer instead of a GaN buffer layer. AlN acts as a back barrier, thereby improving the quantum confinement effect in the two-dimensional electron gas channel and enhancing the gate control capability of the device;

[0030] 4. The present invention adopts a newly developed SiO2 passivation layer based on atomic layer deposition technology (ALD), which has better density, smaller stress, and improved passivation quality, greatly improving the phenomenon of increased leakage after etching the original passivation layer and effectively improving the breakdown voltage.

[0031] The present invention has the advantages of low on-resistance, high withstand voltage, high output power, smaller gate leakage and better gate control capability, and can meet the needs of high-frequency and high-power microwave radio frequency applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 Schematic diagram of the traditional GaN HEMT heterojunction structure;

[0033] Figure 2 This is a schematic diagram of the structure of a heterojunction HEMT device based on an AlN buffer layer on an AlN substrate according to the present invention;

[0034] Figure 3 Made for this invention Figure 2 Schematic diagram of the device flow. DETAILED DESCRIPTION

[0035] In order to further illustrate the technical means and effects adopted by the present invention to achieve the predetermined objectives, the heterojunction HEMT device based on the AlN buffer layer on the AlN substrate and the preparation method thereof proposed by the present invention are described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0036] The above and other technical contents, features and effects of the present invention are clearly presented in the following detailed description of the specific implementation modes in conjunction with the accompanying drawings. Through the description of the specific implementation modes, the technical means and effects adopted by the present invention to achieve the predetermined purpose can be more deeply and specifically understood. However, the attached drawings are only for reference and explanation purposes and are not used to limit the technical solutions of the present invention.

[0037] Reference Figure 2 The present invention is based on a heterojunction HEMT device with an AlN buffer layer on an AlN substrate, comprising a substrate 1, a buffer layer 2, a channel layer 3, a barrier layer 4, a cap layer 5, a source electrode 6, a drain electrode 7, a gate electrode 8, and a passivation layer 9. Among them,

[0038] The substrate 1 is an AlN single crystal obtained by physical vapor deposition;

[0039] The buffer layer 2 has a thickness of 60nm-400nm and is located on the upper part of the substrate 1;

[0040] The channel layer 3 is located on the upper part of the buffer layer 2 and is made of GaN or Al with a thickness of 50nm-200nm. x Ga (1-x) N material, and Al x Ga (1-x) The Al component in N is 20-60%;

[0041] The barrier layer 4 is located on the upper part of the buffer layer 2, and its material is one or a combination of AlGaN, InAlN, AlN, AlScN and Si-doped AlGaN;

[0042] The cap layer 5 is made of GaN with a thickness of 2nm-10nm or SiN with a thickness of 3nm-5nm, and is located on the barrier layer 4;

[0043] The source electrode 6 and the drain electrode 7 are both made of a metal stack of Ti / Al / Ni / Au with thicknesses of 22 / 140 / 45 / 55 nm respectively, and are located on both sides of the cap layer 5;

[0044] The gate 8 is a 40 / 400nm T-shaped Ni / Au metal stack, with a gate foot length of 50nm-250nm and a width of 10um-300um, and is located in the middle of the cap layer 5;

[0045] The passivation layer 9 is made of one or a combination of air, SiO2, Al2O3, and SiN, and covers the top surface of the overall structure.

[0046] Reference Figure 3 The present invention provides the following three embodiments for manufacturing a heterojunction HEMT device based on an AlN buffer layer on an AlN substrate:

[0047] Embodiment 1: A GaN MISHEMT with a barrier layer of 5 nm AlN, a channel layer of 200 nm GaN, and a buffer layer of 200 nm AlN is manufactured on an AlN substrate.

[0048] Step A, epitaxial growth of heterostructures.

[0049] A1) epitaxially growing a 200 nm thick AlN buffer layer 2 on the surface of the AlN substrate 1 by MOCVD process, wherein the process conditions are: the reaction chamber temperature is 1150° C., and the flow rates of the reaction gases NH 3 and TMAl are 1100 sccm and 445 sccm, respectively;

[0050] A2) epitaxially growing a 200 nm thick GaN channel layer 3 on the surface of the AlN buffer layer 2 by MOCVD process, wherein the process conditions are: the reaction chamber temperature is 1050° C., and the flow rates of the reaction gases NH 3 and TMGa are 5000 sccm and 500 sccm, respectively;

[0051] A3) using MOCVD process, epitaxially growing a 5 nm thick AlN barrier layer 4 on the surface of the GaN channel layer 3, the process conditions are: the reaction chamber temperature is 1150°C, and the flow rates of the reaction gases NH3 and TMAl are 1100 sccm and 445 sccm respectively;

[0052] A4) A 5 nm thick SiN cap layer 5 is in-situ grown on the barrier layer 4 by MOCVD process to obtain an epitaxial wafer. The process conditions are: the reaction chamber temperature is 900° C., and the flow rates of the reaction gases NH 3 and SiH 4 are 2400 sccm and 100 sccm respectively.

[0053] Step B, making table isolation.

[0054] B1) performing mesa region photolithography on the obtained novel heteroepitaxial wafer comprising an AlN substrate and an AlN buffer layer;

[0055] B2) Using inductively coupled plasma (ICP) etching process, the cap layer and barrier channel layer in the area between the mesas are completely removed until the AlN buffer layer is etched to form mesa isolation. The etching process conditions are: upper electrode power is 300W, lower electrode power is 65W, reaction chamber pressure is 9.5mtorr, temperature is 20°C, and reaction gas flow ratio is BCl3 / Cl2=30 / 30.

[0056] Step C, making source and drain electrodes.

[0057] C1) performing photolithography of source and drain regions on the table;

[0058] C2) Using electron beam evaporation equipment to prepare metal electrodes in the source and drain regions, wherein the metal is a combination of Ti / Al / Ni / Au with thicknesses of 22 / 140 / 45 / 55 nm respectively, and then using RTP-150 equipment to anneal the metal at an annealing temperature of 860° C. for 45 seconds to complete the production of the source electrode 6 and the drain electrode 7.

[0059] Step D: making the gate 8.

[0060] D1) performing electron beam lithography on the surface of the sample obtained in step C to obtain a plurality of gate metal patterns;

[0061] D2) Using electron beam evaporation equipment to deposit T-shaped Ni / Au metal stacks with thicknesses of 40 / 400 nm respectively on the metal pattern, the gate foot length is 50 nm, and the gate width is 300 um, completing the gate 8.

[0062] Step E, thickening the electrode.

[0063] The source, drain and gate electrode plate areas are photolithographically processed, and the electrode is thickened by using an electron beam evaporation device to form an Au or alloy with a thickness of 1 um.

[0064] Step F: preparing a passivation layer 9.

[0065] An atomic layer deposition (ALD) device is used to deposit SiO2 with a thickness of 40 nm on the surface of the sample obtained in step E to complete the production of the passivation layer 9.

[0066] Step G, preparing metal interconnection lines of source and drain electrodes.

[0067] G1) using RIE etching process to remove the passivation layer 9 on the source and drain electrodes to expose the source and drain electrodes, the etching process conditions are: power 250W, pressure 5.5mtorr, gas Ar and CF4 flow rates are 90sccm and 30sccm respectively;

[0068] G2) Deposit metal interconnects on the source and drain electrodes to complete device fabrication.

[0069] Example 2: A barrier layer of 3 nm AlN and a channel layer of 120 nm Al are fabricated on an AlN substrate. 0.27 Ga 0.73 N. Heterostructure HEMT device with 400nm AlN buffer layer.

[0070] Step 1: epitaxially grow a heterostructure.

[0071] 1-1) Under the conditions that the reaction chamber temperature is 1200° C. and the flow rates of the reaction gases NH 3 and TMAl are 1200 sccm and 500 sccm respectively, a 400 nm thick AlN buffer layer 2 is epitaxially grown on the surface of the AlN substrate 1 by using a MOCVD process;

[0072] 1-2) Under the conditions of a reaction chamber temperature of 1010°C and a reaction gas flow rate of 4000sccm, 60sccm and 320sccm of NH3, TMGa and TMAl, a 120nm thick Al layer was grown on the surface of the AlN buffer layer 2 by MOCVD process. 0.27 Ga 0.73 N channel layer 3;

[0073] 1-3) MOCVD was used to deposit Al at a reaction chamber temperature of 1200°C and a flow rate of 1200sccm and 500sccm of the reaction gas NH3 and TMAl, respectively. 0.27 Ga 0.73 An AlN barrier layer 4 with a thickness of 3 nm is epitaxially grown on the surface of the N channel layer 3;

[0074] 1-4) Under the conditions that the reaction chamber temperature is 950° C. and the flow rates of the reaction gases NH 3 and SiH 4 are 2600 sccm and 150 sccm respectively, a 3 nm thick SiN cap layer 5 is epitaxially grown on the barrier layer by MOCVD process to obtain an epitaxial wafer.

[0075] Step 2: Make the countertop isolation.

[0076] 2-1) performing mesa region photolithography on the obtained novel heteroepitaxial wafer comprising an AlN substrate and an AlN buffer layer;

[0077] 2-2) Under the conditions of upper electrode power of 300 W, lower electrode power of 65 W, reaction chamber pressure of 9 mtorr, temperature of 18 ° C, reaction gas flow ratio of BCl3 / Cl2=30 / 30, inductively coupled plasma ICP etching process is used to etch to the AlN buffer layer, and the cap layer and barrier channel layer in the area between the mesas are completely removed to form mesa isolation.

[0078] Step three: make source and drain electrodes.

[0079] 3-1) Perform source and drain region photolithography on the table;

[0080] 3-2) Using electron beam evaporation equipment, Ti / Al / Ni / Au composite metal electrodes with thicknesses of 22 / 140 / 45 / 55 nm were first prepared in the source and drain regions, and then metal annealing was performed at 840°C for 40s using RTP-150 equipment to complete the production of source electrode 6 and drain electrode 7.

[0081] Step 4: making the gate 8.

[0082] 4-1) performing electron beam lithography on the gate region between the source and drain regions to obtain a plurality of gate metal patterns;

[0083] 4-2) Using electron beam evaporation equipment, a T-shaped Ni / Au metal stack with a thickness of 40 / 400 nm is deposited on the metal pattern, the gate foot length is 100 nm, and the gate width is 100 um, thereby completing the gate 8.

[0084] Step five: thicken the electrode.

[0085] The source, drain and gate electrode plate areas are photolithographically processed, and the electrode is thickened by using an electron beam evaporation device to form an Au or alloy with a thickness of 1 um.

[0086] Step six: making a passivation layer 9.

[0087] An atomic layer deposition (ALD) device is used to deposit SiO2 with a thickness of 50 nm on the surface of the sample obtained in step E to complete the production of the passivation layer 9.

[0088] Step seven, under the conditions of power of 250W, pressure of 5mtorr, and flow rates of Ar and CF4 gases of 80sccm and 25sccm respectively, use RIE etching process to remove the passivation layer 9 on the source and drain electrodes to expose the source and drain electrodes, prepare metal interconnects on the source and drain electrodes, and complete device manufacturing.

[0089] Example 3: Fabricating a barrier layer with a thickness of 10 nm Al on an AlN substrate 0.3 Ga 0.7 N, HEMT device with 100nm GaN channel layer and 60nm AlN buffer layer.

[0090] Step 1: epitaxial growth of heterostructures.

[0091] 1.1) using a MOCVD process, setting the reaction chamber temperature to 1100° C., and the flow rates of the reaction gases NH 3 and TMAl to 1000 sccm and 400 sccm, respectively, to epitaxially grow a 20 nm thick AlN buffer layer 2 on the surface of the AlN substrate 1;

[0092] 1.2) using MOCVD process, setting the process conditions of the reaction chamber temperature to 1000°C, the flow rates of the reaction gases NH3 and TMGa to 4000sccm and 450sccm respectively, and epitaxially growing a 100nm thick GaN channel layer 3 on the surface of the AlN buffer layer 2;

[0093] 1.3) Using MOCVD process, the reaction chamber temperature was set to 1020°C, and the flow rates of the reaction gases NH3, TMGa, and TMAl were 5000sccm, 80sccm, and 400sccm, respectively, to grow Al on the surface of the GaN channel layer 3. 0.2 Ga 0.8 N barrier layer 4;

[0094] 1.4) Using MOCVD technology, the reaction chamber temperature was set to 900° C., and the flow rates of the reaction gases NH 3 and TMGa were 4500 sccm and 80 sccm respectively. A 10 nm thick GaN cap layer 5 was epitaxially grown on the barrier layer 4 to obtain an epitaxial wafer.

[0095] Step 2: Make the countertop isolation.

[0096] 2.1) performing mesa region photolithography on the obtained novel heteroepitaxial wafer comprising an AlN substrate and an AlN buffer layer;

[0097] 2.2) Using inductively coupled plasma (ICP) etching process, the upper electrode power is set to 300 W, the lower electrode power is set to 65 W, the reaction chamber pressure is set to 8.5 mtorr, the temperature is set to 15 ° C, and the reaction gas flow ratio is set to BCl3 / Cl2=30 / 30. The cap layer and the barrier channel layer in the area between the mesas are completely removed, and the AlN buffer layer is etched to form a mesa isolation.

[0098] Step 3: Make source and drain electrodes.

[0099] 3.1) Perform source and drain region photolithography on the table;

[0100] 3.2) Electron beam evaporation equipment is used to prepare metal electrodes in the source and drain regions. The metals are a combination of Ti / Al / Ni / Au with thicknesses of 22 / 140 / 45 / 55 nm, respectively. RTP-150 equipment is then used to anneal the metals at a temperature of 830°C for 30 seconds to complete the production of the source electrode 6 and the drain electrode 7.

[0101] Step 4: making gate 8.

[0102] 4.1) Performing gate region photolithography between source and drain regions to obtain multiple gate metal patterns;

[0103] 4.2) Electron beam evaporation equipment is used to deposit T-shaped Ni / Au metal stacks with thicknesses of 40 / 400 nm respectively on the metal pattern, with a gate foot length of 150 nm and a gate width of 10 um, to complete the production of the gate 8.

[0104] Step 5: thicken the electrode.

[0105] The source, drain and gate electrode plate areas are photolithographically processed, and the electrode is thickened by using an electron beam evaporation device to form an Au or alloy with a thickness of 1 um.

[0106] Step 6: making a passivation layer 9.

[0107] 6.1) Using atomic layer deposition (ALD) equipment, 20 nm thick SiO2 is deposited on the surface of the sample after the source and drain electrodes are made;

[0108] 6.2) Plasma enhanced chemical vapor deposition (PECVD) equipment was used to set the reaction chamber temperature to 200°C, the reaction gas SiH4, N2O, and N2 flow rates to 40 sccm, 700 sccm, and 170 sccm, respectively, to deposit 100 nm thick SiN on the surface of Al2O3 to complete the preparation of the passivation layer 9;

[0109] Step 7, using RIE etching process, setting the process conditions of power to 250W, pressure to 4.5mtorr, gas Ar and CF4 flow rates to 70sccm and 20sccm respectively, remove the passivation layer 9 on the source and drain electrodes, expose the source and drain electrodes, prepare metal interconnects on the source and drain electrodes, and complete device manufacturing.

[0110] The above descriptions are only three specific embodiments of the present invention and do not constitute any limitation to the present invention. Obviously, for professionals in this field, after understanding the content and principles of the present invention, it is possible to make various modifications and changes in form and details without deviating from the principles and structures of the present invention. For example, in the epitaxial heterostructure, in addition to the MOCVD process, the MBE epitaxial process can also be used; in addition to AlGaN, AlN, and Si-doped AlGaN, the heterojunction barrier layer material can also be InAlN; in addition to SiO2 and SiN, the passivation layer can also be AlN or Al2O3 as the passivation layer; in addition to the metal types and thickness combinations mentioned in this embodiment, other metal types and metal thickness combinations can also be used to prepare the electrode when making the electrode; the Al component of AlGaN can take any value between 20% and 60%, etc., but these modifications and changes based on the concept of the present invention are still within the scope of protection of the claims of the present invention.

Claims

1. A heterojunction HEMT device based on an AlN buffer layer on an AlN substrate, comprising, from bottom to top, a substrate (1), a buffer layer (2), a channel layer (3), a barrier layer (4), and a cap layer (5), with a drain electrode (6) and a source electrode (7) on both sides of the cap layer (5), a gate electrode (8) in the middle of the cap layer (5), and a passivation layer (9) covering the top of the device, characterized in that: The substrate (1) is an AlN single crystal substrate; The buffer layer (2) is an AlN film with a thickness of 60nm-400nm; The barrier layer (4) is one or a combination of AlGaN, InAlN, AlN, AlScN and Si-doped AlGaN; The passivation layer (9) is air, SiO2, Al2O3, SiN x One or a combination of .

2. The device according to claim 1, characterized in that: The channel layer (3) is made of GaN or Al with a thickness of 50nm-200nm. x Ga (1-x) N, the Al x Ga (1-x) The Al component in N is 20-60%; The cap layer (5) is made of GaN with a thickness of 2nm-10nm or SiN with a thickness of 3nm-5nm; The source electrode (6) and the drain electrode (7) are ohmic contacts, and the electrode metals are a stacked combination of Ti / Al / Ni / Au, with thicknesses of 22 / 140 / 45 / 55 nm respectively.

3. The device according to claim 1, characterized in that The gate electrode (8) is a T-shaped structure that is wide at the top and narrow at the bottom. The gate foot length of the portion in contact with the cap layer (5) is 50nm-250nm and the width is 10um-300um. There is a Schottky contact between the gate electrode and the cap layer (5). The electrode metal is a Ni / Au metal stack with thicknesses of 40 / 400nm respectively.

4. A method for preparing a heterojunction HEMT device based on an AlN buffer layer on an AlN substrate, characterized in that: The steps include: 1) using an AlN single crystal substrate (1) and epitaxially obtaining a 60nm-400nm AlN thin film buffer layer (2) on the surface of the substrate by metal organic compound vapor deposition process MOCVD; 2) epitaxially obtaining a 50nm-200nm thick GaN or AlGaN channel layer (3), a 5nm-20nm thick AlGaN or 1nm-5nm thick AlN barrier layer (4), and a 2nm-10nm thick GaN or 3nm-5nm thick SiN cap layer (5) on the surface of the buffer layer (2) by an MOCVD process; 3) performing photolithography on the mesa region of the epitaxial wafer, using an inductively coupled plasma (ICP) dry etching process to completely remove the cap layer (5), the barrier layer (4), and the channel layer (3) in the region between the mesas, and etching to the AlN buffer layer (2) to form mesa isolation; 4) performing photolithography on the source and drain regions on the table, evaporating Ti / Al / Ni / Au metal stacks in the source and drain regions using electron beam evaporation equipment, and then performing metal annealing to form a source electrode (6) and a drain electrode (7); 5) performing electron beam lithography on the gate region between the source and drain regions to obtain a plurality of gate metal patterns, and depositing a Ni / Au metal stack on the surface of the gate metal pattern using an electron beam evaporation device to form a gate electrode (8); 6) Photolithography is performed on the source, drain and gate electrode plate areas, and 800nm ​​to 1um Au or alloy is deposited using electron beam evaporation equipment to thicken the electrodes; 7) using an atomic layer deposition (ALD) device to deposit 40nm-50nm thick SiO2 on the surface of the sample after the source and drain electrodes are made, or firstly using ALD to deposit 10nm-20nm of Al2O3, and then using a plasma enhanced chemical vapor deposition (PECVD) process to deposit 50nm-100nm thick SiN, to complete the production of the passivation layer (9); 8) Using RIE etching process to remove the passivation layer (9) on the source and drain electrodes to expose the source and drain electrodes, and preparing metal interconnection lines on the source and drain electrodes to complete the device manufacturing.

5. The method according to claim 4, characterized in that The metal organic compound vapor deposition process MOCVD used in step 1) has the following process conditions: The temperature of the reaction chamber is 1100°C to 1200°C; The reaction gases are NH3 and TMAl, and their flow rates are 1000sccm~1200sccm and 400sccm~500sccm respectively.

6. The method according to claim 4, characterized in that The metal organic compound vapor deposition process MOCVD used in step 2) has the following process conditions: When growing GaN material, the temperature of the reaction chamber is 900°C to 1050°C, and the flow rates of the reaction gases NH3 and TMGa are 4000sccm to 5000sccm and 80sccm to 500sccm respectively; When growing AlGaN material, the temperature of the reaction chamber is 1010°C to 1020°C, and the flow rates of the reaction gases NH3, TMGa, and TMAl are 4000sccm to 5000sccm, 60sccm to 80sccm, and 320sccm to 400sccm, respectively; When growing SiN material, the temperature of the reaction chamber is 850-950° C., and the flow rates of NH 3 and SiH 4 in the reaction chamber are 2400 sccm-2600 sccm and 100 sccm-150 sccm, respectively.

7. The method according to claim 4, characterized in that The plasma ICP dry etching process used in step 3) has the following process conditions: The upper electrode power is 300W; The power of the lower electrode is 65W; The pressure of the reaction chamber is 8.5mtorr~9.5mtorr; The reaction chamber temperature is 15°C to 20°C; The reaction gas flow ratio is BCl3 / Cl2=30 / 30.

8. The method according to claim 4, characterized in that The atomic layer deposition ALD used in step 7) has the following process conditions: The cavity temperature is 250℃~275℃; The flow rates of the reaction chamber gases SAM24 and Plasma O2 are 40-50 sccm and 180-200 sccm respectively; SAM24 pulse boost time is 2-4s, flow rate is 500sccm; The radio frequency power of the plasma generator is 1500W to 1800W, and the action time is 5s to 7s.

9. The method according to claim 4, characterized in that: The plasma enhanced chemical vapor deposition (PECVD) used in step 7) has the following process conditions: The cavity temperature is 200℃~220℃; The flow rates of the reaction chamber gases SiH4, N2O, and N2 are 40sccm~50sccm, 700sccm~750sccm, and 170sccm~190sccm, respectively.

10. The method according to claim 4, characterized in that: The RIE etching process used in step 8) has the following process conditions: RIE power is 250W, pressure is 4.5mtorr-5.5mtorr, and flow rates of Ar and CF4 are 70sccm-90sccm and 20sccm-30sccm respectively; The annealing in step 4) is performed at a temperature of 830° C. to 860° C. and for a time of 30 seconds to 45 seconds.

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