Thin film transistor structure with reduced off-state power consumption and method of manufacturing the same

Abstract

The application relates to a thin film transistor structure for reducing off-state power consumption and a preparation method thereof, and relates to the technical field of thin film transistors.The structure comprises a source electrode and a drain electrode arranged on a substrate; an active layer is arranged in a spacing region between the source electrode and the drain electrode; and a drain electrode isolation layer is arranged on the side of the drain electrode in contact with the active layer.The application prepares an insulation layer in the active layer close to one end of the drain electrode, so that the purpose of reducing the drain current of the thin film transistor in the off state is achieved, and the problem of unstable liquid crystal bias in the holding stage of the thin film transistor is solved.

Description

Technical Field

[0001] This application relates to the field of thin-film transistor technology, specifically to a thin-film transistor structure and its fabrication method for reducing off-state power consumption. Background Technology

[0002] TFT (Thin Film Transistor) is a crucial switching and driving element in display panels. A TFT consists of a gate, a source, and a drain. When used as a switching element, the gate is connected to the scan line in the display panel, the source to the data line, and the drain to the pixel electrode. When the pixel electrode is energized, it charges the storage capacitor, allowing the potential across the liquid crystal to be maintained for a period of time. When the gate is de-energized, the drain has a high potential, while the source has a low potential, creating a significant voltage difference. Under this voltage difference, the small number of charge carriers remaining in the channel between the source and drain move, generating leakage current. This leakage current problem causes the pixel electrode potential to become unstable during the holding phase, resulting in unstable voltage applied to the pixel electrode and reduced brightness of the corresponding pixel unit, thus affecting the display's performance.

[0003] In existing technologies, the leakage problem is generally improved by changing the channel material of the TFT or by changing the structure or manufacturing process of the TFT, but the improvement effect of current technologies is not ideal.

[0004] Therefore, to meet the current need for improvement in leakage current, a thin-film transistor structure that reduces power consumption in the off-state is provided. Summary of the Invention

[0005] This application provides a thin-film transistor structure and its fabrication method for reducing off-state power consumption. By fabricating an insulating layer in the active layer near the drain end, the leakage current of the thin-film transistor in the off-state is reduced, thereby solving the problem of unstable liquid crystal bias voltage in the holding phase of the thin-film transistor.

[0006] To achieve the above objectives, this application provides the following solution.

[0007] In a first aspect, this application provides a thin-film transistor structure for reducing off-state power consumption, the structure comprising:

[0008] The source and drain electrodes are disposed on the substrate; wherein,

[0009] An active layer is provided in the spacer region between the source and the drain;

[0010] A drain isolation layer is provided on the side of the drain electrode that contacts the active layer.

[0011] Furthermore, the source, the drain, the active layer, and the drain isolation layer are covered by a gate dielectric.

[0012] The upper surface of the gate dielectric is provided with a gate, and the gate is opposite to the active layer between the source and the drain.

[0013] Furthermore, the thickness and height of the drain isolation layer are configured so that they do not affect the pinch-off point formed between the source and the drain when the thin-film transistor structure is in the on state.

[0014] Specifically, the thickness of the drain isolation layer is lower than the thickness of the source, the drain, and the active layer.

[0015] Preferably, the active layer partially covers the top surfaces of the source and the drain on both sides, or the active layer is located between the source and the drain.

[0016] Secondly, this application provides a thin-film transistor structure for reducing off-state power consumption and a method for fabricating the same, the method comprising the following steps:

[0017] Fabrication of substrates;

[0018] The source and drain electrodes are formed on the substrate;

[0019] A drain isolation layer is formed on the substrate on the drain side;

[0020] An active layer is formed in the spacer region between the source and the drain; wherein...

[0021] The drain isolation layer is located on the side of the drain that contacts the active layer.

[0022] Furthermore, the method also includes the following steps:

[0023] Generate a gate dielectric to cover the source, the drain, the active layer, and the drain isolation layer;

[0024] A gate is disposed on the upper surface of the gate dielectric, and the gate is opposite to the active layer between the source and the drain.

[0025] Preferably, the thickness and height of the drain isolation layer are configured so as not to affect the pinch-off point formed between the source and the drain when the thin-film transistor structure is in the on state.

[0026] Preferably, the thickness of the drain isolation layer is lower than the thickness of the source, the drain, and the active layer.

[0027] Preferably, the active layer partially covers the top surfaces of the source and the drain on both sides, or the active layer is located between the source and the drain.

[0028] The beneficial effects of the technical solution provided in this application include:

[0029] This application reduces the leakage current of the thin-film transistor in the off-state by preparing an insulating layer near the drain end in the active layer, thereby solving the problem of unstable liquid crystal bias voltage in the holding phase of the thin-film transistor. Attached Figure Description

[0030] Terminology Explanation:

[0031] TFT: Thin Film Transistor;

[0032] ITO: Indium Tin Oxide;

[0033] PVD: Physical Vapor Deposition;

[0034] PECVD: Plasma Enhanced Chemical Vapor Deposition.

[0035] ICPCVD: Inductively Coupled Plasma Chemical Vapor Deposition.

[0036] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0037] Figure 1 A schematic diagram of the thin-film transistor structure for reducing off-state power consumption provided in the embodiments of this application when a top-gate structure is selected;

[0038] Figure 2 This is a schematic diagram of the first structure of the active layer when the top gate structure is selected for the thin film transistor structure that reduces off-state power consumption in the embodiments of this application.

[0039] Figure 3This is a schematic diagram of the second structure of the active layer when the top gate structure is selected for the thin film transistor structure that reduces off-state power consumption in the embodiments of this application.

[0040] Figure 4 A schematic diagram of the structure between the substrate, source, and drain when a top-gate structure is selected for the thin-film transistor structure for reducing off-state power consumption provided in the embodiments of this application.

[0041] Figure 5 A schematic diagram of the first structure of the drain isolation layer when the top gate structure is selected for the thin film transistor structure that reduces off-state power consumption in the embodiments of this application.

[0042] Figure 6 This is a schematic diagram of a second structure of the drain isolation layer when the top gate structure is selected for the thin film transistor structure that reduces off-state power consumption in the embodiments of this application.

[0043] Figure 7 A schematic diagram of the structure between the substrate, source, drain, drain isolation layer and active layer when the top gate structure is selected for the thin film transistor structure for reducing off-state power consumption provided in the embodiments of this application.

[0044] Figure 8 A schematic diagram of the structure of the thin-film transistor structure for reducing off-state power consumption provided in the embodiments of this application when the top gate structure is selected and the TFT is in the on state;

[0045] Figure 9 The first schematic diagram of the thin-film transistor structure for reducing off-state power consumption provided in this application embodiment is a top-gate structure and the TFT is in the off state.

[0046] Figure 10 The second schematic diagram of the principle when the top gate structure is selected for the thin film transistor structure for reducing off-state power consumption provided in the embodiments of this application and the TFT is in the off state;

[0047] Figure 11 This is a schematic diagram of the thin-film transistor structure with a bottom gate structure provided in the embodiments of this application for reducing off-state power consumption.

[0048] Figure 12 This is a schematic diagram of the substrate and gate structure when a bottom gate structure is selected for the thin-film transistor structure for reducing off-state power consumption provided in the embodiments of this application.

[0049] Figure 13 A schematic diagram of the substrate, gate, and gate dielectric when a bottom gate structure is selected for the thin-film transistor structure for reducing off-state power consumption provided in the embodiments of this application.

[0050] Figure 14This is a schematic diagram of the substrate, gate, gate dielectric, source, and drain when a bottom gate structure is selected for the thin-film transistor structure for reducing off-state power consumption provided in the embodiments of this application.

[0051] Figure 15 A schematic diagram of the substrate, gate, gate dielectric, source, drain, and drain isolation layer when a bottom gate structure is selected for the thin-film transistor structure for reducing off-state power consumption provided in the embodiments of this application.

[0052] Figure 16 This is a schematic diagram of the thin-film transistor structure for reducing off-state power consumption provided in this application embodiment when a bottom gate structure is selected and the TFT is in the on state.

[0053] In the figure: 1. Substrate; 2. Source; 3. Drain; 4. Active layer; 5. Drain isolation layer; 6. Gate dielectric; 7. Gate electrode. Detailed Implementation

[0054] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0055] The embodiments of this application will be further described in detail below with reference to the accompanying drawings.

[0056] This application provides a thin-film transistor structure and its fabrication method for reducing off-state power consumption. By fabricating an insulating layer near the drain end in the active layer, the leakage current of the thin-film transistor in the off-state is reduced, thereby solving the problem of unstable liquid crystal bias voltage in the holding phase of the thin-film transistor.

[0057] To achieve the aforementioned technical effects, the overall concept of this application is as follows:

[0058] A thin-film transistor structure for reducing off-state power consumption, the structure comprising:

[0059] Source 2 and drain 3 are disposed on substrate 1; wherein,

[0060] An active layer 4 is provided in the spacer region between the source electrode 2 and the drain electrode 3;

[0061] A drain isolation layer 5 is provided on the side of the drain electrode 3 that contacts the active layer 4.

[0062] The embodiments of this application will be further described in detail below with reference to the accompanying drawings.

[0063] In a first aspect, embodiments of this application provide a thin-film transistor structure for reducing off-state power consumption, the structure comprising:

[0064] Source 2 and drain 3 are disposed on substrate 1; wherein,

[0065] An active layer 4 is provided in the spacer region between the source electrode 2 and the drain electrode 3;

[0066] A drain isolation layer 5 is provided on the side of the drain electrode 3 that contacts the active layer 4.

[0067] Furthermore, the source 2, the drain 3, the active layer 4, and the drain isolation layer 5 are covered by the gate dielectric 6;

[0068] The upper surface of the gate dielectric 6 is provided with a gate 7, and the gate 7 is opposite to the active layer 4 between the source 2 and the drain 3.

[0069] In this application, the thin-film transistor structure can be a top-gate structure or a bottom-gate structure. This application uses the top-gate structure as an example for illustration. The structural layout of the bottom-gate structure is similar to that of the top-gate structure.

[0070] Due to technical limitations, the actual deployment of active layer 4 is as shown in the attached diagram of the manual. Figure 2 and Figure 3 As shown, there are two possible scenarios:

[0071] In the first case, the active layer 4 partially covers the top surfaces of the source 2 and the drain 3 on both sides. Of course, in this case, the overlapping part of the active layer 4 with the source 2 and the drain 3 has no effect on the device characteristics.

[0072] The second scenario: The active layer 4 is located between the source 2 and the drain 3.

[0073] It should be noted that the technical solution of this application embodiment mainly involves preparing an insulating layer, namely a drain isolation layer 5, in the active layer 4 near the drain 3, thereby reducing the leakage current of the thin film transistor in the off state and solving the problem of unstable liquid crystal bias voltage in the holding stage of the thin film transistor.

[0074] In this embodiment of the application, before completing the etching of the source 2 and the drain 3 and the formation of the active layer 4, an insulating layer is formed and etched on the side near the drain 3 to form a drain isolation layer 5, and then the thin film transistor is fabricated according to conventional processes.

[0075] When the transistor is in the on state, a pinch-off point will be formed near the drain 3. There will be a huge electric field between the pinch-off point and the drain 3. Under the action of this huge electric field, the charge carriers are rapidly pulled from the channel into the drain 3, forming the on state current. Therefore, the existence of the drain isolation layer 5 will not affect the on state current of the device.

[0076] However, in the off state, since the drain isolation layer 5 is insulating, there will be a large resistance between the source 2 and the drain 3 of the device, resulting in a very small leakage current.

[0077] Therefore, in this embodiment of the application, without affecting the subthreshold and on-state characteristics of the thin-film transistor, the presence of the channel insulating layer effectively reduces the leakage current of the TFT in the off-state, which is beneficial to reducing the power consumption of the display device.

[0078] Furthermore, the thickness and height of the drain isolation layer 5 are configured so that when the thin-film transistor structure is in the on state, it does not affect the pinch-off point formed between the source 2 and the drain 3.

[0079] Specifically, the thickness of the drain isolation layer 5 is lower than the thickness of the source 2, the drain 3, and the active layer 4.

[0080] Preferably, the drain isolation layer 5 is a plate structure or a prism structure.

[0081] Based on the technical solution of the embodiments of this application, taking a top-gate thin-film transistor as an example, the specific implementation process is described as follows, as shown in the accompanying drawings. Figure 1 As shown, the thin-film transistor structure for reducing off-state power consumption provided in this application embodiment includes a substrate 1, a source 2, a drain 3, an active layer 4, a drain isolation layer 5, a gate dielectric 6, and a gate 7.

[0082] Regarding the selection of substrate 1, substrate 1 serves as the supporting material for the entire device. For display panels, substrate 1 is generally a glass substrate, but it can also be a flexible substrate, such as PET. After substrate 1 is prepared, it needs to be cleaned before use.

[0083] Secondly, as shown in the attached diagram of the instruction manual. Figure 4 As shown, source 2 and drain 3 are generally metal electrodes, such as single-element metals like Mo and Al or Ti / Au stacked metals, or other materials with conductivity, such as ITO, AZO, graphene, etc. They are prepared by PVD and patterned by dry etching or wet etching.

[0084] A metal layer is generated on the substrate 1 to be cleaned and then patterned by photolithography and etching to form the source 2 and drain 3 of the thin film transistor.

[0085] Crucially, the drain isolation layer 5 is an insulating material or an undoped crystalline material with very weak conductivity. It is formed by photolithography and etching on the patterned substrate of source 2 and drain 3, as shown in the attached diagram of the specification. Figure 5 or Figure 6 The structure shown;

[0086] Of course, it should be noted that the height of the drain isolation layer 5 is not required in the direction away from the channel or the gate 7, but it is required not to be higher than the drain 3 in the direction close to the gate 7, and preferably slightly lower than the drain 3. Figure 5 and Figure 6 In the corresponding structural forms, the preferred option can be selected when necessary. Figure 6 The corresponding structure has virtually no impact on other electrical properties of the device;

[0087] in, Figure 6 The structure corresponds to performance superior to Figure 5 The performance corresponding to the structure, Figure 6 The structure has virtually no impact on other electrical properties of the device. Figure 5 It may affect the subthreshold characteristics of the device, but it has no effect on the on-state characteristics and does not affect its use as a switching transistor.

[0088] Figure 6 The structure is more complex to prepare. Figure 5 The process of oxidizing the drain side is relatively simple.

[0089] Specifically, the drain isolation layer 5 is located between the source 2 and the drain 3, close to the drain 3;

[0090] Ideally, the length of the drain isolation layer 5 at the channel break point should be 0 in the left and right directions, while it should not be 0 in other places near the drain 3 in the active layer 4. However, this is difficult to control in the actual fabrication process.

[0091] The drain isolation layer 5 can be formed through the following methods:

[0092] ① This is achieved through a method similar to the formation of sidewalls in MOS technology, such as... Figure 6 As shown, the difference is that it is formed only on the drain electrode 3 side;

[0093] It should be noted that the sidewall process utilizes the anisotropic characteristics of dry etching, eliminating the need for a mask. Dry etching is performed after Dep, and sidewalls are created at the step locations.

[0094] For specific implementation methods, please refer to the sidewall process in the current MOS process.

[0095] ② By covering other areas with a mask such as photoresist, the metal of the drain electrode 3 near the channel is oxidized, making its surface a non-conductive material, i.e. Figure 5 The structure shown.

[0096] ③ After the active region is formed, the portion near the drain electrode 3 is passivated to reduce its conductivity;

[0097] It should be noted that passivation refers to the process of oxidizing a metal with a strong oxidizing agent or by electrochemical methods, so that the surface becomes inactive, i.e., passivation, which is to transform the metal surface into a state that is not easily oxidized.

[0098] ④ The source electrode 2, drain electrode 3 and drain isolation layer 5 are prepared using high-resistivity materials. The resistance of the source electrode 2 and drain electrode 3 is reduced by hydrogen doping, ion implantation and annealing, thereby forming the source electrode 2, drain electrode 3 and drain isolation layer 5.

[0099] The specific operation method can be to use existing high-resistivity materials and existing doping techniques and other related technologies and processes.

[0100] It should be noted that the drain isolation layer 5 needs to be particularly thin in the channel direction to avoid affecting the characteristics of the device in the on state.

[0101] Regarding the active layer 4, also known as the active region, it is a semiconductor material. In display devices, it can be amorphous silicon, amorphous oxide, polycrystalline silicon, etc.

[0102] As shown in the attached diagram of the instruction manual. Figure 7 As shown, based on the formation of the drain isolation layer 5, semiconductor materials are prepared by physical deposition, sputtering, spraying and other methods, and active layer 4 is formed by photolithography and etching.

[0103] Finally, the gate dielectric 6 and the gate 7 are fabricated. The gate dielectric 6 is an insulating material, generally silicon dioxide, silicon nitride, etc., and is fabricated by PECVD, ICPCVD, etc.

[0104] Gate 7, i.e., the gate electrode, is fabricated similarly to the source 2 and drain 3, except that the mask used is different. After the gate dielectric 6 and gate 7 are formed, as shown... Figure 1 As shown, the fabrication of the device described in this proposal is now essentially complete.

[0105] Based on the accompanying drawings in the instruction manual Figures 8-9 The technical solutions of the embodiments of this application are explained in principle as follows:

[0106] When the TFT is in the on state, the active layer 4 forms a channel near the gate 7. When the source-drain voltage is sufficiently large, V G -V T <V DSAt this time, a pinch-off point P will be formed, such as Figure 8 As shown, the carrier concentration between the pinch-off point P and the drain 3 is approximately 0, and the electric field is extremely large. Under the action of this strong electric field, the carriers are pulled from the pinch-off point P to the drain 3, thus forming a saturated source-drain current.

[0107] At this point, the thickness of the effective channel decreases sequentially from source 2 to drain 3 until it becomes zero, as shown below. Figure 8 As shown, in the technical proposal of this application embodiment, since the drain isolation layer 5 is very thin in the channel direction, it is generally smaller than the distance from the pinch-off point to the drain 3, so it will not affect the pinch-off point, that is, it will not affect the on-state characteristics of the device.

[0108] When the TFT is in the off state, as shown in the attached diagram in the manual. Figure 9 As shown, due to the presence of the drain isolation layer 5, the resistance of the drain isolation layer 5 is very large. Therefore, the voltage drops mainly across the drain isolation layer 5. Thus, even if there is a large voltage difference across the drain 3 at this time, the leakage current will be greatly reduced compared to the absence of the drain isolation layer 5.

[0109] In the off state, the gate voltage is zero, and carriers do not accumulate to form a channel under the influence of the gate bias. Therefore, it is reasonable to assume that the carriers are uniformly distributed in the active layer 4.

[0110]

[0111] in, ρ The resistivity of the material l The length of the channel. s Given the area perpendicular to the current direction, it is clear that this technical proposal... s The current is much smaller than that without the drain isolation layer 5, so the off-state current of the transistor shown in this technical proposal will be greatly reduced, that is, the off-state power consumption will be greatly reduced.

[0112] To more clearly describe the technical solutions of the embodiments of this application, a bottom gate structure based on the technical solutions of the embodiments of this application is provided, as shown in the accompanying drawings. Figure 11 As shown;

[0113] For the bottom gate structure, the drain isolation layer 5 can be fabricated using the methods ②③④ mentioned above.

[0114] The thin-film transistor structure for reducing off-state power consumption based on the embodiments of this application can be extended to a common MOS transistor used as a switch.

[0115] Secondly, based on the same inventive concept as the first aspect, embodiments of this application provide a method for fabricating a thin-film transistor structure that reduces off-state power consumption, the method comprising the following steps:

[0116] S1. Fabricate substrate 1;

[0117] S2. A source electrode 2 and a drain electrode 3 are formed on the substrate 1;

[0118] S3. A drain isolation layer 5 is formed on the substrate 1 on one side of the drain electrode 3;

[0119] S4. An active layer 4 is formed in the spacer region between the source electrode 2 and the drain electrode 3; wherein...

[0120] The drain isolation layer 5 is located on the side of the drain 3 that is in contact with the active layer 4.

[0121] Due to technical limitations, the actual deployment of active layer 4 is as shown in the attached diagram of the manual. Figure 2 and Figure 3 As shown, there are two possible scenarios:

[0122] In the first case, the active layer 4 partially covers the top surfaces of the source 2 and the drain 3 on both sides. Of course, in this case, the overlapping part of the active layer 4 with the source 2 and the drain 3 has no effect on the device characteristics.

[0123] The second scenario: The active layer 4 is located between the source 2 and the drain 3.

[0124] Furthermore, the method also includes the following steps:

[0125] S5. Generate a pair of gate dielectrics 6 to cover the source 2, the drain 3, the active layer 4, and the drain isolation layer 5;

[0126] S6. A gate 7 is disposed on the upper surface of the gate dielectric 6, and the gate 7 is opposite to the active layer 4 between the source 2 and the drain 3.

[0127] It should be noted that the technical solution of this application embodiment mainly involves preparing an insulating layer, namely a drain isolation layer 5, in the active layer 4 near the drain 3, thereby reducing the leakage current of the thin film transistor in the off state and solving the problem of unstable liquid crystal bias voltage in the holding stage of the thin film transistor.

[0128] In this embodiment of the application, before completing the etching of the source 2 and the drain 3 and the formation of the active layer 4, an insulating layer is formed and etched on the side near the drain 3 to form a drain isolation layer 5, and then the thin film transistor is fabricated according to conventional processes.

[0129] When the transistor is in the on state, a pinch-off point will be formed near the drain 3. There will be a huge electric field between the pinch-off point and the drain 3. Under the action of this huge electric field, the charge carriers are rapidly pulled from the channel into the drain 3, forming the on state current. Therefore, the existence of the drain isolation layer 5 will not affect the on state current of the device.

[0130] However, in the off state, since the drain isolation layer 5 is insulating, there will be a large resistance between the source 2 and the drain 3 of the device, resulting in a very small leakage current.

[0131] Therefore, in this embodiment of the application, without affecting the subthreshold and on-state characteristics of the thin-film transistor, the presence of the channel insulating layer effectively reduces the leakage current of the TFT in the off-state, which is beneficial to reducing the power consumption of the display device.

[0132] Preferably, the thickness and height of the drain isolation layer 5 are configured so as not to affect the pinch-off point formed between the source 2 and the drain 3 when the thin-film transistor structure is in the on state.

[0133] Preferably, the thickness of the drain isolation layer 5 is lower than the thickness of the source 2, the drain 3 and the active layer 4.

[0134] Preferably, the drain isolation layer 5 is a plate structure or a prism structure.

[0135] Based on the technical solution of the embodiments of this application, taking a top-gate thin-film transistor as an example, the specific implementation process is described as follows, as shown in the accompanying drawings. Figure 1 As shown, the thin-film transistor structure for reducing off-state power consumption provided in this application embodiment includes a substrate 1, a source 2, a drain 3, an active layer 4, a drain isolation layer 5, a gate dielectric 6, and a gate 7.

[0136] Regarding the selection of substrate 1, substrate 1 serves as the supporting material for the entire device. For display panels, substrate 1 is generally a glass substrate, but it can also be a flexible substrate, such as PET. After substrate 1 is prepared, it needs to be cleaned before use.

[0137] Secondly, as shown in the attached diagram of the instruction manual. Figure 4 As shown, source 2 and drain 3 are generally metal electrodes, such as single-element metals like Mo and Al or Ti / Au stacked metals, or other materials with conductivity, such as ITO, AZO, graphene, etc. They are prepared by PVD and patterned by dry etching or wet etching.

[0138] A metal layer is generated on the substrate 1 to be cleaned and then patterned by photolithography and etching to form the source 2 and drain 3 of the thin film transistor.

[0139] Crucially, the drain isolation layer 5 is an insulating material or an undoped crystalline material with very weak conductivity. It is formed by photolithography and etching on the patterned substrate of source 2 and drain 3, as shown in the attached diagram of the specification. Figure 5 or Figure 6 The structure shown;

[0140] Of course, it should be noted that the height of the drain isolation layer 5 is not required in the direction away from the channel or the gate 7, but it is required not to be higher than the drain 3 in the direction close to the gate 7, and preferably slightly lower than the drain 3. Figure 5 and Figure 6 In the corresponding structural forms, the preferred option can be selected when necessary. Figure 6 The corresponding structure has virtually no impact on other electrical properties of the device;

[0141] in, Figure 6 The structure corresponds to performance superior to Figure 5 The performance corresponding to the structure, Figure 6 The structure has virtually no impact on other electrical properties of the device. Figure 5 It may affect the subthreshold characteristics of the device, but it has no effect on the on-state characteristics and does not affect its use as a switching transistor.

[0142] Figure 6 The structure is more complex to prepare. Figure 5 The process of oxidizing the drain side is relatively simple.

[0143] Specifically, the drain isolation layer 5 is located between the source 2 and the drain 3, close to the drain 3;

[0144] Ideally, the length of the drain isolation layer 5 at the channel break point should be 0 in the left and right directions, while it should not be 0 in other places near the drain 3 in the active layer 4. However, this is difficult to control in the actual fabrication process.

[0145] The drain isolation layer 5 can be formed through the following methods:

[0146] ① This is achieved through a method similar to the formation of sidewalls in MOS technology, such as... Figure 6 As shown, the difference is that it is formed only on the drain electrode 3 side;

[0147] It should be noted that the sidewall process utilizes the anisotropic characteristics of dry etching, eliminating the need for a mask. Dry etching is performed after Dep, and sidewalls are created at the step locations.

[0148] For specific implementation methods, please refer to the sidewall process in the current MOS process.

[0149] ② By covering other areas with a mask such as photoresist, the metal of the drain electrode 3 near the channel is oxidized, making its surface a non-conductive material, i.e. Figure 5 The structure shown.

[0150] ③ After the active region is formed, the portion near the drain electrode 3 is passivated to reduce its conductivity;

[0151] It should be noted that passivation refers to the process of oxidizing a metal with a strong oxidizing agent or by electrochemical methods, so that the surface becomes inactive, i.e., passivation, which is to transform the metal surface into a state that is not easily oxidized.

[0152] ④ The source electrode 2, drain electrode 3 and drain isolation layer 5 are prepared using high-resistivity materials. The resistance of the source electrode 2 and drain electrode 3 is reduced by hydrogen doping, ion implantation and annealing, thereby forming the source electrode 2, drain electrode 3 and drain isolation layer 5.

[0153] The specific operation method can be to use existing high-resistivity materials and existing doping techniques and other related technologies and processes.

[0154] It should be noted that the drain isolation layer 5 needs to be particularly thin in the channel direction to avoid affecting the characteristics of the device in the on state.

[0155] Regarding the active layer 4, also known as the active region, it is a semiconductor material. In display devices, it can be amorphous silicon, amorphous oxide, polycrystalline silicon, etc.

[0156] As shown in the attached diagram of the instruction manual. Figure 7 As shown, based on the formation of the drain isolation layer 5, semiconductor materials are prepared by physical deposition, sputtering, spraying and other methods, and active layer 4 is formed by photolithography and etching.

[0157] Finally, the gate dielectric 6 and the gate 7 are fabricated. The gate dielectric 6 is an insulating material, generally silicon dioxide, silicon nitride, etc., and is fabricated by PECVD, ICPCVD, etc.

[0158] Gate 7, i.e., the gate electrode, is fabricated similarly to the source 2 and drain 3, except that the mask used is different. After the gate dielectric 6 and gate 7 are formed, as shown... Figure 1 As shown, the fabrication of the device described in this proposal is now essentially complete.

[0159] Based on the accompanying drawings in the instruction manual Figures 8-9 The technical solutions of the embodiments of this application are explained in principle as follows:

[0160] When the TFT is in the on state, the active layer 4 forms a channel near the gate 7. When the source-drain voltage is sufficiently large, V G -V T <V DSAt this time, a pinch-off point P will be formed, such as Figure 8 As shown, the carrier concentration between the pinch-off point P and the drain 3 is approximately 0, and the electric field is extremely large. Under the action of this strong electric field, the carriers are pulled from the pinch-off point P to the drain 3, thus forming a saturated source-drain current.

[0161] At this point, the thickness of the effective channel decreases sequentially from source 2 to drain 3 until it becomes zero, as shown below. Figure 8 As shown, in the technical proposal of this application embodiment, since the drain isolation layer 5 is very thin in the channel direction, it is generally smaller than the distance from the pinch-off point to the drain 3, so it will not affect the pinch-off point, that is, it will not affect the on-state characteristics of the device.

[0162] When the TFT is in the off state, as shown in the attached diagram in the manual. Figure 9 As shown, due to the presence of the drain isolation layer 5, the resistance of the drain isolation layer 5 is very large. Therefore, the voltage drops mainly across the drain isolation layer 5. Thus, even if there is a large voltage difference across the drain 3 at this time, the leakage current will be greatly reduced compared to the absence of the drain isolation layer 5.

[0163] In the off state, the gate voltage is zero, and carriers do not accumulate to form a channel under the influence of the gate bias. Therefore, it is reasonable to assume that the carriers are uniformly distributed in the active layer 4.

[0164]

[0165] in, ρ The resistivity of the material, l The length of the channel. s Given the area perpendicular to the current direction, it is clear that this technical proposal... s The current is much smaller than that without the drain isolation layer 5, so the off-state current of the transistor shown in this technical proposal will be greatly reduced, that is, the off-state power consumption will be greatly reduced.

[0166] It should be noted that the preparation method provided in this application, its corresponding technical problems, technical means and technical effects are similar in principle to the thin-film transistor structure for reducing off-state power consumption mentioned in the first aspect.

[0167] Thirdly, as shown in the attached diagram of the instruction manual. Figures 11-16 As shown, based on the same inventive concept as the first and second aspects, this application provides a method for fabricating a thin-film transistor structure with reduced off-state power consumption. This method is used to fabricate a bottom-gate structure thin-film transistor with reduced off-state power consumption, and includes the following steps:

[0168] S1. Fabricate substrate 1;

[0169] S2. A gate 7 is formed on the substrate 1;

[0170] S3. Form a gate dielectric 6 on the substrate 1 and the gate 7;

[0171] S4. Form source 2 and drain 3 on gate dielectric 6;

[0172] S5. A drain isolation layer 5 is formed on the gate dielectric 6 on one side of the drain electrode 3;

[0173] S6. An active layer 4 is formed in the spacer region between the source electrode 2 and the drain electrode 3; wherein...

[0174] The drain isolation layer 5 is located on the side of the drain 3 that is in contact with the active layer 4.

[0175] In this embodiment, when the thin-film transistor structure for reducing off-state power consumption adopts a bottom-gate structure, the final fabricated structural schematic diagram is shown in the attached figure of the specification. Figure 11 As shown;

[0176] The structural diagrams corresponding to the different stages of its preparation are shown in the attached figures of the instruction manual. Figures 12 to 15 as well as Figure 11 As shown;

[0177] The attached diagram of the instruction manual Figure 16 The schematic diagram of the thin-film transistor structure when the bottom gate structure is selected to reduce power consumption in the off state and the TFT is in the on state is explained in the embodiments corresponding to the first and second aspects, and will not be repeated here.

[0178] Due to technical limitations, the actual deployment of active layer 4 can be compared to the diagrams in the instruction manual. Figure 2 and Figure 3 As shown, with Figure 2 , Figure 3 The difference is that the bottom of the source 2 and the drain 3 is not the substrate 1 but the gate dielectric 6, which also has the following two situations:

[0179] In the first case, the active layer 4 partially covers the top surfaces of the source 2 and the drain 3 on both sides. Of course, in this case, the overlapping part of the active layer 4 with the source 2 and the drain 3 has no effect on the device characteristics.

[0180] The second scenario: The active layer 4 is located between the source 2 and the drain 3.

[0181] Preferably, the thickness and height of the drain isolation layer 5 are configured so as not to affect the pinch-off point formed between the source 2 and the drain 3 when the thin-film transistor structure is in the on state.

[0182] Preferably, the thickness of the drain isolation layer 5 is lower than the thickness of the source 2, the drain 3 and the active layer 4.

[0183] Preferably, the drain isolation layer 5 is a plate structure or a prism structure.

[0184] Based on the technical solution of the embodiments of this application, taking a bottom-gate thin-film transistor as an example, the specific implementation process is described as follows, as shown in the accompanying drawings. Figure 11 As shown, the thin-film transistor structure for reducing off-state power consumption provided in this application embodiment includes a substrate 1, a source 2, a drain 3, an active layer 4, a drain isolation layer 5, a gate dielectric 6, and a gate 7.

[0185] Regarding the selection of substrate 1, substrate 1 serves as the supporting material for the entire device. For display panels, substrate 1 is generally a glass substrate, but it can also be a flexible substrate, such as PET. After substrate 1 is prepared, it needs to be cleaned before use.

[0186] Next, a gate 7 and a gate dielectric 6 are formed on the substrate 1;

[0187] Furthermore, source 2 and drain 3 are generally made of metal electrodes, such as single-element metals like Mo and Al or Ti / Au multilayer metals, or other materials with conductivity, such as ITO, AZO, graphene, etc. They are prepared by PVD and patterned by dry etching or wet etching.

[0188] A metal layer is generated on the cleaned gate dielectric 6, and then patterned by photolithography and etching to form the source 2 and drain 3 of the thin film transistor.

[0189] Crucially, the drain isolation layer 5 is an insulating material or an undoped crystalline material with very weak conductivity. It is formed by photolithography and etching on the patterned substrate of source 2 and drain 3. Specifically, the structural relationship between source 2, drain 3, and drain isolation layer 5 can be compared to the figures in the specification. Figure 5 or Figure 6 The structure shown is such that, of course, the area below the source 2 and drain 3 is not the substrate 1, but the gate dielectric 6.

[0190] Specifically, the drain isolation layer 5 is located between the source 2 and the drain 3, close to the drain 3;

[0191] Ideally, the length of the drain isolation layer 5 at the channel break point should be 0 in the left and right directions, while it should not be 0 in other places near the drain 3 in the active layer 4. However, this is difficult to control in the actual fabrication process.

[0192] Specifically, for the bottom gate structure, the drain isolation layer 5 can be fabricated using the following methods:

[0193] ② By covering other areas with a mask such as photoresist, the metal of the drain electrode 3 near the channel is oxidized, making its surface a non-conductive material, thus forming a structure similar to the top gate structure. Figure 5 The structure shown;

[0194] ③ After the active region is formed, the portion near the drain electrode 3 is passivated to reduce its conductivity;

[0195] ④ The source electrode 2, drain electrode 3 and drain isolation layer 5 are prepared using high-resistivity materials. The resistance of the source electrode 2 and drain electrode 3 is reduced by hydrogen doping, annealing and other methods, thereby forming the source electrode 2, drain electrode 3 and drain isolation layer 5.

[0196] It should be noted that the drain isolation layer 5 needs to be particularly thin in the channel direction so as not to affect the characteristics of the device in the on state.

[0197] Regarding the active layer 4, also known as the active region, it is a semiconductor material. In display devices, it can be amorphous silicon, amorphous oxide, polycrystalline silicon, etc.

[0198] Based on the formation of the drain isolation layer 5, semiconductor materials are prepared by physical deposition, sputtering, spraying and other methods, and active layer 4 is formed by photolithography and etching.

[0199] It should be noted that the gate dielectric 6 and the gate 7 are fabricated using methods such as PECVD and ICPCVD. The gate dielectric 6 is an insulating material, generally silicon dioxide or silicon nitride.

[0200] Gate 7, i.e., the gate electrode, is fabricated similarly to the source 2 and drain 3, except that the mask used is different. After the gate dielectric 6 and gate 7 are formed, as shown... Figure 11 As shown, the fabrication of the device described in this proposal is now essentially complete.

[0201] Furthermore, the thin-film transistor structure for reducing off-state power consumption based on the embodiments of this application can be extended to a conventional MOS transistor used as a switch.

[0202] It should be noted that the preparation method provided in this application, in terms of its technical problems, technical means and technical effects, is similar to the preparation method mentioned in the second aspect in principle. The thin-film transistor structure with reduced off-state power consumption prepared by it, in terms of its technical problems, technical means and technical effects, is similar to the thin-film transistor structure with reduced off-state power consumption mentioned in the first aspect in principle.

[0203] It should be noted that in this application, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

[0204] The above are merely specific embodiments of this application, enabling those skilled in the art to understand or implement this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A thin-film transistor structure for reducing off-state power consumption, characterized in that, The structure includes: A source (2) and a drain (3) are disposed on a substrate (1); wherein, An active layer (4) is provided in the spacer region between the source (2) and the drain (3); A drain isolation layer (5) is provided on the side of the drain electrode (3) near the active layer (4), and the drain electrode (3) is in contact with the drain isolation layer (5); The thickness and height of the drain isolation layer (5) are configured so that when the thin-film transistor structure is in the open state, it does not affect the pinch-off point formed between the source (2) and the drain (3).

2. The thin-film transistor structure for reducing off-state power consumption as described in claim 1, characterized in that: The source (2), the drain (3), the active layer (4), and the drain isolation layer (5) are covered by the gate dielectric (6); The upper surface of the gate dielectric (6) is provided with a gate (7), and the gate (7) is opposite to the active layer (4) between the source (2) and the drain (3).

3. The thin-film transistor structure for reducing off-state power consumption as described in claim 1, characterized in that: The thickness of the drain isolation layer (5) is lower than the thickness of the source (2), the drain (3) and the active layer (4).

4. The thin-film transistor structure for reducing off-state power consumption as described in claim 1, characterized in that: The active layer (4) partially covers the top surfaces of the source electrode (2) and the drain electrode (3) on both sides, or the active layer (4) is located between the source electrode (2) and the drain electrode (3).

5. A thin-film transistor structure for reducing off-state power consumption and its fabrication method, characterized in that, The method includes the following steps: Fabrication of substrate (1); A source electrode (2) and a drain electrode (3) are formed on the substrate (1); A drain isolation layer (5) is formed on the substrate (1) on the drain (3) side; An active layer (4) is formed in the spacer region between the source (2) and the drain (3); wherein, The drain isolation layer (5) is located on the side of the drain (3) close to the active layer (4), and the drain (3) is in contact with the drain isolation layer (5); The thickness and height of the drain isolation layer (5) are configured so that when the thin-film transistor structure is in the open state, it does not affect the pinch-off point formed between the source (2) and the drain (3).

6. The thin-film transistor structure and its fabrication method for reducing off-state power consumption as described in claim 5, characterized in that, The method further includes the following steps: Generate a gate dielectric (6) to cover the source (2), the drain (3), the active layer (4) and the drain isolation layer (5); A gate (7) is disposed on the upper surface of the gate dielectric (6), and the gate (7) is opposite to the active layer (4) between the source (2) and the drain (3).

7. The thin-film transistor structure and its fabrication method for reducing off-state power consumption as described in claim 5, characterized in that: The thickness of the drain isolation layer (5) is lower than the thickness of the source (2), the drain (3) and the active layer (4).

8. The thin-film transistor structure and its fabrication method for reducing off-state power consumption as described in claim 5, characterized in that: The active layer (4) partially covers the top surfaces of the source electrode (2) and the drain electrode (3) on both sides, or the active layer (4) is located between the source electrode (2) and the drain electrode (3).

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