Display panel and manufacturing method thereof

Abstract

The present application provides a display panel and a method for manufacturing the same. The display panel includes an array substrate and a plurality of pixel unit groups, each pixel unit group consisting of a first pixel unit and a second pixel unit, and the first pixel unit and the second pixel unit are staggered in position as orthographic projections on the array substrate. The first pixel unit includes a first light-emitting unit layer having a first light-emitting color; the second pixel unit includes a second light-emitting unit layer having a second light-emitting color and a third light-emitting unit layer having a third light-emitting color, and the second light-emitting unit layer and the third light-emitting unit layer are sequentially stacked in a direction away from the array substrate. In the display panel provided by the present application, since each pixel unit group consists of a first pixel unit and a second pixel unit, and the second pixel unit includes two stacked light-emitting unit layers having different light-emitting colors, it is possible to achieve full-color display while improving resolution, reducing costs, and enhancing display quality.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a method for preparing the same. Background Art

[0002] Micro-LED (Micro Light-Emitting Diode) displays offer ultra-high pixel density and self-luminescence. Compared to OLED and LCD displays, Micro-LED displays are easier to accurately adjust color, have a longer light lifespan, and offer higher brightness. They are also thinner, lighter, and more energy-efficient, offering broad market application prospects.

[0003] In related technologies, full-color Micro-LED displays are achieved by adding a quantum dot film layer to the display panel and using a blue LED chip to excite the quantum dots within the film, thereby producing colored light. This full-color approach requires a thicker quantum dot film layer to ensure efficient color conversion and light extraction. However, a thicker quantum dot film layer restricts the size of the display pixels, making it difficult to increase the resolution of the display panel and increasing manufacturing costs. It also easily causes crosstalk between adjacent display pixels, a problem that urgently needs to be addressed. Summary of the Invention

[0004] The present application provides a display panel and a method for manufacturing the same, which can effectively improve the problems of existing Micro-LED display panels such as difficulty in improving resolution, high manufacturing cost, and light crosstalk.

[0005] On the one hand, the present application provides a display panel, which includes: an array substrate; a plurality of pixel unit groups, which are arranged on one side of the array substrate, each of the pixel unit groups consisting of a first pixel unit and a second pixel unit, and the first pixel unit and the second pixel unit are staggered in their orthographic projections on the array substrate, wherein the first pixel unit includes a first light-emitting unit layer having a first light-emitting color; the second pixel unit includes a second light-emitting unit layer having a second light-emitting color and a third light-emitting unit layer having a third light-emitting color, and the second light-emitting unit layer and the third light-emitting unit layer are stacked sequentially in a direction away from the array substrate.

[0006] Optionally, the first luminous color is red; the second luminous color is one of blue and green; and the third luminous color is the other of blue and green.

[0007] Optionally, the first pixel unit includes a first semiconductor layer of a first doping type, a first light-emitting unit layer, and a second semiconductor layer of a second doping type, which are sequentially stacked in a direction away from the array substrate; the second pixel unit includes a third semiconductor layer of a second doping type, a second light-emitting unit layer, a fourth semiconductor layer of a first doping type, the third light-emitting unit layer, and a fifth semiconductor layer of a second doping type, which are sequentially stacked in a direction away from the array substrate; wherein the first doping type is one of N-type or P-type, and the second doping type is the other of N-type or P-type.

[0008] Optionally, the first pixel unit also includes: a first electrode, in contact with the first semiconductor layer of the first doping type; a second electrode, in contact with the second semiconductor layer of the second doping type; the second pixel unit also includes: a third electrode, in contact with the third semiconductor layer of the second doping type; a fourth electrode, in contact with the fourth semiconductor layer of the first doping type; a fifth electrode, in contact with the fifth semiconductor layer of the second doping type; wherein the first electrode and the fourth electrode are of the same electrode type, both are one type of anode or cathode, and the first electrode and the fourth electrode are electrically connected; wherein the second electrode, the third electrode and the fifth electrode are of the same electrode type, both are another type of anode or cathode, and the second electrode, the third electrode and the fifth electrode are insulated.

[0009] Optionally, the fourth semiconductor layer of the first doping type includes a first portion not covered by the third light-emitting unit layer, and the fourth electrode is in contact with the first portion.

[0010] Optionally, the array substrate includes: a plurality of pad groups, each pad group corresponding to one of the pixel unit groups, wherein the pad groups include: a first pad, a second pad, a third pad and a fourth pad, the first pad being electrically connected to the first electrode and the fourth electrode, respectively; the second pad being electrically connected to the second electrode, the third pad being electrically connected to the third electrode, and the fourth pad being electrically connected to the fifth electrode.

[0011] Optionally, the first electrode is arranged on the side of the first semiconductor layer of the first doping type facing the array substrate, and the first electrode is in contact and electrically connected with the first pad; the third electrode is arranged on the side of the third semiconductor layer of the second doping type facing the array substrate, and the third electrode is in contact and electrically connected with the third pad.

[0012] Optionally, the surface of the second semiconductor layer of the second doping type facing away from the array substrate is at a first distance from the array substrate; the surface of the fifth semiconductor layer of the second doping type facing away from the array substrate is at a second distance from the array substrate; wherein the second distance is greater than the first distance.

[0013] Optionally, the first electrode is arranged on the side of the first semiconductor layer of the first doping type facing the array substrate, and the first electrode is electrically connected to the first pad; the third electrode is arranged on the side of the third semiconductor layer of the second doping type facing the array substrate, wherein the display panel also includes a plurality of insulating protrusions, the insulating protrusions are arranged between the third electrode and the array substrate, and the third electrode is electrically connected to the third pad through via holes in the insulating protrusions.

[0014] Optionally, the distance between the surface of the insulating protrusion facing away from the array substrate and the array substrate is a third distance; the distance between the surface of the second semiconductor layer of the second doping type facing away from the array substrate and the array substrate is a fourth distance; wherein the third distance is equal to the fourth distance.

[0015] In another aspect, the present application provides a method for manufacturing a display panel, comprising the following steps:

[0016] A first pixel composite layer is formed on one side of a first substrate, the first pixel composite layer comprising a second semiconductor layer of a second doping type, a first light-emitting unit layer, and a first semiconductor layer of a first doping type stacked in sequence; a second pixel composite layer is formed on one side of a second substrate, the second pixel composite layer comprising a fifth semiconductor layer of a second doping type, a third light-emitting unit layer, a fourth semiconductor layer of a first doping type, a second light-emitting unit layer, and a third semiconductor layer of a second doping type stacked in sequence;

[0017] Bonding the side of the first pixel composite layer facing away from the first substrate to one side of an array substrate, and removing the first substrate;

[0018] Bonding the side of the second pixel composite layer facing away from the second substrate to one side of the array substrate, and removing the second substrate;

[0019] Before bonding the side of the first pixel composite layer facing away from the first substrate to a side of an array substrate and removing the first substrate, the first pixel composite layer is patterned; before bonding the side of the second pixel composite layer facing away from the second substrate to a side of the array substrate and removing the second substrate, the second pixel composite layer is patterned.

[0020] Or, after bonding the side of the first pixel composite layer away from the first substrate to a side of an array substrate and removing the first substrate, the first pixel composite layer is patterned; after bonding the side of the second pixel composite layer away from the second substrate to a side of the array substrate and removing the second substrate, the second pixel composite layer is patterned, wherein after completing the patterning of the first pixel composite layer, an insulating protrusion is formed in the patterned area of ​​the first pixel composite layer, and a via hole is formed passing through the insulating protrusion, the distance between the surface of the insulating protrusion away from the array substrate and the array substrate is a third distance, the distance between the surface of the first pixel composite layer away from the array substrate and the array substrate is a fourth distance, and the third distance is equal to the fourth distance; then, the side of the second pixel composite layer away from the second substrate is bonded to a side of the array substrate, and the second substrate is removed.

[0021] The present application provides a display panel and a method for preparing the same. The display panel includes an array substrate and a plurality of pixel unit groups, each pixel unit group consisting of a first pixel unit and a second pixel unit, and the first pixel unit and the second pixel unit are staggered in their orthographic projections on the array substrate. The first pixel unit includes a first light-emitting unit layer having a first light-emitting color; the second pixel unit includes a second light-emitting unit layer having a second light-emitting color and a third light-emitting unit layer having a third light-emitting color, and the second light-emitting unit layer and the third light-emitting unit layer are stacked in sequence in a direction away from the array substrate. In the display panel provided by the present application, since each pixel unit group consists of a first pixel unit and a second pixel unit, and the second pixel unit includes two stacked light-emitting unit layers having different light-emitting colors, it is possible to achieve full-color display while improving resolution, reducing costs, and improving display quality. It can also effectively improve the luminous efficiency of the red light-emitting unit layer, thereby effectively improving the overall luminous efficiency of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0023] Figure 1 A schematic diagram of the film structure of a pixel unit group provided on one side of an array substrate provided in the first embodiment of the present application;

[0024] Figure 2 This is a structural schematic diagram corresponding to step S01 in the method for manufacturing a display panel provided in Example 1 of the present application;

[0025] Figure 3 This is a structural schematic diagram corresponding to step S02 in the method for manufacturing a display panel provided in Example 1 of the present application;

[0026] Figure 4 This is a structural schematic diagram corresponding to step S03 in the method for manufacturing a display panel provided in Example 1 of the present application;

[0027] Figure 5 This is a structural schematic diagram corresponding to step S04 in the method for manufacturing a display panel provided in Example 1 of the present application;

[0028] Figure 6 This is a structural schematic diagram corresponding to step S05 in the method for manufacturing a display panel provided in Example 1 of the present application;

[0029] Figure 7 This is a structural schematic diagram corresponding to step S06 in the method for manufacturing a display panel provided in Example 1 of the present application;

[0030] Figure 8 A schematic diagram of the film structure of a pixel unit group provided on one side of an array substrate according to the second embodiment of the present application;

[0031] Figure 9 This is a structural schematic diagram corresponding to step S11 in the method for manufacturing a display panel provided in Example 2 of the present application;

[0032] Figure 10 This is a structural schematic diagram corresponding to step S12 in the method for manufacturing a display panel provided in Example 2 of the present application;

[0033] Figure 11 This is a structural schematic diagram corresponding to step S13 in the method for manufacturing a display panel provided in Example 2 of the present application;

[0034] Figure 12This is a structural schematic diagram corresponding to step S14 in the method for manufacturing a display panel provided in Example 2 of the present application;

[0035] Figure 13 This is a structural schematic diagram corresponding to step S15 in the method for manufacturing a display panel provided in Example 2 of the present application;

[0036] Figure 14 This is a structural schematic diagram corresponding to step S16 in the method for manufacturing a display panel provided in Example 2 of the present application;

[0037] Figure 15 This is a structural schematic diagram corresponding to step S17 in the method for manufacturing a display panel provided in Example 2 of the present application;

[0038] Figure 16 This is a structural schematic diagram corresponding to step S18 in the method for manufacturing a display panel provided in Example 2 of the present application.

[0039] Reference numerals:

[0040] Array substrate 10; pad group 11; first pad 111; second pad 112; third pad 113; fourth pad 114; pixel unit group 20; first pixel unit 21; first electrode 211; first semiconductor layer 212; first light-emitting unit layer 213; second semiconductor layer 214; second electrode 215; second pixel unit 22; third electrode 221; third semiconductor layer 222; second light-emitting unit layer 223; fourth semiconductor layer 224; first portion 2241; fourth electrode 225; third light-emitting unit layer 226; fifth semiconductor layer 227; fifth electrode 228; insulating protrusion 30; via 31; insulating layer 40; connecting line 50; first substrate 101; first pixel composite layer 102; second substrate 103; second pixel composite layer 104; first composite metal layer 105; second composite metal layer 106; DETAILED DESCRIPTION

[0041] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise specified, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the accompanying drawings; and "inside" and "outside" refer to the outline of the device.

[0042] The disclosure below provides many different embodiments or examples for realizing different structures of the present application. In order to simplify the disclosure of the present application, the components and settings of specific examples are described below. Of course, they are merely examples and are not intended to limit the present application. In addition, the present application may repeat reference numbers and / or reference letters in different examples. Such repetition is for the purpose of simplicity and clarity and does not in itself indicate the relationship between the various embodiments and / or settings discussed. In addition, examples of various specific processes and materials are provided in the present application, but a person of ordinary skill in the art will recognize the application of other processes and / or the use of other materials. Each of the following is described in detail. It should be noted that the order of description of the following embodiments is not intended to limit the preferred order of the embodiments.

[0043] In the related art, the architecture design for achieving full color display of Micro-LED display panels is as follows: each pixel unit group includes a red pixel unit, a green pixel unit and a blue pixel unit, wherein the red pixel unit includes a blue LED chip and a red quantum dot film layer arranged above the blue LED chip, the green pixel unit includes a blue LED chip and a green quantum dot film layer arranged above the blue LED chip, and the blue pixel unit includes a blue LED chip. In this display architecture, since the light-emitting units in each pixel unit, that is, the LED chips, emit blue light, an additional quantum dot film layer is required to excite the quantum dots in the quantum dot film layer with monochromatic light to achieve full color display. However, the quantum dot film layer will restrict the size of the display pixels, making it difficult to improve the resolution of the display panel and increasing the manufacturing cost. At the same time, it is also easy to cause the problem of light crosstalk between adjacent pixel units.

[0044] Example 1

[0045] On the first aspect, the first embodiment of the present application provides a display panel that can achieve full color without setting a quantum dot film layer, thereby improving the resolution of the display panel, reducing manufacturing costs and improving display quality.

[0046] Figure 1 This is a schematic diagram of the film structure of the pixel unit group provided on one side of the array substrate according to the first embodiment of the present application. Figure 1As shown, embodiment 1 of the present application provides a display panel, which includes an array substrate 10 and a plurality of pixel unit groups 20, wherein the pixel unit group 20 is arranged on one side of the array substrate 10, and each of the pixel unit groups 20 is composed of a first pixel unit 21 and a second pixel unit 22, and the first pixel unit 21 and the second pixel unit 22 are staggered in their orthographic projections on the array substrate 10, wherein the first pixel unit 21 includes a first light-emitting unit layer 213 having a first light-emitting color; the second pixel unit 22 includes a second light-emitting unit layer 223 having a second light-emitting color and a third light-emitting unit layer 226 having a third light-emitting color, and the second light-emitting unit layer 223 and the third light-emitting unit layer 226 are stacked in sequence in a direction away from the array substrate 10.

[0047] In the pixel unit group 20 provided in the present application, the first pixel unit 21 can display the first luminescent color through the first luminescent unit layer 213; the second pixel unit 22 can display the second luminescent color through the second luminescent unit layer 223, and / or display the third luminescent color through the third luminescent unit layer 226. Therefore, the display panel can directly achieve full-color display through the first pixel units 21 and the second pixel units 22 in the pixel unit group 20, without the need for a quantum dot film layer, which can effectively reduce manufacturing costs. In addition, it can eliminate the problems of pixel unit size restriction and light crosstalk caused by the provision of a quantum dot film layer, allowing the first pixel units 21 and the second pixel units 22 to be made smaller in size, thereby improving resolution and display quality.

[0048] In addition, the present application enables the second pixel unit 22 to emit the second light-emitting color and / or the third light-emitting color by stacking the second light-emitting unit layer 223 and the third light-emitting unit layer 226 in sequence in a direction away from the array substrate 10, thereby realizing the display function of two pixel units in the related art through one pixel unit, thereby reducing the number of pixel units; compared with the structure in the related art in which light-emitting unit layers of different colors are stacked in the horizontal direction, the present application can save space in the horizontal direction, reduce the layout area of ​​the pixel unit group 20, further improve the resolution of the display panel, and can reduce the number of transfers of the pixel unit in the process, simplify the production and preparation process, and reduce the production cost.

[0049] In some embodiments of the present application, the first luminescent color is red; the second luminescent color is one of blue and green; and the third luminescent color is the other of blue and green.

[0050] The inventors of this application have discovered that the material of the light-emitting unit layer with blue and green luminescent colors is usually InGaN / GaN quantum well material. The coaxial growth of the light-emitting unit layer with blue and green luminescent colors can ensure good epitaxial quality and obtain high light extraction efficiency. In addition, the material of the light-emitting unit layer with red luminescent color is usually AlGaInP / GaInP quantum well material. The difference in materials makes it difficult for the light-emitting unit layer with red luminescent color to grow coaxially with the light-emitting unit layer with blue and green luminescent colors. This application can ensure the luminous effect of the pixel unit and improve the production yield by selecting the first luminescent color as red; the second luminescent color as one of blue and green; and the third luminescent color as the other of blue and green.

[0051] In addition, compared with the structure in the related art in which the red light-emitting layer, the green light-emitting layer and the blue light-emitting layer are stacked in the vertical direction, the present application has no other light-emitting unit layers in the first pixel unit 21 except the light-emitting unit layer with red light-emitting color in the direction perpendicular to the array substrate 10, thereby ensuring the luminous efficiency of the light-emitting unit layer with red light-emitting color; and the luminous efficiency of the red light-emitting unit layer is currently the main factor restricting the overall luminous efficiency of the Micro-LED display panel, so improving the luminous efficiency of the red light-emitting unit layer can effectively improve the overall luminous efficiency of the display panel.

[0052] In summary, compared with the prior art, the present application can effectively balance the resolution of the display panel and the overall luminous efficiency.

[0053] In some embodiments of the present application, the first pixel unit 21 includes a first semiconductor layer 212 of a first doping type, a first light-emitting unit layer 213, and a second semiconductor layer 214 of a second doping type, which are sequentially stacked in a direction away from the array substrate 10; the second pixel unit 22 includes a third semiconductor layer 222 of a second doping type, a second light-emitting unit layer 223, a fourth semiconductor layer 224 of a first doping type, the third light-emitting unit layer 226, and a fifth semiconductor layer 227 of a second doping type, which are sequentially stacked in a direction away from the array substrate 10; wherein the first doping type is one of N-type and P-type, and the second doping type is the other of N-type and P-type.

[0054] In the first pixel unit 21 provided herein, the first semiconductor layer 212 and the second semiconductor layer 214 on either side of the first light-emitting unit layer 213 have different doping types, thereby forming a PN junction. The luminescence state of the first light-emitting unit layer 213 can be controlled by turning on and off the PN junction. In the second pixel unit 22 provided herein, the third semiconductor layer 222 and the fourth semiconductor layer 224 on either side of the second light-emitting unit layer 223 have different doping types, thereby forming a PN junction. The luminescence state of the second light-emitting unit layer 223 can be controlled by turning on and off the PN junction. Furthermore, the fifth semiconductor layer 227 and the fourth semiconductor layer 224 on either side of the third light-emitting unit layer 226 have different doping types, thereby forming a PN junction. The luminescence state of the third light-emitting unit layer 226 can be controlled by turning on and off the PN junction. Furthermore, the luminescence states of the first light-emitting unit layer 213, the second light-emitting unit layer 223, and the third light-emitting unit layer 226 can be independently controlled by the driving circuit in the display panel, achieving full-color display.

[0055] In some embodiments of the present application, the first doping type is P-type; the second doping type is N-type, wherein a periodic stress adjustment layer and a current diffusion layer are further provided between the second-doping type second semiconductor layer 214 and the first light-emitting unit layer 213; a periodic stress adjustment layer and a current diffusion layer are further provided between the second-doping type third semiconductor layer 222 and the second light-emitting unit layer 223; a periodic stress adjustment layer and a current diffusion layer are further provided between the second-doping type fifth semiconductor layer 227 and the third light-emitting unit layer 226; a periodic stress adjustment layer, a current diffusion layer, and a first Bragg reflector layer are further provided between the first-doping type first semiconductor layer 212 and the first light-emitting unit layer 213, the first Bragg reflector layer being capable of transmitting red light; a periodic stress adjustment layer, a current diffusion layer, and a second Bragg reflector layer are further provided between the first-doping type fourth semiconductor layer 224 and the third light-emitting unit layer 226, the second Bragg reflector layer being capable of transmitting blue light and green light. Optionally, the first and second Bragg reflectors include at least one composite film layer, wherein the composite film layer is a stacked structure formed of SiO2 and Ti3O5.

[0056] In some embodiments of the present application, the first pixel unit 21 also includes: a first electrode 211 and a second electrode 215, the first electrode 211 is in contact with the first semiconductor layer 212 of the first doping type; the second electrode 215 is in contact with the second semiconductor layer 214 of the second doping type; the second pixel unit 22 also includes: a third electrode 221, a fourth electrode 225 and a fifth electrode 228, the third electrode 221 is in contact with the third semiconductor layer 222 of the second doping type; the fourth electrode 225 is in contact with the fourth semiconductor layer 224 of the first doping type; the fifth electrode 228 is in contact with the fifth semiconductor layer 227 of the second doping type.

[0057] The first electrode 211 and the fourth electrode 225 are of the same electrode type, and are both anodes or cathodes, and are electrically connected to each other. That is, the first electrode 211 and the fourth electrode 225 are both anodes, or the first electrode 211 and the fourth electrode 225 are both cathodes. Since the first electrode 211 and the fourth electrode 225 are of the same electrode type, the first electrode 211 and the fourth electrode 225 can be electrically connected to the same pad on the array substrate 10, thereby reducing the number of pads, simplifying the structure of the display panel, and reducing the difficulty of bonding.

[0058] The second electrode 215, the third electrode 221, and the fifth electrode 228 are of the same electrode type, and are all either anodes or cathodes. Furthermore, the second electrode 215, the third electrode 221, and the fifth electrode 228 are insulated from each other. That is, the second electrode 215, the third electrode 221, and the fifth electrode 228 are all cathodes, or the second electrode 215, the third electrode 221, and the fifth electrode 228 are all anodes. Because the second electrode 215, the third electrode 221, and the fifth electrode 228 are insulated from each other, the first light-emitting unit layer 213, the second light-emitting unit layer 223, and the third light-emitting unit layer 226 can be independently controlled by the second electrode 215, the third electrode 221, and the fifth electrode 228, respectively, to achieve independent light emission from the first light-emitting unit layer 213, the second light-emitting unit layer 223, and the third light-emitting unit layer 226.

[0059] In some embodiments of the present application, the first doping type fourth semiconductor layer 224 includes a first portion 2241 not covered by the third light emitting unit layer 226 , and the fourth electrode 225 is in contact with the first portion 2241 .

[0060] In the display panel provided in the present application, since the first part 2241 in the fourth semiconductor layer 224 of the first doping type is not covered by the third light-emitting unit layer 226, the fourth electrode 225 can be set on the side of the first part 2241 away from the second light-emitting unit layer 223, thereby reducing the difficulty of setting the fourth electrode 225.

[0061] In some embodiments of the present application, the array substrate 10 includes: multiple pad groups 11, each pad group 11 corresponds to one pixel unit group 20, wherein the pad group 11 includes: a first pad 111, a second pad 112, a third pad 113 and a fourth pad 114, the first pad 111 is electrically connected to the first electrode 211 and the fourth electrode 225 respectively; the second pad 112 is electrically connected to the second electrode 215, the third pad 113 is electrically connected to the third electrode 221, and the fourth pad 114 is electrically connected to the fifth electrode 228.

[0062] In the display panel provided in the present application, since the first pad 111 is electrically connected to the first electrode 211 and the fourth electrode 225 respectively, the first electrode 211 and the fourth electrode 225 can be controlled by one pad, thereby reducing the number of pads set; since the second pad 112 is electrically connected to the second electrode 215, the third pad 113 is electrically connected to the third electrode 221, and the fourth pad 114 is electrically connected to the fifth electrode 228, the second electrode 215, the third electrode 221 and the fifth electrode 228 can be controlled respectively by the second pad 112, the third pad 113 and the third pad 113, thereby realizing independent light emission of the first light-emitting unit layer 213, the second light-emitting unit layer 223 and the third light-emitting unit layer 226.

[0063] Optionally, the array substrate 10 is an integrated circuit wafer, and the integrated circuit wafer includes a driving circuit layer and a plurality of pad groups 11 arranged on the driving circuit layer.

[0064] In some embodiments of the present application, the first electrode 211 is arranged on the side of the first semiconductor layer 212 of the first doping type facing the array substrate 10, and the first electrode 211 is in contact and electrically connected to the first pad 111; the third electrode 221 is arranged on the side of the third semiconductor layer 222 of the second doping type facing the array substrate 10, and the third electrode 221 is in contact and electrically connected to the third pad 113.

[0065] In the display panel provided herein, the first pixel unit 21 and the second pixel unit 22 are disposed on one side of the array substrate 10, for example, by metal bonding. Since the first electrode 211 is in contact and electrically connected to the first pad 111, and the third electrode 221 is in contact and electrically connected to the third pad 113, the electrode connection structure is simplified, making the display panel thinner and lighter. Furthermore, the first pixel unit 21 and the second pixel unit 22 can be formed by chip bonding, simplifying the production process.

[0066] In some embodiments of the present application, the surface of the second semiconductor layer 214 of the second doping type on the side facing away from the array substrate 10 is at a first distance from the array substrate 10; the surface of the fifth semiconductor layer 227 of the second doping type on the side facing away from the array substrate 10 is at a second distance from the array substrate 10; wherein the second distance is greater than the first distance.

[0067] In the display panel provided in the present application, since the distance between the surface of the second semiconductor layer 214 of the second doping type on the side away from the array substrate 10 and the array substrate 10 is greater than the distance between the surface of the fifth semiconductor layer 227 of the second doping type on the side away from the array substrate 10 and the array substrate 10, the overall thickness of the second pixel unit 22 is greater than the overall thickness of the first pixel unit 21. Therefore, after the first pixel unit 21 is formed on one side of the array substrate 10 through a metal bonding process, in the process of forming the second pixel unit 22 on one side of the array substrate 10 through a metal bonding process, it is ensured that the bonding metal layer arranged on the side of the third semiconductor layer 222 away from the second light-emitting unit layer 223 can fully contact the bonding metal layer on the side of the array substrate 10 to complete metal bonding and form the third electrode 221.

[0068] In some embodiments of the present application, the display panel also includes multiple connecting lines 50, the second electrode 215 is electrically connected to the second pad 112 through the connecting lines 50, the fourth electrode 225 is electrically connected to the third pad 113 through the connecting lines 50, and the fifth electrode 228 is electrically connected to the fourth pad 114 through the connecting lines 50.

[0069] In some embodiments of the present application, the display panel further includes an insulating layer 40 , and the insulating layer 40 is disposed between the connecting line 50 and the first pixel unit 21 and between the connecting line 50 and the second pixel unit 22 .

[0070] In a second aspect, the first embodiment of the present application further provides a method for manufacturing a display panel, the method comprising the following steps:

[0071] A first pixel composite layer is formed on one side of a first substrate, the first pixel composite layer comprising a second semiconductor layer of a second doping type, a first light-emitting unit layer, and a first semiconductor layer of a first doping type stacked in sequence; a second pixel composite layer is formed on one side of a second substrate, the second pixel composite layer comprising a fifth semiconductor layer of a second doping type, a third light-emitting unit layer, a fourth semiconductor layer of a first doping type, a second light-emitting unit layer, and a third semiconductor layer of a second doping type stacked in sequence;

[0072] Bonding the side of the first pixel composite layer facing away from the first substrate to one side of an array substrate, and removing the first substrate;

[0073] Bonding the side of the second pixel composite layer facing away from the second substrate to one side of the array substrate, and removing the second substrate;

[0074] Before the step of bonding the side of the first pixel composite layer facing away from the first substrate to a side of an array substrate and removing the first substrate, the first pixel composite layer is patterned; before the step of bonding the side of the second pixel composite layer facing away from the second substrate to a side of the array substrate and removing the second substrate, the second pixel composite layer is patterned.

[0075] Specifically, Figure 2 This is a structural schematic diagram corresponding to step S01 in the method for manufacturing a display panel provided in Example 1 of the present application; Figure 3 This is a structural schematic diagram corresponding to step S02 in the method for manufacturing a display panel provided in Example 1 of the present application; Figure 4 This is a structural schematic diagram corresponding to step S03 in the method for manufacturing a display panel provided in Example 1 of the present application; Figure 5 This is a structural schematic diagram corresponding to step S04 in the method for manufacturing a display panel provided in Example 1 of the present application; Figure 6 This is a structural schematic diagram corresponding to step S05 in the method for manufacturing a display panel provided in Example 1 of the present application; Figure 7 This is a structural diagram corresponding to step S06 in the method for manufacturing a display panel provided in the first embodiment of the present application. Figure 1-Figure 7 As shown, the method for preparing the display panel includes the following steps:

[0076] S01: A first pixel composite layer 102 is formed on one side of a first substrate 101, wherein the first pixel composite layer 102 includes a second semiconductor layer 214 of a second doping type, a first light-emitting unit layer 213, and a first semiconductor layer 212 of a first doping type stacked in sequence; a second pixel composite layer 104 is formed on one side of a second substrate 103, wherein the second pixel composite layer 104 includes a fifth semiconductor layer 227 of a second doping type, a third light-emitting unit layer 226, a fourth semiconductor layer 224 of a first doping type, a second light-emitting unit layer 223, and a third semiconductor layer 222 of a second doping type stacked in sequence. Among them, the first substrate 101 is a GaAs substrate; the second doping type is N-type, and the second semiconductor layer 214 includes GaAs material; the first doping type is P-type, and the first type semiconductor layer includes GaP material; the second substrate 103 is a sapphire substrate, or a substrate containing at least one of GaN, AlN, Si, and SiC; the fifth semiconductor layer 227 and the third semiconductor layer 222 include at least one of GaN, AlGaN, and AlInGaN materials; and the fourth semiconductor layer 224 includes GaN material.

[0077] S02: performing patterning processing on the first pixel composite layer 102 .

[0078] S03: Bond the side of the first pixel composite layer 102 away from the first substrate 101 to the side of an array substrate 10, and remove the first substrate 101. Step S03 specifically includes: forming a first metal bonding layer on the side of the first pixel composite layer 102 away from the first substrate 101, and the material of the first metal bonding layer can be any one of Au, Sn, In, Ti, and Cu; forming a second metal bonding layer on the side of the array substrate 10, and the material of the second metal bonding layer can be any one of Au, Sn, In, Ti, and Cu; bonding the first metal bonding layer and the second metal bonding layer to the side of the first pixel composite layer 102 away from the first substrate 101. The side is bonded to one side of an array substrate 10, wherein the first metal bonding layer and the second metal bonding layer are bonded to form a first electrode 211 of the first pixel unit 21, and the array substrate 10 includes a plurality of pad groups 11, each pad group 11 includes a first pad 111, a second pad 112, a third pad 113 and a fourth pad 114; the first electrode 211 is in contact and electrically connected with the first pad 111, the thickness of the first electrode 211 is 0.1 micron to 3 microns, and the first electrode 211 also has a reflective function; the first substrate 101 is removed.

[0079] S04: performing patterning processing on the second pixel composite layer 104 .

[0080] S05 : Bonding the side of the second pixel composite layer 104 facing away from the second substrate 103 to one side of the array substrate 10 , and removing the second substrate 103 . Step S05 specifically includes: forming a third metal bonding layer on the side of the second pixel composite layer 104 away from the second substrate 103, and the material of the third metal bonding layer can be any one of Au, Sn, In, Ti, and Cu; forming a fourth metal bonding layer on one side of the array substrate 10, and the material of the fourth metal bonding layer can be any one of Au, Sn, In, Ti, and Cu; bonding the side of the second pixel composite layer 104 away from the second substrate 103 to the side of the array substrate 10 by bonding the third bonding layer and the fourth bonding layer, wherein the third metal bonding layer and the fourth metal bonding layer are bonded to form a third electrode 221 of the second pixel unit 22, and the third electrode 221 is in contact and electrically connected with the third pad 113, and the thickness of the third electrode 221 is 0.1 microns to 3 microns, and the third electrode 221 also has a reflective function; removing the second substrate 103.

[0081] S06: Forming a second electrode 215 on a side of the second semiconductor layer 214 of the second doping type facing away from the array substrate 10; forming a fourth electrode 225 on a side of the fourth semiconductor layer 224 of the first doping type facing away from the array substrate 10; and forming a fifth electrode 228 on a side of the fifth semiconductor layer 227 of the second doping type facing away from the array substrate 10. The second electrode 215 is electrically connected to the second pad 112 via a connecting wire 50, and an insulating layer 40 is formed between the connecting wire 50 and the first pixel unit 21; the fourth electrode 225 is electrically connected to the third pad 113 via a connecting wire 50, and the fifth electrode 228 is electrically connected to the fourth pad 114 via a connecting wire 50, and an insulating layer 40 is formed between the connecting wire 50 and the second pixel unit 22.

[0082] In the method for preparing the display panel provided in the present application, the first pixel composite layer 102 is patterned before the step of bonding the side of the first pixel composite layer 102 facing away from the first substrate 101 to the side of an array substrate 10 and removing the first substrate 101; and the second pixel composite layer 104 is patterned before the step of bonding the side of the second pixel composite layer 104 facing away from the first substrate 101 to the side of the array substrate 10 and removing the second substrate 103; therefore, the production preparation process of the display panel can be simplified and the process steps can be reduced.

[0083] Example 2

[0084] Figure 8 This is a schematic diagram of the film structure of the pixel unit group 20 provided on one side of the array substrate 10 according to the second embodiment of the present application. Figure 8 As shown, embodiment 2 of the present application provides a display panel, which includes an array substrate 10 and a plurality of pixel unit groups 20, wherein the pixel unit group 20 is arranged on one side of the array substrate 10, and each of the pixel unit groups 20 is composed of a first pixel unit 21 and a second pixel unit 22, and the first pixel unit 21 and the second pixel unit 22 are staggered in their orthographic projections on the array substrate 10, wherein the first pixel unit 21 includes a first light-emitting unit layer 213 having a first light-emitting color; the second pixel unit 22 includes a second light-emitting unit layer 223 having a second light-emitting color and a third light-emitting unit layer 226 having a third light-emitting color, and the second light-emitting unit layer 223 and the third light-emitting unit layer 226 are stacked in sequence in a direction away from the array substrate 10.

[0085] It should be noted that the structure of the display panel provided in the second embodiment of the present application is similar to the structure of the display panel provided in the first embodiment of the present application, and the same parts will not be described in detail in the second embodiment of the present application.

[0086] The difference is that the first electrode 211 is arranged on the side of the first semiconductor layer 212 of the first doping type facing the array substrate 10, and the first electrode 211 is in contact and electrically connected with the first pad 111; the third electrode 221 is arranged on the side of the third semiconductor layer 222 of the second doping type facing the array substrate 10, wherein the display panel also includes a plurality of insulating protrusions 30, the insulating protrusions 30 are arranged between the third electrode 221 and the array substrate 10, and the third electrode 221 is electrically connected to the third pad 113 through the via 31 in the insulating protrusion 30.

[0087] In the display panel provided in the embodiment of the present application, since the display panel also includes a plurality of insulating protrusions 30, the insulating protrusions 30 are arranged between the third electrode 221 and the array substrate 10, and the third electrode 221 is electrically connected to the third pad 113 through the via hole 31 in the insulating protrusion 30, therefore, the alignment accuracy requirement when the first pixel unit 21 and the array substrate 10 are bonded can be reduced; the alignment accuracy requirement when the second pixel unit 22 and the array substrate 10 are bonded can be reduced; and this is conducive to reducing the production and manufacturing cost of the display panel.

[0088] In some embodiments of the present application, the distance between the surface of the insulating protrusion 30 on the side facing away from the array substrate 10 and the array substrate 10 is a third distance; the distance between the surface of the second semiconductor layer 214 of the second doping type on the side facing away from the array substrate 10 and the array substrate 10 is a fourth distance; wherein, the third distance is equal to the fourth distance.

[0089] In the display panel provided in the present application, since the third distance is equal to the fourth distance, the surface of the insulating protrusion 30 facing away from the array substrate 10 and the surface of the second semiconductor layer 214 of the second doping type facing away from the array substrate 10 can be located on the same horizontal plane, thereby providing flattening conditions for the subsequent formation of the second pixel unit 22, ensuring the formation quality of the second pixel unit 22, and improving the display effect of the display panel.

[0090] In a second aspect, the second embodiment of the present application further provides a method for manufacturing a display panel, the method comprising the following steps:

[0091] A first pixel composite layer is formed on one side of a first substrate, the first pixel composite layer comprising a second semiconductor layer of a second doping type, a first light-emitting unit layer, and a first semiconductor layer of a first doping type stacked in sequence; a second pixel composite layer is formed on one side of a second substrate, the second pixel composite layer comprising a fifth semiconductor layer of a second doping type, a third light-emitting unit layer, a fourth semiconductor layer of a first doping type, a second light-emitting unit layer, and a third semiconductor layer of a second doping type stacked in sequence;

[0092] Bonding the side of the first pixel composite layer facing away from the first substrate to one side of an array substrate, and removing the first substrate;

[0093] Bonding the side of the second pixel composite layer facing away from the second substrate to one side of the array substrate, and removing the second substrate;

[0094] wherein, after the step of bonding the side of the first pixel composite layer away from the first substrate to the side of an array substrate and removing the first substrate, the first pixel composite layer is patterned; after the step of bonding the side of the second pixel composite layer away from the second substrate to the side of the array substrate and removing the second substrate, the second pixel composite layer is patterned, wherein, after completing the patterning of the first pixel composite layer, an insulating protrusion is formed in the patterned area of ​​the first pixel composite layer, and a via hole is formed passing through the insulating protrusion, the distance between the surface of the insulating protrusion away from the array substrate and the array substrate is a third distance, the distance between the surface of the first pixel composite layer away from the array substrate and the array substrate is a fourth distance, and the third distance is equal to the fourth distance; thereafter, the side of the second pixel composite layer away from the second substrate is bonded to the side of the array substrate, and the second substrate is removed.

[0095] Specifically, Figure 9 This is a structural schematic diagram corresponding to step S11 in the method for manufacturing a display panel provided in Example 2 of the present application; Figure 10 This is a structural schematic diagram corresponding to step S12 in the method for manufacturing a display panel provided in Example 2 of the present application; Figure 11 This is a structural schematic diagram corresponding to step S13 in the method for manufacturing a display panel provided in Example 2 of the present application; Figure 12 This is a structural schematic diagram corresponding to step S14 in the method for manufacturing a display panel provided in Example 2 of the present application; Figure 13 This is a structural schematic diagram corresponding to step S15 in the method for manufacturing a display panel provided in Example 2 of the present application; Figure 14 This is a structural schematic diagram corresponding to step S16 in the method for manufacturing a display panel provided in Example 2 of the present application; Figure 15 This is a structural schematic diagram corresponding to step S17 in the method for manufacturing a display panel provided in Example 2 of the present application; Figure 16 This is a structural diagram corresponding to step S18 in the method for preparing a display panel provided in the second embodiment of the present application. Figures 8-16 As shown, the method for preparing the display panel includes the following steps:

[0096] S11: A first pixel composite layer 102 is formed on one side of a first substrate 101, wherein the first pixel composite layer 102 includes a second semiconductor layer 214 of a second doping type, a first light-emitting unit layer 213, and a first semiconductor layer 212 of a first doping type stacked in sequence; a second pixel composite layer 104 is formed on one side of a second substrate 103, wherein the second pixel composite layer 104 includes a fifth semiconductor layer 227 of a second doping type, a third light-emitting unit layer 226, a fourth semiconductor layer 224 of a first doping type, a second light-emitting unit layer 223, and a third semiconductor layer 222 of a second doping type stacked in sequence. Among them, the first substrate 101 is a GaAs substrate; the second doping type is N-type, and the second semiconductor layer 214 includes GaAs material; the first doping type is P-type, and the first type semiconductor layer includes GaP material; the second substrate 103 is a sapphire substrate, or a substrate containing at least one of GaN, AlN, Si, and SiC; the fifth semiconductor layer 227 and the third semiconductor layer 222 include at least one of GaN, AlGaN, and AlInGaN materials; and the fourth semiconductor layer 224 includes GaN material.

[0097] S12: Bonding the side of the first pixel composite layer 102 facing away from the first substrate 101 to a side of an array substrate 10, and removing the first substrate 101. Step S12 specifically includes: forming a first metal bonding layer on the side of the first pixel composite layer 102 facing away from the first substrate 101, the material of the first metal bonding layer can be any one of Au, Sn, In, Ti, and Cu; forming a second metal bonding layer on the side of the array substrate 10, the material of the second metal bonding layer can be any one of Au, Sn, In, Ti, and Cu; bonding the side of the first pixel composite layer 102 facing away from the first substrate 101 to a side of an array substrate 10 by bonding the first metal bonding layer to the second metal bonding layer. The first metal bonding layer and the second metal bonding layer are bonded to form a first composite metal layer 105, and the first composite metal layer 105 is subsequently used to form the first electrode 211 of the first pixel unit 21, wherein the array substrate 10 includes a plurality of pad groups 11, each pad group 11 includes a first pad 111, a second pad 112, a third pad 113 and a fourth pad 114, the first electrode 211 is in contact with and electrically connected to the first pad 111, the thickness of the first electrode 211 is 0.1 microns to 3 microns, and the first electrode 211 also has a reflective function; the first substrate 101 is removed.

[0098] S13 : performing patterning on the first pixel composite layer 102 and the first composite metal layer 105 , so that the patterned first composite metal layer 105 forms a plurality of first electrodes 211 .

[0099] S14: Forming an insulating protrusion 30 in the patterned area of ​​the first pixel composite layer 102. Optionally, the distance between the surface of the insulating protrusion 30 facing away from the array substrate 10 and the array substrate 10 is a third distance, and the distance between the surface of the first pixel composite layer 102 facing away from the array substrate 10 and the array substrate 10 is a fourth distance, and the third distance is equal to the fourth distance. Specifically, a chemical mechanical polishing (CMP) process can be used to make the distance between the surface of the insulating protrusion 30 facing away from the array substrate 10 and the array substrate 10 equal to the distance between the surface of the first pixel composite layer 102 facing away from the array substrate 10 and the array substrate 10. Furthermore, the step of forming an insulating protrusion 30 in the patterned area of ​​the first pixel composite layer 102 specifically includes: forming an insulating protrusion layer in the patterned area of ​​the first pixel composite layer 102 and on the side of the first composite metal layer 105 facing away from the array substrate 10, at this time, the insulating protrusion layer covers the first pixel composite layer 102; then, performing a CMP process on the insulating protrusion layer to remove the insulating protrusion layer on the side of the first pixel composite layer 102 facing away from the array substrate 10, so that the distance between the surface of the insulating protrusion 30 on the side facing away from the array substrate 10 and the array substrate 10 is equal to the distance between the surface of the first pixel composite layer 102 on the side facing away from the array substrate 10 and the array substrate 10.

[0100] S15 : etching the insulating protrusion 30 to form a via hole 31 , and depositing a conductive material in the via hole 31 , wherein the conductive material is electrically connected to the third pad 113 .

[0101] S16 : Bonding the side of the second pixel composite layer 104 facing away from the second substrate 103 to one side of the array substrate 10 , and removing the second substrate 103 . Step S16 specifically includes: forming a third metal bonding layer on the side of the second pixel composite layer 104 facing away from the first substrate 101, and the material of the third metal bonding layer can be any one of Au, Sn, In, Ti, and Cu; forming a fourth metal bonding layer on one side of the array substrate 10, and the material of the fourth metal bonding layer can be any one of Au, Sn, In, Ti, and Cu; bonding the side of the second pixel composite layer 104 facing away from the second substrate 103 to the side of the array substrate 10 by bonding the third bonding layer and the fourth bonding layer, wherein the third metal bonding layer and the fourth metal bonding layer are bonded to form a second composite metal layer 106, and the second composite metal layer 106 is subsequently used to form a third electrode 221 of the second pixel unit 22, and the third electrode 221 is in contact and electrically connected with the third pad 113, and the thickness of the third electrode 221 is 0.1 microns to 3 microns, and the third electrode 221 also has a reflective function; removing the second substrate 103.

[0102] S17 : performing patterning on the second pixel composite layer 104 and the second composite metal layer 106 , so that the patterned second composite metal layer 106 forms a plurality of the third electrodes 221 .

[0103] S18: Forming a second electrode 215 on a side of the second semiconductor layer 214 of the second doping type facing away from the array substrate 10; forming a fourth electrode 225 on a side of the fourth semiconductor layer 224 of the first doping type facing away from the array substrate 10; and forming a fifth electrode 228 on a side of the fifth semiconductor layer 227 of the second doping type facing away from the array substrate 10. The second electrode 215 is electrically connected to the second pad 112 via a connecting wire 50, and an insulating layer 40 is formed between the connecting wire 50 and the first pixel unit 21; the fourth electrode 225 is electrically connected to the third pad 113 via a connecting wire 50, and the fifth electrode 228 is electrically connected to the fourth pad 114 via a connecting wire 50, and an insulating layer 40 is formed between the connecting wire 50 and the second pixel unit 22.

[0104] In the method for preparing the display panel provided in the present application, after the step of bonding the side of the first pixel composite layer 102 facing away from the first substrate 101 to the side of an array substrate 10 and removing the first substrate 101, the first pixel composite layer 102 is patterned; after the step of bonding the side of the second pixel composite layer 104 facing away from the first substrate 101 to the side of the array substrate 10 and removing the second substrate 103, the second pixel composite layer 104 is patterned; therefore, the bonding alignment accuracy requirements can be greatly reduced, which is beneficial to reducing the production and manufacturing costs of the display panel.

[0105] In summary, the present application provides a display panel and a method for preparing the same. The display panel includes an array substrate and a plurality of pixel unit groups, each pixel unit group consisting of a first pixel unit and a second pixel unit, and the first pixel unit and the second pixel unit are staggered in their orthographic projections on the array substrate. The first pixel unit includes a first light-emitting unit layer having a first light-emitting color; the second pixel unit includes a second light-emitting unit layer having a second light-emitting color and a third light-emitting unit layer having a third light-emitting color, and the second light-emitting unit layer and the third light-emitting unit layer are stacked in sequence in a direction away from the array substrate. In the display panel provided by the present application, since each pixel unit group consists of a first pixel unit and a second pixel unit, and the second pixel unit includes two stacked light-emitting unit layers having different light-emitting colors, it is possible to achieve full-color display while improving resolution, reducing costs, and improving display quality.

[0106] The above is a detailed introduction to a display panel and a preparation method thereof provided in an embodiment of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, based on the ideas of the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A display panel, characterized in that: The display panel includes: array substrate; A plurality of pixel unit groups are arranged on one side of the array substrate, each of the pixel unit groups consists of a first pixel unit and a second pixel unit, and the orthographic projections of the first pixel unit and the second pixel unit on the array substrate are staggered, wherein: The first pixel unit includes a first light-emitting unit layer having a first light-emitting color, and the first light-emitting color is red; The second pixel unit includes a second light-emitting unit layer having a second light-emitting color, a third light-emitting unit layer having a third light-emitting color, a third semiconductor layer of a second doping type, a fourth semiconductor layer of a first doping type, and a fifth semiconductor layer of a second doping type, wherein the third semiconductor layer of the second doping type, the second light-emitting unit layer, the fourth semiconductor layer of the first doping type, the third light-emitting unit layer, and the fifth semiconductor layer of the second doping type are sequentially stacked in a direction away from the array substrate, and the number of the semiconductor layer of the first doping type between the second light-emitting unit layer and the third light-emitting unit layer is one, and the semiconductor layer is the fourth semiconductor layer of the first doping type; The second luminescent color is one of blue and green; the third luminescent color is the other of blue and green; the first doping type is one of N-type and P-type, and the second doping type is the other of N-type and P-type.

2. The display panel according to claim 1, wherein: The first pixel unit and the second pixel unit are arranged on one side of the array substrate by metal bonding.

3. The display panel according to claim 2, wherein: The first pixel unit includes a first semiconductor layer of a first doping type, the first light emitting unit layer, and a second semiconductor layer of a second doping type, which are sequentially stacked in a direction away from the array substrate; The second pixel unit includes a third semiconductor layer of the second doping type, the second light emitting unit layer, a fourth semiconductor layer of the first doping type, the third light emitting unit layer, and a fifth semiconductor layer of the second doping type, which are sequentially stacked in a direction away from the array substrate; The first doping type is one of N-type and P-type, and the second doping type is the other of N-type and P-type.

4. The display panel according to claim 3, wherein: The first pixel unit further includes: a first electrode in contact with the first semiconductor layer of the first doping type; a second electrode in contact with the second semiconductor layer of the second doping type; The second pixel unit further includes: a third electrode in contact with the third semiconductor layer of the second doping type; a fourth electrode, contacting the fourth semiconductor layer of the first doping type; a fifth electrode, contacting the fifth semiconductor layer of the second doping type; The first electrode and the fourth electrode are of the same electrode type, both being an anode or a cathode, and are electrically connected to each other. The second electrode, the third electrode and the fifth electrode are of the same electrode type, which are either anodes or cathodes, and the second electrode, the third electrode and the fifth electrode are insulated.

5. The display panel according to claim 4, wherein: The fourth semiconductor layer of the first doping type includes a first portion not covered by the third light emitting unit layer, and the fourth electrode is in contact with the first portion.

6. The display panel according to claim 4, wherein: The array substrate comprises: a plurality of pad groups, each pad group corresponding to one pixel unit group, The pad group includes: a first pad, a second pad, a third pad and a fourth pad. The first pad is electrically connected to the first electrode and the fourth electrode respectively; the second pad is electrically connected to the second electrode, the third pad is electrically connected to the third electrode, and the fourth pad is electrically connected to the fifth electrode.

7. The display panel according to claim 6, wherein: The first electrode is provided on a side of the first semiconductor layer of the first doping type facing the array substrate, and the first electrode is in contact and electrically connected with the first pad; The third electrode is disposed on a side of the third semiconductor layer of the second doping type facing the array substrate, and the third electrode is in contact and electrically connected to the third pad.

8. The display panel according to claim 7, wherein: A surface of the second semiconductor layer of the second doping type facing away from the array substrate is at a first distance from the array substrate; A surface of the fifth semiconductor layer of the second doping type facing away from the array substrate is at a second distance from the array substrate; The second distance is greater than the first distance.

9. The display panel according to claim 6, wherein: The first electrode is provided on a side of the first semiconductor layer of the first doping type facing the array substrate, and the first electrode is in contact and electrically connected with the first pad; The third electrode is arranged on the side of the third semiconductor layer of the second doping type facing the array substrate, wherein the display panel also includes a plurality of insulating protrusions, the insulating protrusions are arranged between the third electrode and the array substrate, and the third electrode is electrically connected to the third pad through via holes in the insulating protrusions.

10. The display panel according to claim 9, wherein: The distance between the surface of the insulating protrusion facing away from the array substrate and the array substrate is a third distance; A distance between a surface of the second semiconductor layer of the second doping type facing away from the array substrate and the array substrate is a fourth distance; The third distance is equal to the fourth distance.

11. A method for preparing a display panel, characterized in that: The method for preparing the display panel comprises the following steps: A first pixel composite layer is formed on one side of a first substrate, the first pixel composite layer comprising a second semiconductor layer of a second doping type, a first light-emitting unit layer, and a first semiconductor layer of a first doping type stacked in sequence; a second pixel composite layer is formed on one side of a second substrate, the second pixel composite layer comprising a fifth semiconductor layer of a second doping type, a third light-emitting unit layer, a fourth semiconductor layer of a first doping type, a second light-emitting unit layer, and a third semiconductor layer of a second doping type stacked in sequence; Bonding the side of the first pixel composite layer facing away from the first substrate to one side of an array substrate, and removing the first substrate; Bonding the side of the second pixel composite layer facing away from the second substrate to one side of the array substrate, and removing the second substrate; Before bonding the side of the first pixel composite layer facing away from the first substrate to a side of an array substrate and removing the first substrate, the first pixel composite layer is patterned; before bonding the side of the second pixel composite layer facing away from the second substrate to a side of the array substrate and removing the second substrate, the second pixel composite layer is patterned. Or, after bonding the side of the first pixel composite layer away from the first substrate to a side of an array substrate and removing the first substrate, the first pixel composite layer is patterned; after bonding the side of the second pixel composite layer away from the second substrate to a side of the array substrate and removing the second substrate, the second pixel composite layer is patterned, wherein after completing the patterning of the first pixel composite layer, an insulating protrusion is formed in the patterned area of ​​the first pixel composite layer, and a via hole is formed passing through the insulating protrusion, the distance between the surface of the insulating protrusion away from the array substrate and the array substrate is a third distance, the distance between the surface of the first pixel composite layer away from the array substrate and the array substrate is a fourth distance, and the third distance is equal to the fourth distance; then, the side of the second pixel composite layer away from the second substrate is bonded to a side of the array substrate, and the second substrate is removed.

Images