Photonic device, photonic device structure and forming method thereof

Abstract

The embodiment of the invention provides a photonic device, a photonic device structure and a forming method thereof. The photonic device includes a substrate, a P-type doping component disposed over the substrate, an N-type doping component disposed over the substrate, an optical absorption layer disposed over the substrate, and a charging layer disposed over the substrate. The optical absorption layer is located between the P-type doped component and the N-type doped component. The optical absorbing layer and the substrate have different material compositions. The charging layer is located between the P-type doped component and the N-type doped component. The charging layer has a substantially linear first side surface. The first side surface is in direct contact with the optical absorbing layer.

Description

Technical Field

[0001] Embodiments of the present application relate to photonic devices, photonic device structures, and methods for forming the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs, each with smaller and more complex circuits than the previous one. Over the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. This scaling-down process generally provides benefits by increasing production efficiency and reducing associated costs.

[0003] As semiconductor devices decrease in size but increase in complexity, they may be deployed in a wide variety of applications. These applications may include photonic devices, such as semiconductor image sensors for sensing radiation (e.g., visible light). For example, complementary metal oxide semiconductor (CMOS) image sensors (CIS) and charge coupled device (CCD) sensors are widely used in a variety of applications, such as digital still cameras, mobile phones, medical equipment, automotive sensors, etc. However, as device sizes become smaller, it may be more difficult to form certain components of photonic devices with the desired accuracy, for example, with respect to the size and / or position of these particular components. As a result, the performance of the photonic devices may be reduced. What is needed is an enhanced scheme to manufacture the components of photonic devices with sufficient accuracy with respect to the size and / or position of the photonic devices, even as the size of semiconductor devices continues to shrink with each technology generation. Summary of the invention

[0004] According to one aspect of an embodiment of the present application, a photonic device is provided, comprising: a substrate; a P-type doped component disposed above the substrate; an N-type doped component disposed above the substrate; an optical absorption layer disposed above the substrate and located between the P-type doped component and the N-type doped component, wherein the optical absorption layer and the substrate have different material compositions; and a charging layer disposed above the substrate and located between the P-type doped component and the N-type doped component, wherein the charging layer has a substantially linear first side surface, and wherein the first side surface is in direct contact with the optical absorption layer.

[0005] According to another aspect of an embodiment of the present application, a photonic device structure is provided, comprising: a substrate; a P-type contact disposed above the substrate in a vertical direction, wherein the P-type contact comprises silicon; an N-type contact disposed above the substrate in a vertical direction, wherein the N-type contact comprises silicon; an optical absorption layer disposed above the substrate in a vertical direction and located between the P-type contact and the N-type contact in a horizontal direction, wherein the optical absorption layer comprises germanium; and a charging layer disposed above the substrate in a vertical direction and located between the optical absorption layer and the N-type contact in a horizontal direction, wherein the charging layer comprises silicon doped with a P-type dopant, and wherein an interface between the optical absorption layer and the charging layer extends substantially in the vertical direction.

[0006] According to another aspect of an embodiment of the present application, a method for forming a photonic device is provided, comprising: forming a semiconductor layer over a substrate; etching an opening in the semiconductor layer; forming an optical absorption layer on a portion of the semiconductor layer exposed by the opening using a selective growth process; forming a charging layer adjacent to the optical absorption layer, the charging layer forming a substantially straight interface with portions of the optical absorption layer and the semiconductor layer; and forming a passivation layer over the optical absorption layer and the charging layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustrative purposes. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1A A planar top view of a semiconductor photonic device according to various aspects of the present disclosure is shown.

[0009] Figure 1B Graphs corresponding to electric fields of semiconductor photonic devices according to various aspects of the present disclosure are shown.

[0010] Figure 2-Figure 34 A series of cross-sectional side views of a semiconductor photonic device at various stages of fabrication corresponding to a process flow are shown according to various aspects of the present disclosure.

[0011] Fig.35 A planar top view of a photonic device according to various aspects of the present disclosure is shown.

[0012] Figure 36A-36H A number of cross-sectional side views of portions of semiconductor photonic devices corresponding to various embodiments according to various aspects of the present disclosure are shown.

[0013] Fig.37A series of cross-sectional side views of a semiconductor photonic device at various stages of fabrication corresponding to a process flow are shown according to various aspects of the present disclosure.

[0014] Fig.38 A flow chart of a method of manufacturing a photonic device according to various aspects of the present disclosure is shown.

[0015] Fig.39 A block diagram of an integrated circuit manufacturing system according to various aspects of the present disclosure is shown. DETAILED DESCRIPTION

[0016] The following disclosure provides many different embodiments or examples for realizing different features of the present disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0017] In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself specify the relationship between the various embodiments and / or configurations discussed. In addition, in the following disclosure, the formation of a component on, connected to and / or coupled to another component may include an embodiment in which the component is formed in a direct contact manner, and may also include an embodiment in which the additional component can be formed as an inserted component so that the component may not be in direct contact. In addition, spatial relative terms, such as, "lower", "upper", "horizontal", "vertical", "above", "above", "below", "below", "upward", "downward", "top", "bottom", etc., and their derivatives (e.g., "horizontally", "downward", "upward", etc.) are used to simplify the relationship between one component of the present disclosure and another component. Spatial relative terms are intended to cover different orientations of devices including components. Further, when "about", "approximately", etc. are used to describe a number or a range of numbers, the term is intended to include numbers within a reasonable range including the described number, such as within + / -10% of the described number or other values ​​understood by those skilled in the art. For example, the term "about 5 nm" includes a size range from 4.5 nm to 5.5 nm.

[0018] The present disclosure relates generally to semiconductor devices and, more particularly, to semiconductor photonic devices. For example, the present disclosure introduces a scheme for fabricating an avalanche photodiode (APD) by a self-aligned process. Using such a self-aligned process, the resulting APD can achieve a narrow width of its doped regions (e.g., a charging layer) and a substantially vertical doping profile of the portion of the doped region disposed directly adjacent to an optical absorption layer. Various aspects of the present disclosure will now be discussed in more detail below.

[0019] Reference now Figure 1A and Figure 1B , shows a schematic partial plan top view of a portion of the APD 100 and a graph 110 corresponding to the APD 100 . Figure 1A The APD 100 in has an X-axis spanning a first horizontal direction and a Y-axis spanning a second horizontal direction. The APD 100 includes a plurality of components arranged adjacent to each other along the X-axis. For example, the APD 100 includes a P+ contact, an optical absorption layer, a charging layer, a multiplication layer (ML), an N+ contact, and a substrate. The substrate may be part of a semiconductor substrate. For example, the substrate may include a silicon material. The P+ contact may include silicon doped with a P-type dopant, and the N+ contact may include silicon doped with an N-type dopant. The P+ contact and the N+ contact may serve as a P-type region and an N-type region of a PN diode. The optical absorption layer—which may include a germanium material in some embodiments—is configured to absorb radiation, such as visible light. The ML—which may include silicon in some embodiments—may function similar to an amplifier and is configured to control the multiplication factor and breakdown voltage of the APD 100. The charging layer is implemented to divide or otherwise separate the electric field of the optical absorption layer and the ML. For example, the charging layer may include a silicon material doped with a P-type dopant, but the dopant concentration level of the charging layer is substantially less than the dopant concentration level of the P+ contact.

[0020] Figure 1B The graph 110 in FIG. 1 also includes an X-axis across the horizontal direction and a Z-axis across the vertical direction. Figure 1B The position along the X axis corresponds to Figure 1A, represents the position along the X-axis in . Meanwhile, the Z-axis represents the electric field strength. In more detail, the graph 110 includes a graph 120 of the electric field of the APD 100 corresponding to different regions of the APD 100. For example, the electric field of the ML is the strongest, which is reflected in the fact that the graph 120 has a maximum height at the position corresponding to the ML. The electric field of the optical absorption layer is substantially weaker, which is reflected by the fact that the height of the graph 120 at the position corresponding to the optical absorption layer is substantially lower. Since the charging layer separates the ML and the optical absorption layer, the electric field of the charging layer changes because the electric field of the charging layer is stronger near the ML and tilts toward the optical absorption layer. One inventive aspect of the present disclosure relates to the formation of the charging layer so that it can achieve a relatively narrow width while directly adjacent to the optical absorption layer, wherein the interface between the charging layer and the optical absorption layer has a substantially vertical doping profile.

[0021] The following will refer to Figure 2-Figure 34 Discussing the APD 100 manufacturing process flow in more detail, Figure 2-Figure 34 are cross-sectional side views of the APD 100 at various stages of fabrication. The cross-sectional views are taken along a plane defined by a horizontal X direction (or X-axis) and a vertical Z direction (or Z-axis).

[0022] Reference now Figure 2 , the manufacture of the APD 100 includes providing a substrate 210 as part of a wafer. The substrate 210 may include a semiconductor material. For example, the substrate 210 may include silicon as the semiconductor material. An insulating layer 220 is formed over the substrate 210. In some embodiments, the insulator layer 220 may include silicon oxide (SiO2). Another semiconductor layer 230 is formed over the insulator layer 220. For example, the semiconductor layer 230 may also include silicon having a <100> lattice direction or having a <111> lattice direction. In this way, a silicon-on-insulator (SOI) structure is formed by the substrate 210, the insulator layer 220, and the semiconductor layer 230. The SOI structure may provide reduced parasitic capacitance, which helps to improve device performance.

[0023] Reference now Figure 3, an etching process 250 is performed on the APD 100 to form a plurality of openings in the semiconductor layer 230. In some embodiments, the etching process 250 includes a photolithography process, and the photolithography process may include one or more photoresist spin coating processes, photoresist exposure processes, post-exposure baking processes, photoresist development processes, etc. (not necessarily performed in this order). The photolithography process may form a patterned photoresist mask on the semiconductor layer 230 (not specifically shown here for simplicity). The etching process 250 may include one or more dry etching processes or wet etching processes to partially etch away the semiconductor layer 230. The patterned photoresist mask is used as a protective mask to prevent etching of a portion of the semiconductor layer 230 thereunder during the etching process 250. As a result of performing the etching process 250, openings 260 and 261 are formed in the semiconductor layer 230. The openings 260 and 261 each extend partially downward through the semiconductor layer 230 in the Z direction. The patterned photoresist mask may be removed after forming the openings 260 and 261 , for example, by a photoresist ashing process or a photoresist stripping process.

[0024] Reference now Figure 4 , a deposition process 270 is performed on the APD 100 to form a dielectric layer 280. The deposition process 270 may include a physical vapor deposition (PVD), a chemical vapor deposition, an atomic layer deposition (ALD) process, or a combination thereof. In some embodiments, the dielectric layer 280 includes silicon oxide. The dielectric layer 280 is deposited on the semiconductor layer 230 and fills the openings 260 and 261.

[0025] Reference now Figure 5 , an etching process 290 is performed on the APD 100 to form an opening 300. In some embodiments, the etching process 290 includes a dry etching process, a wet etching process, or a combination thereof. It should be understood that a photolithography process may also be performed to form a patterned photoresist mask, which may be used as a protective mask during the etching process 290. As a result of the etching process 290, the opening 300 extends downwardly through the dielectric layer 280 and partially through the semiconductor layer 230 in the Z direction. It should be noted that the etching process 290 is specifically configured to ensure that the segment 230A of the semiconductor layer 230 is retained after the etching process 290 has been performed. In other words, the segment 230A of the semiconductor layer 230 is exposed by the opening 300.

[0026] Reference now Figure 6, the APD 100 is subjected to a selective growth process 310 to form an optical absorption layer 320 in the opening 300. In more detail, the segment 230A is used as a seed layer during the selective growth process 310. The selective growth process 310 can then grow a semiconductor material on the segment 230A using a deposition technique (e.g., CVD). In some embodiments, the semiconductor material grown on the segment 230A can include germanium. This germanium material can be referred to as an optical absorption layer 320. The optical absorption layer 320 is selectively grown on the segment 230A (which contains silicon in the present embodiment), but is not grown on the upper surface of the dielectric layer 280 (which contains silicon oxide in the present embodiment). In this way, the optical absorption layer 320 is grown inside the opening 300, rather than outside the opening 300. Note that in Figure 6 In the illustrated embodiment, the thickness (or height) of the optically absorbing layer 320 is configured such that the uppermost surface of the optically absorbing layer 32 has a more vertically elevated position than the uppermost surface of the semiconductor layer 230. However, this may not be the case in alternative embodiments.

[0027] It should also be understood that although germanium is used as an example material for optical absorption layer 320, it is not intended to be limiting unless otherwise stated. For example, in some embodiments, silicon germanium (Si x Ge 1-x , where x is between 0 and 1) compounds may also be used to implement the optical absorption layer 320, depending on the operating wavelength of the APD 100 (eg, varying from about 1100 nm to about 2000 nm).

[0028] After forming the optical absorption layer 320 in the opening 300, a plurality of deposition processes (e.g., CVD, PVD, ALD, or a combination thereof) may be performed to form additional layers, such as layers 330, 340, and 350, on the optical absorption layer 320 in the opening 300. For example, layer 330 may include a semiconductor material such as silicon, layer 340 may include a dielectric material such as silicon oxide, and layer 350 may include another semiconductor material such as polysilicon. Layers 330-350 may have substantially less thickness than the optical absorption layer 320. In the illustrated embodiment, the combination of the optical absorption layer 320 and layers 330-350 still does not completely fill the opening 300. In other words, the uppermost layer of layer 350 has a lower vertical elevation position than the uppermost layer of the dielectric layer 280. Layers 330-350 may be used together as a mask structure in a later process, which will be discussed in more detail below.

[0029] Reference now Figure 7, a dielectric removal process 360 is performed on the APD 100 to remove the dielectric layer 280. The dielectric removal process 360 is configured to remove the dielectric layer 280 without substantially affecting the semiconductor layer 230, the optical absorption layer 320, or the layers 330-350. For example, the dielectric removal process 360 may include one or more etching processes that are configured to have a sufficiently high etching selectivity between the dielectric layer 280 and the other layers 230 and 320-350. In some embodiments, the etching processes of the dielectric removal process 360 may be configured so that the dielectric layer 280 can be etched away at a rate that is more than five times or more than ten times faster than the other layers 230 and the layers 320-350. Therefore, the dielectric layer 280 can be removed while substantially retaining the other layers 230 and the layers 320-350.

[0030] Reference now Figure 8 , a patterned photoresist mask 370 is formed over portions of the APD 100. For example, the patterned photoresist mask 370 is formed to cover the “right side” of the APD 100, including over portions of the semiconductor layer 230 to the “right side” of the optical absorption layer 320, and over portions of the layer 350 to the “right side”. Thereafter, a doping process 380 is performed to convert portions of the semiconductor layer 230 to the “left side” of the optical absorption layer 320 into the P+ contact 400. For example, the doping process 380 may implant a P-type dopant material into the exposed portions of the semiconductor layer 230 (i.e., portions of the semiconductor layer 230 to the “left side” of the optical absorption layer 320). The patterned photoresist mask 370 protects the underlying layers (including the semiconductor layer 230 to the “right side” of the optical absorption layer 320) from being implanted with the dopant material. Similarly, the layers 330-350 may also be used as a masking structure to protect the underlying optical absorption layer 320 from being implanted with the dopant material. As a result, the semiconductor layer 230 on the "left side" of the optical absorption layer 320 is transformed into a P+ contact 400, while the semiconductor layer 230 on the "right side" of the optical absorption layer 320 remains substantially undoped at this stage of manufacturing. It can be understood that the P+ contact 400 corresponds to the P+ contact 400 described above with reference to FIG. Figure 1A and Figure 1B The P+ contact discussed.

[0031] Note that as an inherent result of the unique manufacturing process described above, the optically absorbing layer 320 is formed directly adjacent to the P+ contact 400. For example, the etching of the opening 300 (see Figure 5) and then selectively growing the optical absorption layer 320 in the opening 300, the optical absorption layer 320 can be directly adjacent to the "left side" of the semiconductor layer 230. Thereafter, the doping process 380 converts the portion of the semiconductor layer 230 directly adjacent to the "left side" of the optical absorption layer 320 into the P+ contact 400, while the layers 330-350 protect the optical absorption layer 320 from being doped. In this way, the optical absorption layer 320 is formed to directly adjacent to the P+ contact 400 by self-alignment.

[0032] Reference now Fig. 9 , the patterned photoresist mask 370 is removed, for example, by a photoresist ashing or photoresist stripping process. Thereafter, another patterned photoresist mask 410 is formed over portions of the APD 100. For example, the patterned photoresist mask 410 is formed to cover the “left side” of the APD 100, including over the P+ contact 400, over portions of the optical absorption layer 320 and overlying layers 330-350, and over portions of the semiconductor layer 230 on the “right side” of the optical absorption layer 320.

[0033] Thereafter, a doping process 430 is performed to convert the portion of the semiconductor layer 230 that is not covered by the patterned photoresist mask 410 into an N+ contact 450. For example, the doping process 430 may implant an N-type dopant material into the exposed portion of the semiconductor layer 230. The patterned photoresist mask 410 protects the underlying layers from being implanted with the dopant material. As a result, the exposed portion of the semiconductor layer 230 is transformed into the N+ contact 450, while the portion of the semiconductor layer 230 that is on the "right side" of the optical absorption layer 320 and is covered by the patterned photoresist mask 410 remains substantially undoped at this stage of manufacturing. It should be understood that the N+ contact 450 corresponds to the N+ contact 450 described above with reference to FIG. Figure 1A and Figure 1B N+ contact discussed.

[0034] Reference now Fig.10 , the patterned photoresist mask 410 is removed, for example, by a photoresist ashing or photoresist stripping process. Thereafter, another patterned photoresist mask 470 is formed over portions of the APD 100. For example, the patterned photoresist mask 470 is formed to define an opening 480 that exposes a portion of the semiconductor layer 230 that is directly adjacent to the “right side” of the optical absorption layer 320. The opening 480 also exposes a portion of the layer 350. The remaining components of the APD 100 are covered by the patterned photoresist mask 470.

[0035] Thereafter, a doping process 490 is performed to convert the portions of the semiconductor layer 230 that are not covered by the patterned photoresist mask 470 into the charged layer 500. For example, the doping process 490 may implant a P-type dopant material into the exposed portions of the semiconductor layer 230. The patterned photoresist mask 470 and layers 330-350 protect the underlying layers from being implanted with the dopant material. As a result, the portions of the semiconductor layer 230 exposed by the openings 480 are transformed into the charged layer 500, while the portions of the semiconductor layer 230 covered by the patterned photoresist mask 470 remain substantially undoped at this stage of fabrication. Due to the protection provided by the layers 330-350, the optically absorbing layer 320 also remains undoped. It should be understood that the charged layer 500 corresponds to the above reference numeral 480. Figure 1A and Figure 1B Charging layer discussed.

[0036] It should also be understood that the dosage of the P-type dopant material of the doping process 490 is significantly lower than that of the doping process 380 used to form the P+ contact 400 (see FIG. Figure 8 ) of the P-type dopant material. Thus, the resulting charging layer 500 formed by the doping process 490 is substantially less doped (e.g., has a substantially lower dopant concentration level) than the P+ contact 400. It should also be understood that the dopant concentration levels in the various doping regions of the APD 100 may be adjusted according to breakdown conditions (e.g., to avoid breakdown) and / or to produce a desired electric field distribution.

[0037] It should be noted that as another inherent result of the unique manufacturing process described above, the charging layer 500 is formed directly adjacent to the optically absorptive layer 320. For example, the etching of the opening 300 (see Figure 5 ) and then selectively growing the optical absorption layer 320 in the opening 300 allows the “right side” of the optical absorption layer 32 to directly abut against a portion of the semiconductor layer 230. Thereafter, the doping process 490 converts the portion of the semiconductor layer 230 directly abutting against the “right side” of the optical absorption layer 320 into the charging layer 500, while the layers 330-350 protect the optical absorption layer 320 from being doped. In this way, the charging layer 500 is formed to directly abut against the optical absorption layer 320 by self-alignment.

[0038] It should also be understood that the width of the charging layer 500 (e.g., the horizontal dimension in the X direction) can be flexibly configured. For example, the width of the charging layer 500 is at least partially determined by the width of the opening 480, and the width of the opening 480 is defined by the patterned photoresist mask 470. In embodiments where the width of the charging layer 500 is desired to be slightly smaller, the patterned photoresist mask 470 can be formed to define a narrower opening, which will expose a smaller amount of the semiconductor layer 230 thereunder, and this allows the resulting charging layer 500 (formed by the doping process 490) to have a narrower width. Conversely, in embodiments where the width of the charging layer 500 is desired to be slightly larger, the patterned photoresist mask 470 can be formed to define a wider opening, which will expose a greater amount of the semiconductor layer 230 thereunder, and this allows the resulting charging layer 500 (formed by the doping process 490) to have a wider width.

[0039] Reference now Fig.11 , the patterned photoresist mask 470 is removed, for example, by a photoresist ashing or photoresist stripping process. Thereafter, a deposition process 510 is performed to form a passivation layer 520 on other components of the APD 100. For example, the deposition process 510 may include a CVD process, a PVD process, an ALD process, or a combination thereof, so as to deposit a dielectric material as the passivation layer. In some embodiments, the deposited dielectric material may include a silicon nitride material or a silicon oxide material. The resulting passivation layer 520 protects the components of the APD 100 thereunder from contaminant particles and / or moisture.

[0040] Figure 2-Figure 11 The process flow according to the first embodiment of the present disclosure is shown. Figure 12-Figure 18 The process flow according to the second embodiment of the present disclosure is shown. For the sake of consistency and clarity, similar components in the first and second embodiments will be labeled the same.

[0041] Reference now Fig.12 , APD 100 is above reference Figure 8 That is, the APD100 has gone through the same manufacturing stages discussed above. Figure 2-Figure 8 The processing steps are as follows to form the optical absorption layer 320, the layers 330-350 above the optical absorption layer 320, and the P+ contact 400. Since these processes are substantially the same in the first and second embodiments, the discussion of these processes is not repeated here for simplicity.

[0042] Reference now Fig.13, the patterned photoresist mask 370 is removed, for example, by a photoresist ashing or photoresist stripping process. Thereafter, another patterned photoresist mask 540 is formed over portions of the APD 100. For example, the patterned photoresist mask 540 is formed to cover the “left side” of the APD 100, including over the P+ contact 400, over portions of the optical absorption layer 320 and the layers 330-350 thereover, and over portions of the semiconductor layer 230 that are on the “right side” of the optical absorption layer 320. The patterned photoresist mask 540 is formed to define an opening 480 that exposes a portion of the semiconductor layer 230 that is directly adjacent to the “right side” of the optical absorption layer 320. The opening 480 also exposes a portion of the layer 350. The remaining components of the APD 100 are covered by the patterned photoresist mask 540.

[0043] Thereafter, a doping process 550 is performed to convert the portions of the semiconductor layer 230 that are not covered by the patterned photoresist mask 540 into the charge layer 500. For example, the doping process 550 may implant a P-type dopant material into the exposed portions of the semiconductor layer 230. The patterned photoresist mask 540 and the layers 330-350 protect the underlying layers from being implanted with the dopant material. As a result, the portions of the semiconductor layer 230 exposed by the opening 480 are transformed into the charge layer 500, while the portions of the semiconductor layer 230 covered by the patterned photoresist mask 540 remain substantially undoped at this stage of fabrication. The optical absorption layer 320 also remains undoped due to the protection provided by the layers 330-350. As described above, the charge layer 500 is significantly less doped (e.g., has a substantially lower dopant concentration level) than the P+ contact 400, even though they each contain a P-type dopant.

[0044] Reference now Fig.14 , the patterned photoresist mask 540 is removed, for example, by a photoresist ashing or photoresist stripping process. Thereafter, a sputtering process 570 is performed on the APD 100 to form a spacer layer 580. In some embodiments, the sputtering process 570 forms silicon oxide as the material of the spacer layer 580. The sputtering process 570 is performed so that the spacer layer 580 covers the exposed upper and side surfaces of the APD 100, including the upper and side surfaces of the exposed portions of the optical absorption layer 320 and layers 330-350. In some embodiments, the sputtering process 570 is configured so that the spacer layer 580 has a substantially uniform thickness. It should be understood that this thickness of the spacer layer 580 can be used to control the width of the spacer to be formed in the subsequent process discussed below.

[0045] Reference now Fig.15, one or more etching processes 590 are performed to transform the spacer layer 580 into the spacer layer. In more detail, the one or more etching processes 590 may include one or more isotropic etching processes (e.g., wet etching) to etch away portions of the spacer layer 580. The isotropic etching process is configured to have a sufficiently high etching selectivity between the spacer layer 580 and the remaining components of the APD 100 (e.g., the P+ contact 400, the layer 350, the charging layer 500, and the semiconductor layer 230). In this way, the etching of the spacer layer 580 does not substantially affect the remaining components of the APD 100. The portion of the spacer layer 580 disposed on the exposed side surfaces of the optical absorption layer 320 and the layers 330-350 is substantially higher than the portion of the spacer layer 580 disposed elsewhere on the APD 100. As a result, after the etching process 590 has been performed, a majority of the spacer layer 580 disposed on the exposed side surfaces of the optical absorption layer 320 and the layers 330-350 will remain. These remaining portions of the spacer layer 580 are hereinafter labeled as spacers 580A and 580B. The spacers 580A and 580B can each have a width 600 (eg, a horizontal dimension measured in the X direction). Similarly, when the spacer layer 580 is formed by the above reference Fig.14 The value of width 600 is determined by the thickness of spacer layer 580 when formed by the sputtering process 570 discussed.

[0046] Reference now Fig.16 , a patterned photoresist mask 610 is formed on portions of the APD 100. For example, the patterned photoresist mask 610 is formed to cover the "left side" of the APD 100, including on the P+ contact 400, on portions of the optical absorption layer 320 and the layers 330-350 above, and on the semiconductor layer 230. The patterned photoresist mask 610 is formed to define an opening 620 that exposes the charging layer 500 as well as portions of the layer 350 and the spacer 580B. Thereafter, a doping process 630 is performed to convert the exposed portions of the charging layer 500 into the N+ contact 450. For example, the doping process 630 can implant an N-type dopant material into the exposed portions of the charging layer 500. The patterned photoresist mask 610 protects the underlying layers from being implanted with the dopant material. The spacer 580B also protects the portions of the charging layer 500 below it from being implanted with the dopant material.

[0047] As a result of the doping process 630, the exposed portion of the charging layer 500 is transformed into the N+ contact 450, while the portion of the semiconductor layer 230 covered by the patterned photoresist mask 610 remains substantially undoped at this stage of manufacturing. The remaining portion of the charging layer 500 below the spacer 580B is also substantially unaffected by the doping process 630. In other words, at this stage of manufacturing, the remaining portion of the charging layer 500 is still lightly P-doped. In this way, the charging layer 500 here achieves a substantially elongated and narrow profile (e.g., having a width 600) and directly abuts the optical absorption layer 320. This physical property of the charging layer 500 is an inherent result of performing the unique manufacturing process flow of the present disclosure. For example, the charging layer 500 here is formed in a self-aligned manner so that its horizontal position is defined by the spacer 580B. Since the spacer 580B is formed to directly abut the optical absorption layer 320, the charging layer 500 naturally inherits the horizontal position of the spacer 580B and is therefore also directly abutting the optical absorption layer 320. Furthermore, since the charging layer 500 is defined by the spacer 580B, the charging layer 500 also substantially inherits the width 600 of the spacer 580B. In this way, a lightly P-doped narrow charging layer 500 having a substantially vertical shape is formed directly adjacent to the optical absorption layer 320, which is one of the unique physical characteristics of the present disclosure.

[0048] Reference now Fig.17 , for example, by removing the patterned photoresist mask 610 through a photoresist ashing or photoresist stripping process. Thereafter, another patterned photoresist mask 650 is formed. The patterned photoresist mask 650 exposes the semiconductor layer 230 (previously covered by the patterned photoresist mask 610, see Fig.16 ), but covering the rest of the APD 100. Thereafter, a doping process 660 is performed. The doping process 660 can implant an N-type dopant material into the semiconductor layer 230. The patterned photoresist mask 650 protects the underlying layers from being implanted with the dopant material. As a result, the semiconductor layer 230 is transformed into an N++ contact 450A. It should be understood that the doping process 660 can use a larger dose of N-type dopant than the doping process 630. As a result, the dopant concentration level of the N-type dopant in the N++ contact 450A is greater than the dopant concentration level of the N-type dopant in the N+ contact 450. It should be understood that the N+ contact 450 and the N++ contact 450A can collectively correspond to the N+ contact discussed above with reference to FIG. 1.

[0049] Reference now Fig.18, the patterned photoresist mask 650 is removed, for example, by a photoresist ashing or photoresist stripping process. Thereafter, the above-described deposition process 510 is performed to form a passivation layer 520 on the other components of the APD 100. For example, the deposition process 510 may include a CVD process, a PVD process, an ALD process, or a combination thereof, so as to deposit a dielectric material as the passivation layer. In some embodiments, the deposited dielectric material may include a silicon nitride material or a silicon oxide material. The resulting passivation layer 520 protects the components of the APD 100 thereunder from contaminant particles and / or moisture.

[0050] Figure 2-Figure 11 and Figure 12-Figure 18 1 and 2 show the process flow according to the first and second embodiments of the present disclosure, wherein before performing the various doping processes described above to form the P+ contact 400 and the N+ contact 450, etching of the semiconductor layer 230 is performed (eg, Figure 5 In other words, in the above reference Figure 2-Figure 18 In the first and second embodiments discussed, the doping process for forming the P+ contact 400 and the N+ contact 450 is performed after the selective growth process to form the optical absorption layer 320. However, unless otherwise required, such a process sequence is not limiting. For example, Figure 19-Figure 33 (which will be discussed in more detail below) shows a process flow according to a third embodiment of the present disclosure, in which a doping process for forming an N+ contact and a P+ contact is performed before performing a selective growth process 320 to form an optical absorption layer 320. For reasons of consistency and clarity, similar components in the first, second, and third embodiments will be labeled the same.

[0051] Reference now Fig.19 , APD 100 is above reference Figure 2 That is, the APD 100 includes the substrate 210 , the insulator layer 220 , and the semiconductor layer 230 , but other manufacturing processes have not yet been performed on the APD 100 .

[0052] Reference now Fig. 20 , a patterned photoresist mask 680 is formed. The patterned photoresist mask 680 exposes a portion of the semiconductor layer 230 but covers the rest of the APD 100.

[0053] Reference now Fig.21, a doping process 690 is performed. The doping process 690 can inject a P-type dopant material into the semiconductor layer 230. The patterned photoresist mask 680 protects the semiconductor layer 230 below it from being injected with the dopant material. As a result, the exposed portion of the semiconductor layer 230 is transformed into a P+ contact 400. It can be understood that the P+ contact 400 corresponds to the above reference Figure 1A and Figure 1B The P+ contact discussed.

[0054] Reference now Fig. 22 The patterned photoresist mask 680 is removed, for example, by a photoresist stripping or ashing process. Thereafter, a patterned photoresist mask 700 is formed. The patterned photoresist mask 700 exposes a portion of the semiconductor layer 230 but covers the rest of the APD 100.

[0055] Reference now Fig.23 , a doping process 710 is performed. The doping process 710 can implant a P-type dopant material into the exposed portion of the semiconductor layer 230. The patterned photoresist mask 700 protects the P+ contact 400 and the portion of the semiconductor layer 230 therebelow from being implanted with the dopant material. Fig.17 Doping process 710 is performed with a similar dose as doping process 660 discussed above. As a result, the exposed portion of semiconductor layer 230 is transformed into N++ contact 450A, similar to the above reference numeral 450A. Fig.17 N++ contact 450 discussed.

[0056] Reference now Fig.24 , one or more etching processes 720 are performed on the APD 100. The one or more etching processes 720 are performed using the patterned mask layer 730 as a protective mask so that portions of the APD 100 disposed below the patterned mask layer 730 are not etched by the one or more etching processes 720. In some embodiments, the patterned mask layer 730 may include a dielectric material. The patterned mask layer 730 defines an opening 740 that extends vertically downward through the semiconductor layer 230 and the P+ contact 400 partially by the one or more etching processes 720. It should be noted that after the one or more etching processes 720 have been performed, upper surfaces and side surfaces of portions of the semiconductor layer 230 and portions of the P+ contact 400 remain exposed by the opening 740.

[0057] Reference now Fig.25 , a selective growth process 310 is performed on the APD 100 (see above Figure 6740) to form optical absorption layer 320 in opening 740. As described above, optical absorption layer 320 may include a germanium material. After optical absorption layer 320 is formed in opening 740, layers 330, 340, and 350 are also formed over optical absorption layer 320 in opening 740. For example, layer 330 may include a semiconductor material such as silicon, layer 340 may include a dielectric material such as silicon oxide, and layer 350 may include another semiconductor material such as polysilicon. Compared to optical absorption layer 320, layers 330-350 may have a substantially smaller thickness.

[0058] Reference now Fig.26 , the patterned mask layer 730 is removed. Thereafter, a patterned photoresist mask 750 is formed on the APD 100. The patterned photoresist mask 750 exposes the semiconductor layer 230 and a portion of the layer 350, but covers the rest of the APD 100. In other words, the patterned photoresist mask 750 defines an opening 760, which exposes a portion of the upper surface of the semiconductor layer 230 and the upper surface of the layer 350, as well as a portion of the side surfaces of the layers 330-350 and the side surface of the optical absorption layer 320.

[0059] Reference now Fig. 27 , a doping process 770 is performed through the opening 760. In more detail, the doping process 770 injects a P-type dopant material into the portion of the semiconductor layer 230 exposed by the opening 760. The patterned photoresist mask 750 and layers 330-350 protect the layers beneath them from being injected with the dopant material. As a result, the portion of the semiconductor layer 230 exposed by the opening 760 is transformed into the charging layer 500, while the portion of the semiconductor layer 230 covered by the optical absorption layer 320 remains substantially undoped at this stage of manufacturing. Due to the protection provided by the layers 330-350, the optical absorption layer 320 itself also remains substantially undoped. Likewise, the dosage of the P-type dopant material of the doping process 770 is substantially lower than that of the doping process 690 (see Fig.21 ) of the P-type dopant material. Thus, the resulting charging layer 500 formed by the doping process 770 is substantially less doped (eg, has a substantially lower dopant concentration level) than the P+ contact 400.

[0060] Similar to the other embodiments described above, one of the inherent results of the third embodiment of the present disclosure is that the charging layer 500 is still formed directly adjacent to the optical absorption layer 320. For example, the optical absorption layer 320 is formed before the charging layer 500, and the charging layer 500 is formed by doping the portion of the semiconductor layer 230 that is immediately adjacent to the optical absorption layer 320 in a self-aligned manner. Therefore, the optical absorption layer 320 and the charging layer 500 can achieve a substantially vertical interface extending in the Z direction. Note that another inherent result of the manufacturing process of the third embodiment is that after the charging layer 500 is formed, the substantially undoped portion 230A of the semiconductor layer 230 is still disposed below the optical absorption layer 320. This is because during the doping process 770, this portion of the semiconductor layer 230A is protected from being doped by the optical absorption layer 320 and layers 330-350 above it.

[0061] Reference now Fig.28 , for example, by removing the patterned photoresist mask 750 through a photoresist ashing or photoresist stripping process. Thereafter, a sputtering process 570 is performed on the APD 100 (see above for reference). Fig.14 5 (discussed) to form the spacer layer 580. In some embodiments, the sputtering process 570 forms silicon oxide as the material of the spacer layer 580. The sputtering process 570 is performed so that the spacer layer 580 covers the exposed upper surface and side surfaces of the APD 100, including the upper surface and side surfaces of the exposed portions of the optical absorption layer 320 and the layers 330-350. In some embodiments, the sputtering process 570 is configured so that the spacer layer 580 has a substantially uniform thickness. As described above, this thickness of the spacer layer 580 can be used to control the width of the spacers that will be subsequently formed on the side surfaces of the optical absorption layer 320 and the layers 330-350.

[0062] Reference now Fig.29 , performing etching process 590 (see above Fig.15Discussion) to transform the spacer layer 580 into spacer layers 580A and 580B. For example, the one or more etching processes 590 may include one or more isotropic etching processes to etch away portions of the spacer layer 580 disposed on the upper surfaces of the P+ contact 400, layer 350, charging layer 500, and N++ contact 450A. The spacers 580A and 580B on the side surfaces of the optical absorption layer 320 and layers 330-350 are mostly retained because the etching process 590 only affects the upper segments of these spacers 580B and 580A. Also as described above, the initial thickness of the spacer layer 580 (when it is formed by the sputtering process 570) corresponds to the width 600 of each of the spacer layers 580A and 580B. However, it will be understood that in the third embodiment, the exact value of the width 600 of each spacer 580A and 580B is not necessarily the same as the width 600 of each spacer 580 in the second embodiment (see Fig.15 ).

[0063] Reference now Fig.30 , a patterned photoresist mask 780 is formed on a portion of the APD 100. For example, the patterned photoresist mask 780 is formed to cover the P+ contact 400, a portion of the optical absorption layer 320 and the layers 330-350 above, and the N++ contact 450A. Thus, the patterned photoresist mask 780 defines an opening 790 that exposes the charging layer 500 and a portion of the layer 350 and the spacer 580B.

[0064] Reference now Fig.31 , a doping process 800 is performed to convert the portion of the charging layer 500 that is not covered by the patterned photoresist mask 780 or the spacer 580B into an N+ contact 450. For example, the doping process 800 can inject an N-type dopant material into the exposed portion of the charging layer 500. The patterned photoresist mask 780 and the layers 330-350 and the spacer 580B protect the layers below them from being injected with the dopant material. As a result, the exposed portion of the charging layer 500 is converted into an N+ contact 450, while the portion of the charging layer 500 that is on the "right side" of the optical absorption layer 320 and covered by the spacer 580B remains substantially undoped at this stage of manufacturing. Note that unlike the doping process 710 (see Fig.23 ), the doping process 800 can be configured to use a lighter implant dose. Thus, the N+ contact 450 formed as a result of the doping process 800 has a lower dopant concentration level than the N++ contact 450A, even though both the N+ contact 450 and the N++ contact 450A are doped with N-type dopants. It should be understood that the N+ contact 450 and the N++ contact 450A collectively correspond to the N+ contact 450A described above with reference to FIG. Figure 1A and Figure 1BN+ contact discussed.

[0065] Reference now Fig.32 , the patterned photoresist mask 780 is removed, for example, by a photoresist ashing process or a photoresist stripping process. Thereafter, one or more etching processes 810 are performed to form a plurality of openings. For example, one or more etching processes 810 may etch openings 820 into the P+ contact 400, and etch openings 821 into the N+ contact 450 and the N++ contact 450A.

[0066] Reference now Fig.33 , execute the above reference Fig.11 The deposition process 510 discussed above is performed to form a passivation layer 520 on the other components of the APD 100. For example, the deposition process 510 may include a CVD process, a PVD process, an ALD process, or a combination thereof, to deposit a dielectric material as the passivation layer. In some embodiments, the deposited dielectric material may include a silicon nitride material or a silicon oxide material. The passivation layer 520 completely fills the openings 820-821. The resulting passivation layer 520 protects the components of the APD 100 below it from contaminant particles and / or moisture.

[0067] Now refer to Fig.34 and Fig.35 Discussing the various dimensions and physical characteristics of the APD 100 in more detail, Fig.34 and Fig.35 1 and 10 are respectively a partial cross-sectional side view and a planar top view of the APD 100 according to an embodiment of the present disclosure. Fig.34 and Fig.35 The APD 100 shown corresponds largely to the APD 100 described above with reference to Figure 2-Figure 11 The APD is fabricated in accordance with the first embodiment of the manufacturing process flow discussed. In this particular embodiment, an N+ contact 450 is formed, but an N++ contact is not formed. In addition, Fig.34 The particular embodiment shown does not use spacers 580A and 580B, which are used in accordance with the second embodiment (see Fig.18 ) and the third embodiment (see Fig.33 ) is implemented in the embodiment of the APD 100 manufactured according to the second and third embodiments of the manufacturing process flow. However, it should be understood that, unless otherwise stated, the following discussion on the size and other physical characteristics of the APD 100 is also applicable to the APD 100 manufactured according to the second and third embodiments of the manufacturing process flow. It should also be understood that Figure 34-Figure 35 Conductive pads 840 and 841 are shown respectively over P+ contact 400 and N+ contact 450. These conductive pads 840 and 841 are implemented to provide electrical connections to APD 100.

[0068] like Figure 34-Figure 35As shown, the charging layer 500 is directly adjacent to (e.g., directly abuts) the optical absorption layer 320 and the segment 230A of the semiconductor layer 230. In other words, the side surface of the charging layer 500 forms an interface 850 with the side surface of the optical absorption layer 320 and the segment 230A, wherein the interface 850 extends substantially vertically in the Z direction. This is one of the unique physical characteristics of the APD 100 manufactured according to the present disclosure. Unlike the APD 100 herein, APDs that are not manufactured using the unique manufacturing process flow of the present disclosure typically rely on photolithography to define the positions of their optical absorption layers and charging layers. Unfortunately, due to the limitations of photolithography in terms of precision, especially as the size of semiconductor devices continues to shrink, one result is that the optical absorption layer and the charging layer may not be directly adjacent to each other. For example, there may be a buffer region (e.g., an undoped region) between the optical absorption layer and the charging layer. Such a buffer region is not configured to detect light, and therefore it constitutes wasted space in the APD, which is undesirable.

[0069] Another possible consequence of relying on lithography to define the positions of the optical absorption layer and the charging layer is that the charging layer may not have a completely vertical side surface facing the optical absorption layer. Instead, the charging layer may have a segmented side surface, where parts of the side surface protrude further into the segment of the semiconductor layer below the optical absorption layer. Unfortunately, this may result in the strongest electric field being in the segment of the semiconductor layer below the optical absorption layer, which means that the electric field in the optical absorption layer itself may not be strong enough. As a result, the performance of the APD may be reduced.

[0070] In contrast, the APD 100 herein utilizes a self-aligned process to define the position of the optical absorption layer 320 and the charging layer 500. This allows the charging layer 500 to be formed directly adjacent to the optical absorption layer 320 and the segment 230A while achieving a substantially linear interface 850 extending vertically upward. One advantage is the elimination of the buffer zone, which preserves valuable device space and improves optical detection efficiency. Another benefit is that the strongest electric field is maintained within the optical absorption layer 320, which helps to improve the performance of the APD 100.

[0071] It should be noted that although Figure 34-Figure 35A different interface 850 is shown, but this is for reasons of simplicity. In an actual manufactured device, the interface 850 may have a more gradient-like profile. This is because dopant diffusion may occur between the charging layer 500 (e.g., comprising silicon doped with a P-type dopant) and the optical absorption layer 320 (e.g., comprising substantially undoped germanium), and may also occur between the charging layer 500 and the segment 230A (e.g., comprising substantially undoped silicon). Due to dopant diffusion, the interface 850 in an actual manufactured APD 100 may not appear as a one-dimensional line, but may instead span a distance horizontally in the X direction. In other words, the interface 850 may have a width measured in the X direction, within which the dopant concentration level increases toward the charging layer 500 and decreases toward the optical absorption layer 320 (e.g., thereby presenting a gradient-like profile). In some embodiments, such a width may be the maximum width W of the charging layer 500. C About 8%-12% of the maximum width W C The interface 850 itself may be in the range of between about 50 nanometers (nm) and about 100 nm. Regardless of the exact amount of the horizontal span of the interface 850 or its gradient-like profile, it can still be appreciated that the interface 850 extends substantially vertically and linearly in the Z direction, which is one of the unique physical properties of the APD 100 of the present disclosure.

[0072] Figure 34-Figure 35 Also shown is the horizontal dimension W of the optical absorption layer 320. O and the horizontal dimension W of the undoped semiconductor layer 230 disposed between the charging layer 500 and the N+ contact 450 A , where W O and W A are all measured in the X direction. In some embodiments, W O Greater than or equal to W A , and W A Basically greater than W C In some embodiments, the horizontal dimension W O In the range between about 300 nm and about 1000 nm, the horizontal dimension W A In the range between about 200 nm and about 400 nm.

[0073] Fig.34 Also shown are multiple horizontal dimensions S1, S2, S4, S5, S P and S N In more detail, the horizontal dimension S PHorizontal dimension S1 corresponds to the width of the portion of the P+ contact 400 disposed on the “left” side of the opening 260 (and away from the optical absorption layer 320). Horizontal dimension S2 corresponds to the width of the portion of the P+ contact 400 disposed on the “right” side of the opening 260 (e.g., the portion directly adjacent to the optical absorption layer 320). Horizontal dimension S4 corresponds to the width of the narrower upper portion of the charging layer 500 directly adjacent to the optical absorption layer 320. Horizontal dimension S5 corresponds to the width of the opening 261. Horizontal dimension S N corresponds to the width of the portion of the N+ contact 450 disposed on the “right side” of the opening 261 (and away from the optical absorption layer 320). In some embodiments, S1 need not be substantially different from S5, but S1 and S5 are greater than or equal to W. O . In some embodiments, S1 is much larger than S2 and S4, but S2 and S4 need not be substantially different from each other. In some embodiments, S1 is in a range between about 550 nm and about 650 nm, and S2 is in a range between about 40 nm and about 60 nm. It should be understood that these size ranges are not randomly selected, but are specifically configured to optimize device performance. For example, these ranges are configured to appropriately adjust the electric field strength and / or optical absorption efficiency of various components of the APD 100.

[0074] One of the benefits of the present disclosure is that the horizontal dimension W can be precisely controlled. A and W C This is because the horizontal dimension W A and W C The self-aligned process discussed above is defined rather than relying solely on the capabilities of photolithography. Therefore, the uniformity of the process can be improved. For example, the multiple APDs 100 formed using the process flow of the present disclosure have a horizontal dimension W. A and W C can have substantially similar values, which is desirable from a quality control standpoint. In contrast, APDs formed by other process flows may have significantly greater variation between different APDs in terms of the dimensions of their optically absorbing and charging layer regions.

[0075] Fig.34Also shown are a plurality of vertical dimensions V1, V2, V3, V4, and V5 (each measured in the Z direction). For example, V1 is a vertical dimension corresponding to a vertical protrusion of the optical absorption layer 320 above the charging layer 500. For example, the uppermost surface 860 of the optical absorption layer 320 is located at a higher position in the vertical direction than the uppermost surface 870 of the charging layer 500. The difference in distance between these uppermost surfaces 860 and 870 is reflected by the vertical dimension V1. Note that the N+ contact 450 has an uppermost surface 880 that has a substantially similar vertical height as the uppermost surface 870 of the charging layer 500. Therefore, it can be said that the vertical dimension V1 also corresponds to the vertical distance between the uppermost surface 860 of the optical absorption layer 320 and the uppermost surface 880 of the N+ contact 450.

[0076] V2 is a vertical dimension corresponding to the vertical protrusion of the N+ contact 450 above the semiconductor layer 230. For example, the uppermost surface 880 of the N+ contact 450 is at a higher position in the vertical direction than the uppermost surface 890 of the semiconductor layer 230. The difference in distance between these uppermost surfaces 880 and 890 is reflected by the vertical dimension V2. It should be noted that the N+ contact 450 has another upward-facing surface 881 exposed by the opening 261, and the upward-facing surface 881 is at the same vertical height as the uppermost surface 890 of the semiconductor layer 230. Therefore, it can be said that the vertical dimension V2 also corresponds to the vertical distance between the uppermost surface 880 and the upward-facing surface 881 of the N+ contact 450. It should also be understood that the above discussion on V2 can be applied not only to the N+ contact 450, but also to the P+ contact 400.

[0077] V3 is a vertical dimension corresponding to the distance between the upward-facing surface 881 and the uppermost surface 900 of the insulator layer 220, which also coincides with the lowermost surface of the N+ contact 450. V4 is a vertical dimension corresponding to the distance between the uppermost surface 900 and the uppermost surface 910 of the substrate 210, which also coincides with the lowermost surface of the insulator layer 220. In other words, V4 corresponds to the thickness of the insulator layer 220. V5 is a vertical dimension corresponding to the distance between the uppermost surface 910 and the lowermost surface 911 of the substrate 210. In other words, V5 corresponds to the thickness of the substrate 210. It should also be understood that the above discussion about V3 can be applied not only to the N+ contact 450, but also to the P+ contact 400.

[0078] It should be understood that the vertical dimension V1 depends on the selective growth process 310 described above (see Figure 6) process configuration. For example, a longer growth time may result in a higher V1. In the embodiment shown, V1 is a positive value, which means that the uppermost surface 860 is more vertically elevated than the uppermost surface 870. However, this need not be the case in alternative embodiments. In other words, in some embodiments, the uppermost surface 860 may not be elevated in the vertical direction compared to the uppermost surface 870. At the same time, the vertical dimensions V2 and V3 are configured based on the optical wavelength of light to be detected by the APD 100, and the vertical dimensions V4 and V5 can be flexibly configured based on the manufacturing process needs.

[0079] Another unique physical characteristic of the APD 100 herein relates to the relative vertical arrangement between the bottommost surface 861 of the optical absorption layer 320 and the upper-facing surface 890 (of the semiconductor layer 230) or the upper-facing surface 881 (of the N+ contact 450) or the upper-facing surface 920 (of the P+ contact 400). In more detail, an APD formed by a manufacturing process other than the present disclosure may simultaneously etch openings for its optical absorption layer and the N+ and P+ contacts. That is, the openings in which the optical absorption layer is formed are etched simultaneously with the openings in the N+ and P+ contacts, and the openings are etched in the same type of material (e.g., silicon). Thus, an optical absorption layer formed by a manufacturing process other than the present disclosure will typically have a bottommost surface that is substantially coplanar or at a similar vertical height with the upward-facing surfaces of the P+ and N+ contacts exposed by the openings in the P+ and N+ contacts.

[0080] In contrast, the unique manufacturing process flow of the present disclosure either etches the openings 260-261 (see Figure 3 ) to obtain the P+ contact 400 and the N+ contact 450, and then etch the opening 300 for the optical absorption layer 320 (see Figure 5 ), as in the case of the first and second embodiments of the process flow herein, either in etching the etch openings 820-821 for the P+ contact, N+ contact 450A (see Fig.32 ) before etching the opening 740 for the optical absorption layer 320 (see Fig.24), as is the case with the third embodiment of the process flow herein. Since the openings for the optical absorption layer 320 and the P+ contact 400 and the N+ contact 450 are etched at different times, the depths of these openings can be different. In fact, it may be desirable to configure the opening 300 or the opening 740 for the optical absorption layer 320 to have a deeper depth than the openings for the P+ contact 400 and the N+ contact 450, thereby maximizing the optical detection efficiency of the APD 100. Therefore, one of the inherent results of the unique manufacturing process flow herein is that the bottommost surface 861 of the optical absorption layer 320 is located at a lower vertical height than the upper surface 920 of the P+ contact 400 located below the opening 260 and / or than the upper surface 890 of the semiconductor layer 230 or the upper surface 881 of the P+ contact 450 located below the opening 261. This unique physical characteristic, alone or in combination with the other unique physical features discussed above, can be used to determine evidence of whether the APD is manufactured using the unique process flow of the present disclosure.

[0081] It should also be understood that while the segment 230A of the semiconductor layer 230 located below the optical absorption layer 320 primarily contains undoped silicon, some portions thereof may also contain doped materials. For example, at or near the interface between the P+ contact 400 and the segment 230A of the semiconductor layer 230, dopant diffusion may occur such that a P-type dopant may diffuse from the P+ contact 400 into the portion of the segment 230A located near the interface. As a result, the portion of the segment 230A located near the P+ contact 400 may be slightly doped with a P-type dopant even though the rest of the segment 230A remains substantially undoped.

[0082] It should also be understood that the APD 100 (or at least a portion thereof) may function similarly to a waveguide. Assume W = S2 + W O +S4, h=V3, and H=V2+V3. Also assume Potel = total optical power, and P opt In the range between about 0 dBm and about 10 dBm. Under the single-mode condition of the waveguide, the following conditions need to be met:

[0083]

[0084] In addition, for S1 and S5:

[0085] This means that the total energy of the optical power expansion on both sides of the platform needs to be less than 0.01%, which is an optional condition.

[0086] Under multimode conditions in the waveguide, for S1 and S5:

[0087] This is an optional condition.

[0088] It should further be understood that the exact physical appearance of the optically absorptive layer 320 and / or its relative arrangement with respect to the charging layer 500 may be configured differently in different embodiments. Figure 36A-36H Schematic partial cross-sectional side views of portions of the APD 100 including the optical absorption layer 320 according to different embodiments of the present disclosure are respectively shown.

[0089] In more detail, Fig.36A The optical absorption layer 320 is shown to have a substantially rectangular shape, wherein both the uppermost surface and the lowermost surface of the optical absorption layer 320 are substantially flat. Fig.36B The optical absorption layer 320 is shown to have a polygonal shape, wherein the uppermost surface of the optical absorption layer 32 is substantially flat, but the bottom of the optical absorption layer has a trapezoidal shape. Fig.36C The optical absorption layer 320 is shown to have an arbitrary shape, wherein the uppermost surface of the optical absorption layer 320 is substantially rounded or curved downward (eg, has a concave shape), but the lowermost surface of the optical absorption layer 320 is substantially flat. Fig.36D An optical absorption layer 320 having a polygonal shape similar to Fig.36B , but the optical absorption layer 320 is spaced apart from the charging layer 500. For example, a portion of the semiconductor layer 230A is disposed between the optical absorption layer 320 and the charging layer 500. Fig.36E The optical absorption layer 320 having a polygonal shape is shown, wherein both the upper portion and the bottom portion of the optical absorption layer 320 have a trapezoidal shape. Fig.36F An optical absorption layer 320 having a polygonal shape similar to Fig.36B , but the optical absorption layer 320 is spaced apart from the P+ contact 400. For example, a portion of the semiconductor layer 230A is disposed between the optical absorption layer 320 and the P+ contact 400. Figure 36G An optical absorption layer 320 having an arbitrary shape is shown, wherein the uppermost surface of the optical absorption layer 320 is substantially rounded or curved upward (eg, has a convex shape), and the lowermost surface of the optical absorption layer 320 is substantially rounded or curved downward (eg, has a convex shape). Fig.36H The optical absorption layer 320 having an arbitrary shape is shown, wherein the uppermost surface of the optical absorption layer 320 is substantially rounded or curved upward (e.g., has a convex shape), and the lowermost surface of the optical absorption layer 320 is substantially flat. In addition, the passivation layer is implemented not only on the uppermost surface of the optical absorption layer 320, but also on the uppermost surface of the P+ contact 400 and the uppermost portion of the charging layer 500. The passivation layer 930 protects the charging layer 500 from being exposed to air or other pollution sources.

[0090] Reference now Fig.37 , a light intensity distribution 940 is shown in a cross-sectional side view of APD 100. Light intensity distribution 940 is associated with optical radiation (e.g., in the form of a light beam) injected into APD 100 (e.g., injected into optical absorption layer 320). To ensure that the optical radiation is completely absorbed by optical absorption layer 320, various dimensions of APD 100 are specifically configured. For example, dimension H1 corresponds to the vertical protrusion of P+ contact 400. In some embodiments, H1 is substantially equal to the above reference Fig.34 Dimension H3 corresponds to the overall height of optical absorption layer 320. Dimension H4 corresponds to the desired length (in the Z direction) of optical intensity distribution 940. In some embodiments, H3 is greater than or equal to H4 because H3 is desired to cover optical intensity distribution 940.

[0091] The above discussion relates to implementing the APD 100 as part of an image sensor device. However, it should be understood that the APD 100 (or its components) can also be used to produce three-dimensional integrated circuits (3DICs). For example, a 3DIC manufacturing system may include an optical communication path in which a photodetector is used. Such a photodetector is configured to detect light, and it can operate in a manner similar to the APD 100 described above. Therefore, in some embodiments, the APD 100 can be implemented as a substitute for a photodetector in an optical communication path of a 3DIC manufacturing system. In such a system, the APD 100 can work with a waveguide component to establish an optical communication path. The structural arrangement of the APD 100 in such a system (e.g., as a photodetector in a 3DIC system) is otherwise substantially the same as the APD 100 described above.

[0092] Fig.38 1 is a flow chart showing a method 1000 of manufacturing an image sensor device (eg, APD) according to an embodiment of the present disclosure. The method 1000 includes step 1010 of forming a semiconductor layer over a substrate.

[0093] The method 1000 includes step 1020 of etching an opening in a semiconductor layer.

[0094] The method 1000 includes step 1030 of forming an optical absorption layer on the portion of the semiconductor layer exposed by the opening using a selective growth process.

[0095] Method 1000 includes step 1040 of forming a charging layer directly adjacent to the optical absorption layer. The charging layer forms a substantially straight interface with the optical absorption layer and a portion of the semiconductor layer.

[0096] The method 1000 includes step 1050 of forming a passivation layer over the optical absorption layer and the charging layer.

[0097] It should be understood that method 1000 may include further steps performed before, during, or after steps 1010-1050. For example, in some embodiments, method 1000 may include the step of forming a P-type contact in a first portion of the semiconductor layer disposed on a first side of the optical absorption layer by a first doping process. The optical absorption layer and a second portion of the semiconductor layer are protected from being doped by the first doping process. Method 1000 may also include the step of forming an N-type contact in a second portion of the semiconductor layer disposed on a second side of the optical absorption layer by a second doping process. The second side is opposite to the first side. The optical absorption layer and the P-type contact are protected from being doped by the second doping process. A charging layer is formed in a third portion of the semiconductor layer by a third doping process performed after the second doping process. In some embodiments, method 1000 may also include the step of forming a mask structure on the optical absorption layer before forming the P-type contact or the N-type contact. The mask structure protects the optical absorption layer from being doped by the first doping process and the second doping process.

[0098] As another example, in some embodiments, method 1000 may include the step of forming a P-type contact in a first portion of the semiconductor layer disposed on a first side of the optical absorption layer by a first doping process. The optical absorption layer and a second portion of the semiconductor layer are protected from being doped by the first doping process. A charging layer is formed in a first section of the second portion of the semiconductor layer by a second doping process performed after the first doping process. Method 1000 may also include the step of forming an N-type contact in a second section of a second portion of the semiconductor layer disposed on a second side of the optical absorption layer by a third doping process. The second side is opposite to the first side. The optical absorption layer and the P-type contact are protected from being doped by the second doping process. In some embodiments, method 1000 may further include the following steps: before forming a P-type contact, forming a mask structure over the optical absorption layer; after forming a charging layer, forming a spacer layer, wherein the spacer layer is formed over the P-type contact, over the mask structure, over the charging layer, and over a second portion of the semiconductor layer; converting the spacer layer into a first spacer and a second spacer disposed on opposite side surfaces of the mask structure; and forming another N-type contact in the first portion of the charging layer through a fourth doping process, wherein a second portion of the charging layer directly adjacent to the optical absorption layer is protected from the fourth doping process by at least the second spacer.

[0099] As another example, in some embodiments, method 1000 may include steps performed before forming the optical absorption layer. These steps may include the step of forming a P-type contact in the first portion of the semiconductor layer by a first doping process. Protecting the second portion and the third portion of the semiconductor layer from being doped by the first doping process. Method 1000 may also include the step of forming an N-type contact in the second portion of the semiconductor layer by a second doping process. The third portion of the semiconductor layer and the P-type contact are protected from being doped by the second doping process. The optical absorption layer and the charging layer are formed in the third portion of the semiconductor layer. In some embodiments, the method 1000 may further include the following steps: before forming the charging layer, forming a mask structure over the optical absorption layer, wherein the charging layer is formed by a third doping process that injects a P-type dopant into a third portion of the semiconductor layer directly adjacent to the optical absorption layer, and wherein the mask structure protects the optical absorption layer from being injected in the third doping process; forming a spacer layer after the third doping process, wherein the spacer layer is formed over the P-type contact, over the mask structure, over the charging layer, and over the N-type contact; converting the spacer layer into a first spacer and a second spacer disposed on opposite side surfaces of the mask structure; and forming another N-type contact in the first portion of the charging layer by a fourth doping process, wherein a second portion of the charging layer directly adjacent to the optical absorption layer is protected from the fourth doping process by at least the second spacer. For simplicity, these additional steps are not discussed in detail herein.

[0100] Fig.39 An integrated circuit manufacturing system 1100 according to an embodiment of the present disclosure is shown. The manufacturing system 1100 includes a plurality of entities 1102, 1104, 1106, 1108, 1110, 1112, 1114, 1116 ..., N connected by a communication network 1118. The network 1118 may be a single network, or may be a variety of different networks, such as an intranet and the Internet, and may include wired and wireless communication channels.

[0101] In one embodiment, entity 1102 represents a service system for manufacturing collaboration; entity 1104 represents a user, such as a product engineer who monitors a product of interest; entity 1106 represents an engineer, such as a process engineer who controls a process and related recipes, or an equipment engineer who monitors or adjusts the conditions and settings of a process tool; entity 1108 represents a metrology tool for IC testing and measurement; entity 1110 represents a semiconductor processing tool, such as an EUV tool for performing a lithography process; entity 1112 represents a virtual metrology module associated with processing tool 1110; entity 1114 represents an advanced process control module associated with processing tool 1110 and additional other processing tools; and entity 1116 represents a sampling module associated with processing tool 1110.

[0102] Each entity may interact with other entities and may provide integrated circuit manufacturing, process control and / or computing capabilities to other entities and / or receive these capabilities from other entities. Each entity may also include one or more computer systems for performing calculations and performing automation. For example, the high-level process control module of entity 1114 may include a plurality of computer hardware in which software instructions are encoded. The computer hardware may include a hard drive, a flash drive, a CD-ROM, a RAM memory, a display device (e.g., a monitor), an input / output device (e.g., a mouse and a keyboard). The software instructions may be written in any suitable programming language and may be designed to perform specific tasks.

[0103] The integrated circuit manufacturing system 1100 enables interaction between entities to implement integrated circuit (IC) manufacturing and advanced process control of IC manufacturing. In one embodiment, the advanced process control includes adjusting the processing conditions, settings and / or recipes of a processing tool applied to the associated wafer based on the metrology results.

[0104] In another embodiment, metrology results are measured from a subset of processed wafers according to an optimal sampling rate determined based on process quality and / or product quality. In yet another embodiment, metrology results are measured from selected fields and points of a subset of processed wafers according to optimal sampling fields / points determined based on various characteristics of process quality and / or product quality.

[0105] One of the capabilities provided by the IC manufacturing system 1100 can enable collaboration and information access in areas such as design, engineering and processing, metrology and advanced process control. Another capability provided by the IC manufacturing system 1100 can integrate systems between facilities, such as systems between metrology tools and processing tools. This integration enables facilities to coordinate their activities. For example, integrating metrology tools and processing tools can enable manufacturing information to be more effectively incorporated into the manufacturing process or advanced process control (APC) modules, and can enable the use of metrology tools integrated in related processing tools to obtain wafer data from online or on-site measurements.

[0106] The advanced lithography processes, methods, and materials described above can be used in many applications, including applications in which transistors are implemented as fin field effect transistors (FinFETs). For example, fins can be patterned to create relatively tight spacing between components, and the above disclosure is well suited for this. In addition, spacers used to form the fins (also referred to as mandrels) of the FinFET can be processed according to the above disclosure. It should also be understood that transistors can also be implemented using multi-channel devices, such as full-all-around (GAA) devices. To the extent that the present disclosure relates to fin structures or FinFET devices, such discussion may also apply to GAA devices.

[0107] The present disclosure may provide advantages over conventional devices. However, it should be understood that not all advantages are discussed herein, different embodiments may provide different advantages, and no embodiment requires a particular advantage. One advantage is improved device performance. In more detail, while other photonic devices rely on lithography to define the positions of the optical absorption layer and the charging layer region, the photonic device of the present disclosure utilizes a self-aligned process to define the positioning of the optical absorption layer and the charging layer region. Therefore, the charging layer can be formed directly adjacent to the optical absorption layer, so that the charging layer forms a substantially vertical linear interface with the optical absorption layer and the undoped silicon segment below it. The direct adjacency between the charging layer and the optical absorption layer eliminates the buffer zone between the charging layer and the optical absorption layer that is often present in some other types of photonic devices. Since such a buffer zone is not configured to detect light, it may constitute wasted space on the photonic device, resulting in lower optical detection efficiency of these other types of photonic devices. In contrast, the photonic device of the present disclosure provides enhanced optical detection efficiency, which is at least partially attributed to the elimination of the buffer zone.

[0108] In addition, certain other types of photonic devices that are not manufactured according to the unique process flow of the present disclosure may have nonlinear interfaces between the charging layer and the optical absorption layer and the undoped silicon segment below the optical absorption layer. For example, the charging layer and the optical absorption layer may form a first interface, and the charging layer and the undoped silicon segment may form a second interface, wherein the first interface and the second interface are not aligned (e.g., have different horizontal positions). This may result in an undesirable electric field distribution within the photonic device, which may also have an adverse effect on the performance of the photonic device. In contrast, as an inherent result of the unique self-aligned process flow performed herein, the charging layer can define an interface with the optical absorption layer and the underlying undoped silicon segment, wherein the interface extends in a substantially vertical direction. This allows the electric field within the photonic device to achieve a desired distribution, which in turn improves the performance of the photonic device. Another advantage is that the position and / or size of the optical absorption layer and / or the charging layer can be flexibly adjusted (e.g., by configuring the thickness of spacers or other mask layers), which helps to adjust the electric field distribution within the photonic device. Another benefit is that the self-aligned process can ensure that the optical absorption layer and the charging layer are formed in a more reproducible manner so that their position and / or size do not vary from device to device, which is desirable at least from a quality control perspective. Other advantages can include compatibility with existing manufacturing processes and ease and low cost of implementation.

[0109] One aspect of the present disclosure relates to a photonic device. The photonic device includes a substrate, a P-type doped component disposed on the substrate, an N-type doped component disposed on the substrate, an optical absorption layer disposed above the substrate, and a charging layer disposed above the substrate. The optical absorption layer is located between the P-type doped component and the N-type doped component. The optical absorption layer and the substrate have different material groups. The charging layer is located between the P-type doped component and the N-type doped component. The charging layer has a substantially linear first side surface. The first side surface is in direct contact with the optical absorption layer.

[0110] In some embodiments, the charging layer has a second side surface opposite to the first side surface; and the second side surface is substantially linear.

[0111] In some embodiments, the charging layer is doped with a P-type dopant; and the dopant concentration level of the charging layer is less than the dopant concentration level of the P-type doping component disposed above the substrate.

[0112] In some embodiments, the photonic device further includes a multiplication layer disposed between the charging layer and the N-type doped component.

[0113] In some embodiments, the substrate has a material composition of silicon and the optically absorbing layer has a material composition of germanium.

[0114] In some embodiments, the P-type doped component or the N-type doped component has a recess having a bottom surface facing upward in a vertical direction; and the bottommost surface of the optical absorption layer has a lower vertical height than the bottom surface of the recess.

[0115] In some embodiments, the photonic device further includes a silicon component disposed below the optical absorption layer and between the P-type doped component and the charging layer.

[0116] In some embodiments, the silicon component and the optically absorbing layer have substantially coplanar side surfaces.

[0117] In some embodiments, the photonic device further includes one or more mask layers disposed above the optically absorbing layer.

[0118] In some embodiments, the photonic device further includes: a first dielectric spacer disposed above the P-type doped component and on a first side surface of the optical absorption layer; and a second dielectric spacer disposed above the charging layer and on a second side surface of the optical absorption layer.

[0119] Another aspect of the present disclosure relates to a photonic device structure. The photonic device structure includes a substrate and a P-type contact disposed above the substrate in a vertical direction. The P-type contact includes silicon. The photonic device structure also includes an N-type contact disposed above the substrate in a vertical direction. The N-type contact includes silicon. The photonic device structure also includes an optical absorption layer disposed above the substrate in a vertical direction and located between the P-type contact and the N-type contact in a horizontal direction. The optical absorption layer includes germanium. The photonic device structure also includes a charging layer disposed above the substrate in a vertical direction and located between the optical absorption layer and the N-type contact in a horizontal direction. The charging layer includes silicon doped with a P-type dopant. The interface between the optical absorption layer and the charging layer extends substantially in the vertical direction.

[0120] In some embodiments, the photonic device structure further includes: a silicon layer disposed vertically above the optical absorption layer; a silicon oxide layer disposed vertically above the silicon layer; and a polysilicon layer disposed vertically above the silicon oxide layer.

[0121] In some embodiments, the photonic device structure further comprises an undoped silicon component disposed below the optical absorption layer in a vertical direction, wherein the P-type contact and the charging layer are in direct contact with opposite side surfaces of the undoped silicon component.

[0122] Yet another aspect of the present disclosure relates to a method of forming a photonic device. A semiconductor layer is formed over a substrate. An opening is etched in the semiconductor layer. An optical absorption layer is formed on a portion of the semiconductor layer exposed by the opening using a selective growth process. A charging layer is formed directly adjacent to the optical absorption layer. A passivation layer is formed over the optical absorption layer and the charging layer. The charging layer forms a substantially straight interface with the optical absorption layer and a portion of the semiconductor layer.

[0123] In some embodiments, the method further includes: forming a P-type contact in a first portion of the semiconductor layer disposed on a first side of the optical absorption layer by a first doping process, wherein the optical absorption layer and a second portion of the semiconductor layer are protected from being doped by the first doping process; and forming an N-type contact in a second portion of the semiconductor layer disposed on a second side of the optical absorption layer by a second doping process, the first side being opposite to the second side, wherein the optical absorption layer and the P-type contact are protected from being doped by the second doping process; wherein a charging layer is formed in a third portion of the semiconductor layer by a third doping process performed after the second doping process.

[0124] In some embodiments, the method further includes: forming a mask structure over the optical absorption layer before forming the P-type contact or the N-type contact, wherein the mask structure protects the optical absorption layer from being doped by the first doping process and the second doping process.

[0125] In some embodiments, the method further includes: forming a P-type contact in a first portion of a semiconductor layer disposed on a first side of the optical absorption layer by a first doping process, wherein the optical absorption layer and a second portion of the semiconductor layer are protected from being doped by the first doping process, wherein a charging layer is formed in a first segment of the second portion of the semiconductor layer by a second doping process performed after the first doping process; and forming an N-type contact in a second segment of the second portion of the semiconductor layer disposed on a second side of the optical absorption layer by a third doping process, the first side being opposite to the second side, wherein the optical absorption layer and the P-type contact are protected from being doped by the second doping process.

[0126] In some embodiments, the method also includes: forming a mask structure over the optical absorption layer before forming a P-type contact; forming a spacer layer after forming a charging layer, wherein the spacer layer is formed over the P-type contact, over the mask structure, over the charging layer, and over a second portion of the semiconductor layer; transforming the spacer layer into a first spacer and a second spacer disposed on opposite side surfaces of the mask structure; and forming an additional N-type contact in the first portion of the charging layer through a fourth doping process, wherein a second portion of the charging layer directly adjacent to the optical absorption layer is protected from the fourth doping process by at least the second spacer.

[0127] In some embodiments, the method also includes, before forming the optical absorption layer: forming a P-type contact in a first portion of the semiconductor layer by a first doping process, wherein a second portion and a third portion of the protective semiconductor layer are not doped by the first doping process; and forming an N-type contact in the second portion of the semiconductor layer by a second doping process, wherein the third portion of the protective semiconductor layer and the P-type contact are not doped by the second doping process; wherein the optical absorption layer and the charging layer are formed in the third portion of the semiconductor layer.

[0128] In some embodiments, the method further includes: before forming the charging layer, forming a mask structure over the optical absorption layer, wherein the charging layer is formed by a third doping process, the third doping process injects a P-type dopant into a third portion of the semiconductor layer adjacent to the optical absorption layer, and wherein the mask structure protects the optical absorption layer from being injected during the third doping process; forming a spacer layer after the third doping process, wherein the spacer layer is formed over the P-type contact, over the mask structure, over the charging layer, and over the N-type contact; transforming the spacer layer into a first spacer and a second spacer disposed on opposite side surfaces of the mask structure; and forming an additional N-type contact in the first portion of the charging layer by a fourth doping process, wherein a second portion of the charging layer adjacent to the optical absorption layer is protected from the fourth doping process by at least the second spacer.

[0129] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purpose of the embodiments introduced herein and / or achieving the same advantages thereof. Those skilled in the art will also appreciate that such equivalent structures do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and changes in the present disclosure without departing from the spirit and scope of the present disclosure.

Claims

1. A photonic device, comprising: substrate; A P-type doped component is disposed above the substrate; An N-type doped component is disposed above the substrate; an optical absorption layer disposed above the substrate and between the P-type doped component and the N-type doped component, wherein the optical absorption layer and the substrate have different material compositions; and A charging layer is disposed above the substrate and between the P-type doped component and the N-type doped component, wherein the charging layer has a substantially linear first side surface, and wherein the first side surface is in direct contact with the optical absorption layer.

2. The photonic device according to claim 1, wherein: The charging layer has a second side surface opposite to the first side surface; and The second side surface is substantially linear.

3. The photonic device according to claim 1, wherein: The charging layer is doped with a P-type dopant; and The dopant concentration level of the charging layer is less than the dopant concentration level of the P-type doped component disposed above the substrate. 4 . The photonic device of claim 1 , further comprising a multiplication layer disposed between the charging layer and the N-type doped component.

5. The photonic device according to claim 1, wherein: The P-type doped component or the N-type doped component has a recess having a bottom surface facing upward in a vertical direction; and The bottommost surface of the optical absorption layer has a lower vertical height than the bottom surface of the recess.

6. The photonic device according to claim 1, further comprising: a first dielectric spacer disposed above the P-type doped component and on a first side surface of the optical absorption layer; as well as A second dielectric spacer is disposed above the charging layer and on a second side surface of the optical absorption layer.

7. A photonic device structure, comprising: substrate; A P-type contact is disposed above the substrate in a vertical direction, wherein the P-type contact comprises silicon; An N-type contact disposed above the substrate in the vertical direction, wherein the N-type contact comprises silicon; an optical absorption layer disposed above the substrate in the vertical direction and between the P-type contact and the N-type contact in the horizontal direction, wherein the optical absorption layer comprises germanium; and A charging layer is disposed above the substrate in the vertical direction and between the optical absorption layer and the N-type contact in the horizontal direction, wherein the charging layer comprises silicon doped with a P-type dopant, and wherein an interface between the optical absorption layer and the charging layer substantially extends in the vertical direction.

8. A method of forming a photonic device, comprising: forming a semiconductor layer over the substrate; etching an opening in the semiconductor layer; forming an optical absorption layer on the portion of the semiconductor layer exposed by the opening using a selective growth process; forming a charging layer adjacent to the optically absorbing layer, the charging layer forming a substantially straight interface with the optically absorbing layer and a portion of the semiconductor layer; as well as A passivation layer is formed over the optical absorption layer and the charging layer.

9. The method according to claim 8, further comprising: forming a P-type contact in a first portion of the semiconductor layer disposed on a first side of the optical absorption layer by a first doping process, wherein the optical absorption layer and a second portion of the semiconductor layer are protected from being doped by the first doping process; and forming an N-type contact in a second portion of the semiconductor layer disposed on a second side of the optical absorption layer by a second doping process, the first side being opposite to the second side, wherein the optical absorption layer and the P-type contact are protected from being doped by the second doping process; The charging layer is formed in a third portion of the semiconductor layer through a third doping process performed after the second doping process.

10. The method according to claim 8, further comprising: forming a P-type contact in a first portion of the semiconductor layer disposed on a first side of the optical absorption layer by a first doping process, wherein the optical absorption layer and a second portion of the semiconductor layer are protected from being doped by the first doping process, and wherein the charging layer is formed in a first section of the second portion of the semiconductor layer by a second doping process performed after the first doping process; and An N-type contact is formed in a second section of the second portion of the semiconductor layer disposed on a second side of the optical absorption layer by a third doping process, the first side being opposite to the second side, wherein the optical absorption layer and the P-type contact are protected from being doped by the second doping process.

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