A red light-emitting diode (LED) chip and a manufacturing method thereof

Abstract

The present invention relates to the field of chip technology, and specifically relates to a red light LED chip and a manufacturing method thereof. The red light LED chip includes, from bottom to top, a back electrode, an Si substrate, an Au bonding layer, an In bonding layer, a transition barrier layer, a mirror layer, a dielectric film layer, an ohmic contact layer, an Au filling barrier layer, a GaP window layer, a P-type transition layer, a P-type confinement layer, a P-type waveguide layer, a light-emitting layer, an N-type semiconductor layer, roughened spherical islets, a passivation layer, and a front electrode; the Au filling barrier layer is located in the projection area of the chip dicing channel and is covered by the dielectric film layer; the surface of the ohmic contact layer protruding towards the mirror layer is an arc surface; the surface of the roughened spherical islets is uniformly distributed with pyramid textures. The present invention is optimized in terms of the manufacturing method, and the obtained red light LED chip has high luminous efficiency, good reliability, and stable overall device performance.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and specifically relates to a red light LED chip and a manufacturing method thereof. Background Art

[0002] Light-emitting diodes (LEDs) have the advantages of high luminous efficiency, long service life, green energy conservation and environmental protection, and are widely used in daily life, such as initial lighting, traffic signal display, outdoor stage lights, plant lighting and other fields. With the continuous expansion of the application range and scenarios, higher requirements are put forward for luminous efficiency and reliability. How to improve the luminous efficiency while ensuring the reliability and stability of the device has become an urgent problem to be solved. Summary of the Invention

[0003] Aiming at the deficiencies of the prior art, the present invention provides a red light LED chip and a manufacturing method thereof. The LED chip has high luminous efficiency, good reliability, and stable overall device performance.

[0004] The present invention provides a manufacturing method of a red light LED chip, including the following steps:

[0005] S1. On a GaAs substrate, a red light LED epitaxial wafer is grown by MOCVD (Metal-Organic Chemical Vapor Deposition), and an N-type semiconductor layer, a light-emitting layer, a P-type semiconductor layer, and a GaP window layer are grown in sequence;

[0006] S2. On the epitaxial wafer, a patterned P-plane pattern is fabricated on the surface of the GaP window layer by photolithography and etching technology, and etched through the GaP window layer;

[0007] S3. The surface is first deposited with a dielectric film layer by PECVD (Plasma-Enhanced Chemical Vapor Deposition);

[0008] S4. By photolithography technology, an Au filling barrier layer is inserted in a peeling manner in the area corresponding to the chip dicing lane;

[0009] S5. The surface is secondarily deposited with a dielectric film layer by PECVD;

[0010] S6. By photolithography and etching technology, a dielectric film through-hole is etched on the steps of the patterned P-plane pattern and stopped at the GaP window layer, wherein the through-hole pattern is the same as the shape of the patterned P-plane pattern;

[0011] S7. An ohmic contact layer is deposited by thermal evaporation using a metal evaporator;

[0012] S8. A mirror layer, a transition barrier layer, and an In bonding layer are respectively deposited by electron beam evaporation;

[0013] S9. Take a Si substrate and deposit a layer of Au bonding layer on the surface of the Si substrate by electron beam evaporation;

[0014] S10. Bond the epitaxial wafer and the Si substrate together by metal bonding, and remove the GaAs substrate by chemical etching to expose the roughened layer of the N-type semiconductor layer;

[0015] S11. Complete the fabrication of the front electrode by negative photoresist lithography in combination with the lift-off process;

[0016] S12. Use positive photoresist to pattern the scribing lanes, and perform scribing lane etching by dry etching until reaching the dielectric film layer;

[0017] S13. Spin-coat a dispersant colloid on the surface of the roughened layer except for the front electrode, and use heat curing to make the dispersant colloid into uniformly distributed mask cylinders or spheres. Through dry etching in combination with a roughening solution, make the roughened layer into roughened spherical islands with a pyramidal surface texture. Finally, wash off the dispersant colloid with a cleaning machine;

[0018] S14. Deposit a passivation layer on the area except for the front electrode and the surface treated in S13 by PECVD, and complete the patterning of the passivation layer through photolithography and etching;

[0019] S15. Complete the fabrication of the LED die by mechanically thinning the Si substrate and performing back electrode fabrication, laser cutting, and testing.

[0020] Through optimization of the manufacturing method, the present invention first fabricates a P-side pattern on the surface of the GaP window layer and etches through the GaP window layer, which can isolate the lateral long-distance expansion of the current, thereby enabling the effective injection of current into the light-emitting region. At the same time, it also reduces the light absorption of the GaP window layer and improves the light-emitting efficiency. Then, by inserting an Au filling barrier layer in the dielectric film layer located in the projection area of the scribing lane, it can effectively protect the mirror layer during the dry etching and laser cutting processes, with good reliability. Furthermore, by directly thermally evaporating AuZn, not only is the manufacturing process simple, the time is short, and it is easy to form an alloy, but also the surface formed after evaporation is arc-shaped, increasing its contact area with the mirror layer and having better stability. Finally, by spin-coating a dispersant colloid and heat curing on the roughened surface, a uniformly distributed spherical island is formed on the surface with a pyramidal surface texture, which not only increases the roughened area but also enlarges the light-emitting angle, further improving the light-emitting efficiency.

[0021] Further, in the above technical solution S1, the GaP window layer is a GaP layer with a thickness of 0.5 μm - 1.0 μm; the P-type semiconductor layer, from bottom to top in the epitaxial wafer growth direction, is a P-type waveguide layer, a P-type confinement layer, and a P-type transition layer; the P-type transition layer transitions from P-Al 40 GaInP to P-Al 20 GaInP and then transitions to the GaP window layer in sequence; the material of the roughened layer of the N-type semiconductor layer transitions from N-Al 60 GaInP to N-Al 20 GaInP and then transitions towards the GaP window layer in sequence, with a thickness of 3 μm - 4 μm. In this technical solution, both the P-type transition layer and the roughened layer of the N-type semiconductor layer adopt a gradually changing aluminum composition, which can ensure a gradual change in the crystal lattice and achieve the purpose of improving structural adaptation.

[0022] Further, in the above technical solution S2, the method for fabricating the patterned P-side pattern is as follows: Use ICP to etch away the exposed GaP window layer and etch downward until reaching the P-type confinement layer and then stop, and then use a photoresist remover to remove the photoresist on the surface to obtain it; the ratio of the etched area to the remaining area is 3:7. Due to the problem of refractive index difference in the material of the P-type transition layer, in this technical solution, etching stops at the P-type confinement layer after the P-side pattern is fabricated, which can not only reduce the absorption of the light emitted by the light-emitting layer by the P-type confinement layer but also reduce its absorption of the specularly reflected light towards the front light, further improving the light-emitting efficiency. The photoresist remover is a type of photoresist stripping solution, and any existing photoresist stripping solution that can remove photoresist can be used.

[0023] Further, in the above technical solution S3, the thickness of the first deposited dielectric film layer is 1500 ± 100 Å; in S5, the thickness of the second deposited dielectric film is 3500 ± 200 Å. In this technical solution, the dielectric film layer is deposited in two steps. One is to fill the concave position after the P-side pattern is fabricated to ensure the flatness of the subsequent dielectric film, and the other is to insert an Au filling barrier layer in the dielectric film layer located in the projection area of the dicing lane to improve reliability.

[0024] Further, in the above technical solution S4, the size of the Au filling barrier layer is larger than the size of the chip dicing lane. In this technical solution, the size of the Au filling barrier layer being larger than the size of the chip dicing lane can effectively protect the mirror layer during the dry etching and laser dicing processes.

[0025] Further, in the above technical solution S7, the material of the ohmic contact layer is AuZn, with a thickness of 2000 ± 10 Å, and the total thermal evaporation time is 10 min - 15 min. In this technical solution, the ohmic contact layer alloy is fabricated by direct thermal evaporation. This not only makes the process simpler, shorter in time, and higher in efficiency but also increases the contact area with the mirror layer and has better stability.

[0026] Further, in the above technical solution S8, the material of the mirror layer is Ag, and the thickness is 3000 ± 100 Å; the materials of the transition barrier layer are Ti / Pt / Ti / Pt / Au in sequence, and the total thickness is 10000 ± 500 Å; the thickness of the In bonding layer is 3 ± 0.5 μm; in S9, the thickness of the Au bonding layer is 2 ± 0.2 μm.

[0027] Further, in the above technical solution S10, the bonding temperature is 200 ± 5 °C, the pressure is 2000 ± 10 kgf, and the chemical etching solution used is a mixed solution of ammonia water and hydrogen peroxide with any volume ratio, preferably 15:1. In this technical solution, bonding is carried out in a low-temperature and low-pressure manner, which can reduce the influence on the metal mirror material and the metal layer and ensure the luminous efficiency.

[0028] Further, in the above technical solution S13, the dispersant colloid is a nano-scale resin; the thermal curing method is to heat at 120 °C for 300 s first, and then cure at 200 °C for 30 min; the roughening solution is a mixed solution of phosphoric acid, glacial acetic acid, hydrogen peroxide, and water with any volume ratio.

[0029] The present invention also provides a red light LED chip manufactured by the above manufacturing method. The red light LED chip includes a back electrode, an Si substrate, an Au bonding layer, an In bonding layer, a transition barrier layer, a mirror layer, a dielectric film layer, an ohmic contact layer, an Au filling barrier layer, a GaP window layer, a P-type transition layer, a P-type confinement layer, a P-type waveguide layer, a light-emitting layer, an N-type semiconductor layer, roughened spherical islands, a passivation layer, and a front electrode from bottom to top; the Au filling barrier layer is located in the projection area of the chip dicing channel and is covered by the dielectric film layer; the surface of the ohmic contact layer protruding towards the mirror layer is an arc surface; the surface of the roughened spherical islands is evenly distributed with pyramid textures.

[0030] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0031] The present invention optimizes the manufacturing method. By fabricating a P-side pattern on the surface of the GaP window layer and etching through the GaP window layer and the P-type transition layer, not only can the lateral long-distance expansion of the current be isolated, promoting the effective injection of the current into the light-emitting region, but also the absorption of the light emitted by the light-emitting layer and the specular reflection of the front light by the GaP window layer and the P-type transition layer can be reduced, greatly improving the light-emitting efficiency. By inserting an Au filling barrier layer into the dielectric film layer located in the projection area of the dicing channel, the protective effect on the mirror layer can be effectively exerted during processes such as dry etching and laser cutting, improving the reliability. By using the direct thermal evaporation method to deposit the AuZn alloy, not only is the manufacturing process simple, the time is short, and the alloy is easily formed, but also an arc-shaped surface can be formed after evaporation, increasing its contact area with the mirror layer and having better stability. By spin-coating a dispersant colloid on the surface of the roughened layer and thermally curing it to form uniformly distributed mask cylinders or spheres on the surface, and then through dry etching and in cooperation with a roughening solution, spherical islands are formed with a pyramidal velvet surface, which not only increases the roughening area but also can increase the light-emitting angle, further improving the light-emitting efficiency. The obtained red LED chip has high light-emitting efficiency, good reliability, and stable overall device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 It is a schematic structural diagram of a red-light LED epitaxial wafer on a GaAs substrate according to the present invention;

[0033] Figure 2 It is a schematic structural diagram of a red-light LED chip according to the present invention;

[0034] Figure 3 It is a partially enlarged schematic structural diagram of the spherical islands on the surface of the red-light LED chip according to the present invention.

[0035] Description of the reference numerals in the schematic diagram:

[0036] 1. GaAs substrate; 2. N-type semiconductor layer; 3. Light-emitting layer; 4. P-type semiconductor layer; 4-1. P-type waveguide layer; 4-2. P-type confinement layer; 4-3. P-type transition layer; 5. GaP window layer; 6. Dielectric film layer; 7. Au filling barrier layer; 8. Ohmic contact layer; 9. Mirror layer; 10. Transition barrier layer; 11. In bonding layer; 12. Au bonding layer; 13. Si substrate; 14. Front electrode; 15. Roughened spherical island; 16. Passivation layer; 17. Back electrode; 18. Pyramidal velvet surface. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0037] The following will clearly and completely describe the technical solutions in the embodiments of the present application in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The description of at least one exemplary embodiment below is actually only illustrative and in no way limits the present application and its application or use. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts belong to the scope of protection of the present application.

[0038] In the description of the present application, it should be understood that the use of terms such as "first" and "second" to limit components is only for the convenience of distinguishing the corresponding components. Without further statement, the above terms have no special meanings, so they cannot be understood as limiting the protection scope of the present application.

[0039] In the description of the present application, it should be understood that the orientation or positional relationships indicated by orientation words such as "front, back, up, down, left, right", "horizontal, vertical, perpendicular, horizontal" and "top, bottom" are usually based on the orientation or positional relationships shown in the accompanying drawings. It is only for the convenience of describing the present application and simplifying the description. Without contrary explanation, these orientation words do not indicate and imply that the device or element referred to must have a specific orientation or be constructed and operated in a specific orientation, so they cannot be understood as limiting the protection scope of the present application; the orientation words "inside, outside" refer to the inside and outside relative to the contour of each component itself.

[0040] Please refer to Figures 1 to 3 , it should be noted that the illustrations provided in this embodiment only schematically illustrate the basic concept of the present invention. Therefore, only the components related to the present invention are shown in the illustrations, rather than being drawn according to the number, shape and size of the components in actual implementation. The form, quantity and proportion of each component in actual implementation can be arbitrarily changed, and the layout form of its components may also be more complex. The organic solution for cleaning is a common organic solvent such as acetone and isopropanol.

[0041] Some embodiments of the present invention provide a method for manufacturing a red light LED chip, including the following steps:

[0042] S1. On a GaAs substrate, a red light LED epitaxial wafer is grown by MOCVD, successively growing an N-type semiconductor layer, a light-emitting layer, a P-type semiconductor layer, and a GaP window layer;

[0043] Specifically, a GaAs substrate 1 is provided as a growth substrate for a red light epitaxial wafer structure. First, the program is set in the MOCVD machine. An N-type semiconductor layer 2, a light-emitting layer 3, a P-type semiconductor layer 4, and a GaP window layer 5 are sequentially grown on the GaAs substrate 1. The GaP window layer 5 is mainly a GaP layer with a thickness of 0.5 μm - 1.0 μm. The P-type semiconductor layer 4 includes a P-type waveguide layer 4-1, a P-type confinement layer 4-2, and a P-type transition layer 4-3. The P-type transition layer transitions from P-Al 40 GaInP to P-Al 20 GaInP and sequentially transitions to the GaP window layer 5. The roughened layer in the N-type semiconductor layer 2 is located on the outermost surface of the N-type semiconductor layer, and its material transitions from N-Al 60 GaInP to N-Al 20 GaInP and sequentially transitions toward the GaP window layer, with a thickness of 3 μm - 4 μm. By adopting a gradual aluminum composition, it mainly ensures a gradual change in the lattice for the purpose of achieving structural adaptation.

[0044] S2. On the epitaxial wafer, using photolithography and etching techniques, a patterned P-side pattern is fabricated on the surface of the GaP window layer and etched through the GaP window layer. Specifically, first, the epitaxial wafer is cleaned with an acid-base solution. On the surface of the epitaxial wafer, a patterned P-side pattern is fabricated using positive photoresist masking photolithography. Then, the exposed GaP window layer is etched away using ICP and etched downward until it reaches the P-type confinement layer and stops. Finally, the photoresist on the surface is removed with a photoresist remover to obtain a patterned P-side pattern, where the ratio of the etched area to the remaining area is 3:7. This can reduce the absorption of the light emitted by the light-emitting layer by the P-type confinement layer and reduce the absorption of the specularly reflected light toward the front by the P-type confinement layer, thereby improving the light-emitting efficiency.

[0045] S3. Use PECVD to deposit a dielectric film layer on the surface for the first time. Specifically, the surface of the patterned P-side pattern is cleaned with an acid-base or organic solution, and a SiO2 dielectric film layer with a thickness of 1500 ± 100 Å is deposited through PECVD, which can fill the concave positions after the fabrication of the P-side pattern to ensure the flatness of the subsequent dielectric film.

[0046] S4. Use photolithography technology to insert an Au fill barrier layer in the area corresponding to the chip scribe lane by the lift-off method. Specifically, the fabrication of the Au fill barrier layer is completed through negative photoresist lithography in cooperation with the lift-off process. The Au fill barrier layer is located in the scribe lane area and has a size larger than the scribe lane size. This can effectively protect the mirror layer during dry etching and laser cutting processes and improve the reliability of the chip.

[0047] S5. Deposit a dielectric film layer on the surface for the second time using PECVD; specifically, further clean it using an acid-base or organic solution, which may be sulfuric acid, hydrogen peroxide, acetone, isopropyl alcohol, etc., and then deposit a SiO2 dielectric film layer by PECVD with a thickness of 3500±200 angstroms. The secondary deposited dielectric film may insert an Au-filled barrier layer into the dielectric film layer located in the projection area of ​​the cutting path to improve reliability.

[0048] S6. Using photolithography and etching technology, a dielectric film through hole is etched on the patterned P-face graphic step and terminated at the GaP window layer, wherein the through hole pattern is consistent with the shape of the patterned P-face graphic; specifically, using a positive resist mask, an aligned dielectric film through hole pattern is produced, the dielectric film through hole pattern is located on the patterned P-face graphic step, and the through hole pattern is consistent with the shape of the patterned P-face graphic, which can be circular, rectangular, polygonal, etc.

[0049] S7. Use a metal evaporator to thermally evaporate the ohmic contact layer; specifically, first corrode the dielectric film material with a fluorine-containing solution, and then directly evaporate the ohmic contact layer AuZn by thermal evaporation using a metal evaporator. The thickness of AuZn is 2000±10 angstroms, and the total thermal evaporation time is 10min-15min. By using direct thermal evaporation to make the ohmic contact layer alloy, the process is simpler, the time is short, the efficiency is high, the contact area with the mirror layer is increased, and the stability is good.

[0050] S8. After cleaning with an organic solution, a mirror layer, a transition barrier layer, and an In bonding layer are respectively evaporated by electron beam evaporation. Specifically, the material of the mirror layer is Ag, and the thickness is 3000±100 angstroms. The materials of the transition barrier layer are Ti / Pt / Ti / Pt / Au in sequence, and the total thickness is 10000±500 angstroms. The thickness of the In bonding layer is 3±0.5μm.

[0051] S9. Take a Si substrate and use electron beam evaporation to evaporate a layer of Au bonding layer on the surface of the Si substrate; specifically, the thickness of the Au bonding layer is 2±0.2 μm.

[0052] S10. Bond the epitaxial wafer and the Si substrate together by metal bonding, and remove the GaAs substrate by chemical etching to expose the roughened layer of the N-type semiconductor layer; specifically, the bonding temperature is 200±5°C, the pressure is 2000±10kgf, and the chemical etching solution used is a mixed solution of ammonia water and hydrogen peroxide in a volume ratio of 15:1. By adopting low temperature and low pressure for bonding, the impact on the metal mirror material and the metal layer can be reduced, thereby ensuring the luminous efficiency.

[0053] S11. The front electrode is fabricated by negative photolithography in combination with a lift-off process and then subjected to high-temperature fusion. This step can be fabricated by conventional methods.

[0054] S12. Use a positive photoresist to pattern the scribe lines, and use dry etching to etch the scribe lines until reaching the dielectric film layer; specifically, any conventional cutting method can be used. During the cutting and etching process, the width of the scribe line is less than the width of the Au filling barrier layer and penetrates through the Au filling barrier layer.

[0055] S13. Spin-coat a dispersant colloid on the surface of the roughened layer except for the front electrode, and use heat curing to make the dispersant colloid into uniformly distributed mask cylinders or spheres. Through dry etching and in cooperation with a roughening solution, the roughened layer becomes roughened spherical islands with a surface pyramid texture. Finally, use a cleaning machine to wash away the dispersant colloid.

[0056] S14. Use PECVD to deposit a passivation layer in the area except for the front electrode and the surface treated in S13, and complete the patterning of the passivation layer through photolithography and etching; specifically, the material of the passivation layer is SiO2, and its thickness is the same as that of a conventional red LED chip, preferably 5000 Å - 6000 Å.

[0057] S15. Mechanically thin the Si substrate and perform back electrode fabrication, laser cutting, and testing to complete the production of LED die. Specifically, the above chip fabrication processes are all conventional processes.

[0058] In some specific embodiments of the present invention, a red LED chip is also provided. The schematic structural diagram is as Figure 2 shown. The red LED chip includes a back electrode 17, a Si substrate 13, an Au bonding layer 12, an In bonding layer 11, a transition barrier layer 10, a mirror layer 9, a dielectric film layer 6, an ohmic contact layer 8, an Au filling barrier layer 7, a GaP window layer 5, a P-type transition layer 4-3, a P-type confinement layer 4-2, a P-type waveguide layer 4-1, a light-emitting layer 3, an N-type semiconductor layer 2, roughened spherical islands 15, a passivation layer 16, and a front electrode 14 from bottom to top; the Au filling barrier layer 7 is located in the projection area of the chip scribe line and is covered by the dielectric film layer 6; the surface of the ohmic contact layer 8 protruding towards the mirror layer is an arc surface; the surface of the roughened spherical islands 15 is uniformly distributed with pyramid textures 18. The enlarged schematic diagram of this part of the structure is as Figure 3 shown.

[0059] In summary, the present invention optimizes the manufacturing method. By etching part of the GaP window layer and the P-type transition layer, not only can the lateral long-distance expansion of the current be isolated, promoting the effective injection of the current into the light-emitting region, but also the absorption of the light emitted by the light-emitting layer and the specular reflection of the front light by the GaP window layer and the P-type transition layer can be reduced, greatly improving the light-emitting efficiency; by inserting an Au filling barrier layer in the dielectric film layer located in the projection area of the dicing channel, the role of protecting the mirror layer can be played, improving the reliability; by directly thermally evaporating the AuZn alloy, the manufacturing process is simple, the time is short, and an arc-shaped surface can be obtained, increasing the contact area with the mirror layer and improving the stability; by processing to form spherical islands with a roughened layer and a pyramidal velvet surface, not only the roughened area is increased, but also the light-emitting angle can be increased, further improving the light-emitting efficiency. The obtained red LED chip has high overall light-emitting efficiency, good reliability, and stable performance.

[0060] Finally, it should be emphasized that the above are only the preferred embodiments of the present invention and are not used to limit the present invention. For those skilled in the art, the present invention can have various changes and modifications. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for manufacturing a red LED chip, characterized in that: The following steps are involved: S1. On a GaAs substrate, a red light LED epitaxial wafer is grown by MOCVD, and an N-type semiconductor layer, a light-emitting layer, a P-type semiconductor layer, and a GaP window layer are grown in sequence; the P-type semiconductor layer is a P-type waveguide layer, a P-type confinement layer, and a P-type transition layer from bottom to top in the growth direction of the epitaxial wafer; the P-type transition layer transitions from P-Al40GaInP to P-Al20GaInP in sequence to the GaP window layer in accordance with the material; the roughening layer material of the N-type semiconductor layer transitions from N-Al60GaInP to N-Al20GaInP in sequence toward the GaP window layer, and the thickness is 3μm-4μm; S2. On the epitaxial wafer, a patterned P-face pattern is produced on the surface of the GaP window layer using photolithography and etching technology; the method for producing the patterned P-face pattern is: using ICP to etch away the exposed GaP window layer, and etching down to the P-type confinement layer to stop, and then removing the surface photoresist with a photoresist removal solution to obtain; S3. Depositing a dielectric film layer on the surface for the first time using PECVD; S4. Using photolithography technology, inserting an Au filling barrier layer in the area corresponding to the chip cutting road by stripping; S5. Depositing a dielectric film layer on the surface for the second time using PECVD; S6. Using photolithography and etching technology, a dielectric film through hole is etched on the patterned P-face pattern step and ends at the GaP window layer, wherein the through hole pattern is consistent with the shape of the patterned P-face pattern; S7. Depositing an ohmic contact layer by thermal evaporation using a metal evaporator; S8. using electron beam evaporation to deposit a mirror layer, a transition barrier layer, and an In bonding layer; S9. Take a Si substrate and deposit an Au bonding layer on the surface of the Si substrate by electron beam evaporation; S10. Bonding the epitaxial wafer and the Si substrate together by metal bonding, and removing the GaAs substrate by chemical etching to expose the roughened layer of the N-type semiconductor layer; wherein the bonding temperature is 200±5°C and the pressure is 2000±10kgf; S11. The front electrode is fabricated by negative photolithography and lift-off process; S12. Using positive resist to make cutting path patterns, and using dry etching to etch the cutting paths to the dielectric film layer; S13. Spin-coating the surface of the roughened layer except the front electrode with a dispersant colloid, and using a heat curing method to make the dispersant colloid into uniformly distributed mask cylinders or spheres, and using dry etching and a roughening liquid to make the roughened layer into roughened spherical islands with a pyramid velvet surface, and finally using a cleaning machine to wash away the dispersant colloid; S14. Depositing a passivation layer on the area other than the front electrode and the surface treated in S13 by PECVD, and completing the patterning of the passivation layer by photolithography and etching; S15. The LED core is manufactured by mechanically thinning the Si substrate and performing back electrode fabrication, laser cutting, and testing.

2. The method for manufacturing a red LED chip according to claim 1, characterized in that: In S1, the GaP window layer is a GaP layer with a thickness of 0.5 μm-1.0 μm.

3. The method for manufacturing a red LED chip according to claim 2, characterized in that: In S2, the ratio of the etched area to the retained area is 3:

7.

4. The method for manufacturing a red LED chip according to claim 1, characterized in that: In S3, the thickness of the dielectric film layer deposited for the first time is 1500±100 angstroms; in S5, the thickness of the dielectric film layer deposited for the second time is 3500±200 angstroms.

5. The method for manufacturing a red LED chip according to claim 1, characterized in that: In S4, the size of the Au-filled barrier layer is larger than the chip cutting street size.

6. The method for manufacturing a red LED chip according to claim 1, characterized in that: In S7, the material of the ohmic contact layer is AuZn, the thickness is 2000±10 angstroms, and the total thermal evaporation time is 10 min-15 min.

7. The method for manufacturing a red LED chip according to claim 1, characterized in that: In S8, the material of the mirror layer is Ag, and the thickness is 3000±100 angstroms; the materials of the transition barrier layer are Ti / Pt / Ti / Pt / Au in sequence, and the total thickness is 10000±500 angstroms; the thickness of the In bonding layer is 3±0.5μm; in S9, the thickness of the Au bonding layer is 2±0.2μm.

8. The method for manufacturing a red LED chip according to claim 1, characterized in that: In S10, the chemical etching solution used is a mixed solution of ammonia water and hydrogen peroxide in any volume ratio.

9. The method for manufacturing a red LED chip according to claim 1, characterized in that The dispersant colloid is a nano-scale resin; the thermal curing method is to first heat at 120°C for 300s and then maintain at 200°C for 30min for curing; the roughening liquid is a mixed solution of phosphoric acid, glacial acetic acid, hydrogen peroxide and water in any volume ratio.

10. A red LED chip manufactured by the manufacturing method according to any one of claims 1 to 9.

Images