Light emitting chip manufacturing method

Abstract

The application relates to a light-emitting chip preparation method, which comprises the following steps: preparing a first electrode layer and an epitaxial layer on a driving backboard, the first electrode layer being electrically connected between the driving backboard and the epitaxial layer; etching the epitaxial layer to form a plurality of spaced-apart epitaxial structures; preparing a mask layer on the surface of each epitaxial structure away from the driving backboard; wherein the mask layer comprises a protective layer and a photoresist; adopting a dry etching technology to pattern the first electrode layer to expose the driving backboard between the epitaxial structures; wherein the photoresist is used to protect the epitaxial structures, and the protective layer melts and flows along the sidewalls of the epitaxial structures to cover the sidewalls during dry etching; removing the mask layer and respectively preparing a second electrode layer on each epitaxial structure. The light-emitting chip preparation method can improve the light-emitting efficiency and light-emitting effect of the light-emitting chip and improve the yield of the prepared light-emitting chip.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a method for fabricating a light-emitting chip. Background Technology

[0002] The two electrodes of a light-emitting chip are usually made of metals with good conductivity, such as platinum (Pt), gold (Au), and titanium (Ti). Because these metals have strong passivation properties and are difficult to etch, and because light-emitting chips are usually micrometer-sized, dry etching technology is generally used to etch the electrode layer to prepare the electrodes of the light-emitting chip.

[0003] During the etching process of the electrode layer using dry etching technology, the physical bombardment of the electrode layer by high-energy ions may cause metal particles in the electrode layer to sputter onto the sidewalls of the epitaxial structure. The metal sputtered onto the sidewalls may cause the current to be unable to pass through the quantum well layer in the epitaxial structure or cause a short circuit in the light-emitting chip, thereby reducing the luminous efficiency and luminous effect of the light-emitting chip and reducing the yield of the light-emitting chip. Summary of the Invention

[0004] In view of the shortcomings of the prior art, the purpose of this application is to provide a method for fabricating light-emitting chips that can improve the yield of light-emitting chip fabrication.

[0005] This application provides a method for fabricating a light-emitting chip, including the following steps:

[0006] A first electrode layer and an epitaxial layer are fabricated on a driving backplane, wherein the first electrode layer is electrically connected between the driving backplane and the epitaxial layer;

[0007] Etch the epitaxial layer to form multiple spaced epitaxial structures;

[0008] A mask layer is prepared on the surface of each epitaxial structure facing away from the driving backplane; wherein the mask layer includes a protective layer and a photoresist;

[0009] The first electrode layer is patterned using a dry etching technique to expose the driving backplane between the epitaxial structures; wherein, photoresist is used to protect the epitaxial structures, and the protective layer melts during dry etching and flows along the sidewalls of the epitaxial structures to cover the sidewalls.

[0010] The mask layer was removed and a second electrode layer was fabricated on each epitaxial structure.

[0011] The light emitting chip preparation method can bond the epitaxial layer to the driving back plate to realize the electrical connection between the driving back plate and the epitaxial layer, and further realize the light emitting function of the light emitting chip prepared by the light emitting chip preparation method. At the same time, by bonding the epitaxial layer to the driving back plate, signals can be transmitted to each light emitting chip to control the light emission of each light emitting chip, ensuring that the light emitting effect of each light emitting chip meets the display requirements. By preparing the first electrode layer and the second electrode layer on the opposite sides of the epitaxial structure in the direction perpendicular to the plane of the driving back plate, the first electrode layer and the second electrode layer can jointly act to pass current to the epitaxial structure to turn on the epitaxial structure and emit light outward. The light emitting chip with a vertical structure has good anti-static ability and good heat dissipation ability. By preparing the first electrode layer and the second electrode layer on the opposite sides of the epitaxial structure in the direction perpendicular to the plane of the driving back plate, the light emitting chip prepared by the light emitting chip preparation method has a vertical structure, thereby improving the working performance of the prepared light emitting chip.

[0012] The light emitting chip preparation method can bond the epitaxial layer to the driving back plate to realize the electrical connection between the driving back plate and the epitaxial layer, and further realize the light emitting function of the light emitting chip prepared by the light emitting chip preparation method. At the same time, by bonding the epitaxial layer to the driving back plate, signals can be transmitted to each light emitting chip to control the light emission of each light emitting chip, ensuring that the light emitting effect of each light emitting chip meets the display requirements. By preparing the first electrode layer and the second electrode layer on the opposite sides of the epitaxial structure in the direction perpendicular to the plane of the driving back plate, the first electrode layer and the second electrode layer can jointly act to pass current to the epitaxial structure to turn on the epitaxial structure and emit light outward. The light emitting chip with a vertical structure has good anti-static ability and good heat dissipation ability. By preparing the first electrode layer and the second electrode layer on the opposite sides of the epitaxial structure in the direction perpendicular to the plane of the driving back plate, the light emitting chip prepared by the light emitting chip preparation method has a vertical structure, thereby improving the working performance of the prepared light emitting chip.

[0013] In the process of patterning the first electrode layer by dry etching technology, the high-energy ions after dissociation physically bombard the mask layer, causing the temperature of the mask layer to rise, and then the protective layer melts and flows to cover the side wall of the epitaxial structure, so as to protect the side wall of the epitaxial structure, avoid the sputtering of metal particles onto the epitaxial structure in the process of etching the first electrode layer, and cause the current to pass through the quantum well layer in the epitaxial structure or the short circuit of the light emitting chip. The phenomenon of adverse phenomenon occurs, so as to improve the yield of the light emitting chip prepared by the light emitting chip preparation method, and ensure the light emitting efficiency and light emitting effect of the light emitting chip. At the same time, by synchronously heating the protective layer and making the protective layer melt and cover the side wall of the epitaxial structure by using the energy generated in the process of dry etching while etching the first electrode layer, the preparation process of the light emitting chip preparation method can be further simplified, and the preparation efficiency of the light emitting chip preparation method can be further improved.

[0014] In an embodiment, the protective layer is located between the epitaxial structure and the photoresist.

[0015] In the embodiment, the photoresist is located at the outermost layer by locating the protective layer between the epitaxial structure and the photoresist, i.e. covering the photoresist on the side of the protective layer away from the driving backboard, so as to ensure that the photoresist forms a protective effect on the epitaxial structure, and the photoresist can form a protective effect on the protective layer, and the etching precision and etching effect in the subsequent dry etching process of the first electrode layer can be improved.

[0016] In an embodiment, the melting point temperature of the protective layer is between 70°C and 120°C.

[0017] In the embodiment, the melting point temperature of the protective layer is between 70°C and 120°C, so that the energy generated in the dry etching process can reach the melting point temperature of the protective layer, thereby ensuring the melting effect and efficiency of the protective layer, and avoiding the phenomenon that the melting point temperature of the protective layer is too high to melt. At the same time, by controlling the melting point temperature of the protective layer to be between 70°C and 120°C, the shaping effect of the protective layer can be ensured, and the phenomenon that the protective layer may melt in advance due to the high ambient temperature before etching the first electrode layer can be avoided.

[0018] In an embodiment, the material of the protective layer is polyimide (PI) or polymethyl methacrylate (PMMA).

[0019] In the embodiment, the film layer of polyimide or polymethyl methacrylate has good heat sensitivity and fluidity, and by setting the material of the protective layer as polyimide or polymethyl methacrylate, the heat sensitivity of the protective layer can be improved, and the flow effect and flow efficiency of the protective layer on the sidewall of the epitaxial structure can be improved.

[0020] In an embodiment, the epitaxial structure has opposite top and bottom surfaces, the top surface is located on the side of the epitaxial structure away from the driving backboard, and the projection of the top surface on the driving backboard is accommodated in the bottom surface.

[0021] In the embodiment, by setting the projection of the top surface on the driving backboard to be accommodated in the bottom surface, the sidewall of the epitaxial structure is formed perpendicular to the plane of the driving backboard or inclined relative to the plane of the driving backboard, i.e. the cross section of the epitaxial structure is formed as a "right trapezoid" or "rectangle", which can further improve the flow effect of the protective layer on the sidewall of the epitaxial structure, and further improve the coverage effect and coverage efficiency of the protective layer.

[0022] In an embodiment, the protective layer melts and flows along the sidewall of the epitaxial structure during dry etching, comprising:

[0023] The protective layer continuously covers the sidewall along the circumference of the epitaxial structure.

[0024] In the embodiment, the protective layer continuously covers the sidewall along the circumference of the epitaxial structure, so that the protective layer can continuously cover and protect the sidewall along the circumference of the epitaxial structure, and the coverage of the protective layer on the epitaxial structure can be ensured and improved, thereby further improving the yield of the light emitting chip prepared by the light emitting chip preparation method.

[0025] In one embodiment, the protective layer melts and flows along the sidewall of the epitaxial structure during dry etching, comprising:

[0026] The protective layer at least completely covers the sidewall of the epitaxial structure.

[0027] In the embodiment, the protective layer at least completely covers the sidewall of the epitaxial structure, so that the coverage of the protective layer on the epitaxial structure can be ensured and improved, thereby further improving the protection effect of the protective layer on the epitaxial structure, and further improving the yield of the light emitting chip prepared by the light emitting chip preparation method.

[0028] In one embodiment, a mask layer is prepared on the surface of each epitaxial structure away from the driving backplate, comprising:

[0029] A pre-mask layer is prepared on the surface of each epitaxial structure away from the driving backplate by using a spin coating method.

[0030] The pre-mask layer is patterned by using an exposure and development technology to expose the first electrode layer between the epitaxial structures, and the pre-mask layer forms a mask layer on the surface of each epitaxial structure away from the driving backplate.

[0031] In the embodiment, the mask layer is prepared on the surface of each epitaxial structure away from the driving backplate by using a spin coating method, so that the uniformity of each protective layer can be improved in the planar direction along the driving backplate, thereby improving the uniformity of the protective layer flowing on the sidewall from each position around the epitaxial structure, and further improving the coverage effect and uniformity of the protective layer, thereby avoiding the adverse phenomenon of affecting the protection effect of the protective layer on the sidewall of the epitaxial structure due to uneven coverage.

[0032] In one embodiment, the mask layer is removed and a second electrode layer is prepared on each epitaxial structure, comprising:

[0033] The mask layer is removed by using an organic stripping solution.

[0034] A second electrode layer is prepared on each epitaxial structure.

[0035] In the embodiment, the mask layer is removed by using the organic stripping solution, the metal particles sputtered on the protection layer can be removed at the same time when the mask layer is removed to facilitate the subsequent process preparation, the epitaxial structure with good performance is obtained, and the working performance and working efficiency of the epitaxial structure are improved.

[0036] In one embodiment, before the second electrode layer is prepared on each epitaxial structure, the following steps are included:

[0037] A passivation layer is prepared on each epitaxial structure, and the passivation layer covers the epitaxial structure and the first electrode layer;

[0038] A via hole is prepared on the surface of the passivation layer away from the driving backboard, and the via hole penetrates to the epitaxial structure;

[0039] Then, the second electrode layer is prepared on each epitaxial structure, including:

[0040] The second electrode layer is prepared on the surface of the passivation layer away from the driving backboard, and the second electrode layer extends into the via hole and is electrically connected to the epitaxial structure.

[0041] In the embodiment, the passivation layer is prepared on each epitaxial structure, which can protect the layer structure of each epitaxial structure, the first electrode layer, and the like, avoid the pollution of harmful impurities or the oxidation of each layer structure in the light-emitting chip, and further ensure the normal working performance and working effect of the light-emitting chip. The via hole is formed in the passivation layer to facilitate the preparation of the second electrode layer, and the second electrode layer can be electrically connected to the epitaxial structure to realize the conduction of the epitaxial structure. BRIEF DESCRIPTION OF DRAWINGS

[0042] Figure 1 The working scene diagram of the light-emitting chip prepared by the light-emitting chip preparation method of the present application;

[0043] Figure 2 The cross-sectional structure diagram of the light-emitting chip in the embodiment shown in Figure 1

[0044] Figure 3 The working flow diagram of the light-emitting chip preparation method of the present application;

[0045] Figure 4 The structure diagram of one side view when the epitaxial layer is bonded on the driving backboard;

[0046] Figure 5 The structure diagram of one side view when the epitaxial layer is bonded on the driving backboard; Figure 4

[0047] Figure 6 The working flow diagram of the mask layer prepared on the surface of each epitaxial structure away from the driving backboard;​​

[0048] Figure 7 Structure diagram of one side view when preparing a pre-mask layer on the surface of each epitaxial structure away from the substrate;

[0049] Figure 8 Structure diagram of one side view when forming a mask layer on the surface of each epitaxial structure away from the substrate;

[0050] Figure 9 Structure diagram of one side view when patterning the first electrode layer by using dry etching technology;

[0051] Figure 10 Structure diagram of one side view when removing the mask layer in the embodiment shown in FIG. 8; Figure 9

[0052] Structure diagram of one side view when etching the first electrode layer to the driving layer by using dry etching method; Figure 11

[0053] Structure diagram of one side view when removing the mask layer in the embodiment shown in FIG. 8; Figure 12

[0054] Structure diagram of one side view when removing the mask layer in the embodiment shown in FIG. 8; Figure 13 Figure 12 Structure diagram of one side view when removing the mask layer in the embodiment shown in FIG. 8;

[0055] Figure 14 Structure diagram of one side view when removing the mask layer in the embodiment shown in FIG. 8;

[0056] Figure 15 Structure diagram of one side view when removing the mask layer in the embodiment shown in FIG. 8;

[0057] Figure 16 Structure diagram of one side view when removing the mask layer in the embodiment shown in FIG. 8.

[0058] Reference signs:

[0059] 10 - light emitting chip; 101 - substrate; 102 - driving layer; 103 - driving back plate; 11 - first electrode layer; 111 - second side wall; 112 - etching surface; 12 - second electrode layer; 13 - epitaxial structure; 131 - top surface; 132 - side wall; 133 - bottom surface; 13a - epitaxial layer; 14 - passivation layer; 141 - via hole; 20 - mask layer; 20a - pre-mask layer; 21a - pre-protection layer; 21 - protection layer; 22a - pre-photoresist; 22 - photoresist; S - gap. DETAILED DESCRIPTION

[0060] ​For the purposes of the present application, a more complete description of which will follow, reference will be made to the accompanying drawings referenced below. The drawings illustrate preferred embodiments of the application. However, the application can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and fully convey the scope of the application to those skilled in the art.

[0061] The following description of several embodiments with reference to the additional drawings is used to illustrate specific embodiments in which the application can be implemented. The numbers of components in this document, such as "first", "second", etc., are only used to distinguish the described objects and do not have any sequential or technical meaning. The "connection" and "coupling" mentioned in the present application, unless otherwise specified, include direct and indirect connections (couplings). The direction terms mentioned in the present application, such as "up", "down", "front", "back", "left", "right", "inner", "outer", "side" and the like, are only the direction of the attached drawings, therefore, the direction terms used are for better, clearer description and understanding of the application, and are not intended to indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the application.

[0062] In the description of the present application, it should be noted that unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connection" should be understood broadly, for example, it can be a fixed connection, or it can be a detachable connection, or it can be an integral connection; it can be a mechanical connection; it can be directly connected, or indirectly connected through an intermediate medium; it can be the connection between two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances. It should be noted that the terms "first", "second" and the like in the specification and claims of the present application and the drawings are used to distinguish different objects, and are not used to describe a specific order. In addition, the terms "include", "may include", "contain" or "may contain" used in the present application indicate the existence of the corresponding functions, operations, elements, etc. disclosed in the specification, and do not limit other one or more functions, operations, elements, etc. In addition, the term "include" or "contain" means the existence of the corresponding features, numbers, steps, operations, elements, components or combinations thereof disclosed in the specification, and does not exclude the existence or addition of one or more other features, numbers, steps, operations, elements, components or combinations thereof, and is intended to cover non-exclusive inclusion.

[0063] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the specification of the present application herein is only for the purpose of describing the specific embodiments and is not intended to limit the present application.

[0064] Please refer to Figure 1 and Figure 2 , Figure 1 Fig. 1 is a schematic diagram of a working scene of a light emitting chip 10 prepared by a light emitting chip preparation method of the present application, Figure 2 Fig. 2 is a schematic diagram of a cross-sectional structure of the light emitting chip 10 at a position A-A in the embodiment shown in Fig. 1. As shown in Figs. 1 and 2, Figure 1 Fig. 3 is a schematic diagram of a cross-sectional structure of the light emitting chip 10 at a position A-A in the embodiment shown in Fig. 1. As shown in Figs. 1 and 3, Figure 1 and Figure 2 As shown in Figs. 1 and 3, the plurality of light emitting chips 10 are all mounted on a driving backboard 103. The driving backboard 103 comprises a substrate 101 and a driving layer 102, the driving layer 102 is laminated on one side surface of the substrate 101, the driving layer 102 is located between the light emitting chip 10 and the substrate 101, and is electrically connected with each light emitting chip 10, so as to control the plurality of light emitting chips 10 to emit light.

[0065] Among them, the plurality of light emitting chips 10 are arranged on the side surface of the driving layer 102 away from the substrate 101.

[0066] The light emitting chip 10 is used to emit light outwardly, and the color of the light emitted by each light emitting chip 10 can be different. Among them, the color of the light emitted by each light emitting chip 10 can be but is not limited to any one of red, green, blue and yellow.

[0067] The driving layer 102 is used to drive and control the light emission of each light emitting chip 10, that is, the driving layer 102 can transmit signals to each light emitting chip 10 to control the light emission of each light emitting chip 10, so as to ensure that the light emission effect of each light emitting chip 10 meets the display requirements. For example, the driving layer 102 can be but is not limited to a transmission wire arranged on the substrate 101 and the like.

[0068] It should be noted that, on the driving backboard 103, other structures or components for driving and controlling the light emission of the light emitting chip 10 can also be provided, so as to realize different design requirements of the light emitting chip 10.

[0069] For example, in a possible embodiment, the driving backboard 103 can also be provided with a driving chip (not shown in the figure), a plurality of driving circuits (not shown in the figure) and the like, the driving chip is connected with each light emitting chip 10 through each driving circuit, and the driving chip can also provide driving signals for each light emitting chip 10, so as to realize the effect of controlling the light emission of each light emitting chip 10, and further meet different light emission requirements.

[0070] It should be noted that, in the above embodiment, Figure 1In the illustrated embodiment, only one possible arrangement and number of the light emitting chips 10 are exemplarily illustrated, but the number and arrangement of the light emitting chips 10 are not limited to this. In other embodiments of the present application, the arrangement and number of the light emitting chips 10 can be adjusted according to actual design requirements, which are not specifically limited in the embodiments of the present application.

[0071] Meanwhile, it should be noted that, in the Figure 1 In the illustrated embodiment, only one possible structure size and structure shape of the driving layer 102 and the light emitting chip 10 are exemplarily introduced, but the actual structure shape and actual structure size of the driving layer 102 and the light emitting chip 10 are not limited to this.

[0072] As shown in the Figure 2 The substrate 101 is used to provide support and bearing for the functional structures or components such as the light emitting chip 10 and the driving layer 102. That is, various electronic devices or structures for realizing the function of the light emitting chip 10 can be provided on the substrate 101, so that the substrate 101 forms a bearing and fixing effect on the various electronic devices or structures of the light emitting chip 10.

[0073] The substrate 101 can be, but is not limited to, silicon (Si), germanium (Ge), or copper (Cu).

[0074] In an embodiment, the material of the substrate 101 can include any one of silicon (Si), germanium (Ge), and copper (Cu). Since the materials of silicon, germanium, and copper have the characteristics of high thermal conductivity, by setting the material of the substrate 101 to include at least one of silicon, germanium, and copper, the heat dissipation efficiency and effect of the substrate 101 can be improved, thereby improving the working performance and working life of the light emitting chip 10.

[0075] Furthermore, Figure 2 Only one structure shape and size, such as area, thickness, and the like, of the substrate 101 are exemplarily illustrated, and the specific structure shape or size of the substrate 101 is not limited to this. That is, the structure shape and size of the substrate 101 can be adjusted according to actual needs.

[0076] Further, the light emitting chip 10 can be, but is not limited to, an LED, a mini-LED, a Micro-LED, and the like. Meanwhile, the structure of the light emitting chip 10 can be, but is not limited to, a vertical structure, a flip-chip structure, a face-up structure, and the like.

[0077] The embodiments of the present application exemplarily introduce each light emitting chip 10 as a vertical structure chip.

[0078] In Figure 2In the shown embodiment, each light emitting chip 10 is a vertical structure chip, that is, two electrode layers of each light emitting chip 10 are respectively located at opposite sides of the epitaxial structure.

[0079] Specifically, the light emitting chip 10 comprises a first electrode layer 11, an epitaxial structure 13 and a second electrode layer 12. The epitaxial structure 13 is stacked between the first electrode layer 11 and the second electrode layer 12 in a direction perpendicular to the plane of the substrate 101, and the first electrode layer 11 and the second electrode layer 12 are both electrically connected with the epitaxial structure 13.

[0080] By setting the epitaxial structure 13 to be electrically connected between the first electrode layer 11 and the second electrode layer 12, the first electrode layer 11 and the second electrode layer 12 can jointly act to pass current to the epitaxial structure 13, so as to turn on the epitaxial structure 13 and emit light outward.

[0081] Meanwhile, the epitaxial structure 13 is stacked between the first electrode layer 11 and the second electrode layer 12, so that the light emitting chip 10 forms a vertical structure chip, thereby improving the anti-static capability and heat dissipation capability of the light emitting chip 10, and further ensuring the working performance and working efficiency of the light emitting chip 10.

[0082] Among them, the polarities of the first electrode layer 11 and the second electrode layer 12 are opposite. That is, when the first electrode layer 11 in the epitaxial structure 13 is an N-type electrode layer, the second electrode layer 12 is a P-type electrode layer. At this time, the first electrode layer 11 can transmit electrons to the multi-quantum well layer in the epitaxial structure 13, and the second electrode layer 12 can transmit holes to the multi-quantum well layer in the epitaxial structure 13. The electrons and holes recombine in the multi-quantum well layer to form photons and emit light, so as to form the effect of the epitaxial structure 13 emitting light outward.

[0083] Or, when the first electrode layer 11 in the epitaxial structure 13 is a P-type electrode layer, the second electrode layer 12 is an N-type electrode layer. At this time, the first electrode layer 11 transmits holes to the multi-quantum well layer, and the second electrode layer 12 transmits electrons to the multi-quantum well layer. The electrons and holes recombine in the multi-quantum well layer to form photons and emit light, so as to form the effect of the epitaxial structure 13 emitting light outward.

[0084] It should be noted that, in the above embodiment, Figure 2 In the shown embodiment, only the first electrode layer 11 of the epitaxial structure 13 is an N-type electrode layer, and the second electrode layer 12 is a P-type electrode layer, which is exemplarily described for the light emitting chip 10, but the first electrode layer 11 is not limited to only being an N-type electrode layer, and the second electrode layer 12 is not limited to only being a P-type electrode layer.

[0085] Meanwhile, in the above embodiment, Figure 2In the shown embodiment, only one possible structure arrangement position and connection position between the epitaxial structure 13, the first electrode layer 11 and the second electrode layer 12 in the light emitting chip 10 is taken as an example for exemplarily illustrating the position of each functional layer structure in the light emitting chip 10, and the position of each functional layer structure in the light emitting chip 10 is not limited to this, which can be adjusted according to actual needs.

[0086] In one embodiment, please refer to Figure 2 . In Figure 2 In the shown embodiment, the light emitting chip 10 further comprises a passivation layer 14, which covers the epitaxial structure 13 and the first electrode layer 11. And a through hole 141 is formed on the surface of the passivation layer 14 away from the driving back plate 103, that is, a through hole 141 is formed on the surface of the passivation layer 14 away from the substrate 101. Wherein, the through hole 141 penetrates to the epitaxial structure 13.

[0087] Specifically, as shown in Figure 3 , the passivation layer 14 covers the top surface 131, the side wall 132 of the epitaxial structure 13, and the second side wall 111 of the first electrode layer 11, and is connected to the surface of the driving layer 102 away from the substrate 101. Wherein, at least part of the top surface 131 of the epitaxial structure 13 is exposed outward from the through hole 141.

[0088] The second electrode layer 12 is arranged on the surface of the passivation layer 14 away from the substrate 101, and the second electrode layer 12 extends into the through hole 141 and is electrically connected to the epitaxial structure 13.

[0089] It can be understood that by arranging the passivation layer 14, the effect of protecting each epitaxial structure 13, first electrode layer 11 and other layer structures can be achieved, avoiding the pollution or oxidation of each layer structure in the light emitting chip 10 by harmful impurities, and thus the normal working performance and working effect of the light emitting chip 10 can be ensured. By forming the through hole 141 on the passivation layer 14, the subsequent preparation of the second electrode layer 12 is facilitated, and the effect that the second electrode layer 12 can form an electrical connection with the epitaxial structure 13 is achieved, realizing the effect of conducting the epitaxial structure 13.

[0090] Please refer to Figure 3 , Figure 3 is a working flow diagram of the light emitting chip preparation method of the present application. The light emitting chip preparation method of the present application is used to prepare the light emitting chip 10 described in any of the above embodiments. In Figure 4 In the shown embodiment, the light emitting chip preparation method of the present application comprises the following steps:

[0091] S100, preparing a first electrode layer 11 and an epitaxial layer 13a on a driving back plate 103, the first electrode layer 11 being electrically connected between the driving back plate 103 and the epitaxial layer 13a;

[0092] Specifically, please refer toFigure 4 , Figure 4 This is a schematic diagram of the structure from one side when the epitaxial layer 13a is bonded on the driving backplate 103. In step S100, "preparing the first electrode layer 11 and the epitaxial layer 13a on the driving backplate 103", the epitaxial layer 13a can be grown on the growth substrate first, and the driving layer 102 and the first electrode layer 11 can be prepared on the substrate 101 by means of metal evaporation or other processes, but are not limited to. Then the epitaxial layer 13a is transferred from the growth substrate and bonded to the first electrode layer 11, and the growth substrate is removed.

[0093] It is understandable that transferring the epitaxial layer 13a and bonding it with the first electrode layer 11 can achieve the effect of bonding the epitaxial layer 13a to the driving backplane 103, so as to facilitate the subsequent process of fabricating the light-emitting chip 10.

[0094] like Figure 5 As shown, a driving layer 102, a first electrode layer 11, and an epitaxial layer 13a are formed on one side surface of the substrate 101, and the driving layer 102, the first electrode layer 11, and the epitaxial layer 13a are stacked sequentially. That is, the driving layer 102 is stacked between the substrate 101 and the first electrode layer 11, and the epitaxial layer 13a is stacked on the side of the first electrode layer 11 that is away from the substrate 101.

[0095] S200, etching the epitaxial layer 13a to form multiple spaced epitaxial structures 13;

[0096] Please see Figure 5 , Figure 4 for Figure 5 A schematic diagram of the structure from one side when fabricating multiple epitaxial structures 13 in the illustrated embodiment. (See diagram below.) Figure 5 As shown, the epitaxial layer 13a can be etched using, but not limited to, dry etching or wet etching methods, to form a plurality of spaced epitaxial structures 13 on the side of the first electrode layer 11 away from the substrate 101.

[0097] In other words, multiple epitaxial structures 13 are spaced apart on the side of the first electrode layer 11 away from the substrate 101, and each epitaxial structure 13 is electrically connected to the first electrode layer 11.

[0098] It should be noted that, in Figure 6 In the illustrated embodiment, the formation of two epitaxial structures 13 on the surface of the first electrode layer 11 away from the substrate 101 is used as an example for illustrative purposes only. However, this application does not limit the embodiment to the formation of only two epitaxial structures 13 after etching the epitaxial layer 13a. The number, size, shape, and other characteristics of the epitaxial structures 13 formed after etching the epitaxial layer 13a can be changed according to actual design requirements, and this application does not impose specific limitations on this.

[0099] S300, preparing a mask layer 20 on the surface of each epitaxial structure 13 away from the driving backboard 103; wherein the mask layer 20 comprises a protection layer 21 and a photoresist 22;

[0100] Please refer to Figure 6 , Figure 6 The work flow diagram for preparing the mask layer 20 on the surface of each epitaxial structure 13 away from the driving backboard 103. In Figure 7 the embodiment shown, the step S300 of "preparing a mask layer 20 on the surface of each epitaxial structure 13 away from the driving backboard 103" comprises:

[0101] S301, using a spin coating method to prepare a pre-mask layer 20a on the surface of each epitaxial structure 13 away from the driving backboard 103;

[0102] Please refer to Figure 7 , Figure 7 The structure diagram of a one-side perspective view for preparing the pre-mask layer 20a on the surface of each epitaxial structure 13 away from the substrate 101. As Figure 7 shown, the spin coating method can be used to prepare the pre-mask layer 20a on the surface of each epitaxial structure 13 away from the substrate 101.

[0103] The pre-mask layer 20a comprises a pre-protection layer 21a and a pre-photoresist 22a.

[0104] In Figure 7 the embodiment shown, the pre-protection layer 21a is laminated between the epitaxial structure 13 and the pre-photoresist 22a. Specifically, the spin coating method can be used to sequentially coat the pre-protection layer 21a and the pre-photoresist 22a on the surface of each epitaxial structure 13 away from the substrate 101.

[0105] In other words, the pre-protection layer 21a can be coated on the surface of each epitaxial structure 13 away from the substrate 101 first, and then the pre-photoresist 22a can be coated on the surface of the pre-protection layer 21a away from the substrate 101, so as to form the effect that the pre-protection layer 21a and the pre-photoresist 22a are sequentially on the surface of each epitaxial structure 13 away from the substrate 101.

[0106] It can be understood that by using the spin coating method to prepare the pre-mask layer 20a on the surface of each epitaxial structure 13 away from the substrate 101, a plurality of mask layers 20 can be ultimately formed, so as to improve the uniformity of each protection layer 21 in the planar direction along the substrate 101, and further improve the uniformity of the protection layer 21 flowing on the side wall 132 from the circumferential direction of the epitaxial structure 13, and further improve the coverage effect and the coverage uniformity of the protection layer 21, so as to avoid the adverse phenomenon of affecting the protection effect of the protection layer 21 on the side wall of the epitaxial structure 13 due to uneven coverage.

[0107] It should be noted that inFigure 8 In the embodiment shown, only the preparation of the pre-mask layer 20a by the spin coating method is exemplarily described, but the application is not limited to the preparation of the pre-mask layer 20a by the spin coating method. In other embodiments of the application, the pre-mask layer 20a can also be prepared by other possible methods or processes, which are not specifically limited in the application.

[0108] S302, the pre-mask layer 20a is patterned by exposure and development technology to expose the first electrode layer 11 between the epitaxial structures 13, and the pre-mask layer 20a forms a mask layer 20 on the surface of each epitaxial structure 13 away from the driving back plate 103.

[0109] Please refer to Figure 8 , Figure 8 is a structural schematic diagram of a one-side view when the mask layer 20 is formed on the surface of each epitaxial structure 13 away from the substrate 101. Figure 8 In the embodiment shown, the pre-mask layer 20a can be patterned by exposure and development technology to expose the first electrode layer 11 between the epitaxial structures 13, and the pre-mask layer 20a forms a mask layer 20 on the surface of each epitaxial structure 13 away from the substrate 101.

[0110] Specifically, as shown in Figure 8 each epitaxial structure 13 has opposite top and bottom surfaces 131 and 133, and the top surface 131 is located on the side of the epitaxial structure 13 away from the driving back plate 103. The pre-mask layer 20a can be exposed and developed to form a mask layer 20 on the top surface 131 of each epitaxial structure 13, i.e., each mask layer 20 covers the top surface 131 of one epitaxial structure 13.

[0111] It can be understood that by preparing the photoresist 22 on the side of each epitaxial structure 13 away from the substrate 101, the epitaxial structure 13 can be protected in the subsequent preparation process, avoiding damage to the epitaxial structure 13 in the subsequent etching process and affecting the working performance and efficiency of the epitaxial structure 13.

[0112] An embodiment, please refer to Figure 8 . As shown in Figure 9 the protective layer 21 is located between the epitaxial structure 13 and the photoresist 22.

[0113] By setting the protective layer 21 between the epitaxial structure 13 and the photoresist 22, i.e., covering the photoresist 22 on the side of the protective layer 21 away from the substrate 101, the photoresist 22 is located in the outermost layer, so as to ensure that the photoresist 22 has a protective effect on the epitaxial structure 13, and the photoresist 22 can have a protective effect on the protective layer 21, and can improve the etching precision and etching effect in the subsequent dry etching process of the first electrode layer 11.

[0114] In an embodiment, the melting point temperature of the protective layer 21 is between 70°C and 120°C.

[0115] In the embodiment, the melting point temperature of the protective layer 21 is between 70°C and 120°C, so that the energy generated in the subsequent dry etching process can reach the melting point temperature of the protective layer 21, thereby ensuring the melting effect and efficiency of the protective layer 21, and avoiding the phenomenon that the melting point temperature of the protective layer 21 is too high to be melted.

[0116] At the same time, by controlling the melting point temperature of the protective layer 21 between 70°C and 120°C, the shaping effect of the protective layer 21 can be ensured, and the phenomenon that the protective layer 21 may be prematurely melted due to the high ambient temperature before etching the first electrode layer 11 can be avoided.

[0117] In an embodiment, the material of the protective layer 21 is polyimide (PI) or polymethyl methacrylate (PMMA).

[0118] The film layer of polyimide or polymethyl methacrylate has good heat sensitivity and fluidity. By setting the material of the protective layer 21 as polyimide or polymethyl methacrylate, the heat sensitivity of the protective layer 21 can be ensured, thereby ensuring the flow effect and efficiency of the protective layer 21 on the side wall 132 of the epitaxial structure 13.

[0119] S400, the first electrode layer 11 is patterned by using dry etching technology to expose the driving back plate 103 between the epitaxial structures 13; wherein the photoresist 22 is used to protect the epitaxial structure 13, and the protective layer 21 melts and flows along the side wall 132 of the epitaxial structure 13 to cover the side wall 132 during dry etching;

[0120] Please refer to Figure 9 , Figure 9 is a structure schematic diagram from one side view when the first electrode layer 11 is patterned by using dry etching technology. In step S400, the first electrode layer 11 is etched by using dry etching technology to expose the driving back plate 103 between the epitaxial structures 13, which can realize the preparation of the micron size order light emitting chip 10.

[0121] By preparing the mask layer 20 on the surface of each epitaxial structure 13 away from the substrate 101, and patterning the first electrode layer 11 by using dry etching technology, the first electrode layer 11 between the epitaxial structures 13 is removed and the driving back plate 103 between the epitaxial structures 13 is exposed, thereby forming a plurality of independent light emitting chips 10 bonded on the driving back plate 103.

[0122] Meanwhile, by etching the first electrode layer 11 between the epitaxial structures 13 to form a plurality of independent light emitting chips 10, the effect that each light emitting chip 10 is directly bonded to the driving back plate 103 is formed, and thus the preparation process of the vertical structure light emitting chip 10 can be simplified and the preparation efficiency of the vertical structure light emitting chip 10 can be improved.

[0123] Further, in the process of patterning the first electrode layer 11 by using the dry etching technology, the high-energy ions after dissociation physically bombard the mask layer 20 to make the temperature of the mask layer 20 rise, and thus the protective layer 21 melts and flows to cover the sidewall 132 of the epitaxial structure 13.

[0124] Since the energy generated by the high-energy ions after dissociation physically bombarding the mask layer 20 in the process of etching the first electrode layer 11 by using the dry etching technology is large, the temperature of the protective layer 21 rises quickly, that is, the temperature of the protective layer 21 reaches the melting point of the protective layer 21 at a fast speed to melt.

[0125] However, the etching speed of the dry etching technology is slow when etching the first electrode layer 11. Therefore, in a possible embodiment, as shown in Figure 9 the protective layer 21 melts and flows along the sidewall 132 of the epitaxial structure 13 to the side of the bottom surface 133 of the epitaxial structure 13 to be able to protect the sidewall of the epitaxial structure, avoid the phenomenon that metal particles are sputtered onto the epitaxial structure 13 in the process of etching the first electrode layer 11, and cause the current to be unable to pass through the quantum well layer in the epitaxial structure 13 or the short circuit of the light emitting chip 10, so as to be able to improve the yield of the light emitting chip 10 prepared by the light emitting chip preparation method of the present application and ensure the light emitting efficiency and light emitting effect of the light emitting chip 10.

[0126] In a possible embodiment, please refer to Figure 9 . As shown in Figure 9 , the step S400 “the protective layer 21 melts and flows along the sidewall 132 of the epitaxial structure 13 when dry etching” includes:

[0127] The protective layer 21 continuously covers the sidewall 132 along the circumference of the epitaxial structure 13.

[0128] In the present embodiment, by setting the protective layer 21 to continuously cover the sidewall 132 along the circumference of the epitaxial structure 13, the protective layer 21 can continuously cover and protect the sidewall 132 along the circumference of the epitaxial structure 13, and thus the coverage rate and coverage effect of the protective layer 21 on the epitaxial structure 13 can be ensured and improved, so as to further improve the yield of the light emitting chip 10 prepared by the light emitting chip preparation method of the present application.

[0129] In a possible embodiment, please refer to Figure 9 . As shown in Figure 9As shown, step S400, "the protective layer 21 melts during dry etching and flows along the sidewall 132 of the epitaxial structure 13," includes:

[0130] The protective layer 21 at least completely covers the sidewall 132 of the extensional structure 13.

[0131] In this embodiment, by setting the protective layer 21 to at least completely cover the sidewall 132 of the epitaxial structure 13, the coverage effect and coverage rate of the protective layer 21 on the epitaxial structure 13 can be guaranteed, thereby further improving the protective effect of the protective layer 21 on the epitaxial structure 13, and thus improving the yield of the light-emitting chip 10 prepared by the light-emitting chip preparation method of this application.

[0132] One embodiment is also described below. Figure 9 .like Figure 9 As shown, the projection of the top surface 131 of the extension structure 13 onto the drive backplate 103 is contained within the bottom surface 133, that is, the projection of the top surface 131 onto the drive layer 102 is contained within the bottom surface 133.

[0133] Specifically, in Figure 9 In the embodiment shown, the area of ​​the top surface 131 is smaller than the area of ​​the bottom surface 133 along the planar direction of the substrate 101, thereby forming the effect that the projection of the top surface 131 on the driving layer 102 is contained within the bottom surface 133, so that the sidewall 132 of the epitaxial structure 13 is formed perpendicular to the plane of the substrate 101 or inclined relative to the plane of the substrate 101.

[0134] That is, the cross-section of the extension structure 13 forms a "trapezoidal" shape, which can further improve the flow effect of the protective layer 21 on the sidewall 132 of the extension structure 13, and further improve the coverage effect and coverage efficiency of the protective layer 21.

[0135] It should be noted that, in Figure 10 The embodiments shown are only exemplified by one possible embodiment in which the projection of the top surface 131 on the driving layer 102 is contained within the bottom surface 133. However, the relative sizes of the top surface 131 and the bottom surface 133 are not limited to this. In other embodiments of this application, the relative sizes of the top surface 131 and the bottom surface 133 can be adjusted according to actual design requirements. This application does not make any specific limitations in this regard.

[0136] For example, in one possible embodiment, the area of ​​the top surface 131 can be equal to the area of ​​the bottom surface 133 along the planar direction of the substrate 101, so as to form the effect that the sidewall 132 of the epitaxial structure 13 is perpendicular to the substrate 101, so that the cross section of the epitaxial structure 13 forms a "rectangular" shape, thereby further improving the flow effect and flow rate of the protective layer 21 on the sidewall 132.

[0137] One embodiment, please refer to Figure 10 , Figure 9 is Figure 10 structure diagram of one side view when the protective layer 21 flows to the second side wall 111 of the first electrode layer 11 in the embodiment shown. As Figure 11 shown, the step S400 "the protective layer 21 melts and flows along the side wall 132 of the epitaxial structure 13 when dry etching" includes:

[0138] When the protective layer 21 completely covers the side wall 132 of the epitaxial structure 13, the protective layer 21 continues to flow along the second side wall 111 of the first electrode layer 11 towards the substrate 101, and there is a gap S between the side of the protective layer 21 close to the substrate 101 and the etching surface 112 of the first electrode layer 11.

[0139] It can be understood that in the embodiment, when the protective layer 21 completely covers the side wall 132 of the epitaxial structure 13, the protective layer 21 continues to flow along the second side wall 111. At this time, there is a gap S between the side of the protective layer 21 close to the substrate 101 and the etching surface 112 of the first electrode layer 11, and the value of S is greater than 0, so as to avoid that the protective layer 21 flows too fast to affect the etching effect and etching efficiency of the first electrode layer 11.

[0140] Further, please refer to Figure 11 , Figure 11 is a structure diagram of one side view when the first electrode layer 11 is etched to the driving layer 102 by using the dry etching method. As Figure 12 shown, when the first electrode layer 11 is etched to the driving layer 102 by using the dry etching method, the driving layer 102 between the epitaxial structures 13 is exposed, so as to form a plurality of independent light emitting chips 10 bonded on the driving layer 102.

[0141] In the process of etching the first electrode layer 11 by using the dry etching method, the protective layer 21 completely covers the side wall 132 of the epitaxial structure 13, which avoids the phenomenon that metal particles are sputtered on the epitaxial structure 13 in the process of etching the first electrode layer 11, and thus the epitaxial structure 13 with good performance can be obtained.

[0142] S500, remove the mask layer 20 and prepare the second electrode layer 12 on each epitaxial structure 13 respectively.

[0143] Please refer to Figure 12 , Figure 12 is a working flow diagram of removing the mask layer 20 and preparing the second electrode layer 12 on each epitaxial structure 13 respectively. As Figure 13 shown, the step S500 "remove the mask layer 20 and prepare the second electrode layer 12 on each epitaxial structure 13 respectively" includes:

[0144] S501. Remove the mask layer 20 using an organic adhesive remover;

[0145] Please see Figure 13 , Figure 12 for Figure 13 A schematic diagram of the structure from one side when the mask layer 20 is removed in the illustrated embodiment. Figure 14 In the embodiment shown, an organic resist remover can be used to remove the protective layer 21 and the photoresist 22, and while cleaning and removing the mask layer 20, it can also remove the metal particles sputtered onto the protective layer 21.

[0146] In other words, both the protective layer 21 and the photoresist 22 in the mask layer 20 are adhesive layers. The mask layer 20 can be removed by an organic resist remover. While removing the mask layer 20 to facilitate subsequent process fabrication, the metal particles sputtered onto the protective layer 21 can be removed simultaneously to obtain a high-performance epitaxial structure 13, thereby improving the working performance and efficiency of the epitaxial structure 13.

[0147] S502, a second electrode layer 12 is prepared on each epitaxial structure 13.

[0148] Please see Figure 14 , Figure 14 This is a schematic diagram illustrating the workflow for fabricating a second electrode layer 12 on each epitaxial structure 13. (See diagram below.) Figure 15 As shown, step S502, "fabricating a second electrode layer 12 on each epitaxial structure 13", includes:

[0149] S5021. A passivation layer 14 is prepared on each epitaxial structure 13, and the passivation layer 14 covers the epitaxial structure 13 and the first electrode layer 11.

[0150] Please see Figure 15 , Figure 15 A schematic diagram of the structure from one side when a passivation layer 14 is fabricated on each epitaxial structure 13. (See diagram below.) Figure 15 As shown, the passivation layer 14 covers the surface of each epitaxial structure 13 facing away from the substrate 101 and covers the second sidewall 111 of the first electrode layer 11 to form multiple independent light-emitting chips 10.

[0151] in, Figure 2 The passivation layer 14 in the illustrated embodiment can be with Figure 15 The passivation layer 14 in the illustrated embodiment has the same technical effects and structural features, and will not be described again here. Figure 16 The structural features and technical effects of the passivation layer 14 in the illustrated embodiment.

[0152] S5022. A through hole 141 is prepared on the surface of the passivation layer 14 away from the driving backplate 103, and the through hole 141 extends to the epitaxial structure 13.

[0153] Referring to Figure 16 , Figure 16 is a schematic structural view of the one side view when the via hole 141 is prepared on the surface of the passivation layer 14 away from the substrate 101. In Figure 16 the embodiment shown, the via hole 141 can be prepared on the surface of the passivation layer 14 away from the substrate 101 by etching or the like.

[0154] Specifically, each via hole 141 penetrates the passivation layer 14 in a direction perpendicular to the plane of the substrate 101, so that at least part of the top surface 131 of the epitaxial structure 13 corresponding to each via hole 141 is exposed, facilitating the subsequent preparation of the second electrode layer 12 and enabling the second electrode layer 12 to be electrically connected to the epitaxial structure 13.

[0155] wherein, Figure 2 the via hole 141 in the embodiment shown can have the same technical effects and structural features as the via hole 141 in the embodiment shown in Figure 16 , and thus will not be described here in detail Figure 2 the structural features and technical effects of the via hole 141 in the embodiment shown.

[0156] S5023, the second electrode layer 12 is prepared on the surface of the passivation layer 14 away from the driving back plate 103, and the second electrode layer 12 extends into the via hole 141 and is electrically connected to the epitaxial structure 13.

[0157] Specifically, please refer to Figure 2 . As shown in ​ , the second electrode layer 12 is prepared on the surface of the passivation layer 14 away from the substrate 101, and the second electrode layer 12 extends into the via hole 141 and is electrically connected to the epitaxial structure 13, thereby completing the preparation of the light emitting chip 10.

[0158] Generally, in the process of etching the electrode layer by dry etching technology, high-energy ions physically bombard the electrode layer, which can cause metal particles in the electrode layer to be sputtered onto the sidewall of the epitaxial structure. The metal sputtered onto the sidewall can cause the current to be unable to pass through the quantum well layer in the epitaxial structure or the short circuit of the light emitting chip.

[0159] The light emitting chip preparation method of the present application can form a plurality of independent light emitting chips 10 bonded on the driving back plate 103 by preparing a mask layer 20 on the surface of each epitaxial structure 13 away from the driving back plate 103, and patterning the first electrode layer 11 by dry etching technology to remove the first electrode layer 11 between the epitaxial structures 13 and expose the driving back plate 103 between the epitaxial structures 13.

[0160] Meanwhile, by etching the first electrode layer 11 between the epitaxial structures 13 to form a plurality of independent light emitting chips 10, the effect that each light emitting chip 10 is directly bonded to the driving back plate 103 is formed, and thus the preparation process of the vertical structure light emitting chip 10 can be simplified, and the preparation efficiency of the vertical structure light emitting chip 10 can be improved.

[0161] By preparing the photoresist 22 on the side of each epitaxial structure 13 away from the substrate 101, the epitaxial structure 13 can be protected in the subsequent preparation process, and damage to the epitaxial structure 13 in the subsequent etching process is avoided, and the working performance and working efficiency of the epitaxial structure 13 are affected.

[0162] In the process of patterning the first electrode layer 11 by using the dry etching technology, the dissociated high-energy ions physically bombard the mask layer 20 to make the temperature of the mask layer 20 rise, and then the protective layer 21 melts and flows to cover the sidewall 132 of the epitaxial structure 13, so as to protect the sidewall 132 of the epitaxial structure 13, avoid the sputtering of metal particles onto the epitaxial structure 13 in the process of etching the first electrode layer 11, and cause the current to pass through the quantum well layer in the epitaxial structure 13 or the short circuit of the light emitting chip 10. The phenomenon of bad phenomenon occurs, so as to improve the yield of the light emitting chip 10 prepared by the light emitting chip preparation method of the present application, and ensure the light emitting efficiency and light emitting effect of the light emitting chip 10.

[0163] Meanwhile, by etching the first electrode layer 11 at the same time, the energy generated in the dry etching process is used to heat the protective layer 21 synchronously and make the protective layer 21 melt and cover the sidewall 132 of the epitaxial structure 13, which can further simplify the preparation process of the light emitting chip preparation method of the present application, and further improve the preparation efficiency of the light emitting chip preparation method of the present application.

[0164] It should be understood that the terms "first", "second" and the like are used only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first", "second" can explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, the meaning of "a plurality of" is two or more, unless otherwise specifically limited.

[0165] In the description of the specification, the description using the terms "one embodiment", "some embodiments", "an exemplary embodiment", "an example", "a specific example" or "some examples" etc. means that the particular feature, structure, material or characteristic being described is included in at least one embodiment or example of the application. The illustrative appearances of the above-mentioned terms in various places in the specification are not necessarily intended to refer to the same embodiment or example. Moreover, the particular features, structures, materials or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0166] It should be understood that the application is not limited to the examples described above, which can be modified or transformed by a person of ordinary skill in the art according to the above description, and all these modifications and transformations shall fall within the protection scope of the claims of the application. A person of ordinary skill in the art can understand that all or part of the processes of the above embodiments are implemented, and equivalent changes are made according to the claims of the application, which still fall within the scope of the application.

Claims

1. A method of manufacturing a light emitting chip, characterized by, The method comprises the following steps: Preparation of a first electrode layer and an epitaxial layer on a driving backplane, the first electrode layer being electrically connected between the driving backplane and the epitaxial layer; Etching the epitaxial layer to form a plurality of spaced epitaxial structures; Preparation of a mask layer on the surface of each epitaxial structure away from the driving backplane; wherein the mask layer comprises a protective layer and a photoresist; Patterning the first electrode layer using dry etching technology to expose the driving backplane between the epitaxial structures; wherein the photoresist is used to protect the epitaxial structures, and the protective layer melts and flows along the sidewalls of the epitaxial structures during dry etching to cover the sidewalls; Removal of the mask layer and preparation of a second electrode layer on each epitaxial structure; The protective layer is located between the epitaxial structure and the photoresist.

2. The light emitting chip manufacturing method of claim 1, wherein, The melting point temperature of the protective layer is between 70°C and 120°C.

3. The light emitting chip manufacturing method of claim 2, wherein the first and second electrodes are formed by a photolithography process. The material of the protective layer is polyimide or polymethyl methacrylate.

4. The light emitting chip manufacturing method of claim 1, wherein The epitaxial structure has opposite top and bottom surfaces, the top surface being located on the side of the epitaxial structure away from the driving backplane, and the projection of the top surface on the driving backplane being contained within the bottom surface.

5. The light emitting chip manufacturing method according to any one of claims 1 to 4, wherein The protective layer melts and flows along the sidewalls of the epitaxial structure during dry etching, comprising: The protective layer continuously covers the sidewalls of the epitaxial structure in the circumferential direction.

6. The method of claim 5, wherein the step of forming the light emitting chip is performed by a method comprising: The protective layer melts and flows along the sidewalls of the epitaxial structure during dry etching, comprising: ​ The protective layer at least completely covers the sidewalls of the epitaxial structure.

7. The light emitting chip manufacturing method according to any one of claims 1 to 4, wherein The preparation of a mask layer on the surface of each epitaxial structure away from the driving backplane, comprising: Preparation of a pre-mask layer on the surface of each epitaxial structure away from the driving backplane using a spin coating method; Patterning the pre-mask layer using exposure and development technology to expose the first electrode layer between the epitaxial structures, the pre-mask layer forming the mask layer on the surface of each epitaxial structure away from the driving backplane.

8. The light emitting chip manufacturing method according to any one of claims 1 to 4, wherein The removal of the mask layer and the preparation of a second electrode layer on each epitaxial structure, comprising: Removal of the mask layer using an organic stripping solution; Preparation of the second electrode layer on each epitaxial structure.

9. The light emitting chip manufacturing method of claim 8, wherein, Before the preparation of the second electrode layer on each epitaxial structure, comprising: Preparation of a passivation layer on each epitaxial structure, the passivation layer covering the epitaxial structure and the first electrode layer; Preparation of a via on the surface of the passivation layer away from the driving backplane, the via penetrating to the epitaxial structure; Then, the preparation of the second electrode layer on each epitaxial structure, comprising: Preparation of the second electrode layer on the surface of the passivation layer away from the driving backplane, the second electrode layer extending into the via and being electrically connected to the epitaxial structure.

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