Envelope detector, amplitude demodulator and electronic equipment

Abstract

The embodiment of the invention provides an envelope detector, an amplitude demodulator and electronic equipment, and is applied to the technical field of electronic device signal processing. The envelope detector comprises a comparison circuit and a first filter circuit. The output end of the comparison circuit is coupled with the input end of the first filter circuit. The first input end of the comparison circuit is used for inputting a first analog signal. The second input end of the comparison circuit is used for inputting a first reference signal. The comparison circuit is used for outputting a first DC signal according to a first analog signal and a first reference signal. The level value of the first direct current signal is used for indicating the size relation between the first analog signal and the first reference signal. The first filter circuit is used for outputting a first envelope signal according to the first DC signal. The signal amplitude of the first envelope signal is used for indicating the signal peak value of the first direct current signal. According to the embodiment of the invention, low-cost, high-processing-precision and high-processing-rate envelope detection processing on the first analog signal is realized.

Description

Technical Field

[0001] The present application relates to the technical field of electronic device signal processing, and in particular to an envelope detector, an amplitude demodulator and an electronic device. Background Art

[0002] Envelope detectors are provided in many electronic devices (such as transmitting devices, receiving devices, etc.). The input analog signal is processed by the envelope detector to obtain the corresponding envelope signal. The electronic device performs subsequent signal processing based on the generated envelope signal to achieve various functions. There are many ways to implement envelope detectors, but low-cost envelope detectors usually have low processing accuracy and processing rate, while envelope detectors with high processing accuracy and high processing rate have very complex structures and very high device costs. Summary of the invention

[0003] The embodiment of the present application provides an envelope detector, an amplitude demodulator and an electronic device, thereby obtaining an envelope detector with low cost, high processing rate and high processing accuracy.

[0004] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0005] In a first aspect, an envelope detector is proposed, which includes a comparison circuit and a first filtering circuit. The output end of the comparison circuit is coupled to the input end of the first filtering circuit. The first input end of the comparison circuit is used to input a first analog signal. The second input end of the comparison circuit is used to input a first reference signal. Wherein: the comparison circuit is used to: output a first DC signal according to the first analog signal and the first reference signal. The first analog signal carries a first data signal, and the signal amplitude of the first analog signal is used to indicate the values ​​of multiple bits of the first data signal. The level value of the first DC signal is used to indicate the magnitude relationship between the first analog signal and the first reference signal. The first filtering circuit is used to: output a first envelope signal according to the first DC signal; the signal amplitude of the first envelope signal is used to indicate the values ​​of multiple bits of the first data signal.

[0006] In an embodiment of the present application, the voltage value of the first reference signal is determined according to the ASK modulation parameters of the first analog signal received in the actual application scenario. The first reference signal and the first analog signal are input through a comparison circuit, and the sizes of the first reference signal and the first analog signal are compared to obtain a first DC signal. The level value of the first DC signal can indicate the size relationship between the first analog signal and the first reference signal, that is, the size of the signal peak value of the first analog signal and the signal amplitude of the first reference signal. Then, based on the first DC signal filtering, the first envelope signal is obtained, and the first envelope signal can be used to indicate the values ​​of multiple bits of the first data information carried on the first analog signal. By combining the comparison circuit with the first filtering circuit in the embodiment of the present application, low-cost, high processing accuracy and high processing rate envelope detection processing of the first analog signal is realized.

[0007] In one possible implementation, a common-mode interference signal is carried on the first analog signal. The envelope detector further includes an anti-common-mode interference circuit. The anti-common-mode interference circuit is coupled to the first input terminal of the comparison circuit. In an embodiment of the present application, when a common-mode interference signal exists, the anti-common-mode interference circuit can remove the influence of the common-mode interference signal on the comparison circuit.

[0008] In some examples, the anti-common mode interference circuit may be a common mode interference filtering circuit. In this case, the anti-common mode interference circuit is used to: input a first analog signal carrying a common mode interference signal, and then output the first analog signal after filtering out the common mode interference signal to the comparison circuit. Exemplarily, the common mode interference filtering circuit may be an anti-common mode coupling inductor, etc. The embodiment of the present application may directly filter out the common mode interference signal to eliminate interference.

[0009] In some examples, the anti-common mode interference circuit is a second filter circuit. The first end of the second filter circuit is coupled to the first input end of the comparison circuit. The second end of the second filter circuit is coupled to the second input end of the comparison circuit. The second filter circuit is used to: the first end of the second filter circuit inputs the first analog signal, and the second end of the second filter circuit outputs the common mode interference signal to the second input end of the comparison circuit. In an embodiment of the present application, the common mode interference signal can be transmitted to the first input end and the second input end of the comparison circuit respectively. In the process of comparison processing performed by the comparison circuit, the common mode interference signals of the two input ends can compensate for the comparison voltage difference when comparing the voltage values ​​to achieve interference removal.

[0010] In a possible implementation, the second filtering circuit includes a first equivalent resistor. A first end of the first equivalent resistor is coupled to a first input end of the comparison circuit. A second end of the first equivalent resistor is coupled to a second input end of the comparison circuit. The first equivalent resistor is used to: input a first analog signal to the first end of the first equivalent resistor, and output a common-mode interference signal to the second input end of the comparison circuit at the second end of the first equivalent resistor.

[0011] In a possible implementation, the first equivalent resistor is further used for: the second end of the first equivalent resistor outputs a first reference signal to the second input end of the comparison circuit. In the embodiment of the present application, the frequency response to the common-mode interference signal can be achieved by the equivalent resistor to filter the common-mode interference signal from the first input end of the comparison circuit to the second input end.

[0012] In a possible implementation, the second filtering circuit includes a first equivalent capacitor. The first end of the first equivalent capacitor is coupled to the first input end of the comparison circuit. The second end of the first equivalent capacitor is coupled to the second input end of the comparison circuit. The first equivalent capacitor is used for: the first end of the first equivalent capacitor inputs the first analog signal, and the second end of the first equivalent capacitor outputs the common-mode interference signal to the second input end of the comparison circuit. In an embodiment of the present application, the frequency response to the common-mode interference signal can be achieved by the equivalent capacitor to filter the common-mode interference signal from the first input end of the comparison circuit to the second input end.

[0013] In a possible implementation, the envelope detector further includes a first equivalent resistor. The first end of the first equivalent resistor and the first end of the first equivalent capacitor are connected in parallel and coupled to the first input end of the comparison circuit. The second end of the first equivalent resistor and the second end of the first equivalent capacitor are connected in parallel and coupled to the second input end of the comparison circuit. The first equivalent resistor is used for: the first end of the first equivalent resistor inputs a first analog signal, and the second end of the first equivalent resistor outputs a first reference signal to the second input end of the comparison circuit. In the embodiments of the present application, in some examples, voltage division can be achieved by the first equivalent resistor to generate a first reference signal. The common-mode interference signal is filtered through by the first equivalent capacitor. In some examples, voltage division can be achieved by the first equivalent resistor to generate a first reference signal. The common-mode interference signal is filtered through by the first equivalent resistor and the first equivalent capacitor.

[0014] In a possible implementation, the envelope detector further includes a second equivalent resistor. The first end of the second equivalent resistor is coupled to the first input end of the comparison circuit; the second end of the second equivalent resistor is grounded. In the embodiment of the present application, the comparison voltage difference between the first input end and the second input end of the comparison circuit can be adjusted by the second equivalent resistor to match different comparison voltage differences under different scene requirements, thereby improving the processing accuracy of the envelope detector.

[0015] In one possible implementation, the envelope detector further includes a reference signal circuit. The second filter circuit includes a first equivalent capacitor. The output end of the reference signal circuit is coupled to the second input end of the comparison circuit. The first end of the first equivalent capacitor is coupled to the first input end of the comparison circuit. The second end of the first equivalent capacitor is coupled to the second input end of the comparison circuit. The reference signal circuit is used to: output a first reference signal to the first input end of the comparison circuit. In an embodiment of the present application, the first reference signal can be generated by the reference signal circuit. Alternatively, the first reference signal is generated by combining the reference signal circuit and the first equivalent resistor.

[0016] In a possible implementation, the envelope detector further includes a first bias circuit. The output end of the first bias circuit is coupled to the first input end of the comparison circuit. The first bias circuit is used to: output a first bias voltage to the first input end of the comparison circuit. In the embodiment of the present application, the voltage at the first input end of the comparison circuit is adjusted by the first bias circuit to adjust the comparison voltage difference between the first input end and the second input end of the comparison circuit, so as to match different comparison voltage differences under different scene requirements, thereby improving the processing accuracy of the envelope detector.

[0017] In a possible implementation, the envelope detector further includes a second bias circuit. The output end of the second bias circuit is coupled to the second input end of the comparison circuit. The second bias circuit is used to: output a second bias voltage to the second input end of the comparison circuit. In the embodiment of the present application, the voltage at the second input end of the comparison circuit is adjusted by the second bias circuit to adjust the comparison voltage difference between the first input end and the second input end of the comparison circuit, so as to match different comparison voltage differences under different scene requirements, thereby improving the accuracy of the envelope detector.

[0018] In a possible implementation, the envelope detector further includes a limiting circuit. The limiting circuit is coupled to the first input terminal of the comparison circuit. In the embodiment of the present application, the first analog signal input to the envelope detector is limited by the limiting circuit to avoid loss, interference and other problems to subsequent devices.

[0019] In the second aspect, the embodiment of the present application further proposes an amplitude demodulator, which includes a shaping circuit and an envelope detector as described in the first aspect. The output end of the envelope detector is coupled to the input end of the shaping circuit. Wherein: the envelope detector is used to: input a first analog signal and output an envelope signal to the shaping circuit; the first analog signal carries a first data signal, and the signal amplitude of the first analog signal is used to indicate the values ​​of multiple bits of the first data signal. The shaping circuit is used to: obtain a first level signal according to the envelope signal; the level value of the first level signal is used to indicate the values ​​of multiple bits of the first data signal.

[0020] In a third aspect, an embodiment of the present application further proposes an electronic device, which includes a circuit board and the envelope detector as described in the first aspect above; the envelope detector is arranged on the circuit board.

[0021] In a fourth aspect, an embodiment of the present application further proposes a chip system, which includes at least one controller and at least one interface circuit. At least one controller and at least one interface circuit can be interconnected via lines. The controller is used to support the chip system to implement the various functions or steps in the above method embodiments, and at least one interface circuit can be used to receive signals from other devices (such as communication interfaces, data processing circuits, baseband signal generation circuits, power amplification systems, antennas, processors, memories, etc.), or to send signals to other devices (such as communication interfaces, data processing circuits, baseband signal generation circuits, power amplification systems, antennas, processors, memories, etc.). The chip system may include chips and may also include other discrete devices.

[0022] Regarding the technical principles and beneficial effects of the second, third and fourth aspects, reference may be made to the relevant description of the first aspect mentioned above and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A schematic diagram of a switch modulation signal proposed in an embodiment of the present application;

[0024] Figure 2 A schematic diagram of the structure of a receiving device proposed in an embodiment of the present application;

[0025] Figure 3 A schematic diagram of the structure of a first amplitude demodulator proposed in an embodiment of the present application;

[0026] Figure 4 A schematic diagram of the structure of a second amplitude demodulator proposed in an embodiment of the present application;

[0027] Figure 5 The embodiment of the present application Figure 4 A schematic diagram of a demodulated signal of a second amplitude demodulator shown;

[0028] Figure 6 A schematic diagram of the structure of an envelope detector proposed in an embodiment of the present application Figure 1 ;

[0029] Figure 7 The embodiment of the present application Figure 6 A schematic diagram of a demodulated signal of an envelope detector shown;

[0030] Figure 8 A schematic diagram of another envelope detector proposed in the embodiment of the present application Figure 2 ;

[0031] Fig. 9 For example, the embodiment of the present application Figure 8 A schematic diagram of a demodulated signal of an envelope detector shown;

[0032] Fig.10 A schematic diagram of the structure of another envelope detector proposed in the embodiment of the present application Figure 3 ;

[0033] Fig.11 A schematic diagram of the structure of another envelope detector proposed in the embodiment of the present application Figure 4 ;

[0034] Fig.12 A schematic diagram of the structure of another envelope detector proposed in the embodiment of the present application Figure 5 ;

[0035] Fig.13 A schematic diagram of the structure of another envelope detector proposed in the embodiment of the present application Figure 6 ;

[0036] Fig.14 A schematic diagram of the structure of another envelope detector proposed in the embodiment of the present application Figure 7 ;

[0037] Fig.15 A schematic diagram of the structure of another envelope detector proposed in the embodiment of the present application Figure 8 ;

[0038] Fig.16 A schematic diagram of the structure of another envelope detector proposed in the embodiment of the present application Figure 9 ;

[0039] Fig.17 A schematic diagram of the structure of another envelope detector proposed in the embodiment of the present application Figure 10 ;

[0040] Fig.18 A schematic diagram of the structure of a chip system proposed in an embodiment of the present application. DETAILED DESCRIPTION

[0041] It should be noted that the terms "first", "second", etc. involved in the embodiments of the present application are only used to distinguish features of the same type and cannot be understood as indicating relative importance, quantity, order, etc.

[0042] The terms "exemplary" or "for example" and the like in the embodiments of the present application are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of the terms "exemplary" or "for example" is intended to present the related concepts in a specific way.

[0043] The terms "coupling" and "connection" involved in the embodiments of the present application should be understood in a broad sense. For example, they may refer to a direct physical connection, or an indirect connection achieved through electronic devices, such as a connection achieved through resistors, inductors, capacitors or other electronic devices.

[0044] First, some basic concepts involved in the embodiments of this application are explained:

[0045] Detector: A detector is a device used to detect some useful information in a fluctuating analog signal. It can be used to identify the existence or change of waves, oscillations or signals. Detectors are usually used to extract information carried by the analog signal. Detectors can generally be divided into synchronous detectors, envelope detectors, etc. The envelope signal output by the envelope detector corresponds to the envelope of the input analog signal. The output envelope signal can be used for: In the transmitting device, detection feedback processing of the modulated signal to be transmitted. Or, in the receiving device, demodulation of the received modulated signal.

[0046] Modulation and demodulation: Modulation and demodulation are important means of modern communication. Modulation is to use data signals to control certain parameters (such as phase, amplitude, etc.) of the waveform of the carrier signal, which is an analog signal, to obtain a modulated signal. Among them, the modulated signal is an analog signal, and the parameters of its waveform change with the parameters of the data signal (that is, the data signal is carried on the carrier signal). Demodulation is the inverse process of modulation, which is the process of recovering the data signal from the modulated signal. Depending on whether the data signal carried on the carrier signal is an analog signal or a digital signal, modulation technology can be divided into two categories: analog modulation and digital modulation. Among them, digital modulation can be divided into amplitude shift keying (ASK), frequency shift keying (FSK) and phase shift keying (PSK).

[0047] ASK modulation is a modulation method that controls the amplitude change of the carrier signal according to the data value of the data signal in the form of a digital signal. According to the data value of the data signal, the amplitude of the carrier signal is adjusted to obtain a modulated signal after ASK modulation. For example, a simple ASK modulation method is On-Off Keying (OOK) modulation, such as Figure 1As shown, OOK modulation is based on a modulation switch S1. The modulation switch S1 is used to receive a carrier signal and a data signal, and the data signal is in the form of a digital signal. The data signal is used to control the on and off of the modulation switch S1, which can be specifically: the data signal has multiple bits, and the multiple bits are combined to obtain a string of data values. Each bit has a different level value, and different level values ​​correspond to different data values ​​of each bit. Each bit of the data signal is sent to the modulation switch S1 in sequence. When the data signal is a first level (for example, a high level representing data 1), the modulation switch S1 is controlled to be turned on to output a carrier signal; when the data signal is a second level (for example, a low level representing data 0), the modulation switch S1 is controlled to be turned off to not output a carrier signal. The modulation signal is obtained according to the signal waveform output by the modulation switch S1 within a period of time. The signal amplitude corresponding to the waveform of the modulation signal corresponds to the data value of the data signal. The transmitting device transmits the modulation signal, and after receiving the modulation signal, the receiving device detects the amplitude of the modulation signal to obtain the corresponding data value of the data signal, that is, the demodulation of the modulation signal is completed. Therefore, in ASK modulation, the signal peak of the modulated signal changes with the data value of the data signal. By connecting the signal peak points of the modulated signal together, an envelope can be obtained, and the change of the envelope corresponds to the change of the data value of the data signal.

[0048] The embodiment of the present application provides an electronic device, which includes a circuit board and an envelope detector. The envelope detector is arranged on the circuit board. Exemplarily, the electronic device can be a receiving device, a transmitting device, a signal processing device, etc.

[0049] Take the electronic device as the receiving device as an example, Figure 2 As shown, the receiving device 1000 includes an amplitude demodulator 100 and a data processor 200. The amplitude demodulator 100 is used to: output a first level signal according to a first analog signal. The first analog signal carries a first data signal, and the signal amplitude of the first analog signal is used to indicate the values ​​of multiple bits of the first data signal. The level value of the first level signal is used to indicate the values ​​of multiple bits of the first data signal. In an embodiment of the present application, the first analog signal is a modulated signal that carries the first data signal after ASK modulation. The amplitude demodulator 100 obtains a first level signal according to the first analog signal. The level of the first level signal corresponds to the values ​​of multiple bits of the first data signal.

[0050] In some possible implementations, such as Figure 2 The amplitude demodulator 100 shown may be a first amplitude demodulator based on an analog-to-digital converter for digital detection. Figure 3As shown, the first amplitude demodulator 100A includes an analog-to-digital converter 10 and a digital controller 20. The analog-to-digital converter 10 is used to: input a first analog signal, and convert the first analog signal into a first digital signal. The value of the first digital signal is used to indicate the signal amplitude of the first analog signal. The digital controller 20 is used to: output a first level signal according to the first digital signal. In the embodiment of the present application, the first analog signal is converted into a first digital signal through analog-to-digital conversion, and the amplitude of the waveform of the first analog signal is indicated by the value of the first digital signal to complete digital detection. Then, the digital controller 20 outputs the first level signal according to the value of the first digital signal. In the embodiment of the present application, when the analog-to-digital converter 10 is used, an additional controller needs to be set to manage and control the processing process of the analog-to-digital conversion, so that the hardware complexity of the amplitude demodulator 100 is greatly increased. At the same time, the processing rate and processing accuracy of the digital detection depend on the processing rate and processing accuracy of the analog-to-digital converter 10. The processing rate and processing accuracy of the analog-to-digital converter 10 are positively correlated with the hardware complexity of the analog-to-digital converter 10. When high processing rate and high processing accuracy are required, such as Figure 3 The hardware complexity and hardware cost of the illustrated embodiments tend to be significant.

[0051] In some possible implementations, such as Figure 2 The amplitude demodulator 100 shown may be a second amplitude demodulator based on a detection device that performs envelope detection. Figure 4 As shown, the second amplitude demodulator 100B includes an envelope detector 30 and a shaping circuit 40. The output end of the envelope detector 30 is coupled to the input end of the shaping circuit 40. Wherein:

[0052] The envelope detector 30 is used to input a first analog signal and output a first envelope signal to the shaping circuit 40. The shaping circuit 40 is used to obtain a first level signal according to the first envelope signal.

[0053] In the embodiment of the present application, the first analog signal is a modulated signal after ASK modulation. The first data signal is a data value of the first data signal carried by the modulated signal. Figure 5 As shown, the envelope detector 30 outputs a first envelope signal according to the first analog signal, and the first envelope signal corresponds to the signal peak envelope of the first analog signal. The shaping circuit 40 obtains a first level signal according to the first envelope signal. The first level signal is a digital signal, which has a constant level value (for example, a constant high level corresponds to data 1, and a constant low level corresponds to data 0). The first level signal in the form of a digital signal is a signal that the data processor 200 can perform signal data processing. Figure 2As shown, the amplitude demodulator 100 outputs the obtained first level signal to the data processor 200, and the data processor 200 performs corresponding data processing based on the first level signal.

[0054] In some examples, such as Figure 4 The envelope detector 30 shown may be based on a detector diode. Figure 6 As shown, the envelope detector 30 includes a detection diode D1, a filter capacitor CD and a filter resistor RD. The output end of the detection diode D1 is coupled to the input end of the shaping circuit 40. The filter capacitor CD and the filter resistor RD form a low-pass filter and are coupled to the output end of the detection diode D1. Among them: the input end of the detection diode D1 is used to input a first analog signal. The output end of the detection diode D1 is used to output a unilateral amplitude modulation signal. The low-pass filter formed by the filter capacitor CD and the filter resistor RD is used to: output a baseband envelope signal according to the unilateral amplitude modulation signal, and the signal amplitude of the baseband envelope signal is used to indicate the data value of the first data signal. The shaping circuit 40 obtains a first level signal according to the baseband envelope signal. In an embodiment of the present application, the diode has unilateral conductivity, such as Figure 7 As shown, the signal amplitude of the first analog signal carrying the first data signal changes according to the change of the data value of the first data signal. After the first analog signal is input to the detector diode D1, only the forward voltage part of the first analog signal can pass through the detector diode D1, so that the detector diode D1 outputs the forward voltage part of the first analog signal, that is, the single-sided amplitude modulation signal. Then, the low-pass filter formed by the filter capacitor CD and the filter resistor RD processes the signal part corresponding to each frequency cycle in the single-sided amplitude modulation signal, specifically: as the signal amplitude of the single-sided amplitude modulation signal input to the low-pass filter changes (corresponding to the change of the input voltage), the filter capacitor CD will charge and discharge, etc., so that the signal amplitude in each frequency cycle of the single-sided amplitude modulation signal can be averaged to obtain the baseband envelope signal. The waveform of the baseband envelope signal is used to indicate the data value of the first data signal, which may be: when the signal amplitude of the baseband envelope signal is greater than the first amplitude (for example, 0), the data value of the first data signal is 1; when the signal amplitude of the baseband envelope signal is less than or equal to the first amplitude (for example, 0), the data value of the first data signal is 0. The baseband envelope signal is shaped by the shaping circuit 40 to obtain a first level signal.

[0055] But in Figure 6In the embodiment shown, the cost of the detector diode D1 is relatively low, but the detector diode D1 has a conduction voltage drop, that is, when the signal amplitude of the first analog signal is greater than the conduction voltage drop of the detector diode D1, the detector diode D1 can output the corresponding conduction signal. Therefore, when part or all of the forward signal of the first analog signal is less than or equal to the conduction voltage drop, the detector diode D1 cannot achieve normal operation. Because the conduction voltage drop of the detector diode D1 is usually at the level of several hundred millivolts (mV), this means that the accuracy of the detector diode D1 is not high and can only process large signals with larger amplitudes. For example, when the signal amplitude of the first analog signal is greater than the conduction voltage drop, but the signal amplitude of part of the first analog signal is close to the conduction voltage drop, there will be problems such as the cutting distortion of the bottom signal of the first analog signal by the detector diode D1, resulting in low detection accuracy. At the same time, when the first analog signal is such as Figure 7 In the case of a single-sided amplitude modulated signal as shown, the detector diode D1 cannot perform envelope detection processing.

[0056] In some examples, such as Figure 4 The envelope detector 30 shown may be based on a detector tube. Figure 6 The detector diode D1 shown in the figure uses a detector tube as Figure 4 The envelope detector 30 shown can improve the processing accuracy of the envelope signal obtained based on the first analog signal. However, the detector tube is set inside the chip and can only be used in scenarios with chip specifications. Its flexibility of use is limited, and the dynamic range of application is limited. In addition, the device cost of the detector tube is relatively high, and the processing rate of the detector tube is limited by the performance of the chip in which it is located. In general, the processing rate of the detector is relatively low. If the processing rate of the detector tube needs to be increased, the performance of the chip in which it is located needs to be improved accordingly, which increases the cost sharply.

[0057] In some possible implementations, in order to achieve high processing rate and high processing accuracy detection at a low cost, such as Figure 4 The envelope detector 30 shown may be based on a comparison circuit. Figure 8 As shown, the envelope detector 30 includes a comparison circuit 1 and a first filtering circuit 2. The output end of the comparison circuit 1 is coupled to the input end of the first filtering circuit 2. The first input end of the comparison circuit 1 is used to input a first analog signal. The second input end of the comparison circuit 1 is used to input a first reference signal. Wherein: the comparison circuit 1 is used to: output a first DC signal according to the first analog signal and the first reference signal. The level value of the first DC signal is used to indicate the magnitude relationship between the first analog signal and the first reference signal. The first filtering circuit 2 is used to: output a first envelope signal according to the first DC signal. The signal amplitude of the first envelope signal is used to indicate the signal amplitude peak value of the first DC signal.

[0058] Exemplarily, the comparison circuit 1 can be based on a first comparator. In the embodiment of the present application, the comparator is a device with a relatively mature design in the industry, which has low cost and strong availability. And the comparator has good signal processing consistency under high and low temperature environments. The comparison threshold of the comparator is flexibly adjustable (the threshold adjustment can be completed by adjusting the value of the first reference signal). The detection threshold of the comparator is at the level of several millivolts (mV), and it has high detection accuracy and fast response processing rate. The embodiment of the present application adopts a solution of combining the comparison circuit 1 with the first filter circuit 2, which has higher reliability, larger dynamic range, and higher detection sensitivity than the above-mentioned detection diode D1 and detection tube to realize envelope detection. And compared with the above Figure 3 The embodiment of digital detection shown in the figure, the present application implements for example Figure 8 The circuit structure of the embodiment shown is more concise, the devices used are simpler and more mature, and the cost is quite low. The embodiment of the present application realizes envelope detection with high processing rate and high processing accuracy at low cost by combining the comparison circuit 1 and the first filter circuit 2.

[0059] In this application Figure 8 In the embodiment shown, in ASK modulation, the signal peak value of the obtained modulation signal (i.e., the first analog signal) varies with the data value of the first data signal. The first reference signal is set according to the modulation parameters (such as signal amplitude, etc.) during ASK modulation. The comparison circuit 1 inputs the first reference signal and the first analog signal. When the first analog signal is greater than or equal to the first reference signal, the comparison circuit 1 outputs a first level (such as a high level); when the first analog signal is less than the first reference signal, the comparison circuit 1 outputs a second level (such as a low level). The comparison circuit 1 obtains a first DC signal in the form of a DC signal according to the first analog signal. When the signal amplitude of the first DC signal is greater than 0, the level of the first DC signal is the first level, indicating that the first analog signal is greater than or equal to the first reference signal. When the signal amplitude of the first DC signal is equal to 0, the level of the first DC signal is the second level, indicating that the first analog signal is less than the first reference signal. The value of the first DC signal can reflect the corresponding relationship between the signal amplitude of the first analog signal and the data value of the first data signal. The high-frequency signal on the first DC signal is filtered out by the first filtering circuit 2, and the low-frequency envelope waveform is retained to obtain the first envelope signal. The first envelope signal represents the change of the signal peak value of the first DC signal. When the signal amplitude of the first envelope signal is greater than the second amplitude (for example, 0), the data value of the first data signal is 1; when the signal amplitude of the first envelope signal is equal to the second amplitude (for example, 0), the data value of the first data signal is 0. The first envelope signal is shaped based on the second amplitude by the shaping circuit 40 to obtain a regular first level signal, and the level value of the first level signal. The first level signal is output to the data processor 200 to complete the data processing of the first data signal.

[0060] For example, Fig. 9 As shown, ASK modulation is performed according to the first data signal to obtain a first analog signal. Take the first data signal including 4 bits, and the corresponding values ​​of the 4 bits are 0101 as an example. In the case where the carrier signal is modulated by OOK modulation: the 4 bits of the first data signal are sequentially controlled as follows Figure 1 The modulation switch S1 shown in the figure is turned on or off, and the following can be obtained: Fig. 9 The comparison circuit 1 obtains the first analog signal as shown in FIG. Fig. 9 As shown in the figure, the signal segment of the first DC signal having a signal amplitude greater than 0 corresponds to the first signal segment of the first analog signal, wherein the first signal segment of the first analog signal is a signal segment corresponding to the value 1 of the first data signal. The first DC signal is shaped by the shaping circuit 40 to obtain a regular first level signal.

[0061] In some possible implementations, the first analog signal carries a common-mode interference signal. Fig.10 As shown, the envelope detector 30 also includes an anti-common mode interference circuit 3; the anti-common mode interference circuit 3 is coupled to the first input terminal of the comparison circuit 1. In the embodiment of the present application, in some application scenarios, there is no common mode interference signal on the first analog signal. At this time, the first analog signal and the first reference signal can be directly input into the comparison circuit 1 for comparison. In some application scenarios, there will be a common mode interference signal on the first analog signal. At this time, it is necessary to remove the interference of the common mode interference signal, and then input the first analog signal into the comparison circuit 1 to ensure the accuracy of signal processing.

[0062] In some examples, the anti-common mode interference circuit 3 is a common mode interference filtering circuit. At this time, the anti-common mode interference circuit 3 is used to: input a first analog signal carrying a common mode interference signal, and then output the first analog signal after filtering out the common mode interference signal to the comparison circuit 1. Exemplarily, the common mode interference filtering circuit can be an anti-common mode coupling inductor, etc.

[0063] In some examples, such as Fig.11As shown, the anti-common mode interference circuit 3 is a second filter circuit 3A. The first end of the second filter circuit 3A is coupled to the first input end of the comparison circuit 1. The second end of the second filter circuit 3A is coupled to the second input end of the comparison circuit 1. The second filter circuit 3A is used to: the first end of the second filter circuit 3A inputs a first analog signal, and the second end of the second filter circuit 3A outputs a common mode interference signal to the second input end of the comparison circuit 1. In the embodiment of the present application, the second filter circuit 3A is respectively coupled to the first input end and the second input end of the comparison circuit 1. When the first input end of the comparison circuit 1 inputs a first analog signal carrying a common mode interference signal, the second filter circuit 3A filters the common mode interference signal from the first input end of the comparison circuit 1 to the second input end of the comparison circuit 1, so that the first input end and the second input end of the comparison circuit 1 are both input with a common mode interference signal. When the comparison circuit 1 compares the signals input to the first input end and the second input end, the interference compensation in the comparison process can be realized by inputting the common mode interference signal to both input ends.

[0064] In an embodiment of the present application, the first analog signal and the common-mode interference signal are electromagnetic wave signals of a certain frequency. The common-mode interference signal has a certain frequency response, that is, when the transmission path meets a certain frequency response, filtering can be achieved. In an embodiment of the present application, according to parameters such as the frequency of the signal in the actual application scenario, a corresponding frequency response relationship can be set for the second filter circuit 3A to achieve the effect of filtering the common-mode interference signal. In some examples, the second filter circuit 3A can be an equivalent resistor, an equivalent capacitor, an equivalent inductor, etc., or a combination of at least two of an equivalent resistor, an equivalent capacitor, and an equivalent inductor.

[0065] In some possible implementations, the first reference signal may be provided to the second input terminal of the comparison circuit 1 through the second filter circuit 3A.

[0066] For example, Fig.12 As shown, the second filtering circuit 3A includes a first equivalent resistor R1. The first end of the first equivalent resistor R1 is coupled to the first input end of the comparison circuit 1. The second end of the first equivalent resistor R1 is coupled to the second input end of the comparison circuit 1. The first equivalent resistor R1 is used for: the first end of the first equivalent resistor R1 inputs a first analog signal, and the second end of the first equivalent resistor R1 outputs a common-mode interference signal to the second input end of the comparison circuit 1. In the embodiment of the present application, by setting the resistance value of the first equivalent resistor R1 to achieve a certain frequency response, the common-mode interference signal is filtered out. At the same time, the first equivalent resistor R1 has a certain resistance value, which will achieve the effect of voltage division, and the first reference signal is obtained by inputting the voltage division of the first equivalent resistor R1, and the first reference signal is output to the second input end of the comparison circuit 1.

[0067] For example, Fig.13 As shown, the second filtering circuit 3A includes a first equivalent resistor R1 and a first equivalent capacitor C1. The first end of the first equivalent capacitor C1 is coupled to the first input end of the comparison circuit 1. The first end of the first equivalent resistor R1 and the first end of the first equivalent capacitor C1 are coupled to the first input end of the comparison circuit 1 after being connected in parallel. The second end of the first equivalent resistor R1 and the second end of the first equivalent capacitor C1 are coupled to the second input end of the comparison circuit 1 after being connected in parallel. In some examples, the first equivalent capacitor C1 has a frequency response relationship for filtering through common-mode interference signals, and the first equivalent resistor R1 does not have a frequency response relationship for filtering through common-mode interference signals. At this time, the first equivalent resistor R1 is used for: the first end of the first equivalent resistor R1 inputs the first analog signal, and the second end of the first equivalent resistor R1 outputs the first reference signal to the second input end of the comparison circuit 1. The first equivalent capacitor C1 is used for: the first end of the first equivalent capacitor C1 inputs the first analog signal, and the second end of the first equivalent capacitor C1 outputs the common-mode interference signal to the second input end of the comparison circuit 1. In some examples, the first equivalent capacitor C1 and the first equivalent resistor R1 have a frequency response relationship for filtering common-mode interference signals. At this time, the first end of the first equivalent capacitor C1 and the first equivalent resistor R1 connected in parallel inputs the first analog signal, the second end of the first equivalent capacitor C1 outputs the common-mode interference signal, and the second end of the second equivalent resistor R2 outputs the first reference signal.

[0068] Exemplarily, the second filtering circuit 3A includes a first equivalent resistor R1 and a first equivalent inductor. In some examples, the first equivalent resistor R1 and the first equivalent inductor are connected in parallel. In some examples, the first equivalent resistor R1 and the first equivalent inductor are connected in series. In an embodiment of the present application, a first reference signal is obtained by the first equivalent resistor R1. The first equivalent resistor R1 and the first equivalent inductor are used together to realize a frequency response with respect to a common-mode interference signal to filter through the common-mode interference signal. Alternatively, a frequency response with respect to a common-mode interference signal is realized by the first equivalent inductor to filter through the common-mode interference signal.

[0069] In some possible implementations, a first reference signal is provided to the comparison circuit 1 through a reference signal circuit. Fig.14 As shown, the envelope detector 30 also includes a reference signal circuit 4. The output end of the reference signal circuit 4 is coupled to the second input end of the comparison circuit 1. The reference signal circuit 4 is used to: output a first reference signal to the first input end of the comparison circuit 1. In the embodiment of the present application, a constant first reference signal can be generated by the reference signal circuit 4 and passed to the second input end of the comparison circuit 1.

[0070] For example, in an embodiment where the first reference signal is outputted through the reference signal circuit 4, the common mode interference signal can be filtered out through an equivalent capacitor. Fig.14As shown, the first end of the first equivalent capacitor C1 is coupled to the first input end of the comparison circuit 1. The second end of the first equivalent capacitor C1 is coupled to the second input end of the comparison circuit 1. The first equivalent capacitor C1 is used for: the first end of the first equivalent capacitor C1 inputs the first analog signal, and the second end of the first equivalent capacitor C1 outputs the common-mode interference signal to the second input end of the comparison circuit 1. In the embodiment of the present application, the first equivalent capacitor C1 can be used to filter the common-mode interference signal, and the first reference signal can be output through the reference signal circuit 4.

[0071] For example, in an embodiment where the first reference signal is outputted through the reference signal circuit 4, the common mode interference signal can be filtered through by the first equivalent inductor. The first end of the first equivalent inductor is coupled to the first input end of the comparison circuit 1, and the second end of the first equivalent inductor is coupled to the second input end of the comparison circuit 1.

[0072] In some possible implementations, the first reference signal may be generated by the reference signal circuit 4 and the first equivalent resistor R1 in the second filter circuit 3A, and output to the second input terminal of the comparison circuit 1 .

[0073] For example, Fig.15 As shown, the second filtering circuit 3A includes a first equivalent resistor R1. The first end of the first equivalent resistor R1 is coupled to the first input end of the comparison circuit 1. The second end of the first equivalent resistor R1 and the output end of the reference signal circuit 4 are commonly coupled to the second input end of the comparison circuit 1. In the embodiment of the present application, a first reference signal can be jointly generated by the first equivalent resistor R1 and the reference signal circuit 4, and output to the second input end of the comparison circuit 1. Regarding the relevant description of the second filtering circuit 3A filtering through the common-mode interference signal when the reference signal circuit 4 and the first equivalent resistor R1 in the second filtering circuit 3A jointly generate the first reference signal, reference can be made to the relevant description of filtering through the common-mode interference signal in the embodiment in which the reference signal circuit 4 generates the first reference signal and the embodiment in which the first equivalent resistor R1 in the second filtering circuit 3A generates the first reference signal, which will not be repeated here.

[0074] In some possible implementations, the comparison voltage difference between the first input terminal and the second input terminal of the comparison circuit 1 can be adjusted according to different application scenarios. In the embodiment of the present application, the comparison voltage difference between the first input terminal and the second input terminal of the comparison voltage 1 is related to the amplitude parameter of ASK modulation, the demodulation accuracy of ASK demodulation, etc. According to the parameter setting of the actual application device, the demodulation accuracy of the application scenario and other requirements, different comparison voltage differences can be set accordingly. For example, when there is no first analog signal input at the first input terminal of the comparison circuit 1, and the first reference signal is input at the second input terminal of the comparison circuit 1, the voltage value of the first input terminal of the comparison circuit 1 is less than the voltage value of the second input terminal of the comparison circuit 1, and the comparison circuit 1 outputs a low level. During ASK modulation, the minimum value of the signal amplitude of the signal segment representing data 1 on the first analog signal is 10mV. After the first analog signal is input to the first input terminal of the comparison circuit 1, it is only necessary to ensure that the comparison voltage difference is less than or equal to 10mV to meet the first DC signal output by the comparison circuit 1 to meet the subsequent demodulation processing requirements.

[0075] In some examples, the comparison voltage difference can be adjusted by adjusting the voltage division degree of the first reference signal. Fig.15 As shown, the envelope detector 30 further includes a second equivalent resistor R2; a first end of the second equivalent resistor R2 is coupled to the first input end of the comparison circuit 1; and a second end of the second equivalent resistor R2 is grounded. In the embodiment of the present application, the voltage value at the first input end and / or the second input end of the comparison circuit 1 can be adjusted by the second equivalent resistor R2 to adjust the comparison voltage difference between the first input end and the second input end of the comparison circuit 1.

[0076] In some examples, the comparison voltage difference can be adjusted by adjusting the voltage value at the first input terminal of the comparison circuit 1 and / or the voltage value at the second input terminal of the comparison circuit 1:

[0077] For example, Fig.15 As shown, the envelope detector 30 further includes a first bias circuit 5. The output end of the first bias circuit 5 is coupled to the first input end of the comparison circuit 1. The first bias circuit 5 is used to output a first bias voltage to the first input end of the comparison circuit 1. In the embodiment of the present application, the first bias voltage is output to the first input end of the comparison circuit 1 through the first bias circuit 5 to increase the voltage at the first input end of the comparison circuit 1, thereby increasing the comparison voltage difference.

[0078] For example, Fig.15As shown, the envelope detector 30 also includes a second bias circuit 6. The output end of the second bias circuit 6 is coupled to the second input end of the comparison circuit 1. The second bias circuit 6 is used to: output a second bias voltage to the second input end of the comparison circuit 1. In the embodiment of the present application, the second bias circuit 6 outputs a second bias voltage to the second input end of the comparison circuit 1, and the voltage value at the second input end of the comparison circuit 1 is increased by the second bias voltage.

[0079] In some possible implementations, such as Fig.16 As shown, the envelope detector 30 also includes a limiting circuit 7. The limiting circuit 7 is coupled to the first input terminal of the comparison circuit 1. In the embodiment of the present application, the first analog signal after ASK modulation has a change in signal amplitude. In practical applications, depending on the selection of the device, the maximum signal amplitude of the first analog signal may exceed the processable signal amplitude of certain devices. Excessive signal amplitude may cause device loss or reduce signal processing accuracy. Because in the demodulation process, the data corresponding to the signal segment with a signal amplitude greater than a certain value of the first analog signal is regarded as data 1, then limiting the larger signal amplitude will not affect the subsequent demodulation. Therefore, the signal amplitude of the input first analog signal can be processed by the limiting circuit 7. For example, Fig.17 As shown, the limiting circuit 7 may be a limiting diode D2.

[0080] In some possible implementations, in actual applications, according to the waveform of the first analog signal obtained by ASK modulation, the first filter circuit 2 can be adaptively adjusted to filter out the high-frequency signal in the corresponding first DC signal and obtain a low-frequency signal representing the peak change of the first DC signal.

[0081] For example, Fig.17 As shown, the first filter circuit 2 includes a third equivalent resistor R3, a fourth equivalent resistor R4, a second equivalent inductor L2, a third equivalent inductor L3 and a second equivalent capacitor C2. The first end of the third equivalent resistor R3 is coupled to the output end of the comparison circuit 1 as the input end of the first filter circuit 2. The second end of the third equivalent resistor R3 is coupled to the first end of the third equivalent inductor L3 through the second equivalent inductor L2. The second end of the third equivalent inductor L3 is coupled to the input end of the shaping circuit 40 as the output end of the first filter circuit 2. The second equivalent capacitor C2 is grounded and coupled to the second end of the second equivalent inductor L2 and the first end of the third equivalent inductor L3. The fourth equivalent resistor R4 is grounded and coupled to the second end of the third equivalent inductor L3.

[0082] In some possible implementations, the shaping circuit 40 includes an operational amplifier or a second comparator, which receives the second reference signal and the first DC signal through the operational amplifier or the second comparator, and outputs a first level signal by comparing the second reference signal with the first DC signal.

[0083] In some possible implementations, such as Figure 4 As shown, the second amplitude demodulator 100B further includes a first amplifier 50. The output end of the first amplifier 50 is coupled to the input end of the envelope detector 30. In the embodiment of the present application, when the signal power of the first analog signal (i.e., the modulated signal) received by the receiving device is large, the amplitude demodulator 100 can directly perform signal processing on the first analog signal. When the signal power of the first analog signal is small, the first analog signal can be amplified by the first amplifier 50 and then output to the amplitude demodulator 100 for signal processing.

[0084] In some possible implementations, when the electronic device is a transmitting device, the transmitted ASK signal (i.e., the first analog signal) may also be detected based on an envelope detector, and some feedback processing may be performed based on the detection. Regarding the technical principle and beneficial effects of using an envelope detector to process the first analog signal in a transmitting device, reference may be made to the relevant description of the aforementioned embodiment, which will not be repeated here.

[0085] The embodiment of the present application proposes an envelope detector, an amplitude demodulator and an electronic device, which are applied to the field of electronic device signal processing technology. In the traditional envelope detection technology, the method of using a detector diode to realize envelope detection is low in cost, but the application scenario and detection accuracy are limited. The method of realizing detection by a detector tube is relatively expensive and limited to the application within the chip, and the detection performance is limited by the chip performance. Through the digital detection method, the processing accuracy and processing rate are greatly dependent on the large power consumption and high cost support of the analog-to-digital converter, and the cost is extremely high. In the embodiment of the present application, the envelope detection processing of the ASK signal is realized by combining a comparison circuit with a first filter circuit. As a common and mature device on the market, the comparison circuit is low in cost. Compared with the detection diode, in the method of applying the comparison circuit, the processing performance consistency is good under high and low temperature conditions of the comparison circuit, and the comparison voltage difference is flexible and adjustable, the detection accuracy (i.e., the comparison voltage difference) is at the level of several millivolts, and the response speed is fast. Compared with the implementation method using a detector diode and a detector tube, the embodiment of the present application has higher reliability, a larger dynamic adjustment range and application range, and a higher detection sensitivity as a whole. Moreover, the embodiment of the present application can select comparison circuits with different performances according to the application scenario to meet the corresponding processing rate and processing accuracy requirements. In the application scenario of high processing accuracy and high processing rate, the cost of selecting a high-performance comparison circuit is also much lower than the application scenario of digital detection. In addition, the system complexity of the comparison circuit combined with the first filtering circuit is also much lower than the system complexity of the application scenario of digital detection.

[0086] The present application also proposes a chip system, such as Fig.18 As shown, the chip system 300 includes at least one controller 310 and at least one interface circuit 320. At least one controller 310 and at least one interface circuit 320 can be interconnected through lines. The controller 310 is used to support the chip system to implement various functions or steps in the above method embodiments, and at least one interface circuit 320 can be used to receive signals from other devices (such as communication interfaces, data processing circuits, baseband signal generation circuits, power amplification systems, antennas, processors, memories, etc.), or send signals to other devices (such as communication interfaces, data processing circuits, baseband signal generation circuits, power amplification systems, antennas, processors, memories, etc.). The chip system 300 may include chips and may also include other discrete devices.

[0087] The controller involved in the embodiments of the present application may be a chip. For example, it may be a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a system on chip (SoC), a central processor unit (CPU), a network processor (NP), a digital signal processor (DSP), a microcontroller unit (MCU), a programmable logic device (PLD), or other integrated chips.

[0088] It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0089] Those of ordinary skill in the art will appreciate that the modules and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0090] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and modules described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0091] In the several embodiments proposed in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the modules is only a logical function division. There may be other division methods in actual implementation, such as multiple modules or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or modules, which can be electrical, mechanical or other forms.

[0092] The modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical modules, that is, they may be located in one device or distributed on multiple devices. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment.

[0093] In addition, each functional module in each embodiment of the present application may be integrated into one device, or each module may exist physically separately, or two or more modules may be integrated into one device.

[0094] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using a software program, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loading and executing a computer program instruction on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from a website site, a computer, a server or a data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (Digital Subscriber Line, DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium may be any available medium that a computer can access or may contain one or more servers, data centers and other data storage devices that can be integrated with a medium. The available medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape), an optical medium (eg, a DVD), or a semiconductor medium (eg, a solid state disk (SSD)).

[0095] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. An envelope detector, characterized in that: It comprises a comparison circuit and a first filtering circuit; the output end of the comparison circuit is coupled to the input end of the first filtering circuit; the first input end of the comparison circuit is used to input a first analog signal; the second input end of the comparison circuit is used to input a first reference signal; The first analog signal carries a first data signal, and the signal amplitude of the first analog signal is used to indicate the values ​​of multiple bits of the first data signal; wherein: The comparison circuit is used to: output a first DC signal according to the first analog signal and the first reference signal; the level value of the first DC signal is used to indicate the magnitude relationship between the first analog signal and the first reference signal; The first filtering circuit is used to: output a first envelope signal according to the first DC signal; the signal amplitude of the first envelope signal is used to indicate the values ​​of multiple bits of the first data signal.

2. An envelope detector according to claim 1, characterized in that: The first analog signal carries a common-mode interference signal; the envelope detector also includes an anti-common-mode interference circuit; the anti-common-mode interference circuit is coupled to the first input terminal of the comparison circuit.

3. An envelope detector according to claim 2, characterized in that: The anti-common mode interference circuit is a second filter circuit; the first end of the second filter circuit is coupled to the first input end of the comparison circuit; the second end of the second filter circuit is coupled to the second input end of the comparison circuit; the second filter circuit is used to: The first analog signal is input into a first terminal of the second filtering circuit, and the second terminal of the second filtering circuit outputs the common-mode interference signal to a second input terminal of the comparison circuit.

4. The envelope detector according to claim 3, characterized in that: The second filtering circuit includes a first equivalent resistor; a first end of the first equivalent resistor is coupled to a first input end of the comparison circuit; a second end of the first equivalent resistor is coupled to a second input end of the comparison circuit; and the first equivalent resistor is used to: The first analog signal is input into a first end of the first equivalent resistor, and the common-mode interference signal is output to a second input end of the comparison circuit by a second end of the first equivalent resistor.

5. An envelope detector according to claim 4, characterized in that: The first equivalent resistor is further used for: a second end of the first equivalent resistor outputting the first reference signal to a second input end of the comparison circuit.

6. The envelope detector according to claim 3, characterized in that: The second filtering circuit includes a first equivalent capacitor; a first end of the first equivalent capacitor is coupled to a first input end of the comparison circuit; a second end of the first equivalent capacitor is coupled to a second input end of the comparison circuit; and the first equivalent capacitor is used to: The first analog signal is input to a first end of the first equivalent capacitor, and the second end of the first equivalent capacitor outputs the common-mode interference signal to a second input end of the comparison circuit.

7. The envelope detector according to claim 6, characterized in that: The envelope detector further includes a first equivalent resistor; a first end of the first equivalent resistor and a first end of the first equivalent capacitor are connected in parallel and coupled to a first input end of the comparison circuit; a second end of the first equivalent resistor and a second end of the first equivalent capacitor are connected in parallel and coupled to a second input end of the comparison circuit; the first equivalent resistor is used to: The first analog signal is input into a first end of the first equivalent resistor, and the first reference signal is output to a second input end of the comparison circuit by a second end of the first equivalent resistor.

8. An envelope detector according to claim 4 or 7, characterized in that: The envelope detector further includes a second equivalent resistor; a first end of the second equivalent resistor is coupled to the first input end of the comparison circuit; and a second end of the second equivalent resistor is grounded.

9. The envelope detector according to claim 6, characterized in that: The envelope detector further includes a reference signal circuit; the second filter circuit includes a first equivalent capacitor; the output end of the reference signal circuit is coupled to the second input end of the comparison circuit; the first end of the first equivalent capacitor is coupled to the first input end of the comparison circuit; the second end of the first equivalent capacitor is coupled to the second input end of the comparison circuit; the reference signal circuit is used to: The first reference signal is output to a first input terminal of the comparison circuit.

10. An envelope detector according to any one of claims 1 to 9, characterized in that: The envelope detector further includes a first bias circuit; an output terminal of the first bias circuit is coupled to a first input terminal of the comparison circuit; and the first bias circuit is used to: A first bias voltage is output to a first input terminal of the comparison circuit.

11. An envelope detector according to any one of claims 1 to 10, characterized in that: The envelope detector further includes a second bias circuit; an output terminal of the second bias circuit is coupled to a second input terminal of the comparison circuit; and the second bias circuit is used to: A second bias voltage is output to a second input terminal of the comparison circuit.

12. An envelope detector according to any one of claims 1 to 11, characterized in that: The envelope detector further comprises a limiting circuit; the limiting circuit is coupled to the first input terminal of the comparison circuit.

13. An amplitude demodulator, characterized in that: The invention comprises a shaping circuit and an envelope detector as claimed in any one of claims 1 to 12; the output end of the envelope detector is coupled to the input end of the shaping circuit; wherein: The envelope detector is used to: input a first analog signal and output an envelope signal to the shaping circuit; the first analog signal carries a first data signal, and the signal amplitude of the first analog signal is used to indicate the values ​​of multiple bits of the first data signal; The shaping circuit is used to obtain a first level signal according to the envelope signal; the level value of the first level signal is used to indicate the values ​​of multiple bits of the first data signal.

14. An electronic device, characterized in that: It comprises a circuit board and the envelope detector according to any one of claims 1 to 12; the envelope detector is arranged on the circuit board.

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