System and method for phase interpolation

Abstract

The invention relates to a system and method for phase interpolation. A system includes a first phase interpolator, a second phase interpolator, and a circuit. The circuit is configured to receive a first signal and a second signal provided by the first phase interpolator and a third signal and a fourth signal provided by the second phase interpolator. A first circuit is configured to provide at least eight phase signals, each of which is at a respective phase angle in response to the first signal, the second signal, the third signal, and the fourth signal.

Description

Technical Field

[0001] Generally speaking, the present disclosure relates to systems and methods for phase interpolation and clock signal generation, including but not limited to systems and methods for skew and / or jitter reduction associated with clock signals and / or data transfer in communication systems. Background Art

[0002] Data communication systems (e.g., WiFi networks, fiber optic networks, Ethernet, wide area networks, local area networks, storage networks, cellular networks, etc.) often use clock signals to synchronize operations. One example of a data communication system is a passive optical network (PON). A PON can use fiber optic telecommunication technology to deliver broadband network access to end customers. The PON can implement a point-to-multipoint topology in which a single optical fiber serves multiple endpoints by using unpowered or passive fiber optic splitters to divide the fiber bandwidth between the endpoints. The endpoints include electronic data transceivers on a medium, such as a wired medium (e.g., a cable).

[0003] The data transceiver often includes a serializer / deserializer (SERDES) for transmitting data on a recovered clock signal. The SERDES employs a phase interpolator (PI) or similar functional circuit to shift the transmit (or receive) phase in time and / or frequency relative to a local timing reference so that the SERDES can transmit (or receive) data at the same frequency as the frequency of the data transmitted (or received) from a remote peer device detected by the SERDES receiver (or transmitter). The sampling limit of a receiver using a multi-phase clock signal can be affected by static skew and dynamic skew of the interleaved clock paths. Summary of the invention

[0004] In one aspect, the present disclosure relates to a system comprising: a first phase interpolator; a second phase interpolator; and a first circuit configured to receive a first signal and a second signal provided by the first phase interpolator and a third signal and a fourth signal provided by the second phase interpolator, wherein the first circuit is configured to provide at least eight phase signals, each of the eight phase signals being at a corresponding phase angle in response to the first signal, the second signal, the third signal, and the fourth signal.

[0005] In another aspect, the present disclosure relates to a device comprising: a first circuit configured to provide a first phase signal at a first inverting output and a second phase signal at a first non-inverting output, the first phase signal having a phase difference of 180 degrees relative to the second phase signal; a second circuit configured to receive the first phase signal at a second non-inverting input and the second phase signal at a second inverting input, and to provide a third phase signal at a second inverting output and a fourth phase signal at a second non-inverting output, the fourth phase signal having a phase difference of 180 degrees relative to the third phase signal; and a first switch configured to connect the first inverting output to the first non-inverting output in response to a first clock signal.

[0006] In another aspect, the present disclosure relates to a method comprising: receiving a first clock signal and a second clock signal provided by a first phase interpolator; receiving a third clock signal and a fourth clock signal provided by a second phase interpolator, wherein the first clock signal, the second clock signal, the third clock signal and the fourth clock signal are each at a corresponding phase angle; using an oscillator to provide a plurality of phase signals, wherein each of the phase signals is at a corresponding phase angle, wherein the number of the phase signals is greater than four; and providing the phase signals to a first buffer and using a first skew control signal to correct a skew associated with the phase signals in the first buffer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various objects, aspects, features and advantages of the present disclosure will become more apparent and better understood by referring to the detailed description in conjunction with the accompanying drawings, wherein like reference characters identify corresponding elements throughout. In the drawings, like reference symbols generally indicate identical, functionally similar and / or structurally similar elements.

[0008] Figure 1A is a schematic block diagram depicting an embodiment of a network environment including one or more wireless communication devices communicating with one or more devices or stations;

[0009] Figure 1B and 1C is a schematic block diagram depicting an embodiment of a computing device for use in conjunction with the methods and systems described herein;

[0010] Figure 2 is a schematic block diagram of a clock signal system including a phase interpolator and an injection locked oscillator according to some embodiments;

[0011] Figure 3 According to some embodiments Figure 2 A more detailed schematic block diagram of an injection locked oscillator illustrated in FIG.

[0012] Figure 4 is a diagram illustrating a method for inputting Figure 3 The phase signal of the injection locked oscillator illustrated in FIG. Figure 3 A waveform diagram showing the relationship between the least significant bit of the integral nonlinearity of the phase signal output by the injection locked oscillator and the phase interpolation code as illustrated in FIG. 1 ; and

[0013] Figure 5 is a diagram illustrating a method for inputting Figure 3 The phase signal of the injection locked oscillator illustrated in FIG. Figure 3 , which is a waveform diagram of the relationship between the least significant bits of the dynamic in-phase and quadrature skew of the phase signal output by the injection-locked oscillator and the phase interpolation code.

[0014] The details of various embodiments of the method and system are set forth in the accompanying drawings and the description below. DETAILED DESCRIPTION

[0015] For the purpose of reading the description of the following various embodiments, the following description of the various parts of this specification and their corresponding contents may be helpful:

[0016] - Section A describes a network environment and a computing environment that can be used to practice the embodiments described herein; and

[0017] - Section B describes embodiments of systems and methods for reducing skew in a communication environment, a storage environment, or a computing environment.

[0018] Some embodiments relate to a system for providing a phase output signal. The system includes a first phase interpolator, a second phase interpolator, and a first circuit. The first circuit is configured to receive a first signal and a second signal provided by the first phase interpolator and a third signal and a fourth signal provided by the second phase interpolator. The first circuit is configured to provide at least eight phase signals, each of the eight phase signals being at a corresponding phase angle in response to the first signal, the second signal, the third signal, and the fourth signal.

[0019] In some embodiments, the first circuit is configured as an injection locked oscillator. In some embodiments, the first circuit includes a number of amplifiers. Each of the amplifiers includes an inverting output and a non-inverting output. Each of the non-inverting output and the inverting output provides one of the phase signals. In some embodiments, the first circuit includes a switch, and each switch is disposed between the non-inverting output and the inverting output of a corresponding one of the amplifiers. In some embodiments, the amplifiers each include an inverting input and a non-inverting input. The inverting output of the first amplifier in the amplifiers is coupled to the non-inverting input of the second amplifier in the amplifiers, and the non-inverting output of the first amplifier is coupled to the inverting input of the second amplifier. In some embodiments, the inverting output of the second amplifier is coupled to the inverting input of the third amplifier in the amplifiers, and the non-inverting output of the second amplifier is coupled to the non-inverting input of the third amplifier. In some embodiments, the inverting output of the third amplifier is coupled to the non-inverting input of the fourth amplifier in the amplifiers, and the non-inverting output of the third amplifier is coupled to the inverting input of the fourth amplifier.

[0020] In some embodiments, the amplifier is an operational amplifier. In some embodiments, the switches each include a gate configured to receive one of the first signal, the second signal, the third signal, or the fourth signal. In some embodiments, the first signal is an in-phase signal and the third signal is a quadrature signal. In some embodiments, the second circuit is configured to buffer input signals related to the first signal, the second signal, the third signal, and the fourth signal, and receive a first skew control signal. In some embodiments, the third circuit is configured to buffer the eight phase signals. The third circuit receives a second skew control signal.

[0021] Some embodiments relate to a device. The device includes a first circuit configured to provide a first phase signal at a first inverting output and a second phase signal at a first non-inverting output. The first phase signal has a phase difference of 180 degrees relative to the second phase signal. The device also includes a second circuit configured to receive the first phase signal at a second non-inverting input and the second phase signal at a second inverting input, and to provide a third phase signal at a second inverting output and a fourth phase signal at a second non-inverting output. The fourth phase signal has a phase difference of 180 degrees relative to the third phase signal. The device also includes a first switch configured to connect the first inverting output to the first non-inverting output in response to a first clock signal.

[0022] In some embodiments, the first clock signal is provided by a first phase interpolator. In some embodiments, a third circuit is configured to receive the third phase signal at a third inverting input and the fourth phase signal at a third non-inverting input, and to provide a fifth phase signal at a third inverting output and a sixth phase signal at a third non-inverting output. The fifth phase signal has a phase difference of 180 degrees relative to the sixth phase signal. In some embodiments, the device further includes a second switch, the second switch being configured to connect the second inverting output to the second non-inverting output in response to a second clock signal. The second clock signal has a phase difference of 90 degrees relative to the first clock signal.

[0023] In some embodiments, the device further includes a fourth circuit configured to receive the fifth phase signal at a fourth non-inverting input and the sixth phase signal at a fourth inverting input, and to provide a seventh phase signal at a fourth inverting output and an eighth phase signal at a fourth non-inverting output. The seventh phase signal has a phase difference of 180 degrees relative to the eighth phase signal. In some embodiments, the device further includes a third switch configured to connect the third inverting output to the third non-inverting output in response to a third clock signal. The third clock signal has a phase difference of 180 degrees relative to the first clock signal.

[0024] In some embodiments, the device further includes a fourth switch. The fourth non-inverting output is coupled to the first non-inverting input of the first circuit, and the fourth inverting output is coupled to the first inverting input of the first circuit. The fourth switch is configured to connect the fourth inverting output to the fourth non-inverting output in response to a fourth clock signal, and the fourth clock signal has a phase difference of 270 degrees relative to the first clock signal.

[0025] Some embodiments relate to a method. The method includes: receiving a first clock signal and a second clock signal provided by a first phase interpolator; and receiving a third clock signal and a fourth clock signal provided by a second phase interpolator. The first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are each at a corresponding phase angle. The method further includes using an oscillator to provide a number of phase signals, each of the phase signals being at a corresponding phase angle. The number of the phase signals is greater than four. The method further includes providing the phase signals to a first buffer and using a first skew control signal to correct a skew associated with the phase signals in the first buffer.

[0026] In some embodiments, the method further includes controlling switches in the oscillator using the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal. In some embodiments, the oscillator is an injection locked oscillator. In some embodiments, the method further includes: a second buffer providing the clock signal; using a second skew control signal to correct a skew associated with the clock signal in the second buffer; and providing the input clock signal from the second buffer to the first phase interpolator and the second phase interpolator.

[0027] In some embodiments, phase adjustment may refer to a change in the phase of a signal. A phase adjustment may be an increase or decrease in the phase of a signal by a fixed or proportional amount.

[0028] A. Computing and Network Environment

[0029] Before discussing specific embodiments of the present solution, aspects of the operating environment and associated system components (eg, hardware elements) are described in conjunction with the methods and systems described herein. Figure 1A , depicting an embodiment of a network environment. In brief, the network environment includes a wireless communication system, which includes one or more base stations 106, one or more wireless communication devices 102, and network hardware components or network hardware. For example, the wireless communication device 102 may include a laptop computer 102, a tablet computer 102, a personal computer 102, and / or a cellular phone device 102. For details of the embodiments of each wireless communication device and / or base station, refer to Figure 1B and 1C In one embodiment, the network environment may be a specific network environment, an infrastructure wireless network environment, a subnet environment, and the like.

[0030] Terms such as "wireless communication device", "user equipment", "mobile station", "mobile", "mobile device", "subscriber station", "subscriber equipment", "access terminal", "terminal", "microphone" and similar terms may refer to a wireless device utilized by a subscriber or user of a wireless communication service to receive or communicate data, control, voice, video, sound, game, or substantially any data stream or signaling stream. In the present disclosure, the foregoing terms may be utilized interchangeably. Similarly, in the present disclosure, terms such as "access point (AP)", "wireless access point (WAP)", "base station", "base transceiver station", "Node B", "evolved Node B (eNode B or eNB)", "home Node B (HNB)", "home access point (HAP)" and similar terms may be utilized interchangeably and refer to a wireless network component or device that serves and receives data, control, voice, video, sound, game, or substantially any data stream or signaling stream from a group of wireless devices. In some embodiments, a phase interpolator may refer to a circuit or device that can shift the phase of a clock signal according to an analog or digital command.

[0031] Reference again Figure 1A , the network devices 106 may be operably coupled to the network hardware via a local area network connection. The network hardware may include routers, gateways, switches, bridges, modems, system controllers, appliances, etc., which may provide a local area network connection for the communication system. Each of the network devices 106 may have an associated antenna or antenna array for communicating with the wireless communication devices 102 in its area. The wireless communication devices 102 may register with a particular access point or base station 106 to receive services from the communication system (e.g., via SU-MIMO or MU-MIMO configuration). For direct connections (e.g., point-to-point communications), some wireless communication devices 102 may communicate directly via an assigned channel and communication protocol. Some of the wireless communication devices 102 may be mobile or relatively static relative to the access point or base station 106.

[0032] In some embodiments, the base station 106 includes a device or module (including a combination of hardware and software) that allows the wireless communication device 102 to connect to a wired network using LTE, Wi-Fi / or other standards. The base station 106 may be implemented, designed, and / or constructed to operate in a wireless local area network (WLAN), such as in a cellular network. In some embodiments, the base station 106 may be connected to a router (e.g., via a wired network) as a standalone device. In other embodiments, the base station may be a component of a router. The base station 106 may provide access to a network to multiple devices 102. For example, the base station 106 may be connected to a wired Ethernet connection and use a radio frequency link to provide wireless connections for other devices 102 to utilize the wired connection. The base station 106 may be constructed and / or implemented to support standards for sending and receiving data using one or more radio frequencies. For example, those standards and frequencies used may be defined by IEEE or 3GPP. The base station 106 may be implemented and / or used to support cellular coverage, public Internet hotspots, and / or implemented and / or used on an internal network to extend the range of a network signal (e.g., Wi-Fi).

[0033] In some embodiments, the network device 106 may be used for a wireless network (e.g., IEEE 802.11, Bluetooth, ZigBee, cellular, any other type of radio frequency based network protocol, and / or variations thereof) (e.g., indoors or within a building). Each of the wireless communication devices 102 may include a built-in radio and / or may be coupled to a radio. Such wireless communication devices 102 and / or network devices 106 may operate in accordance with various aspects of the disclosure presented herein to enhance performance, reduce cost and / or size, and / or enhance broadband applications. Each wireless communication device 102 may be equipped with the ability to act as a client node seeking access to resources (e.g., data and connections to network nodes such as servers) via one or more base stations 106.

[0034] The network connection may include any type and / or form of network and may include any of the following: a point-to-point network, a broadcast network, a telecommunications network, a data communications network, a computer network. The topology of the network may be a bus, star, or ring network topology. The network may be any network topology that is known to those skilled in the art that has the ability to support the operations described herein. In some embodiments, different types of data may be transmitted via different protocols. In other embodiments, the same type of data may be transmitted via different protocols.

[0035] The communication device 102 and the base station 106 may be deployed as and / or executed on any type and form of computing device, such as a computer, network device, or appliance having the ability to communicate over any type and form of network and perform the operations described herein. Figure 1B and 1C A block diagram of a computing device 100 is depicted for practicing an embodiment of a wireless communication device 102 or base station 106. Figure 1B and 1C As shown in FIG. 1 , each computing device 100 includes a central processing unit 121 and a main memory unit 122. Figure 1B As shown in FIG. 1 , computing device 100 may include storage device 128, installation device 116, network interface 118, I / O controller 123, display devices 124a to 124n, keyboard 126, and pointing device 127 (e.g., mouse). Storage device 128 may include, but is not limited to, an operating system and / or software. Figure 1C As shown in , each computing device 100 may also include additional optional elements that communicate with the central processing unit 121, such as a memory port 103, a bridge 170, one or more input / output devices 130a to 130n (generally referred to using element symbol 130), and a cache memory 140.

[0036] The central processing unit 121 is any logic circuit system that responds to instructions fetched from the main memory unit 122 and processes the instructions. In many embodiments, the central processing unit 121 is provided by a microprocessor unit, such as: a microprocessor manufactured by Intel Corporation of Mountain View, California; a microprocessor manufactured by International Business Machines of White Plains, New York; a microprocessor manufactured by ARM Holdings, plc of Cambridge, England, or a microprocessor manufactured by Advanced Micro Devices of Sunnyvale, California. The computing device 100 may be based on any of these processors or any other processor capable of performing operations as described herein.

[0037] The main memory unit 122 may be one or more memory chips capable of storing data and allowing direct access to any storage location by the microprocessor or central processing unit 121, such as any type or variant of static random access memory (SRAM), dynamic random access memory (DRAM), ferroelectric RAM (FRAM), NAND flash memory, NOR flash memory, and solid state disk (SSD). The main memory unit 122 may be based on any of the memory chips described above or any other available memory chip capable of performing the operations described herein. Figure 1B In the embodiment shown in , the central processing unit 121 communicates with the main memory unit 122 via a system bus 150 (described in more detail below). Figure 1C An embodiment of a computing device 100 is depicted in which the processor communicates directly with the main memory unit 122 via the memory port 103. For example, in Figure 1C In the embodiment, the main memory unit 122 may be a DRAM.

[0038] Figure 1C An embodiment is depicted in which the main processor or central processing unit 121 communicates directly with the cache memory 140 via a bipolar bus (sometimes referred to as a backside bus). In other embodiments, the main processor or central processing unit 121 communicates with the cache memory 140 using a system bus 150. Typically, the cache memory 140 has a faster response time than the main memory unit 122 and is provided by, for example, SRAM, BSRAM, or EDRAM. Figure 1C , the central processing unit 121 communicates with various I / O devices 130a-130n via a local system bus or system bus 150. For example, various buses such as a VESA VL bus, an ISA bus, an EISA bus, a Micro Channel Architecture (MCA) bus, a PCI bus, a PCI-X bus, a PCI-Express bus, or a NuBus may be used to connect the central processing unit 121 to any of the I / O devices 130. For embodiments in which the I / O device is a video display 124, the central processing unit 121 may communicate with the display 124 using an Advanced Graphics Port (AGP). Figure 1C An embodiment of a computer or computing device 100 is depicted in which a main processor or central processing unit 121 can communicate directly with an I / O device 130b, such as via HYPERTRANSPORT, RAPIDIO, or INFINIBAND communication techniques. Figure 1C Also depicted is an embodiment in which local buses are mixed with direct communications: central processing unit 121 communicates with I / O device 130a using a local interconnect bus while communicating directly with I / O device 130b.

[0039] There may be a variety of I / O devices 130a to 130n in the computing device 100. Input devices include keyboards, mice, track pads, track balls, microphones, dials, touch pads, touch screens, and drawing tablets. Output devices include video displays, speakers, inkjet printers, laser printers, projectors, and pigment sublimation printers. Figure 1B , I / O devices 130a-130n may be controlled by an I / O controller 123. The I / O controller may control one or more I / O devices, such as a keyboard 126 and a pointing device 127 (e.g., a mouse or optical pen). In addition, the I / O devices may also provide storage media and / or installation media or installation devices 116 for the computing device 100. In yet another embodiment, the computing device 100 may provide a USB connection (not shown) to receive a handheld USB storage device, such as the USB flash drive series of devices manufactured by Twintech Industry, Inc. of Los Alamitos, California.

[0040] Reference again Figure 1B , the computing device 100 may support any suitable installation device 116, such as a disk drive, a CD-ROM drive, a CD-R / RW drive, a DVD-ROM drive, a flash memory drive, a tape drive in various formats, a USB device, a hard disk, a network interface, or any other device suitable for installing software and programs. The computing device 100 may further include a storage device, such as one or more hard disk drives or a redundant array of independent disks, for storing an operating system and other related software and for storing application software programs, such as any program or software 120 for implementing (e.g., constructed and / or designed for) the systems and methods described herein. Optionally, any of the installation devices 116 may also be used as a storage device. In addition, the operating system and software may be run from a bootable medium.

[0041] In addition, the computing device 100 may include a network interface 118 that interfaces to a network through various connections, including but not limited to a standard telephone line, a LAN or WAN link (e.g., 802.11, T1, T3, 56kb, X.25, SNA, DECNET), a broadband connection (e.g., ISDN, Frame Relay, ATM, Gigabit Ethernet, Ethernet-over-SONET), a wireless connection, or some combination of any or all of the above. Connections may be established using various communication protocols, such as TCP / IP, IPX, SPX, NetBIOS, Ethernet, ARCNET, SONET, SDH, Fiber Distributed Data Interface (FDDI), RS232, IEEE 802.11, IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, IEEE 802.11n, IEEE802.11ac, IEEE 802.11ad, CDMA, GSM, WiMax, LTE, LTE-A, and direct asynchronous connections. In one embodiment, the computing device 100 communicates with other computing devices 100' via any type and / or form of gateway or tunneling protocol, such as Secure Sockets Layer (SSL) or Transport Layer Security (TLS). The network interface 118 may include a built-in network adapter, a network interface card, a PCMCIA network card, a card bus network adapter, a wireless network adapter, a USB network adapter, a modem, or any other device suitable for interfacing the computing device 100 to any type of network that has communication capabilities and performs the operations described herein.

[0042] In some embodiments, the computing device 100 may include or be connected to one or more display devices 124a to 124n. Thus, any one of the I / O devices 130a to 130n and / or the I / O controller 123 may include any type and / or form of suitable hardware, software, or a combination of hardware and software to support, enable, or provide the computing device 100 with connection and use of the display devices 124a to 124n. For example, the computing device 100 may include any type and / or form of video adapters, video cards, drivers, and / or libraries for interfacing, communicating, connecting, or otherwise using the display devices 124a to 124n. In one embodiment, the video adapter may include multiple connectors for interfacing to the display devices 124a to 124n. In other embodiments, the computing device 100 may include multiple video adapters, each of which is connected to the display devices 124a to 124n. In some embodiments, any part of the operating system of the computing device 100 may be implemented for using multiple display devices 124a to 124n. Those skilled in the art will recognize and appreciate the various ways and embodiments in which the computing device 100 may be implemented to have one or more display devices 124a - 124n .

[0043] In another embodiment, the I / O devices 130a to 130n can be a bridge between the system bus 150 and an external communication bus, for example, the external communication bus is a USB bus, an Apple Desktop Bus, an RS-232 serial connection, a SCSI bus, a FireWire bus, a FireWire 800 bus, an Ethernet bus, an AppleTalk bus, a Gigabit Ethernet bus, an Asynchronous Transfer Mode bus, a Fibre Channel bus, a Serial Attached Small Computer System Interface bus, a USB connection, or an HDMI bus.

[0044] Figure 1B and 1CA computing device 100 of the type depicted in the figure may operate under the control of an operating system that controls the scheduling of tasks and access to system resources. The computing device 100 may run any operating system, such as any of the following: versions of the Microsoft WINDOWS operating system, different versions of the Unix and Linux operating systems, any version of the MAC OS for Macintosh computers, any embedded operating system, any real-time operating system, any open source operating system, any proprietary operating system, any operating system for mobile computing devices, or any other operating system capable of running on a computing device and performing the operations described herein. Typical operating systems include, but are not limited to, Android produced by Google, WINDOWS 7, 8 produced by Microsoft Corporation of Redmond, Washington, MACOS produced by Apple Computer, Inc. of Cupertino, California, WebOS produced by Research in Motion (RIM), OS / 2 produced by International Business Machines Corporation (IBM) of Armonk, New York, and a freely available Linux operating system or any type and / or form of Unix operating system released by Caldera Corporation of Salt Lake City, Utah, etc.

[0045] The computer system or computing device 100 may be any workstation, phone, sensor, desktop computer, laptop or notebook computer, server, handheld computer, mobile phone or other portable telecommunication device, media playback device, gaming system, mobile computing device, or any other type and / or form of computing device, telecommunication device, or media device with communication capabilities. The computing device 100 has sufficient processor power and memory capacity to perform the operations described herein.

[0046] In some embodiments, computing device 100 may have a different processor, operating system, and input device consistent with the device. For example, in one embodiment, computing device 100 is a smart phone, mobile device, tablet computer, or personal digital assistant. In another embodiment, computing device 100 is an Android-based mobile device, an iPhone smart phone manufactured by Apple Computer, Inc. of Cupertino, California, or a Blackberry or WebOS-based handheld device or smart phone, such as those manufactured by Dynamic Research, Inc. In addition, computing device 100 can be any workstation, desktop computer, laptop or notebook computer, server, handheld computer, mobile phone, any other computer or other form of computing device or telecommunication device with communication capabilities and sufficient processor power and memory capacity to perform the operations described herein.

[0047] Aspects of the operating environment and components described above will be apparent in the context of the systems and methods disclosed herein.

[0048] B. Systems and methods for reducing skew in a communication environment, storage environment, or computing environment

[0049] Systems and methods for phase interpolation and / or multi-phase clock signal generation are described herein. In some embodiments, a phase interpolator is configured to correct for skew (e.g., static skew and dynamic skew). The dynamic skew may be a code-dependent skew. In some embodiments, a phase interpolator may be used in any product that uses a high-precision clock signal, including but not limited to data centers, network switches, coherent optical transceivers, and 5G / microwave broadband data acquisition devices. In some embodiments, a phase interpolator may refer to any circuit for adjusting the phase of a signal. In some embodiments, a phase interpolator may be provided in a receiver for adjusting the phase of a sampling clock in very fine increments and may be used to provide a multi-phase clock signal. In some embodiments, the phase interpolator may be a current-controlled phase interpolator, a voltage-controlled interpolator, an injection-locked oscillator-based interpolator, a delay-locked loop (e.g., delay gate)-based phase interpolator, and the like. In some embodiments, the phase of a signal may be adjusted according to an analog command or a digital command or signal. In some embodiments, systems and methods for phase interpolation are used for clock and data recovery (CDR), loop timing mode, and spread spectrum clock (SSC).

[0050] In some embodiments, systems and methods for phase interpolation provide higher linearity and deeper phase interpolation resolution than conventional phase interpolators. In some embodiments, the phase interpolator provides dynamic deskew for advanced modulators (e.g., Phase Amplitude Modulation (PAM) 4 and Quadrature Amplitude Modulation (QAM) 16 / 64). In some embodiments, the phase interpolator is configured to compensate for phase interpolator integral nonlinearity (INL) and code-dependent skew, and is configured to operate on links with data rates between 56 Gigabits per second (Gb / s) and 200 Gb / s. In some embodiments, the phase interpolator operates on links with data rates higher than 200 Gb / s.

[0051] In some embodiments, the systems and methods for phase interpolation are less susceptible to jitter mismatch due to delayed components in the tunable buffer and skew from the injection locked oscillator at asymmetric phase injection. In some embodiments, the systems and methods for phase interpolation do not require inductive filtering techniques to improve jitter performance. In some embodiments, the skew or jitter tolerance of other components can be increased because of the SERDES architecture related jitter reduction. In some embodiments, a system on a chip can use the systems and methods and accommodate its circuitry.

[0052] In some embodiments, skew may refer to the magnitude of the time difference between two events that would ideally occur at the same time. Skew may include various types of jitter. In some embodiments, jitter may refer to the difference between an actual clock period and an ideal, expected, or average clock period. Jitter may involve deviations or displacements of signal pulses in a high-frequency digital signal (e.g., a clock signal). In some embodiments, jitter corresponds to time domain instability. Jitter may have at least two characteristics: (1) a varying frequency component; and (2) an amplitude (e.g., the amplitude of a varying time component). In some embodiments, when analyzing jitter in serial data or a clock, the signal is compared to a clean clock signal or a noise-free clock signal or other signal as a reference point. In some embodiments, to measure jitter in serial data, an average ideal clock signal associated with the serial data is measured.

[0053] In some embodiments, deterministic jitter may refer to bounded jitter (e.g., having a minimum and maximum range). Deterministic jitter is generally different from random jitter, which is Gaussian in nature and unbounded. In some embodiments, deterministic jitter may include data-dependent jitter (DDj), periodic jitter (Pj), jitter caused by INL, jitter caused by differential nonlinearity (DNL), jitter caused by power supply ripple, and combinations thereof.

[0054] refer to Figure 2 In some embodiments, the clock signal system 200 is configured to perform phase interpolation with improved INL and skew performance. In some embodiments, the system 200 can be part of a SERDES. In some embodiments, the system 200 includes a buffer 202, an in-phase (I) interpolator 204, a quadrature (Q) phase interpolator 206, an injection locked oscillator 208, and a buffer 210. A clock input 222 is coupled to the input of the buffer 202, and a clock output 224 is coupled to the output of the buffer 210. Advantageously, in some embodiments, the clock signal system 200 has excellent I / Q phase interpolation linearity, well-defined skew between interleaved clock paths, and robustness to process, voltage, and temperature variations. In some embodiments, the clock signal system 200 is a system based on an injection locked oscillator of second-order superharmonic symmetry. In some embodiments, the clock signal system 200 is a multi-phase interleaved system.

[0055] In some embodiments, the clock input 222 receives a multi-phase clock signal. In some embodiments, the multi-phase clock signal includes an in-phase signal, an inverted in-phase signal, a quadrature signal, and an inverted quadrature signal. Each of the in-phase signal, the inverted in-phase signal, the quadrature signal, and the inverted quadrature signal is provided on its own wire (e.g., a 4-wire clock bus). The clock signal system 200 is configured to increase the number of phase signals provided at the clock output 224 to a number higher than the number of phase signals provided at the clock input 222 (e.g., twice or four times the number). In some embodiments, the clock output 224 provides an in-phase signal, an inverted in-phase signal, a quadrature signal, an inverted quadrature signal, a 45-degree phase signal, an inverted 45-degree signal, a 135-degree phase signal, and an inverted 135-degree phase signal. Depending on the design criteria and system parameters, the number of phase signals provided at the clock input 222 and the clock output 224 may vary and may be any number (e.g., 2, 4, 6, 8, 12, 16, 32 ...).

[0056] In some embodiments, a phase signal may refer to a signal having a specific phase angle difference (e.g., 0 to 360 degrees) with another signal or reference. In some embodiments, the phase signals have substantially the same frequency. A phase difference may refer to the difference in phase angles of two waves or signals (e.g., two phase signals). In some embodiments, a phase angle may refer to an angle representing a phase difference associated with two signals or references (e.g., 0 degrees). In some embodiments, an in-phase signal may refer to any signal provided at a frequency, and a quadrature signal may refer to any signal provided at the frequency with a phase delay (e.g., 90 degrees) relative to the in-phase signal. In some embodiments, an anti-signal may refer to a signal that is 180 degrees out of phase with respect to another signal. In some embodiments, a 45-degree phase signal may refer to a signal that is 45 degrees out of phase with respect to the in-phase signal. In some embodiments, a 135-degree phase signal may refer to a signal that is 135 degrees out of phase with respect to the in-phase signal.

[0057] Buffer 202 provides a buffered version of each of the in-phase signal, the anti-in-phase signal, the quadrature signal, and the anti-quadrature signal. The buffered in-phase signal, the buffered anti-in-phase signal, the buffered quadrature signal, and the buffered anti-quadrature signal are provided to an in-phase phase interpolator 204, and the buffered in-phase signal, the buffered anti-in-phase signal, the buffered quadrature signal, and the buffered anti-quadrature signal are provided to a quadrature phase interpolator 206.

[0058] In some embodiments, buffer 202 is a signal buffer circuit and includes a control input 226. In some embodiments, buffer 202 is a clock signal buffer circuit. In some embodiments, a clock signal buffer circuit may refer to any circuit that can buffer, copy, reproduce, or generate a derivative signal for one or more of the signals at an input. In some embodiments, buffering may refer to the act of providing isolation, delay, or temporary storage in a circuit. Buffering may involve copying, delaying, reproducing, generating derivative signals, and the like. In some embodiments, the clock signal buffer circuit may include a jitter attenuator or a jitter cleaner. Control input 226 may receive a skew control signal for clock and data recovery. A skew control signal may be provided at input 222 to correct static skew. The skew control signal may represent a correction for a difference in phase between a delta IQ1 or an in-phase signal and a quadrature signal that exceeds a desired phase difference. The skew control signal may be provided by a digital calibration circuit.

[0059] In some embodiments, the skew control signal is a command that causes buffer 202 to selectively delay one signal (e.g., an in-phase signal, an anti-in-phase signal, a quadrature signal, and an anti-quadrature signal) relative to another signal to remove skew or other errors in some embodiments. Selectable delay paths can be used to selectively delay signals in response to the command. In some embodiments, clock buffer 202 is configured to remove static skew or residual skew at clock input 222. In some embodiments, residual skew or static skew can be detected by even / odd path cross correlation and compensated for using the skew control signal in some embodiments.

[0060] The in-phase phase interpolator 204 receives a buffered in-phase signal and a buffered anti-in-phase signal from the clock buffer 202, and receives a buffered quadrature signal and a buffered anti-quadrature signal from the buffer 202. The in-phase phase interpolator 204 is configured to provide a wide operating frequency for phase interpolation of the in-phase signal and the buffered anti-in-phase signal. In some embodiments, the phase interpolation is a phase rotation. In some embodiments, the in-phase phase interpolator 204 can be a circuit system configured to generate a desired phase shift / phase interpolation from a control signal / word. In some embodiments, the in-phase phase interpolator 204 can each represent a single phase interpolator or multiple phase interpolators and can be implemented as a mixer configured to generate a phase-shifted clock signal. The in-phase phase interpolator 204 provides a phase-interpolated in-phase phase signal and an anti-phase interpolated in-phase phase signal to the injection locked oscillator 208.

[0061] The quadrature phase interpolator 206 receives a buffered in-phase signal and a buffered anti-in-phase signal from the clock buffer 202, and receives a buffered quadrature signal and a buffered anti-quadrature signal from the buffer 202. The quadrature phase interpolator 206 is configured to provide a wide operating frequency for phase interpolation of the quadrature signal and the buffered anti-quadrature signal. In some embodiments, the quadrature phase interpolator 206 may be a circuit system configured to generate a desired phase shift / phase interpolation from a control signal / word. In some embodiments, the quadrature phase interpolator 206 and the in-phase phase interpolator 204 may each represent a single phase interpolator or multiple phase interpolators, and may be implemented as a mixer configured to generate a phase-shifted clock signal. The quadrature phase interpolator 206 provides a phase-interpolated quadrature phase signal and an anti-phase interpolated quadrature phase signal to the injection locked oscillator 208.

[0062] The injection locked oscillator 208 receives the phase interpolated in-phase signal and the anti-phase interpolated in-phase signal from the in-phase interpolator 204, and receives the phase interpolated quadrature-phase signal and the anti-phase interpolated quadrature-phase signal from the quadrature-phase interpolator 206. The phase interpolated in-phase signal, the anti-phase interpolated in-phase signal, the phase interpolated quadrature-phase signal, and the anti-phase interpolated quadrature-phase signal are symmetrically injected signals, which the injection locked oscillator 208 uses to generate eight phase signals. The number of phase signals may be related to the number of injected signals (e.g., multiples thereof - 2, 4, etc.). In some embodiments, the frequency of the eight phase signals is half the frequency of the symmetrically injected signals. In some embodiments, the injection locked oscillator 208 is configured to compensate for both static skew and dynamic skew between the phase signals. In some embodiments, the injection locked oscillator 208 is configured to provide an in-phase phase signal, an inverted in-phase phase signal, a quadrature phase signal, and an inverted quadrature phase signal, as well as additional phase signals (e.g., a 45 degree phase signal, an inverted 45 degree phase signal, a 135 degree phase signal, and an inverted 135 degree phase signal). The phase signals may have a phase delay between 0 and 360 degrees at any increment. In some embodiments, the injection locked oscillator 208 may filter out input jitter. The injection locked oscillator 208 provides eight phase signals to the buffer 210.

[0063] Buffer 210 is similar to buffer 202 and is configured to provide eight phase signals to clock output 224. In some embodiments, buffer 210 is a signal buffer circuit and includes a control input 220. In some embodiments, buffer 210 is a clock signal buffer circuit. Control input 220 may receive a skew control signal for clock and data recovery. A skew control signal may be provided at output 224 to correct static skew. The skew control signal may represent a correction of the difference between the difference IQ2 or the in-phase signal and the quadrature signal exceeding the desired phase difference. The skew control signal may be provided by a digital calibration circuit. In an analog / digital converter architecture, the cross-correlation between the I path and the Q path may be used to detect static I / Q skew at the input and output of the phase interpolator. The skew control signal for buffer 202 may further reduce dynamic skew, while the skew control signal for buffer 210 may correct any remaining static skew in the last stage of the clock path. In an embodiment, the skew control signal may represent a correction of a difference between a phase of at least one of the delta IQ2 or the phase signal and a desired phase, or a difference between a phase difference between at least two of the phase signals and a desired difference. In some embodiments, the skew control signal may refer to a signal (e.g., a command) for adjusting a phase relationship to reduce skew. The skew control signal may be a digital signal or an analog signal.

[0064] In some embodiments, the skew control signal is a command that causes buffer 210 to selectively delay one signal relative to another signal (e.g., provide an in-phase phase signal and an inverted in-phase phase signal, a quadrature phase signal, a 45 degree phase signal, an inverted 45 degree phase signal, a 135 degree phase signal, and an inverted 135 degree phase signal) to remove skew or other errors. In some embodiments, buffer 210 is configured to remove static skew or residual skew at clock output 224. In some embodiments, residual skew or static skew between all paths can be detected by even / odd path cross correlation and compensated for using the skew control signal in some embodiments.

[0065] refer to Figure 3 The phase-interpolated in-phase signal, the phase-interpolated quadrature-phase signal, the anti-phase-interpolated in-phase signal, and the anti-phase-interpolated quadrature-phase signal may be used to control the injection-locked oscillator 208 ( Figure 2). The injection locked oscillator 300 includes a number of amplifiers, such as differential amplifiers or operational amplifiers 302, 304, 306, and 308. The number of operational amplifiers 302, 304, 306, and 308 may be equal to the number of output phase signals divided by 2 or the number of input phase signals at the clock input 222. The injection locked oscillator 300 includes a number of switches, such as switches 310, 312, 314, and 316. The number of switches 310, 312, 314, and 316 may be equal to the number of output phase signals divided by 2 or the number of input phase signals at the clock input 222.

[0066] In some embodiments, operational amplifiers 302, 304, 306, and 308 are coupled in a loop. In some embodiments, the non-inverting input of amplifier 302 is coupled to the non-inverting output of amplifier 308, and the inverting input of amplifier 302 is coupled to the inverting output of amplifier 308. In some embodiments, the non-inverting input of amplifier 304 is coupled to the inverting output of amplifier 302, and the inverting input of amplifier 304 is coupled to the non-inverting output of amplifier 302. In some embodiments, the non-inverting input of amplifier 306 is coupled to the inverting output of amplifier 304, and the inverting input of amplifier 306 is coupled to the non-inverting output of amplifier 304. In some embodiments, the non-inverting input of amplifier 308 is coupled to the inverting output of amplifier 306, and the inverting input of amplifier 308 is coupled to the non-inverting output of amplifier 306.

[0067] In some embodiments, switch 310 is disposed between the non-inverting input of amplifier 304 and the inverting input of amplifier 304, with the drain coupled to node 320 and the source coupled to node 322. In some embodiments, switch 312 is disposed between the non-inverting input of amplifier 306 and the inverting input of amplifier 306, with the drain coupled to node 324 and the source coupled to node 326. In some embodiments, switch 314 is disposed between the non-inverting input of amplifier 308 and the inverting input of amplifier 308, with the drain coupled to node 328 and the source coupled to node 330. In some embodiments, switch 316 is disposed between the non-inverting input of amplifier 302 and the inverting input of amplifier 302, with the drain coupled to node 332 and the source coupled to node 334.

[0068] In some embodiments, switches 310, 312, 314, and 316 are transistors (e.g., metal oxide field effect transistors (MOSFETS). Switches 310, 312, 314, and 316 each include a gate coupled to receive one of the phase-interpolated in-phase signal, the phase-interpolated quadrature-phase signal, the anti-phase-interpolated in-phase signal, and the anti-phase-interpolated quadrature-phase signal, respectively. In some embodiments, the phase-interpolated in-phase signal, the phase-interpolated quadrature-phase signal, the anti-phase-interpolated in-phase signal, and the anti-phase-interpolated quadrature-phase signal are provided by phase interpolators 204 and 206 ( Figure 2 ) are provided and the corresponding switches 310, 312, 314 and 316 are opened and closed. In some embodiments, the phase-interpolated in-phase signal, the phase-interpolated quadrature-phase signal, the anti-phase-interpolated in-phase signal and the anti-phase-interpolated quadrature-phase signal are symmetrically injected into the injection-locked oscillator. Due to the nature of phase tracking in the symmetrical injection-locked oscillator, compensation can be provided for any non-ideal skew between the four injected phase signals (e.g., the phase-interpolated in-phase signal, the phase-interpolated quadrature-phase signal, the anti-phase-interpolated in-phase signal and the anti-phase-interpolated quadrature-phase signal).

[0069] An injection locked oscillator may refer to a circuit that generates one or more periodic or oscillating signals. In some embodiments, the signal may be a sine wave, a square wave, a clock signal, a sawtooth signal, and the like. The circuit may use injection locking to synchronize one signal with another signal. An amplifier may refer to a circuit that receives an input signal and provides an output signal according to a gain. The gain may be any number, including numbers greater than, less than, and equal to 1. In some embodiments, an operational amplifier may refer to an amplifier having a gain and an input impedance. In some embodiments, the gain and input impedance may be relatively high. In some embodiments, an operational amplifier may have inverting and non-inverting inputs and outputs for performing operations on input voltages. In some embodiments, generally speaking, the operational amplifier operates according to a current rule in which no current flows into the inverting input and the non-inverting input and a voltage rule in which the output of the operational amplifier attempts to ensure that the voltage difference between the inverting input and the non-inverting input is zero. In some embodiments, an inverting input may refer to a circuit input in which a signal change at the non-inverting output is 180 degrees out of phase with a change at the inverting input. In some embodiments, a non-inverting input may refer to a circuit input in which a signal change at the non-inverting input is 180 degrees out of phase with a change at the inverting output. In some embodiments, a non-inverting output may refer to a circuit output where the signal change at the inverting input is 180 degrees out of phase with the change at the non-inverting output. In some embodiments, an inverting output may refer to a circuit output where the signal change at the non-inverting input is 180 degrees out of phase with the change at the inverting output. In some embodiments, non-inverting inputs and outputs are labeled with a positive sign, and inverting inputs and outputs are labeled with a negative sign.

[0070] In some embodiments, a switch may refer to any type of switching device, including but not limited to a transistor. A transistor may refer to any type of transistor, including field effect transistors FETS, insulated gate FETs, bipolar junction transistors, and the like. In some embodiments, the transistor is a P-channel or N-channel metal oxide semiconductor field effect transistor (MOSFET). A P-channel transistor includes a P-channel, which is a channel composed of mostly hole carriers between the source and drain of the transistor. An N-channel transistor includes an N-channel, which is a channel composed of mostly electron carriers between the source and drain of the transistor. In some embodiments, the terms drain and source are used interchangeably and may refer to regions of a transistor. In some embodiments, a gate may refer to a transistor structure for controlling the opening (e.g., toward a non-conductive state) and closing (e.g., toward a conductive state) of a transistor.

[0071] The injection locked oscillator 300 is configured to provide a clock output 224 ( Figure 2) provides eight phase signals, one phase signal at each of nodes 320, 322, 324, 326, 328, 330, 332 and 334. In some embodiments, the phase signal at node 320 corresponds to an in-phase phase signal, the phase signal at node 322 corresponds to a phase-delayed signal by 180 degrees relative to the phase signal at node 320, the phase signal at node 324 corresponds to a phase-delayed signal by 225 degrees relative to the phase signal at node 320, the phase signal at node 328 corresponds to a phase-delayed signal (e.g., a quadrature signal) by 90 degrees relative to the phase signal at node 320, the phase signal at node 330 corresponds to a phase-delayed signal by 270 degrees relative to the phase signal at node 320, the phase signal at node 332 corresponds to a phase-delayed signal by 315 degrees relative to the phase signal at node 320, the phase signal at node 334 corresponds to a phase-delayed signal by 135 degrees relative to the phase signal at node 320, and the phase signal at node 326 corresponds to a phase-delayed signal by 45 degrees relative to the phase signal at node 320. In some embodiments, the eight phase signals are generated using a superharmonic injection architecture.

[0072] In some embodiments, a transmitter may refer to any circuit for transmitting data across a medium (e.g., a cable). A transmitter may include circuitry for encoding, modulating, processing, and providing data in a serial manner. In some embodiments, a transmitter provides data using a transmission clock signal. In some embodiments, a receiver may refer to any circuit for receiving data from a medium (e.g., a cable). A receiver may include circuitry for decoding, demodulating, processing, and receiving data from a medium.

[0073] In some embodiments, a clock signal may refer to an oscillating signal (e.g., a square wave signal or other form of signal) that oscillates between at least two states (e.g., a high state and a low state) and is used for transmission of data. Using the clock signal system 200 provides improved receiver jitter tolerance, improved transmitter output jitter, and improved effective number of bits for a communication system. The clock signal may be a square wave signal, a sinusoidal signal, a trapezoidal signal, and the like. In some embodiments, a state may refer to any physical or virtual quantity or representation that varies with time or space or any other independent variable(s). In some embodiments, a state may be a specific code or a combination of codes.

[0074] In some embodiments, the clock signal system 200 is implemented as a field programmable gate array, an application specific integrated circuit, hardware, a software execution processor, a state machine, and a combination thereof. In some embodiments, a processing circuit as part of a SERDES provides operations as described herein. In some embodiments, the processing circuit may be configured to perform filtering, triggering, and jitter reduction operations. In some embodiments, instructions for the processing circuit may be stored in a non-temporary medium (e.g., a memory). The memory may be one or more devices (e.g., RAM, ROM, flash memory, hard disk storage) for storing data and / or computer code, which are used to complete and / or facilitate the various processes described herein. The memory may be or include non-temporary volatile memory, non-volatile memory, and non-temporary computer storage media. The memory may include a database component, an object code component, a script component, or any other type of information structure for supporting various activities and the information structure described in the present invention. The memory may be communicatively coupled to the processor circuit. The clock signal system 200 may be implemented in many different ways and in many different combinations of hardware and software and circuit design. For example, all or part of an embodiment may be a circuit system including an instruction processor (e.g., a central processing unit (CPU)), a microcontroller, or a microprocessor; an application specific integrated circuit (ASIC), a programmable logic device (PLD), or a field programmable gate array (FPGA); or a circuit system including discrete logic or other circuit components (including analog circuit components, digital circuit components, or both); or any combination thereof.

[0075] As examples, the circuitry may include discrete interconnected hardware components and / or may be combined on a single integrated circuit die, distributed among multiple integrated circuit dies, or implemented in a multiple chip module (MCM) of multiple integrated circuit dies in a common package. In some embodiments, an integrated circuit package may be a combination of two or more packages.

[0076] refer to Figure 4 , waveform 400 is related to the INL performance of a 9-bit resolution phase interpolator at 28 gigahertz (GHz). Y-axis 402 represents the least significant bit (LSB) of INL, and X-axis 404 represents the phase interpolator code. Curve 406 represents the injection locked oscillator 300 ( Figure 3), and curve 408 represents the performance before injection locked oscillator 300. In some embodiments, curves 406 and 408 show that the INL distribution of the phase interpolator INL is improved when injection locked oscillator 300 is used. In some embodiments, injection locked oscillator 300 suppresses the PI INL from 6.6LSB at 9-bit resolution to 2.5LSB. An LSB is equal to 1 / 28GHz / 512, where number 512 is the PI step size or resolution.

[0077] refer to Figure 5 , waveform 500 is related to the dynamic skew performance of a 9-bit resolution phase interpolator at 28 GHz. Y-axis 502 represents the least significant bit (LSB) of the dynamic I / Q skew, and X-axis 504 represents the phase interpolator code. Curve 508 represents the injection locked oscillator 300 ( Figure 3 ), and curve 506 represents the performance after injection locking the oscillator 300. In some embodiments, curves 506 and 508 show that the dynamic I / Q distribution at the clock output 224 is improved when the injection locked oscillator 300 is used. In some embodiments, the maximum dynamic I / Q skew is reduced by more than eight times (5.9 LSB to 0.7 LSB) using the injection locked oscillator 300. In some embodiments, the symmetrical injection provides excellent skew cancellation across all temperature, power supply and process corners, and advantageously, device mismatch does not affect the dynamic cancellation performance. LSB is equal to 1 / 28 GHz / 512, where the number 512 is the PI step size or resolution.

[0078] It should be noted that certain paragraphs of the present disclosure may refer to terms such as "first" and "second" in conjunction with devices, frequencies, etc., for the purpose of identifying or distinguishing one from another or others. These terms are not intended to relate entities (e.g., a first device and a second device) only in time or according to sequence, although in some cases, these entities may include such a relationship. These terms also do not limit the number of possible entities (e.g., devices) that can operate in a system or environment. In some embodiments, communicative coupling can refer to a situation in which two or more devices communicate directly or indirectly with each other through a wireless or wired medium.

[0079] It should be understood that the systems described above may provide multiple of any or each of those components, and that these components may be provided in a standalone machine, or in some embodiments, in multiple machines in a distributed system. In addition, the systems and methods described above may be provided as one or more computer-readable programs or executable instructions embodied on or in one or more articles of manufacture. The articles of manufacture may be floppy disks, hard disks, CD-ROMs, flash memory cards, PROMs, RAMs, ROMs, or magnetic tapes. In general, the computer-readable programs may be implemented in any programming language (e.g., LISP, PERL, C, C++, C#, PROLOG) or in any bytecode language (e.g., JAVA). The software programs or executable instructions may be stored as object code on or in one or more articles of manufacture.

[0080] Any embodiment disclosed herein may be combined with any other embodiment, and references to "embodiment", "some embodiments", "alternative embodiments", "various embodiments", "one embodiment", etc. are not necessarily mutually exclusive and are intended to indicate that specific features, structures or characteristics described in conjunction with the embodiments may be included in at least one embodiment. Such terms as used herein do not necessarily all refer to the same embodiment. Any embodiment may be combined with any other embodiment, inclusively or exclusively, in any manner consistent with the aspects and embodiments disclosed herein. In the above description, for the purpose of explanation, numerous specific details are stated to provide a thorough understanding of the described embodiments. However, those skilled in the art will appreciate that other embodiments may be practiced without some of these details. In other examples, structures and devices are shown in block diagram form. Several embodiments are described herein, and although various features are attributed to different embodiments, it should be understood that the features described with respect to one embodiment may also be combined with other embodiments. However, for the same reason, a single feature or several features of any described embodiment should not be considered necessary for each embodiment of the present invention, as other embodiments of the present invention may omit these features. Similarly, when an element is referred to herein as "connected" or "coupled" to another element, it will be understood that the element may be directly connected to another element, or there may be an intermediate element between the elements. On the contrary, when an element is referred to as "directly connected" or "directly coupled" to another element, it will be understood that there is no intermediate element in the "direct" connection between the elements. However, the presence of a direct connection does not exclude other connections in which there may be intermediate elements. A circuit or circuit system may refer to any active or passive component and its connection and combination thereof. The circuit system may further include or access instructions (e.g., software or firmware instructions) for execution by the circuit system. As an example, the circuit system may include discrete interconnected hardware components and / or may be combined on a single integrated circuit die, distributed between multiple integrated circuit dies, or implemented in multiple chip modules (MCMs) of multiple integrated circuit dies in a common package. In some embodiments, an integrated circuit package may be a combination of two or more packages.

[0081] Although the foregoing written description of the methods and systems enables those skilled in the art to make and use various embodiments of these methods and systems, those skilled in the art will understand and appreciate the variations, combinations, and equivalents of the specific embodiments, methods, and examples presented herein. Therefore, the present methods and systems are not limited to the embodiments, methods, and examples described above, but to all embodiments and methods within the scope and spirit of the present disclosure.

Claims

1. A system comprising: a first phase interpolator; a second phase interpolator; and A first circuit is configured to receive a first signal and a second signal provided by the first phase interpolator and a third signal and a fourth signal provided by the second phase interpolator, wherein the first circuit is configured to provide at least eight phase signals, each of the eight phase signals being at a corresponding phase angle in response to the first signal, the second signal, the third signal, and the fourth signal. 2 . The system of claim 1 , wherein the first circuit is configured as an injection locked oscillator.

3. The system of claim 1, wherein the first circuit comprises a plurality of amplifiers, wherein each of the amplifiers comprises an inverting output and a non-inverting output, wherein each of the non-inverting output and the inverting output provides one of the phase signals. 4 . The system of claim 3 , wherein the first circuit comprises a plurality of switches, wherein each switch is disposed between the non-inverting output and the inverting output of a respective one of the amplifiers.

5. The system of claim 4, wherein the amplifiers each include an inverting input and a non-inverting input, wherein an inverting output of a first of the amplifiers is coupled to a non-inverting input of a second of the amplifiers, and the non-inverting output of the first amplifier is coupled to an inverting input of the second amplifier.

6. The system of claim 5, wherein an inverting output of the second amplifier is coupled to an inverting input of a third amplifier of the amplifiers, and a non-inverting output of the second amplifier is coupled to a non-inverting input of the third amplifier.

7. The system of claim 3, wherein the amplifier is an operational amplifier.

8. The system of claim 4, wherein the switches each include a gate configured to receive one of the first signal, the second signal, the third signal, or the fourth signal.

9. The system of claim 8, wherein the first signal is an in-phase signal and the third signal is a quadrature signal.

10. The system of claim 1, further comprising a second circuit configured to buffer a plurality of input signals related to the first signal, the second signal, the third signal, and the fourth signal, wherein the second circuit receives a first skew control signal. 11 . The system of claim 10 , further comprising a third circuit configured to buffer the eight phase signals, wherein the third circuit receives a second skew control signal.

12. An apparatus comprising: a first circuit configured to provide a first phase signal at a first inverting output and a second phase signal at a first non-inverting output, the first phase signal having a phase difference of 180 degrees relative to the second phase signal; a second circuit configured to receive the first phase signal at a second non-inverting input and the second phase signal at a second inverting input and to provide a third phase signal at a second inverting output and a fourth phase signal at a second non-inverting output, the fourth phase signal having a phase difference of 180 degrees relative to the third phase signal; and A first switch is configured to connect the first inverting output to the first non-inverting output in response to a first clock signal.

13. The apparatus of claim 12, wherein the first clock signal is provided by a first phase interpolator.

14. The apparatus according to claim 12, further comprising: a third circuit configured to receive the third phase signal at a third inverting input and the fourth phase signal at a third non-inverting input and to provide a fifth phase signal at a third inverting output and a sixth phase signal at a third non-inverting output, the fifth phase signal having a phase difference of 180 degrees relative to the sixth phase signal; and A second switch is configured to connect the second inverting output to the second non-inverting output in response to a second clock signal having a 90 degree phase difference with respect to the first clock signal.

15. The apparatus according to claim 14, further comprising: a fourth circuit configured to receive the fifth phase signal at a fourth non-inverting input and the sixth phase signal at a fourth inverting input and to provide a seventh phase signal at a fourth inverting output and an eighth phase signal at a fourth non-inverting output, the seventh phase signal having a phase difference of 180 degrees relative to the eighth phase signal; and A third switch is configured to connect the third inverting output to the third non-inverting output in response to a third clock signal, the third clock signal having a phase difference of 180 degrees relative to the first clock signal.

16. The apparatus of claim 15, further comprising a fourth switch, wherein the fourth non-inverting output is coupled to a first non-inverting input of the first circuit and the fourth inverting output is coupled to a first inverting input of the first circuit; and Wherein the fourth switch is configured to connect the fourth inverting output to the fourth non-inverting output in response to a fourth clock signal, the fourth clock signal having a phase difference of 270 degrees relative to the first clock signal.

17. A method comprising: receiving a first clock signal and a second clock signal provided by a first phase interpolator; receiving a third clock signal and a fourth clock signal provided by a second phase interpolator, wherein the first clock signal, the second clock signal, the third clock signal and the fourth clock signal are each at a corresponding phase angle; using an oscillator to provide a plurality of phase signals, each of the phase signals being at a respective phase angle, wherein the number of the phase signals is greater than four; and The phase signal is provided to a first buffer and a first skew control signal is used to correct a skew associated with the phase signal in the first buffer.

18. The method according to claim 17, further comprising: The first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are used to control switches in the oscillator. The method of claim 18 , wherein the oscillator is an injection locked oscillator.

20. The method of claim 17, further comprising: providing the clock signal to a second buffer; using a second skew control signal to correct a skew associated with the clock signal in the second buffer; and The clock signal is provided from the second buffer to the first phase interpolator and the clock signal is provided from the second buffer to the second phase interpolator.

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