Speed regulation switch starting circuit
By designing a speed control switch start circuit, using components such as decoder and operational amplifier to detect and isolate the speed control signal, the problem of direct high-speed start of the device when it is shut down or not reset to zero is solved, and the safe, controllable and automated adjustment of the device is achieved. .
Patent Information
- Application Number
- CN202411131424.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-18
- Publication Date
- 2024-12-10
- Estimated Expiration
- Not applicable · inactive patent
AI Technical Summary
The prior art cannot detect the equipment status when the equipment is started at a speed regulation, resulting in the equipment directly entering high-speed startup when it is shut down or not returning to zero. The operator cannot control it, which may cause an accident.
A speed regulator switch start circuit is designed, through the second potentiometer R2, the eighth resistor R8, the eleventh resistor R11, the eighth resistor R18, the twentieth resistor R20, the twentieth resistor R21, and the third translation The coder U3, the fifth operational amplifier U5, the sixth operational amplifier U6, the seventh digital potentiometer U7, the second MOS tube Q2, the fourth transistor Q4, the sixth MOS tube Q6 and other components realize the speed regulation signal Detection and isolation control to prevent the equipment from entering the high-speed startup state directly, and to perform automatic shutdown and automatic start inspection when the speed adjustment is completed.
It effectively avoids the high-speed start problem of the equipment when speed regulation is started, ensures that the operator is controllable, and realizes automatic shutdown and automatic start of the second adjustment after speed regulation, improving the safety and reliability of the equipment.
Smart Images
Figure CN119109450A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the technical field of switch control, and in particular to a speed regulating switch starting circuit. Background Art
[0002] Publication No.: CN209526703U discloses a switch circuit and a multi-wire switch, which can monitor the logic signal of the switch unit through the switch circuit in conjunction with the controller, ensuring the uniqueness of the start and stop conditions of the equipment and avoiding the problem of equipment misstarting due to a short circuit of the switch. However, the defect is that the state of the equipment cannot be detected when the equipment is started by the speed control signal. When the speed is adjusted when the equipment is in the shutdown state or the speed control knob is not returned to zero before the equipment is turned off, the equipment will directly enter the high-speed start state after starting, resulting in the operator being unable to control and causing accidents. Summary of the invention
[0003] In view of the above technical problems, the purpose of the present invention is to provide a speed control switch starting circuit, including a second potentiometer R2, an eighth resistor R8, an eleventh resistor R11, an eighteenth resistor R18, a twentieth resistor R20, a twenty-first resistor R21, a third decoder U3, a fifth operational amplifier U5, a sixth operational amplifier U6, a seventh digital potentiometer U7, a second MOS tube Q2, a fourth transistor Q4, and a sixth MOS tube Q6, wherein one end of the second potentiometer R2 and one end of the eighth resistor R8 are connected to a power supply, the other end of the second potentiometer R2 is connected to the in-phase end of the fifth operational amplifier U5, the output end of the fifth operational amplifier U5, the collector of the fourth transistor Q4, one end of the eleventh resistor R11, one end of the twentieth resistor R20, and one end of the twenty-first resistor R21, the inverting end of the fifth operational amplifier U5 is connected to the source of the second MOS tube Q2, the other end of the eighth resistor R8, the in-phase end of the sixth operational amplifier U6, and the twelfth pin of the seventh digital potentiometer U7, and the The output end of the sixth operational amplifier U6 is connected to the source of the sixth MOS tube Q6, the drain of the sixth MOS tube Q6 is connected to the base of the fourth transistor Q4, the gate of the sixth MOS tube Q6 is connected to the sixth pin of the third decoder U3, the fifth pin of the seventh digital potentiometer U7 is connected to the other end of the eleventh resistor R11, the third pin of the seventh digital potentiometer U7 is connected to one end of the eighteenth resistor R18, the fifth pin of the third decoder U3 is connected to the gate of the second MOS tube Q2, the second pin of the third decoder U3 is connected to the first logic signal V1, the third pin of the third decoder U3 is connected to the second logic signal V2, the drain of the second MOS tube Q2 is connected to the speed regulation signal V3, the seventh pin of the third decoder U3 is connected to the start signal V4, and the emitter of the fourth transistor Q4, the tenth pin of the seventh digital potentiometer U7, the eleventh pin of the seventh digital potentiometer U7, the other end of the eighteenth resistor R18, the other end of the twentieth resistor R20, the other end of the twenty-first resistor R21 and the ground are connected.
[0004] Furthermore, it also includes a fifth resistor R5, a ninth resistor R9, a twelfth resistor R12, a fourteenth resistor R14, a fifteenth resistor R15, a nineteenth resistor R19, a twenty-second resistor R22, a first operational amplifier U1, a second operational amplifier U2, a fourth operational amplifier U4, an eighth NOT gate U8, a ninth AND gate U9, a first transistor Q1, a third thyristor Q3, a fifth thyristor Q5, and a first capacitor C1. The emitter of the first transistor Q1 is connected to the power supply, the base of the first transistor Q1, the output end of the second operational amplifier U2, and one end of the fifth resistor R5 are connected to the interrupt signal V5, the inverting end of the second operational amplifier U2 is connected to the output end of the fourth operational amplifier U4 and one end of the ninth resistor R9, the inverting end of the fourth operational amplifier U4 is connected to the other end of the ninth resistor R9 and one end of the nineteenth resistor R19, the in-phase end of the fourth operational amplifier U4 is connected to one end of the first capacitor C1 and one end of the twelfth resistor R12, and the other end of the first capacitor C1 is connected to the first operational amplifier U 1 output terminal, the inverting terminal of the first operational amplifier U1, and one end of the fifteenth resistor R15 are connected, the non-inverting terminal of the first operational amplifier U1 is connected to the non-inverting terminal of the fifth operational amplifier U5, the collector of the first triode Q1 is connected to the anode of the third thyristor Q3 and the anode of the fifth thyristor Q5, the cathode of the third thyristor Q3 and one end of the fourteenth resistor R14 are connected to the first connecting terminal of the ninth AND gate U9, the cathode of the fifth light emitting diode D5 is connected to the second connecting terminal of the ninth AND gate U9 and one end of the twenty-second resistor R22, the output terminal of the ninth AND gate U9 is connected to the third pin of the seventh digital potentiometer U7, the control electrode of the third thyristor Q3 is connected to the output terminal of the fifth operational amplifier U5 and the input terminal of the eighth NOT gate U8, the control electrode of the fifth thyristor Q5 is connected to the output terminal of the eighth NOT gate U8, the other end of the fifth resistor R5, the other end of the twelfth resistor R12, the other end of the fourteenth resistor R14, the other end of the fifteenth resistor R15, the other end of the nineteenth resistor R19, the other end of the twenty-second resistor R22 and the ground terminal are connected.
[0005] Furthermore, it includes a tenth resistor R10 and a sixteenth resistor R16, one end of the tenth resistor R10 is connected to the second logic signal V2, one end of the sixteenth resistor R16 is connected to the first logic signal V1, and the other ends of the tenth resistor R10 and the sixteenth resistor R16 are connected to the ground.
[0006] Furthermore, it also includes a fourth resistor R4 and a seventeenth resistor R17, wherein one end of the fourth resistor R4 is connected to the power supply, the other end of the fourth resistor R4 is connected to the inverting end of the sixth operational amplifier U6 and one end of the seventeenth resistor R17, and the other end of the seventeenth resistor R17 is connected to the ground.
[0007] Furthermore, it includes a first resistor R1 and a third resistor R3, wherein one end of the first resistor R1 is connected to the power supply, the other end of the first resistor R1 is connected to the in-phase end of the second operational amplifier U2 and one end of the third resistor R3, and the other end of the third resistor R3 is connected to the ground.
[0008] Furthermore, it also includes a sixth resistor R6 and a seventh resistor R7, one end of the sixth resistor R6 is connected to the gate of the second MOS tube Q2, one end of the seventh resistor R7 is connected to the gate of the sixth MOS tube Q6, and the other ends of the sixth resistor R6 and the seventh resistor R7 are connected to the ground.
[0009] Furthermore, it also includes a thirteenth resistor R13, one end of the thirteenth resistor R13 is connected to the first pin of the third decoder U3, and the other end of the thirteenth resistor R13 is connected to the ground.
[0010] Furthermore, it also includes a first switch and a second switch, wherein the first switch is connected to V1 and the second switch is connected to V2, and is used to replace V1 and V2 for manual input.
[0011] Furthermore, the fourth resistor R4 is an adjustable resistor.
[0012] The beneficial effects of the present invention compared with the prior art are: The present invention can detect and isolate the speed regulation signal to avoid directly starting the device at high speed through the speed regulation signal, which makes the operator unable to control the device. It can automatically stop the device for inspection after the speed regulation is completed and automatically start the device for inspection during the secondary regulation. BRIEF DESCRIPTION OF THE DRAWINGS
[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the prior art and the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0014] Figure 1 This is a schematic diagram of the starting circuit structure provided by the present invention.
[0015] Figure 2 This is another schematic diagram of the structure of a starting circuit provided by the present invention. DETAILED DESCRIPTION
[0016] In order to make the objects and advantages of the present invention more clearly understood, the present invention is specifically described below in conjunction with embodiments. It should be understood that the following text is only used to describe one or several specific implementations of the present invention, and does not strictly limit the scope of protection specifically requested by the present invention.
[0017] The invention discloses a speed regulating switch starting circuit, comprising a second potentiometer R2, an eighth resistor R8, an eleventh resistor R11, an eighteenth resistor R18, a twentieth resistor R20, a twenty-first resistor R21, a third decoder U3, a fifth operational amplifier U5, a sixth operational amplifier U6, a seventh digital potentiometer U7, a second MOS tube Q2, a fourth transistor Q4, and a sixth MOS tube Q6, wherein one end of the second potentiometer R2 and one end of the eighth resistor R8 are connected to a power supply, the other end of the second potentiometer R2 is connected to a non-inverting end of the fifth operational amplifier U5, an output end of the fifth operational amplifier U5, a collector of the fourth transistor Q4, one end of the eleventh resistor R11, one end of the twentieth resistor R20, and one end of the twenty-first resistor R21, the inverting end of the fifth operational amplifier U5 is connected to a source of the second MOS tube Q2, the other end of the eighth resistor R8, the non-inverting end of the sixth operational amplifier U6, and the twelfth pin of the seventh digital potentiometer U7, and the sixth operational amplifier Q6 is connected to a power supply. The output end of U6 is connected to the source of the sixth MOS tube Q6, the drain of the sixth MOS tube Q6 is connected to the base of the fourth transistor Q4, the gate of the sixth MOS tube Q6 is connected to the sixth pin of the third decoder U3, the fifth pin of the seventh digital potentiometer U7 is connected to the other end of the eleventh resistor R11, the third pin of the seventh digital potentiometer U7 is connected to one end of the eighteenth resistor R18, the fifth pin of the third decoder U3 is connected to the gate of the second MOS tube Q2, the second pin of the third decoder U3 is connected to the first logic signal V1, the third pin of the third decoder U3 is connected to the second logic signal V2, the drain of the second MOS tube Q2 is connected to the speed regulation signal V3, the seventh pin of the third decoder U3 is connected to the start-up signal V4, the emitter of the fourth transistor Q4, the tenth pin of the seventh digital potentiometer U7, the eleventh pin of the seventh digital potentiometer U7, the other end of the eighteenth resistor R18, the other end of the twentieth resistor R20, the other end of the twenty-first resistor R21 and the ground are connected.
[0018] Specifically, it also includes a fifth resistor R5, a ninth resistor R9, a twelfth resistor R12, a fourteenth resistor R14, a fifteenth resistor R15, a nineteenth resistor R19, a twenty-second resistor R22, a first operational amplifier U1, a second operational amplifier U2, a fourth operational amplifier U4, an eighth NOT gate U8, a ninth AND gate U9, a first transistor Q1, a third thyristor Q3, a fifth thyristor Q5, and a first capacitor C1. The emitter of the first transistor Q1 is connected to a power supply, the base of the first transistor Q1, the output end of the second operational amplifier U2, and one end of the fifth resistor R5 are connected to an interrupt signal V5, the inverting end of the second operational amplifier U2 is connected to the output end of the fourth operational amplifier U4 and one end of the ninth resistor R9, the inverting end of the fourth operational amplifier U4 is connected to the other end of the ninth resistor R9 and one end of the nineteenth resistor R19, the in-phase end of the fourth operational amplifier U4 is connected to one end of the first capacitor C1 and one end of the twelfth resistor R12, the other end of the first capacitor C1 is connected to the first operational amplifier U 1 output terminal, the inverting terminal of the first operational amplifier U1, and one end of the fifteenth resistor R15 are connected, the non-inverting terminal of the first operational amplifier U1 is connected to the non-inverting terminal of the fifth operational amplifier U5, the collector of the first triode Q1 is connected to the anode of the third thyristor Q3 and the anode of the fifth thyristor Q5, the cathode of the third thyristor Q3 and one end of the fourteenth resistor R14 are connected to the first connecting terminal of the ninth AND gate U9, the cathode of the fifth light emitting diode D5 is connected to the second connecting terminal of the ninth AND gate U9 and one end of the twenty-second resistor R22, the output terminal of the ninth AND gate U9 is connected to the third pin of the seventh digital potentiometer U7, the control electrode of the third thyristor Q3 is connected to the output terminal of the fifth operational amplifier U5 and the input terminal of the eighth NOT gate U8, the control electrode of the fifth thyristor Q5 is connected to the output terminal of the eighth NOT gate U8, the other end of the fifth resistor R5, the other end of the twelfth resistor R12, the other end of the fourteenth resistor R14, the other end of the fifteenth resistor R15, the other end of the nineteenth resistor R19, the other end of the twenty-second resistor R22 and the ground terminal are connected.
[0019] Specifically, it also includes a tenth resistor R10 and a sixteenth resistor R16, one end of the tenth resistor R10 is connected to the second logic signal V2, one end of the sixteenth resistor R16 is connected to the first logic signal V1, and the other ends of the tenth resistor R10 and the sixteenth resistor R16 are connected to the ground.
[0020] Specifically, it also includes a fourth resistor R4 and a seventeenth resistor R17, wherein one end of the fourth resistor R4 is connected to the power supply, the other end of the fourth resistor R4 is connected to the inverting end of the sixth operational amplifier U6 and one end of the seventeenth resistor R17, and the other end of the seventeenth resistor R17 is connected to the ground.
[0021] Specifically, it also includes a first resistor R1 and a third resistor R3, wherein one end of the first resistor R1 is connected to the power supply, the other end of the first resistor R1 is connected to the in-phase end of the second operational amplifier U2 and one end of the third resistor R3, and the other end of the third resistor R3 is connected to the ground.
[0022] Specifically, it also includes a sixth resistor R6 and a seventh resistor R7, one end of the sixth resistor R6 is connected to the gate of the second MOS tube Q2, one end of the seventh resistor R7 is connected to the gate of the sixth MOS tube Q6, and the other ends of the sixth resistor R6 and the seventh resistor R7 are connected to the ground.
[0023] Specifically, it also includes a thirteenth resistor R13, one end of the thirteenth resistor R13 is connected to the first pin of the third decoder U3, and the other end of the thirteenth resistor R13 is connected to the ground end.
[0024] Specifically, it also includes a first switch and a second switch, wherein the first switch is connected to V1 and the second switch is connected to V2, and is used to replace V1 and V2 for manual input.
[0025] Specifically, the fourth resistor R4 is an adjustable resistor.
[0026] See also Figure 1 In one embodiment, in the present invention, V1 and V2 are used to input logic signals, V3 is used to output speed regulation signals, and V4 is a non-speed regulation direct start signal. The third decoder U3 is used for V1 and V2 input decoding. When V1 and V2 are input, the third decoder U3 outputs a truth table as follows: when 0 and 0, the seventh pin of the third decoder U3 outputs a low level to V4, indicating that the non-speed regulation start state is adopted; when 1 and 0, the sixth pin of the third decoder U3 outputs a high level, and the fifth pin of the third decoder U3 outputs a low level signal to the gate of the second MOS tube Q2, and the second MOS tube Q2 is turned on and output to V3, indicating that it is currently in the speed regulation start state; when 0 and 1, the sixth pin of the third decoder U3 outputs a low level, and the fifth pin of the third decoder U3 outputs a high level and the second MOS tube Q2 is turned off, indicating that it is in the shutdown state.
[0027] Considering that the equipment is mistakenly started in high-speed mode, which may cause the operator to be unable to control and cause accidents, the speed control signal is first detected and isolated, and then the speed is gradually adjusted after starting. The second potentiometer R2 and the twenty-first resistor R21 set the speed control signal. Assuming that the current state is stopped, but the speed control signal is preset by the second potentiometer R2 knob, the voltage signal at the second potentiometer R2 end is fed back to the in-phase end of the fifth operational amplifier U5, and the output signal of the fifth operational amplifier U5 is fed back to the fifth pin of the seventh digital potentiometer U7 through the eleventh resistor R11. The third pin of the seventh digital potentiometer U7 is looped through the eighteenth resistor R18. The seventh digital potentiometer U7 increases the voltage at the connection end of the eighth resistor R8 and the twelfth pin of the seventh digital potentiometer U7. The fourth resistor R4 and the seventeenth resistor R17 are used to set the maximum startup current reference signal. When the maximum startup current reference signal set by the fourth resistor R4 and the seventeenth resistor R17 is adjusted, the sixth operational amplifier U6 outputs, and the signal is input to the base of the fourth transistor Q4 through the sixth MOS tube Q6. The fourth transistor Q4 The seventh digital potentiometer U7 is turned on, the fifth pin of the seventh digital potentiometer U7 is connected to the circuit through the eleventh resistor R11 and the fourth transistor Q4, and the seventh digital potentiometer U7 stops increasing. After entering the speed regulation start state, the fifth pin of the third decoder U3 outputs a low level, the second MOS tube Q2 is turned on, and at the same time, the sixth pin of the third decoder U3 outputs a signal that is fed back to the gate of the sixth MOS tube Q6. The sixth MOS tube Q6 and the fourth transistor Q4 are turned off. The output end signal of the fifth operational amplifier U5 is input to the fifth pin of the seventh digital potentiometer U7 through the eleventh resistor R11 again. The seventh digital potentiometer U7 adjusts the voltage of the connection end between the eighth resistor R8 and the twelfth pin of the seventh digital potentiometer U7 to gradually increase, and then is fed back to V3 through the second MOS tube Q2, so as to isolate the part of the preset speed regulation signal in the stop state that is greater than the maximum starting current reference signal. When entering the speed regulation start state from the stop state, the speed regulation signal V3 gradually increases after the isolation is released, so as to avoid high-speed starting when starting from the stop state. When entering the stop state, the sixth MOS tube Q6 is turned on again, and the seventh digital potentiometer U7 is reset by downward adjustment.
[0028] Taking into account the automatic stop inspection after the V3 speed control signal is consistent with the preset adjustment of the second potentiometer R2 and the automatic start inspection during the secondary inspection, the output signal of the fifth operational amplifier U5 is also fed back to the anode of the third thyristor Q3 and the input of the eighth NOT gate U8. In the shutdown state, the output terminal of the fifth operational amplifier U5 outputs a signal. At the same time, after the power supply passes through the emitter, base, and fifth resistor R5 circuit of the first transistor Q1, the collector signal of the first transistor Q1 is fed back to the anode of the third thyristor Q3 and the anode of the fifth thyristor Q5. When the fifth operational amplifier U5 outputs a signal, the signal is fed back to the control electrode of the third thyristor Q3, the third thyristor Q3 is turned on, and the eighth NOT gate U8 is turned off. The collector terminal voltage of the first transistor Q1 is fed back through the anode, cathode, and fourteenth resistor R5 of the third thyristor Q3. R14, the grounding end loop, the voltage at the end of the fourteenth resistor R14 is fed back to the ninth AND gate U9, when the voltage at the connection end of the eighth resistor R8 and the twelfth pin of the seventh digital potentiometer U7 is greater than the in-phase end of the third decoder U3, the fifth operational amplifier U5 is turned off, the eighth NOT gate U8 outputs a signal to the control electrode of the fifth thyristor Q5, the fifth thyristor Q5 is turned on, the collector of the first transistor Q1 is fed back to the ninth AND gate U9 through the fifth thyristor Q5, the twenty-second resistor R22, and the grounding end loop, the voltage at the end of the twenty-second resistor R22 is fed back to the ninth AND gate U9, the output end signal of the ninth AND gate U9 is fed back to the third pin of the seventh digital potentiometer U7, the seventh digital potentiometer U7 is turned off, at this time when V5 inputs a signal, the signal is fed back to the base of the first transistor Q1, the first transistor Q1 is turned off , after the anodes of the third thyristor Q3 and the fifth thyristor Q5 have no input, the ninth AND gate U9 is cut off, the third pin of the seventh digital potentiometer U7 is checked again after passing through the loop of the eighteenth resistor R18, and at the same time, the voltage signal at the second potentiometer R2 is also fed back to the in-phase terminal of the first operational amplifier U1, the first operational amplifier U1 outputs a signal to the first capacitor C1 and passes through the loop of the fifteenth resistor R15, when the secondary speed regulation is performed, the output terminal signal of the first operational amplifier U1 is coupled to the voltage change of the in-phase terminal of the fourth operational amplifier U4 through the first capacitor C1, the output terminal signal of the fourth operational amplifier U4 passes through the loop of the ninth resistor R9 and the nineteenth resistor R19, and the voltage at the terminal of the nineteenth resistor R19 is fed back to the inverting terminal of the fourth operational amplifier U4 for amplification, and at the same time, the fourth operational amplifier U4 The output signal is fed back to the inverting end of the second operational amplifier U2, and the non-inverting end of the second operational amplifier U2 sets a reference signal. The reference signal is greater than the offset voltage output by the first capacitor C1 through the twelfth resistor R12 loop of the fourth operational amplifier U4 when the first operational amplifier U1 does not change. When the fourth operational amplifier U4 outputs, the second operational amplifier U2 outputs a signal to the first transistor Q1, the first transistor Q1 is turned off, the third thyristor Q3 and the fifth thyristor Q5 are reset, the ninth AND gate U9 has no output, and the third pin of the seventh digital potentiometer U7 is adjusted after being pulled down by the eighteenth resistor R18. When the second potentiometer R2 is adjusted, the input of the first capacitor C1 does not change and is decoupled through the twelfth resistor R12 loop, and the fourth operational amplifier U4 is turned off.The first transistor Q1 is turned on, and the output of the fifth operational amplifier U5 changes as the voltage at the eighth resistor R8 rises. The third thyristor Q3 and the fifth thyristor Q5 are looped again to make the ninth AND gate U9 output, and the seventh digital potentiometer U7 is turned off, completing the secondary adjustment start and stop detection. When V5 inputs a signal, the automatic start and stop detection functions are turned off, which is convenient for continuous speed regulation.
[0029] The non-inverting terminal of the second operational amplifier U2 can also be set with a reference signal through the power supply, and when there is no need to adjust the maximum startup current reference signal of the inverting terminal of the sixth operational amplifier U6, it can also be fixedly set by the power input. The sixth resistor R6 and the seventh resistor R7 are used for the MOS tube gate loop to increase the response speed, and the tenth resistor R10 and the sixteenth resistor R16 are used to pull down the signal when the signal is manually input through the switch. At this time, the original connection between the seventh pin of the third decoder U3 and V4 is changed to the fourth pin of the third decoder U3.
[0030] See also Figure 2 In one embodiment, the starting circuit includes three signal lines, Kin1, Kin2, and POTV, and a fluctuation switch. The fluctuation switch includes an adjustable resistor and five contacts, A, B, C, D, and G. The variable resistor is connected to RK5 and the D contact to feedback the voltage signal of the POTV speed regulation. Kin1 and Kin2 are connected to RK4, RK3 and the A and B contacts through RK1 and RK2. RK4 and RK3 are used to pull up the initial signal. The fluctuation switch switches the connection between the ground terminal and A and B to change the state of Kin1 and Kin2 to control the start and stop of the device. After starting, the speed is adjusted according to the voltage of POTV.
[0031] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations within the meaning and scope of the equivalent elements of the claims be included in the invention. Any marking in a claim should not be considered as limiting the claim to which it relates.
Claims
1. A speed regulating switch starting circuit, characterized in that: It includes a second potentiometer, an eighth resistor, an eleventh resistor, an eighteenth resistor, a twentieth resistor, a twenty-first resistor, a third decoder, a fifth operational amplifier, a sixth operational amplifier, a seventh digital potentiometer, a second MOS tube, a fourth triode, and a sixth MOS tube; One end of the second potentiometer and one end of the eighth resistor are connected to the power supply, the other end of the second potentiometer is connected to the in-phase end of the fifth operational amplifier, the output end of the fifth operational amplifier, the collector of the fourth transistor, one end of the eleventh resistor, one end of the twentieth resistor, and one end of the twenty-first resistor, the inverting end of the fifth operational amplifier and the source of the second MOS tube, the other end of the eighth resistor, the in-phase end of the sixth operational amplifier, and the twelfth pin of the seventh digital potentiometer are connected, the output end of the sixth operational amplifier is connected to the source of the sixth MOS tube, the drain of the sixth MOS tube is connected to the base of the fourth transistor, the gate of the sixth MOS tube is connected to the sixth pin of the third decoder, and the seventh digital potentiometer is connected to the inverting end of the fifth operational amplifier and the source of the second MOS tube. The fifth pin of the potentiometer is connected to the other end of the eleventh resistor, the third pin of the seventh digital potentiometer is connected to one end of the eighteenth resistor, the fifth pin of the third decoder is connected to the gate of the second MOS tube, the second pin of the third decoder is connected to the first logic signal V1, the third pin of the third decoder is connected to the second logic signal V2, the drain of the second MOS tube is connected to the speed regulation signal V3, the seventh pin of the third decoder is connected to the start signal V4, the emitter of the fourth transistor, the tenth pin of the seventh digital potentiometer, the eleventh pin of the seventh digital potentiometer, the other end of the eighteenth resistor, the other end of the twentieth resistor, the other end of the twenty-first resistor and the ground are connected.
2. The speed regulating switch starting circuit according to claim 1, characterized in that: It also includes a fifth resistor, a ninth resistor, a twelfth resistor, a fourteenth resistor, a fifteenth resistor, a nineteenth resistor, a twenty-second resistor, a first operational amplifier, a second operational amplifier, a fourth operational amplifier, an eighth NOT gate, a ninth AND gate, a first triode, a third thyristor, a fifth thyristor, and a first capacitor; The emitter of the first transistor is connected to the power supply, the base of the first transistor, the output end of the second operational amplifier, one end of the fifth resistor and the interrupt signal V5 are connected, the inverting end of the second operational amplifier is connected to the output end of the fourth operational amplifier and one end of the ninth resistor, the inverting end of the fourth operational amplifier is connected to the other end of the ninth resistor and one end of the nineteenth resistor, the non-inverting end of the fourth operational amplifier is connected to one end of the first capacitor and one end of the twelfth resistor, the other end of the first capacitor is connected to the output end of the first operational amplifier, the inverting end of the first operational amplifier and one end of the fifteenth resistor, the non-inverting end of the first operational amplifier is connected to the non-inverting end of the fifth operational amplifier, and the collector of the first transistor is connected to the output end of the first operational amplifier, the inverting end of the first operational amplifier and one end of the fifteenth resistor. The electrode is connected to the anode of the third thyristor and the anode of the fifth thyristor, the cathode of the third thyristor is connected to one end of the fourteenth resistor and the first connection end of the ninth AND gate, the cathode of the fifth light-emitting diode is connected to the second connection end of the ninth AND gate and one end of the twenty-second resistor, the output end of the ninth AND gate is connected to the third pin of the seventh digital potentiometer, the control electrode of the third thyristor is connected to the output end of the fifth operational amplifier and the input end of the eighth NOT gate, the control electrode of the fifth thyristor is connected to the output end of the eighth NOT gate, and the other end of the fifth resistor, the other end of the twelfth resistor, the other end of the fourteenth resistor, the other end of the fifteenth resistor, the other end of the nineteenth resistor, the other end of the twenty-second resistor and the ground are connected.
3. The speed regulating switch starting circuit according to claim 1, characterized in that: Also includes a tenth resistor and a sixteenth resistor; One end of the tenth resistor is connected to the second logic signal V2, one end of the sixteenth resistor is connected to the first logic signal V1, and the other ends of the tenth resistor and the sixteenth resistor are connected to the ground.
4. The speed regulating switch starting circuit according to claim 1, characterized in that: Also includes a fourth resistor and a seventeenth resistor; One end of the fourth resistor is connected to the power supply, the other end of the fourth resistor is connected to the inverting end of the sixth operational amplifier and one end of the seventeenth resistor, and the other end of the seventeenth resistor is connected to the ground.
5. The speed regulating switch starting circuit according to claim 2, characterized in that: Also includes a first resistor and a third resistor; One end of the first resistor is connected to the power supply, the other end of the first resistor is connected to the in-phase terminal of the second operational amplifier and one end of the third resistor, and the other end of the third resistor is connected to the ground terminal.
6. The speed regulating switch starting circuit according to claim 1, characterized in that: Also includes a sixth resistor and a seventh resistor; One end of the sixth resistor is connected to the gate of the second MOS tube, one end of the seventh resistor is connected to the gate of the sixth MOS tube, and the other end of the sixth resistor and the other end of the seventh resistor are connected to the ground end.
7. The speed regulating switch starting circuit according to claim 1, characterized in that: A thirteenth resistor is also included; One end of the thirteenth resistor is connected to the first pin of the third decoder, and the other end of the thirteenth resistor is connected to the ground end.
8. The speed regulating switch starting circuit according to claim 1, characterized in that: Also includes a first switch and a second switch; The first switch is connected to V1, and the second switch is connected to V2, and is used to replace V1 and V2 for manual input.
9. The speed regulating switch starting circuit according to claim 4, characterized in that: The fourth resistor is an adjustable resistor.
Citation Information
Patent Citations
Switching circuit and multi-wire system switch
CN209526703U
Cited By
Self-gain signal compensation amplifier
CN120498396A
A self-gain signal compensation amplifier
CN120498396B