Nonlinear DRAM digital equalization

Abstract

The invention relates to non-linear DRAM digital equalization. The signal processing system employs various techniques to enhance data transfer quality. In some cases, the memory controller uses a neural network (e.g., a time delay neural network (TDNN)) to implement non-linear processing to improve equalization. In some other cases, the memory controller uses an activation function to implement non-linear processing to improve equalization. The system may merge a finite impulse response (FIR) filter with the activation function applied to its output. A memory controller including a cache may store a pre-computed value of the activation function. Various types of activation functions or neural network configurations may be employed to introduce nonlinearity and accommodate different application requirements. The present disclosure is applicable to communication systems, control systems, and other digital signal processing systems requiring efficient processing of complex data transmission modes.

Description

Technical Field

[0001] The present disclosure relates to signal processing, for example, non-linear DRAM digital equalization. Background Art

[0002] In some communication systems, data transfer rates have increased significantly due to the growing demand for high-speed data transmission. Therefore, more efficient encoding and decoding schemes are increasingly needed to ensure reliable data transmission. One such scheme is four-level pulse amplitude modulation (PAM4) encoding, which is widely used in high-speed data transmission applications.

[0003] PAM4 encoding is a modulation technique that allows four different levels of amplitude to be transmitted for a given signal. By using PAM4 encoding, twice the amount of data can be transmitted compared to traditional binary encoding schemes that use only two amplitude levels. However, due to various factors (such as noise, signal distortion and attenuation), imperfect data transmission may occur.

[0004] One of the consequences of imperfect data transmission is that the received signal may not exhibit a perfect square plot. A square plot is a visual representation of a transmitted signal in which each amplitude level is represented by a voltage level. In an ideal case, the received signal would have a perfect square plot in which each amplitude level is well defined and separated from the other amplitude levels.

[0005] However, in real-world situations, the received signal may exhibit a non-square pattern due to various factors that cause signal distortion. This may lead to errors when decoding the signal because the decoder may have difficulty distinguishing between different amplitude levels. This may result in reduced accuracy and reliability of the transmitted data. Summary of the invention

[0006] In one aspect, the present disclosure provides an apparatus for signal processing, comprising: a finite impulse response (FIR) filter configured to process a first input signal to reduce linear distortion in the input signal; and a neural network node configured to implement an activation function to apply a nonlinear activation function to reduce nonlinear distortion in the input signal.

[0007] In another aspect, the present disclosure provides an apparatus for signal processing, comprising: a neural network configured to process a first input signal for signal equalization and provide an output signal, the output signal representing signal noise or distortion; and a summing circuit junction configured to subtract the output from a second input signal.

[0008] In another aspect, the present disclosure provides a method for signal processing, comprising: processing an input signal using a finite impulse response (FIR) filter to reduce linear distortion in the input signal; and applying a nonlinear activation function to reduce nonlinear distortion in the input signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a block diagram of a communication system arranged according to examples described herein.

[0010] Figure 2 is a block diagram of another communication system arranged according to the examples described herein.

[0011] FIG. 3a is a diagram illustrating a method for filtering an input signal y using a finite impulse response (FIR) filter and an activation function according to examples described herein. k Block diagram of a signal processing system performing equalization.

[0012] FIG. 3b is a diagram illustrating a method for filtering an input signal y using an FIR filter and an activation function according to examples described herein. k Block diagram of another signal processing system performing equalization.

[0013] FIG. 3c is a diagram illustrating a method for using a neural network to analyze an input signal y according to an example described herein. k Block diagram of a signal processing system performing equalization.

[0014] Figure 4 is a block diagram of a receiver arranged according to the examples described herein.

[0015] Figure 5 is a block diagram of a neural network arranged according to the examples described herein.

[0016] Figure 6 is a block diagram of a processing unit arranged according to the examples described herein.

[0017] Figure 7 is a flow chart of a method according to examples described herein. DETAILED DESCRIPTION

[0018] Specific details will be set forth below to provide a full understanding of the embodiments of the present disclosure. However, it will be apparent to those skilled in the art that the embodiments of the present disclosure may be practiced without various knowledge of these specific details. In other examples, well-known wireless communication components, circuits, control signals, timing protocols, computing system components, and software operations are not shown in detail in order to avoid unnecessarily obscuring the described embodiments of the present disclosure.

[0019] The memory controller and the memory device may communicate with each other and may encode and decode the data before and / or after transmission. Some encoding techniques (e.g., PAM4 encoding) may be used for high-speed data transmission. However, imperfect data transmission of high-speed data transmission scenarios may result in a less than square eye diagram. An eye diagram may be a graphical representation of a digital signal that may illustrate the waveform of a signal over time. A less than square eye diagram may indicate that the signal does not transition cleanly between amplitude levels (e.g., between four amplitude levels in the case of PAM4), which may result in errors in data transmission. This distortion or loss of amplitude levels may be caused by one or more factors, such as noise or signal reflections.

[0020] To improve the quality of data transmission and ensure more accurate decoding of PAM4 signals, advanced signal processing techniques such as equalization or error correction coding can be used. These techniques can help mitigate the effects of imperfect data transmission and improve the overall quality of the signal.

[0021] The present disclosure describes utilizing activation functions or neural networks to improve the quality of data transmission. Activation functions or one or more neural networks may be used to improve the shape of eye diagrams in a communication system via equalization. Equalization may be a technique for adjusting the frequency response of a channel to compensate for distortion (e.g., ISI) and improve the accuracy of data transmission.

[0022] In some examples, an activation function may be added to a finite impulse response (FIR) filter to implement nonlinear filtering to improve the quality of data transmission using PAM4 signals.

[0023] In some other examples, a neural network can be used as an equalizer in a communication system. The neural network can be trained to learn the mapping between a distorted input signal and a desired output signal, which can be the transmitted data. Using a neural network as an equalizer can have several advantages over traditional equalization techniques (e.g., FIR filters). For example, the neural network can be able to adapt to changes in channel characteristics and handle nonlinear distortion. In some cases, the neural network can be able to replace the entire FIR filter.

[0024] Figure 11 is a block diagram of a wireless communication system arranged according to the examples described herein. Computing system 100 includes an electronic device 110. Electronic device 110 coupled to antenna 101 includes sensor 117. Electronic device 110, which may be implemented on a reconfigurable fabric, includes processing unit 111 and control instructions 113. Control instructions 113 may be stored, for example, as encoded executable instructions on a non-transitory computer-readable medium, which, when executed by a processor (e.g., a reconfigurable fabric), is configured to cause electronic device 110 to perform certain operations described herein. In some examples, electronic device 110 may communicate with another device using a physical connection. In other examples, electronic device 110 includes antenna 101 to transmit or receive wireless communication signals, such as modulated RF signals, on a specific wireless frequency band. Electronic device 110 may include a memory 105 for storing information and a controller 106 configured to communicate with memory 105.

[0025] The control instructions 113 may configure the corresponding electronic device 110 for a specific configuration. The control instructions 113 may be implemented locally on each electronic device 110. The electronic device 110 may utilize the corresponding control instructions 113 to control wired or wireless communications; and control the corresponding sensor 117. In other examples, fewer, additional and / or different components may be provided. For example, although each electronic device is described above as including a single sensor, in other examples, each electronic device 110 may include multiple sensors. Alternatively, the electronic device 110 may include, for example Figure 2 The memory device 210 of the memory device and the memory device such as Figure 2 An additional memory controller of the memory controller 205.

[0026] The electronic devices described herein (eg Figure 1 The electronic device 110 shown in ) can generally be implemented using any electronic device that desires wired or wireless communication capabilities. For example, the electronic device 110 can be implemented using a mobile phone, a smart watch (or other wearable device), a computer (e.g., a server, a laptop, a tablet computer, a desktop computer), or a radio. In some examples, the electronic device 110 can be introduced into and / or communicate with other devices that desire communication capabilities, including devices associated with the Internet of Things (IoT), such as (but not limited to) cars, airplanes, helicopters, appliances, tags, cameras, or other devices. Although in Figure 1 Although not explicitly shown, in some examples, electronic device 110 may include any of a variety of components, including but not limited to memory, input / output devices, circuit systems, processing units (e.g., processing elements and / or processors), or combinations thereof.

[0027] To support wired communications, the electronic device may include any number of input and / or output pins or contacts (not shown). To support wireless communications, the electronic device 110 may include multiple antennas. For example, the electronic devices 110 may each have more than two antennas. Although the electronic device 110 includes one antenna, generally any number of antennas may be used, including 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 32, or 96 antennas. Other numbers of antennas may be used in other examples.

[0028] Each processing unit 111 may be implemented using one or more operand processing units, such as an arithmetic logic unit (ALU), a bit manipulation unit, a multiplication unit, an accumulation unit, an adder unit, a lookup table unit, a memory lookup unit, or any combination thereof. In some instances, each processing unit 111 may include circuitry, including custom circuitry, and / or firmware for performing the functions described herein. For example, the circuitry may include a multiplication / accumulation unit for performing the described functions, as described herein. Each processing unit 111 may be implemented as a microprocessor or a digital signal processor (DSP), or any combination thereof. For example, the processing unit 111 may include several levels of cache, such as a level 1 cache and a level 2 cache, a core, and registers. In some instances, one or more processing units 111 may communicate with the memory 105 (e.g., via the memory controller 106). Communication between the memory 105 and the controller 106 may be performed in Figure 2 Further described in .

[0029] Sensor 117 may be any type of sensor for monitoring and / or detecting changes in environmental conditions of respective electronic device 110, which may be referred to as environmental characteristics of each respective electronic device 110. For example, sensor 117 may utilize a sensor mechanism to monitor environmental conditions around it to detect or monitor changes in the environment. Sensor 117 may utilize various detection mechanisms, including but not limited to electrical, chemical, mechanical, or any combination thereof. For example, sensor 117 may utilize a mechanical actuator that converts energy into an electrical signal to detect changes in a road or building structure. As another example, sensor 117 may utilize a chemical sensor that converts energy into an electrical signal to detect changes in sugar levels in the blood. Various types of sensors may be used, such as any type of sensor that may be utilized in an electronic device and coupled to processing unit 111.

[0030] In some examples, the memory 105 and / or the controller 106 may employ an activation function or a neural network to improve the quality of data transmission therebetween (or to communicate with other devices). The activation function or one or more neural networks may be used to improve the shape of eye diagrams in a communication system through equalization, which may improve the communication reliability of the memory 105 and / or the controller 106. In some examples, an activation function may be added to a finite impulse response (FIR) filter to implement nonlinear filtering to improve the quality of data transmission using PAM4 signals. In other examples, a neural network may be used as an equalizer in the memory 105 and / or the controller 106. The neural network may be trained to learn the mapping between a distorted input signal and a desired output signal, which may be the transmitted data. Using a neural network as an equalizer may have several advantages over traditional equalization techniques (e.g., FIR filters). For example, the neural network may be able to adapt to changes in channel characteristics and handle nonlinear distortion. In some cases, the neural network may be able to replace the entire FIR filter.

[0031] Figure 2 A communication system 200 is illustrated that uses encoding (e.g., PAM4 encoding) according to examples described herein. System 200 includes a controller 205 that communicates with a memory device 210 via a transmission line (e.g., a conductive line or trace) 215. Controller 205 includes a controller transceiver 220 that communicates over transmission line 215 using controller pins 235. Memory device 210 includes a memory device transceiver 240 that transmits or receives over transmission line 215 via device pins 245. Memory device 210 includes a plurality of memory banks. In some examples, Figure 1 The electronic device 110 may implement the controller 205 and / or the memory device 210 .

[0032] The controller 205 includes a cache 250 coupled to an activation function (AF) circuit 255 coupled to the controller transceiver 220. The AF circuit 255 implements an activation function to improve data transmission using an encoding such as PAM4 encoding. The cache 250 may be a temporary storage mechanism that retains frequently accessed or recently used data for fast retrieval. The memory controller 205 may reduce the processing time required for non-linear operations, thereby improving overall system performance by storing pre-computed activation function values ​​in the cache 250.

[0033] When applying the activation function of the AF circuit 255, the memory controller 205 may check whether the corresponding output value for the given input already exists in the cache. If so, the controller 205 may retrieve the cached value and use it as the output of the AF circuit 255. If the value does not exist in the cache, the AF circuit 255 may calculate the activation function output for the given input, store the result in the cache 250, and use the calculated value as the output.

[0034] The transmission line 215 includes a command / address bus 225 and a data bus 230. The command / address bus 225 is used to transmit control signals and storage addresses between the controller 205 and the memory device 210. The data bus 230 is used to transmit data between the controller 205 and the memory device 210.

[0035] Controller transceiver 220 communicates with memory device transceiver 240 via transmission line 215 using controller pin 235 and device pin 245. Controller transceiver 220 may convert the data to be transmitted into a format suitable for transmission via transmission line 215, for example, using PAM4 encoding. Memory device transceiver 240 may receive the transmitted data and convert it back to its original format. Additionally or alternatively, memory device transceiver 240 converts the data to be transmitted into a format suitable for transmission via transmission line 215, for example, using PAM4 encoding. In some examples, memory device 210 may include corresponding AF 255 and cache 250.

[0036] In some examples, the AF circuit 255 may employ one or more neural networks to improve the quality of data transmission between them (or to communicate with other devices). The one or more neural networks may be used to improve the shape of the eye diagram in the communication system through equalization, which may improve the communication reliability of the controller transceiver 220 (or memory device transceiver 240). In some examples, the neural network may be used as an equalizer in the memory 105 and / or the controller 106. The neural network may be trained to learn the mapping between the distorted input signal and the desired output signal, which may be the transmitted data. Using a neural network as an equalizer may have several advantages over traditional equalization techniques (e.g., FIR filters). For example, the neural network may be able to adapt to changes in channel characteristics and handle nonlinear distortion. In some cases, the neural network may be able to replace the entire FIR filter.

[0037] FIG. 3a is a diagram illustrating a method for using an FIR filter 310 - a and an activation function 315 - a to process an input signal y according to an embodiment of the present disclosure. k 305-a is a block diagram of a signal processing system 300-a that performs equalization. In some examples, Figure 1 The electronic device 110 and / or Figure 2The controller 205 and / or the memory device 210 may implement the signal processing system 300-a. The signal processing system 300-a includes several components, including a first summing circuit 320-a, an activation function 315-a, a decision slicer 325-a, an FIR filter 310-a with a unit delay 330-a and a tap 335-a, and a second summing circuit 340-a.

[0038] The input signal y k 305-a is provided to the first summing circuit 320-a. The first summing circuit 320-a receives two inputs: an input signal y k 305-a and the output from the FIR filter. The first summing circuit 320-a is derived from the input signal y k 305-a Subtract the output from the FIR filter to generate an intermediate signal z k 345-a.

[0039] Then, the intermediate signal z generated by the first summing circuit 320-a is k 345-a is provided to the activation function 315-a. The activation function 315-a is implemented by k 345-a applies a nonlinear transformation to introduce nonlinear processing capabilities into the system. This transformation allows the system to effectively process and mitigate nonlinear distortions or artifacts in the input signal that a linear FIR filter alone may not be able to handle.

[0040] The output of the activation function 315-a is then provided to a decision slicer 325-a, which operates under an input clock signal (clk) 350-a. The decision slicer 325-a, also known as a slicer or quantizer, is responsible for making decisions on the received signal and converting the continuous or discrete time signal from the activation function 315-a into a discrete time, discrete amplitude signal. The output of the decision slicer is represented as d k 355-a.

[0041] Output d from the decision slicer k 355-a is fed into the FIR filter 310-a, which in some cases can be implemented in a direct form discrete time configuration. The FIR filter 310-a includes a series of unit delays 330-a, taps 335-a with coefficients h, and a second summing circuit 340-a. The unit delays 330-a are used to store and offset the input samples, thereby allowing the FIR filter 310-a to operate on the sequence of input samples over time. The taps 335-a represent the FIR filter coefficients (h) multiplied by the corresponding delayed input samples. These weighted samples are then combined using the second summing circuit 340-a to produce the output of the FIR filter 310-a.

[0042] The output of the FIR filter 310-a is then fed back to the first summing circuit 320-a where it is converted from the input signal y k 305-a Subtract the output. This feedback process allows the system to adaptively equalize the input signal by canceling or reducing undesired components or distortion.

[0043] FIG. 3 b is a diagram illustrating a method for filtering an input signal y using an FIR filter 310 - b and an activation function 315 - b according to examples described herein. k 305-b is a block diagram of a signal processing system 300-b that performs equalization. In some examples, Figure 1 The electronic device 110 and / or Figure 2 The controller 205 and / or the memory device 210 may implement the signal processing system 300-b. In this configuration, the activation function 315-b is placed after the output of the FIR filter 310-b and before the first summing circuit 320-b. The signal processing system 300-b includes several components, including a first summing circuit 320-b, an activation function 315-b, a decision slicer 325-b, an FIR filter 310-b with a unit delay 330-b, a tap 335-b, and a second summing circuit 340-b.

[0044] The input signal y k 305-b is provided to the first summing circuit 320-b, which converts the signal z k The decision slicer 325-b is provided to the decision slicer 325-b, which operates under the input clock signal (clk) 350-b. The decision slicer 325-b, also known as a slicer or quantizer, is responsible for making decisions on the received signal and converting the continuous or discrete time signal into a discrete time, discrete amplitude signal. The output of the decision slicer is represented as d k 355-b.

[0045] Output d from the decision slicer k 355-b is fed into FIR filter 310-b, which in some cases can be implemented in a direct form discrete time configuration. FIR filter 310-b includes a series of unit delays 330-b, taps 335-b with coefficients h, and a second summing circuit 340-b. Unit delays 330-b are used to store and offset input samples, thereby allowing FIR filter 310-b to operate on the input sample sequence over time. Taps 335-b represent FIR filter coefficients (h) multiplied by corresponding delayed input samples. Then, these weighted samples are combined using a second summing circuit to generate the output of FIR filter 310-b.

[0046] The output of FIR filter 310-b is then provided to activation function 315-b. Activation function 315-b introduces nonlinear processing capabilities to the system by applying a nonlinear transformation to the output of FIR filter 310-b. This transformation allows the system to effectively process and mitigate nonlinear distortions or artifacts in the input signal that the linear FIR filter 310-b may not be able to handle alone.

[0047] The output of activation function 315-b is then fed back to first summing circuit 320-b where it is fed from input signal y k 305-b subtracts the output to generate an intermediate signal z k 345-b. This feedback process allows the system to adaptively equalize the input signal by canceling or reducing undesirable components or distortion.

[0048] One difference in this configuration is that the activation function 315-b is placed after the FIR filter output and before the first summing circuit 320-b, which allows the filter output to be compared with the input signal y. k 305-b Non-linear processing is applied directly to the filter outputs before combining.

[0049] FIG. 3c is a diagram illustrating a method for using a neural network to analyze an input signal y according to an example described herein. k 305-c is a block diagram of a signal processing system 300-c that performs equalization. In some examples, Figure 1 The electronic device 110 and / or Figure 2 The controller 205 and / or the memory device 210 may implement the signal processing system 300-c. The signal processing system 300-c includes several components, including a summing circuit 320-c, a decision slicer 325-c, and a neural network 330-c, which in some cases may be a time delay neural network (TDNN).

[0050] The input signal y k 305-c is provided to the summing circuit 320-c, and the input signal y is provided to the summing circuit 320-c. k 305-c is combined with the output of the neural network 330-c to generate an intermediate signal z k 345-c.

[0051] Then, the intermediate signal z k345-c is provided to a decision slicer 325-c, which operates under an input clock signal (clk) 350-c. The decision slicer 325-c, also known as a slicer or quantizer, is responsible for making decisions on the received signal and converting the continuous or discrete time signal into a discrete time, discrete amplitude signal. The output of the decision slicer is represented by d k 355-c.

[0052] Output d from the decision slicer k 355-c is fed to the neural network 330-c. In some cases, the neural network 330-c may be implemented as a time delay neural network (TDNN), which is capable of modeling a series of data by introducing delays into the input data via delay neurons.

[0053] Neural network processes input data k 355-c, and provides the indication to be applied to the input signal y k Then, this output signal is fed back to the summing circuit 320-c, where the input signal y k 305-c subtracts the output signal to generate a balanced intermediate signal z k 345-c. The summing circuit 320-c adds or subtracts the signals, effectively combining the input signal yk 305-c with the output from the neural network 330-c to produce the intermediate signal z k 345-c, equalized version of the input signal.

[0054] The signal processing system 300-c depicted in the figure uses a neural network 330-c to process the input signal y k 305-c performs equalization, and the neural network 330-c may be a time-delay neural network in some cases. The components including the summing circuit 320-c, the decision slicer 325-c, and the neural network 330-c work to process and equalize the input signal, mitigating distortion and artifacts that may be present due to the characteristics of the signal. The neural network 330-c achieves adaptive equalization by learning the appropriate adjustments to be applied to the input signal based on the output from the decision slicer, and allows nonlinear filtering that cannot be achieved using only linear FIR filters.

[0055] Figure 4 4 is a block diagram illustrating a receiver 400 (e.g., a PAM4 receiver). The PAM4 receiver is designed to decode and process PAM4 encoded data and includes several key components, including a PAM4 decoder 405, an activation function 410, a cache 415, and three receive (RCV) operational amplifiers (op amps) 420. In some examples, Figure 1 The electronic device 110, Figure 2 The controller 205 and / or the memory device 210 and / or Figures 3A to 3C Any of the signal processing systems 300 - a to c may implement the receiver 400 , respectively.

[0056] The PAM4 decoder 405 is responsible for converting the PAM4 encoded data received from the RCV op amp 420 into two separate binary signals, the most significant bit (MSB) 425 and the least significant bit (LSB) 430. These two output signals represent the decoded data and may be further processed or utilized by other components in the system.

[0057] The activation function 410 communicates with the PAM4 decoder 405 and introduces nonlinear processing capabilities to the system. It applies a nonlinear transformation to the input data from the PAM4 decoder 405, thereby allowing the receiver to effectively process and mitigate nonlinear distortion or artifacts in the received PAM4 encoded data that linear processing alone may not be able to handle.

[0058] Cache 415 is used to provide data to activation function 410. Cache 415 stores pre-computed values ​​or other relevant information that may be needed for efficient processing of activation function 410. This stored data can help reduce the computational complexity and latency of activation function 410, ultimately improving the overall performance of PAM4 receiver 400.

[0059] Three RCV op amps 420 are used to amplify and process incoming PAM4 encoded data (DQ) 435 before providing it to the PAM4 decoder 405. Each op amp 420 has a positive terminal connected to the data line (DQ) 435 and a negative terminal connected to one of the reference voltages 440: VREFDU, VREFDM, and VREFDL. These reference voltages help set the appropriate thresholds for each op amp 420 to properly process the PAM4 encoded data.

[0060] VREFDU, VREFDM, and VREFDL are reference voltages used to establish the decision levels of the three RCV op amps. VREFDU is connected to the negative terminal of the first op amp 420-a, VREFDM is connected to the negative terminal of the second op amp 420-b, and VREFDL is connected to the negative terminal of the third op amp 420-c. These reference voltages are critical for accurate signal detection and decoding of PAM4 encoded data.

[0061] Figure 53c . . is a block diagram of a neural network 500 according to examples described herein. Neural network 500 can be implemented as a nonlinear filter, such as in neural network 330-c in FIG. 3c . In some examples, neural network 500 can be a delay neural network (e.g., a time delay neural network (TDNN)).

[0062] The neural network 500 can model a series of data by introducing delays into the input data via delay neurons of the delay layer 505. Each delay neuron (e.g., z-1) of the delay layer 505 can receive input from a previous neuron with a certain delay. For example, the delay neuron 506 delays the input signal y(n) and outputs the previous input data y(n-1) (e.g., represented by n-1). The delay neuron 506 can provide the delayed input signal y(n-1) to the subsequent delay neuron (e.g., delay neuron 507) and one or more input neurons of the first hidden layer 510.

[0063] The first hidden layer 510 of the neural network 500 may include one or more neurons that receive data. Weights may be applied to the series of data and provided to the second hidden layer 515. Additional weights may be applied to the data and provided to the output layer 520.

[0064] During the training phase of the neural network 500, one or more optimization algorithms (e.g., gradient descent) can be used to adjust the weights of the network to reduce the error between the predicted output and the actual output. The network can be trained using supervised learning, unsupervised learning, or both. Once trained, the neural network 500 can be used to predict future values ​​of a data series based on past values.

[0065] The TDNN architecture of the neural network 500 allows for efficient processing of time series data by introducing temporal dependencies into its structure. This enables the neural network to capture patterns and relationships in data across different time steps, thereby enhancing its predictive power and overall performance.

[0066] The first hidden layer 510, the second hidden layer 515, or both may include one or more layers of neurons that perform nonlinear transformations on weighted input data. These transformations enable the neural network to learn complex nonlinear relationships in time series data. The hidden layer may employ various activation functions, such as sigmoid, hyperbolic tangent (tanh), rectified linear unit (ReLU), or leaky ReLU, to introduce nonlinearity into the neural network.

[0067] The output layer 520 generates the final output of the neural network, which may represent a predicted value of the data series or a processed version of the input signal. The output layer may be composed of one or more output neurons, each of which uses an activation function to generate a final output value.

[0068] Neural network 500 can be used in various applications requiring nonlinear filtering, such as signal processing, communication systems, and control systems. By replacing the traditional FIR filter with a TDNN architecture, the system can benefit from the enhanced processing power provided by the neural network, thereby achieving improved performance and adaptability to complex data patterns.

[0069] Neural network 500 can be implemented using a variety of hardware and software components, including dedicated processing units, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), or general purpose processors running software implementations. The choice of implementation may depend on the specific requirements of the application, such as processing speed, power consumption, and adaptability to changing data patterns.

[0070] Figure 6 is a block diagram of a processing unit 605 arranged in a computing system 600 according to examples described herein. For example, the system 600 may include Figure 1 The electronic device 110 and / or Figure 2 205 and / or the memory device 210 of the controller 205 and / or the memory device 210. For example, the processing unit 111 may include the processing unit 605, and the memory 105 may include the memory 602. The processing unit 605 may receive input data (e.g., X(i,j)) 610a to c from this computing system. In some examples, the input data 610a to c may be input data, such as data received from a sensor or data stored in the memory 602. For example, the data stored in the memory 602 may be output data generated by one or more processing units implementing another processing stage. The processing unit 605 may include multiplication units / accumulation units 612a to c, 616a to c and memory lookup units 614a to c, 618a to c, which when mixed with the weight data retrieved from the memory 602 may generate output data (e.g., B(u,v)) 620a to c. In some examples, the output data 620a to c may be used as input data for another processing stage or as output data to be transmitted via an antenna. In some examples, processing unit 605 may communicate with memory 602 (eg, memory 210 ) via a controller (eg, controller 205 ).

[0071] When implementing one or more processing units 605, a computer-readable medium at an electronic device may execute corresponding control instructions to perform operations through executable instructions within the processing unit 605. For example, the control instructions provide instructions to the processing unit 605, which, when executed by the computing device, cause the processing unit 605 to configure the multiplication units 612a to c to multiply the input data 610a to c with the weight data, and configure the accumulation units 616a to c to accumulate the processing results to generate the output data 620a to c.

[0072] The multiplication unit / accumulation unit 612a-c, 616a-c multiplies two operands from the input data 610a-c to produce a multiplication processing result that is accumulated by the accumulation unit portion of the multiplication unit / accumulation unit 612a-c, 616a-c. The multiplication unit / accumulation unit 612a-c, 616a-c adds the multiplication processing result to update the processing result stored in the accumulation unit portion, thereby accumulating the multiplication processing result. For example, the multiplication unit / accumulation unit 612a-c, 616a-c can perform a multiplication-accumulation operation so that two operands M and N are multiplied and then added to P to produce a new version of P stored in its corresponding multiplication unit / accumulation unit. The memory lookup unit 614a-c, 618a-c retrieves weight data stored in the memory 602. For example, the memory lookup unit can be a lookup table that retrieves a specific weight. The output of the memory lookup units 614a-c, 618a-c is provided to the multiplication units / accumulation units 612a-c, 616a-c, which can be used as multiplication operands in the multiplication unit portions of the multiplication units / accumulation units 612a-c, 616a-c. Using this circuit system arrangement, output data (e.g., B(u,v)) 620a-c can be generated based on the input data (e.g., X(i,j)) 610a-c.

[0073] In some examples, for example, weight data from memory 602 may be mixed with input data X(i, j) 610a to c to generate output data B(u, v) 620a to c. The weight data may be expressed as follows based on the relationship between input data X(i, j) 610a to c and output data B(u, v) 620a to c:

[0074]

[0075] where a' k,l 、a' m ' ,n are the weights of the first set of multiplication / accumulation units 612a to c and the second set of multiplication / accumulation units 616a to c, respectively, and wherein f(·) represents the mapping relationship performed by the memory lookup units 614a to c, 618a to c. As described above, the memory lookup units 614a to c, 618a to c retrieve weights to mix with the input data. Therefore, the output data can be provided by manipulating the input data using a set of weights associated with the desired transmission protocol stored in the memory using the multiplication / accumulation units. The resulting mapped data can be manipulated by additional multiplication / accumulation units using several sets of additional weights associated with the desired transmission protocol stored in the memory. The several sets of weights multiplied at each level of the processing unit 605 can represent or provide an estimate of the processing of the input data in specially designed hardware (e.g., FPGA).

[0076] Furthermore, it can be shown that, as represented by equation (1), in some instances, system 600 can approximate any nonlinear mapping with arbitrarily small error, and the mapping of system 600 is given by weights a′ k,l 、a' m ' ,n For example, if such weight data is specified, any mapping and processing between input data X(i,j) 610a-c and output data B(u,v) 620a-c can be performed by system 600. Such a relationship as derived from the circuit system arrangement depicted in system 600 can be used to train the entities of computing system 600 to generate weight data. For example, using equation (1), the entities of computing system 600 can compare the input data and the output data to generate weight data.

[0077] In an example of system 600, processing unit 605 utilizes memory lookup units 614a to c, 618a to c to mix weight data with input data X(i, j) 610a to c. In some examples, memory lookup units 614a to c, 618a to c may be referred to as lookup table units. Weight data may be associated with a mapping relationship of input data X(i, j) 610a to c to output data B(u, v) 620a to c. For example, weight data may represent a nonlinear mapping of input data X(i, j) 610a to c to output data B(u, v) 620a to c. In some examples, the nonlinear mapping of weight data may represent a Gaussian function, a piecewise linear function, a sigmoid function, a thin plate spline function, a complex quadratic function, a cubic approximation, an inverse complex quadratic function, or a combination thereof. In some examples, some or all of memory lookup units 614a to c, 618a to c may be deactivated. For example, one or more of the memory lookup units 614a-c, 618a-c may operate as a gain unit with unity gain.

[0078] Each of the multiplication units / accumulation units 612a-c, 616a-c may include multiple multipliers, multiple accumulation units, or and / or multiple adders. Any of the multiplication units / accumulation units 612a-c, 616a-c may be implemented using an ALU. In some examples, any of the multiplication units / accumulation units 612a-c, 616a-c may include one multiplier and one adder that each perform multiple multiplications and multiple additions, respectively. The input-output relationship of the multiplication / accumulation units 612, 616 may be expressed as:

[0079]

[0080] where "I" represents the number of multiplications performed in the unit, C i represents a weight accessible from a memory such as memory 602, and B in(i) represents a factor from the input data X(i,j) 610a-c or from the output of the multiplication unit / accumulation unit 612a-c, 616a-c. In the example, the output B of a group of multiplication units / accumulation units out Equal to weight data C i Multiply by the output B of another set of multiplication unit / accumulation unit in The sum of (i). in (i) It is also possible to make the output B of a set of multiplication units / accumulation units for input data out Equal to weight data C i Multiplies the sum of the input data.

[0081] Figure 7 is a flow chart of a method 700 according to an example described herein. The example method 700 may use, for example, Figure 1 The communication system 100, Figure 2 The communication system 200 described herein Figure 1 The operations described in blocks 702, 704 may also be stored as control instructions in a computer-readable medium at the memory controller 205 or the memory device 210. In some examples, the method 700 may be implemented in a non-transitory computer-readable medium that includes instructions executable to cause a wireless communication device to perform one or more operations of the method 700.

[0082] The method 700 may include processing an input signal using a FIR filter to reduce linear distortion in the input signal at 702. In some examples, the method 700 may include configuring the FIR filter with adjustable filter coefficients.

[0083] The method 700 may include applying a non-linear activation function at 704 to reduce non-linear distortion in the input signal. In some examples, the method 700 may include storing pre-computed values ​​of the non-linear activation function in a cache. In some examples, the method 700 may include initializing the cache during system startup. In some examples, the method 700 may include checking the pre-computed activation function values ​​in the cache during processing. In some examples, the method 700 may include applying the non-linear activation function before the summing circuit junction. In some examples, the method 700 may include applying the non-linear activation function after the summing circuit junction. In some examples, wherein the non-linear activation function is selected from the group consisting of sigmoid, tanh, ReLU, and leaky ReLU.

[0084] Steps 702 and 704 of method 700 are used for illustrative purposes. In some examples, steps 702 and 704 may be performed in a different order. In some other examples, various steps 702 and 704 may be eliminated. In still other examples, various steps 702 and 704 may be split into additional steps, supplemented with other steps, or combined together into fewer steps. Other variations of these particular steps are contemplated, including changes in the order of the steps, changes in the content of the steps that are separated or combined into other steps, etc.

[0085] Certain details are set forth above to provide a full understanding of the described examples. However, it will be apparent to those skilled in the art that the examples may be practiced without these specific details. The description herein, together with the accompanying drawings, describes example configurations and does not represent all examples that may be implemented or within the scope of the claims. The terms "exemplary" and "example" as used herein mean "used as an example, instance, or illustration," rather than "preferred" or "better than other examples." Specific embodiments include specific details for facilitating the understanding of the described techniques. However, these techniques may be practiced without these specific details. In some examples, well-known structures and devices are shown in block diagram form in order to avoid blurring the concepts of the described examples.

[0086] The information and signals described herein may be represented using any of a variety of different processes and technologies. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0087] The techniques described herein may be used in various wireless communication systems, which may include multiple access cellular communication systems, and which may employ code division multiple access (CDMA), time division multiple access (TDMA), frequency division multiple access (FDMA), orthogonal frequency division multiple access (OFDMA), or single carrier frequency division multiple access (SC-FDMA), or any combination of such techniques. Some of these techniques have been adopted in or are related to standardized wireless communication protocols by organizations such as the Third Generation Partnership Project (3GPP), the Third Generation Partnership Project 2 (3GPP2), and the IEEE. These wireless standards include Ultra Mobile Broadband (UMB), Universal Mobile Telecommunications System (UMTS), Long Term Evolution (LTE), Advanced LTE (LTE-A), LTE-A Pro, New Radio (NR), IEEE 802.11 (WiFi), and IEEE 802.16 (WIMAX), among others.

[0088] The various illustrative blocks and modules described in connection with the disclosure herein may be implemented or performed with a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0089] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on a computer-readable medium or transmitted via a computer-readable medium as one or more instructions or codes. Computer-readable media include both non-transitory computer storage media and communication media, and the communication media include any media that facilitates the transfer of a computer program from one place to another. Non-transitory storage media may be any available media that can be accessed by a general or special-purpose computer. By way of example and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), or optical disk storage devices, magnetic disk storage devices, or other magnetic storage devices or any other non-transitory media that can be used to carry or store desired program code components in the form of instructions or data structures and can be accessed by a general or special-purpose computer or a general or special-purpose processor.

[0090] Moreover, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technology (such as infrared, radio and microwave), then the definition of medium includes coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technology (such as infrared, radio and microwave). Combinations of the above are also included within the scope of computer-readable media.

[0091] Other examples and implementations are within the scope of the present disclosure and the appended claims. For example, due to the nature of software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hard wiring, or a combination of any of these. Features that implement the functions may also be physically located at various locations, including portions that are distributed so that the functions are implemented at different physical locations.

[0092] Moreover, as used herein, "or" as used in a list of items (e.g., a list of items preceded by a phrase such as "at least one of" or "one or more of") in the inclusion claims indicates an inclusion list such that a list of at least one of (e.g.) A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Moreover, as used herein, the phrase "based on" should not be interpreted as a reference to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "based at least in part on."

[0093] It should be understood from the foregoing that although specific examples have been described herein for illustrative purposes, various modifications may be made while remaining within the scope of the claimed technology. The description herein is provided to enable a person skilled in the art to make or use the present disclosure. A person skilled in the art will readily appreciate various modifications of the present disclosure, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but conforms to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A device for signal processing, include: a finite impulse response (FIR) filter configured to process a first input signal to reduce linear distortion in the input signal; and A neural network node is configured to implement an activation function to apply a non-linear activation function to reduce non-linear distortion in the input signal.

2. The apparatus of claim 1, wherein the nonlinear activation function is selected from the group consisting of sigmoid, hyperbolic tangent tanh, rectified linear unit (ReLU), leaky ReLU, or a combination thereof.

3. The device according to claim 1, further comprising: include: A cache is configured to store pre-computed values ​​of the non-linear activation function.

4. The apparatus of claim 3, wherein the cache is configured to check pre-computed activation function values ​​during processing.

5. The device according to claim 1, further comprising: include: A summing circuit junction is configured to subtract the output of the FIR filter from a second input signal and provide the output of the summing circuit junction to the neural network node configured to implement the activation function.

6. The device according to claim 1, further comprising: include: A summing circuit junction configured to subtract the output of the FIR filter from a second input signal, wherein the neural network node configured to implement the activation function is located between the output of the FIR filter and the summing circuit junction.

7. A device for signal processing, wherein include: a neural network configured to process a first input signal for signal equalization and provide an output signal, the output signal representing signal noise or distortion; and A summing circuit junction is configured to subtract the output from a second input signal.

8. The apparatus of claim 7, wherein the neural network comprises one or more delay neurons, and wherein the neural network is a time delay neural network (TDNN).

9. The apparatus of claim 7, wherein the neural network comprises one or more hidden layers and an output layer.

10. The apparatus of claim 7, wherein the neural network is configured to process time series data.

11. The apparatus of claim 7, wherein the neural network is trained using supervised learning, unsupervised learning, or both.

12. The apparatus according to claim 7, further comprising: include: A slicer is configured to convert a continuous or discrete-time signal from the summing circuit junction into a discrete-time, discrete-amplitude signal for the neural network.

13. A method for signal processing, wherein include: Processing an input signal using a finite impulse response (FIR) filter to reduce linear distortion in the input signal; and A non-linear activation function is applied to reduce non-linear distortion in the input signal.

14. The method according to claim 13, further comprising: include: Precomputed values ​​of the non-linear activation function are stored in a cache.

15. The method according to claim 14, further comprising: include: The cache is initialized during system startup.

16. The method according to claim 14, further comprising: include: The pre-computed activation function values ​​in the cache are checked during processing.

17. The method according to claim 13, further comprising: include: The non-linear activation function is applied before the summing circuit junction.

18. The method according to claim 13, further comprising: include: The non-linear activation function is applied after the summing circuit junction.

19. The method of claim 13, wherein the nonlinear activation function is selected from the group consisting of sigmoid, tanh, rectified linear unit (ReLU), and leaky ReLU.

20. The method according to claim 13, further comprising: include: The FIR filter is configured with adjustable filter coefficients.

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