Semiconductor structure and manufacturing method thereof

Abstract

The invention provides a semiconductor structure and a manufacturing method thereof, the semiconductor structure comprises a substrate and a storage structure, the substrate is provided with first contact pads, and the first contact pads comprise a first type of contact pads and a second type of contact pads; the storage structure is arranged on the substrate, the storage structure comprises first capacitors and second capacitors which are arranged in a stacked mode, connecting plugs are arranged between the adjacent first capacitors, the first capacitors are connected with the first type of contact pads, and the second capacitors are connected with the second type of contact pads through the connecting plugs; the cross-sectional area of the connection plug is smaller than that of the first capacitor. The semiconductor structure disclosed by the invention can increase the critical dimensions of the first capacitor and the second capacitor and reduce the depth-to-width ratio of the first capacitor and the second capacitor while avoiding short circuit between adjacent capacitors and open circuit of the capacitors, thereby improving the capacitance, and further improving the performance of the semiconductor structure while ensuring the yield of the semiconductor structure.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] Capacitors are important components in chips, and the size of capacitors affects chip performance. As chip size continues to shrink and storage density increases, capacitors are increasingly densely distributed in chips. Usually, the aspect ratio of capacitors is increased to meet capacitor size requirements.

[0003] However, the above capacitors are prone to short circuits, open circuits and other problems, which affect the chip yield. Summary of the invention

[0004] The following is a summary of the subject matter of the detailed description of the present disclosure. This summary is not intended to limit the scope of the claims.

[0005] The present disclosure provides a semiconductor structure and a manufacturing method thereof.

[0006] A first aspect of the present disclosure provides a semiconductor structure, the semiconductor structure comprising:

[0007] A substrate, on which a first contact pad is disposed, wherein the first contact pad includes a first type of contact pad and a second type of contact pad;

[0008] A storage structure is arranged on the substrate, the storage structure comprises a first capacitor and a second capacitor which are stacked, wherein a connection plug is arranged between adjacent first capacitors, the first capacitor is connected to the first type of contact pad, and the second capacitor is connected to the second type of contact pad through the connection plug;

[0009] A cross-sectional area of ​​the connecting plug is smaller than a cross-sectional area of ​​the first capacitor.

[0010] In some embodiments of the present disclosure, projections of the first capacitor and the second capacitor on the substrate are staggered or alternately arranged.

[0011] In some embodiments of the present disclosure, the first contact pads are arranged in an array.

[0012] In a row of first contact pads, at least one second-type contact pad is disposed between adjacent first-type contact pads;

[0013] In a column of first contact pads, at least one second-type contact pad is disposed between adjacent first-type contact pads.

[0014] In some embodiments of the present disclosure, the storage structure also includes a first conductive layer covering the first capacitor and the connecting plug, and a second conductive layer covering the second capacitor, and the first conductive layer and the second conductive layer are in contact at the outermost periphery of the first capacitor and the second capacitor.

[0015] In some embodiments of the present disclosure, an isolation layer is provided between the first capacitor and the second capacitor, a second contact pad is provided in the isolation layer, and at least a portion of the second contact pad connects the connection plug to the second capacitor.

[0016] In some embodiments of the present disclosure, the top surface of the second contact pad is flush with the top surface of the isolation layer; or,

[0017] The top surface of the second contact pad is lower than the top surface of the isolation layer. An opening is provided at a position of the isolation layer corresponding to the second contact pad, and at least a portion of the top surface of the second contact pad is exposed through the corresponding opening.

[0018] In some embodiments of the present disclosure, the aspect ratio of the first capacitor and the second capacitor is 16-32; and / or,

[0019] The first capacitor and the second capacitor have the same height; and / or,

[0020] The heights of the first capacitor and the second capacitor are both 800-1080 nm;

[0021] The diameters of the first capacitor and the second capacitor are both 40-75 nm.

[0022] A second aspect of the present disclosure provides a method for manufacturing a semiconductor structure, the method comprising:

[0023] Providing a substrate, on which a first contact pad is disposed, wherein the first contact pad includes a first type of contact pad and a second type of contact pad;

[0024] Forming a first capacitor and a second capacitor stacked in sequence on the substrate, wherein a connecting plug is provided between adjacent first capacitors, the first capacitor is connected to the first type of contact pad, and the second capacitor is connected to the second type of contact pad through the connecting plug;

[0025] A cross-sectional area of ​​the connecting plug is smaller than a cross-sectional area of ​​the first capacitor.

[0026] In some embodiments of the present disclosure, the first contact pads are arranged in an array, at least one second contact pad is disposed between adjacent first contact pads, and the first capacitor and the second capacitor stacked sequentially on the substrate include:

[0027] forming a first capacitor on the substrate in contact with the first type of contact pad;

[0028] forming a first conductive layer covering the first capacitor;

[0029] forming a through hole in the first conductive layer, wherein the through hole exposes a top surface of the second-type contact pad;

[0030] forming the connecting plug in the through hole, wherein the bottom end of the connecting plug contacts the second-type contact pad;

[0031] forming the second capacitor on the first capacitor, wherein the second capacitor is connected to the connection plug;

[0032] A second conductive layer covering the second capacitor is formed, and the second conductive layer and the first conductive layer are in contact at the outermost peripheries of the first capacitor and the second capacitor.

[0033] In some embodiments of the present disclosure, before forming the connecting plug in the through hole, the manufacturing method further includes:

[0034] forming a first isolation material layer on the first conductive layer, wherein the first isolation material layer covers the sidewalls of the through hole and the top surface of the first conductive layer;

[0035] The connecting plug is formed in the through hole, comprising:

[0036] forming a conductive material layer on the first isolation material layer, wherein the conductive material layer covers the top surface of the first isolation material layer and fills the space enclosed by the first isolation material layer in the through hole, and the first isolation material layer and the conductive material layer in the through hole constitute the connecting plug;

[0037] Before forming the second capacitor on the first capacitor, the manufacturing method further includes:

[0038] Patterning the conductive material layer covering the top surface of the first isolation material layer to form a second contact pad;

[0039] A second isolation material layer is formed, wherein the second isolation material layer covers the first isolation material layer and exposes at least a portion of the top surface of the second contact pad, the first isolation material layer and the second isolation material layer constitute an isolation layer, wherein the second contact pad is located in the isolation layer, and at least a portion of the second contact pad is used to connect the connection plug to the second capacitor.

[0040] The semiconductor structure and the manufacturing method thereof provided by the embodiments of the present disclosure have the following beneficial effects:

[0041] The capacitors in the storage structure are arranged in layers, and the first capacitor close to the substrate is directly connected to the first contact pad on the substrate, and the second capacitor far from the substrate is connected to the first contact pad through the connecting plug between the first capacitors. In this way, the number of capacitors in a single-layer capacitor layer can be reduced, and the cross-sectional area of ​​the connecting plug is smaller than the cross-sectional area of ​​the first capacitor. Therefore, while avoiding short circuits between adjacent capacitors and short circuits of the capacitors themselves, the critical dimensions of the first capacitor and the second capacitor can be increased and the aspect ratio of the first capacitor and the second capacitor can be reduced, thereby increasing the capacitance, thereby improving the performance of the semiconductor structure while ensuring the yield of the semiconductor structure.

[0042] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The accompanying drawings incorporated into the specification and constituting a part of the specification illustrate embodiments of the present disclosure and are used together with the description to explain the principles of the embodiments of the present disclosure. In these drawings, similar reference numerals are used to represent similar elements. The drawings described below are some embodiments of the present disclosure, rather than all embodiments. For those skilled in the art, other drawings can be obtained based on these drawings without paying creative work.

[0044] Figure 1 It is a structural diagram of a semiconductor structure in the related art;

[0045] Figure 2 is a top view of a substrate of a semiconductor structure shown according to an exemplary embodiment;

[0046] Figure 3 is a top view of a substrate of a semiconductor structure according to another exemplary embodiment;

[0047] Figure 4 is a structural diagram of a semiconductor structure for forming an initial supporting layer and an initial sacrificial layer according to an exemplary embodiment;

[0048] Figure 5 is a structural diagram of a semiconductor structure for forming a supporting layer and a sacrificial layer according to an exemplary embodiment;

[0049] Figure 6 is a structural diagram of a semiconductor structure for forming a first lower electrode plate according to an exemplary embodiment;

[0050] Figure 7 is a structural diagram of a semiconductor structure for forming a first dielectric layer and a first upper plate according to an exemplary embodiment;

[0051] Figure 8 is a structural diagram of a semiconductor structure for forming a first conductive layer according to an exemplary embodiment;

[0052] Fig. 9 is a structural diagram of a semiconductor structure for forming a through hole according to an exemplary embodiment;

[0053] Fig.10 is a structural diagram of a semiconductor structure for forming a first isolation material layer according to an exemplary embodiment;

[0054] Fig.11 is a structural diagram of a semiconductor structure for forming a conductive material layer according to an exemplary embodiment;

[0055] Fig.12 is a structural diagram of a semiconductor structure for forming a second contact pad according to an exemplary embodiment;

[0056] Fig.13 is a structural diagram of a semiconductor structure for forming a second isolation material layer according to an exemplary embodiment;

[0057] Fig.14 yes Fig.13 The enlarged view of point A in the middle;

[0058] Fig.15 is a structural diagram of a semiconductor structure forming a second capacitor according to an exemplary embodiment;

[0059] Fig.16 is a structural diagram of a semiconductor structure forming a support structure according to another exemplary embodiment;

[0060] Fig.17 is a structural diagram of a semiconductor structure forming a first lower electrode plate, a first dielectric layer and a first upper electrode plate according to another exemplary embodiment;

[0061] Fig.18 is a structural diagram of a semiconductor structure for forming a first conductive layer according to another exemplary embodiment;

[0062] Fig.19 is a structural diagram of a semiconductor structure for forming a through hole according to another exemplary embodiment;

[0063] Fig. 20 is a structural diagram of a semiconductor structure for forming a first isolation material layer according to another exemplary embodiment;

[0064] Fig.21 is a structural diagram of a semiconductor structure for forming a conductive material layer according to another exemplary embodiment;

[0065] Fig. 22 is a structural diagram of a semiconductor structure showing a second contact pad and a second isolation material layer formed according to another exemplary embodiment;

[0066] Fig.23 is a structural diagram of a semiconductor structure forming a second capacitor according to another exemplary embodiment;

[0067] Fig.24 is a structural diagram of a semiconductor structure according to yet another exemplary embodiment;

[0068] Fig.25 is a flow chart of a method for manufacturing a semiconductor structure according to an exemplary embodiment;

[0069] Fig.26 The present invention is a flow chart showing a method for manufacturing a semiconductor structure according to an exemplary embodiment.

[0070] Reference numerals:

[0071] 1. substrate; 2. storage structure; 201. first capacitor; 2011. first upper plate; 2012. first dielectric layer; 2013. first lower plate; 202. second capacitor; 2021. second upper plate; 2022. second dielectric layer; 2023. second lower plate; 203. third capacitor; 3. first contact pad; 301. first type contact pad; 302. second type contact pad; 4. connecting plug; 5. first conductive layer; 6. second conductive layer; 7. isolation layer; 701. first isolation material layer; 702. second isolation material layer; 8. second contact pad; 801. third type contact pad; 802. fourth type contact pad; 9. supporting structure; 10. initial supporting layer; 11. initial sacrificial layer; 12. supporting layer; 13. sacrificial layer; 14. through hole; 15. capacitor hole; 16. conductive plug; 21. conductive material layer; 22. third contact pad.

[0072] 1', substrate; 2', storage structure; 9', support structure; 18, contact pad; 19, capacitor; 1901, lower plate; 1902, dielectric layer; 1903, upper plate; 20, conductive layer. DETAILED DESCRIPTION

[0073] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the disclosed embodiments will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present disclosure. It should be noted that the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other without conflict.

[0074] As semiconductor structures continue to shrink in size and storage density continues to increase, such as dynamic random access memory (DRAM), the capacitance requirements are usually met by increasing the aspect ratio of the capacitor. However, the capacitor is prone to short circuits and open circuits, which affects the chip yield. Figure 1 , the semiconductor structure in the related art includes a substrate 1' and a storage structure 2' arranged on the substrate 1', wherein the substrate 1' includes a plurality of contact pads 18 arranged in an array, and the storage structure 2' includes capacitors 19 corresponding to each contact pad 18. The capacitor 19 includes a stacked lower plate 1901, a dielectric layer 1902 and an upper plate 1903, a side wall of the lower plate 1901 is provided with a support structure 9' for supporting the capacitor 19, and the bottom of the lower plate 1901 is electrically connected to the contact pad 18, and the semiconductor structure also includes a conductive layer 20 covering each capacitor 19.

[0075] In order to meet the storage density requirements, the capacitors in the semiconductor structure are arranged more densely, and in order to meet the capacitor size requirements, the depth and width of the capacitors are relatively large. For example, the critical dimension of capacitor 19 is set to 30-60nm. At this time, if the critical dimension (Critical Dimension, CD) of capacitor 19 is set larger, the spacing between capacitors 19 is smaller, which can easily cause short circuits between adjacent capacitors 19. If the critical dimension of capacitor 19 is set smaller, the difficulty of the manufacturing process of capacitor 19 will be increased, and capacitor 19 is prone to short circuit problems during the manufacturing process, affecting the yield of the semiconductor structure.

[0076] Based on this, an exemplary embodiment of the present disclosure provides a semiconductor structure and a manufacturing method thereof, wherein the capacitors of the semiconductor structure are arranged in layers, and a first capacitor 201 close to the substrate is directly connected to the first contact pad 3 on the substrate 1, and a second capacitor 202 far from the substrate 1 is connected to the first contact pad 3 through a connecting plug 4 between the first capacitors 201. In this way, the number of capacitors in a single-layer capacitor layer can be reduced, and the cross-sectional area of ​​the connecting plug 4 is smaller than the cross-sectional area of ​​the first capacitor 201. Therefore, while avoiding short circuits between adjacent capacitors and short circuits of the capacitors themselves, the critical dimensions of the first capacitor 201 and the second capacitor 202 can be increased and the aspect ratio of the first capacitor 201 and the second capacitor 202 can be reduced, thereby increasing the capacitor size, and then improving the performance of the semiconductor structure while ensuring the yield of the semiconductor structure.

[0077] An exemplary embodiment of the present disclosure provides a semiconductor structure, referring to Fig.15 The semiconductor structure includes a substrate 1 and a storage structure 2 . A first contact pad 3 is disposed on the substrate 1 . The first contact pad 3 includes a first type contact pad 301 and a second type contact pad 302 .

[0078] The substrate 1 may be, for example, a silicon (Si) substrate, a germanium (Ge) substrate, a SiGe substrate, a silicon on insulator (SOI) or a germanium on insulator (GOI), etc., for supporting the storage structure 2 thereon. The substrate 1 may also be a semiconductor substrate having a device structure, for example, a transistor may be formed on the substrate 1. The first type of contact pad 301 and the second type of contact pad 302 may be electrically connected to the source / drain in the transistor, and the materials of the first type of contact pad 301 and the second type of contact pad 302 may be the same, for example, they may be conductive materials such as metal copper and tungsten.

[0079] The storage structure 2 is arranged on the substrate 1, referring to Fig.15 The storage structure 2 includes a first capacitor 201 and a second capacitor 202 which are stacked.

[0080] Among them, reference Fig.13 as well as Fig. 22 A connecting plug 4 is provided between adjacent first capacitors 201, the first capacitor 201 is connected to the first type contact pad 301, and the second capacitor 202 is connected to the second type contact pad 302 through the connecting plug 4. The cross-sectional area of ​​the connecting plug 4 is smaller than the cross-sectional area of ​​the first capacitor 201. The cross-sectional area here refers to the area of ​​the surface cut by the surface parallel to the substrate. The cross-sectional area of ​​the connecting plug 4 can be, for example, the through hole 14 (see Fig. 9 ), the cross-sectional area of ​​the first capacitor 201 may be, for example, the cross-sectional area of ​​the capacitor hole 15 for accommodating the first capacitor 201.

[0081] It is understandable that the capacitor in the storage structure can be Fig.15 The two layers shown in can also be set as Fig.24 The three layers and above shown can be set according to actual needs. When the capacitors in the storage structure are three layers or more, for example, the capacitors are divided into N layers and N is greater than or equal to 3, each capacitor layer is provided with a plurality of capacitors connected to different first contact pads 3. For example, the capacitors in the first capacitor layer are directly connected to the first type of contact pads 301, and the capacitors in the nth capacitor layer are connected to the second type of contact pads 302 via the connecting plugs 4 in the n-1th to the 1st layers, wherein, in the 1st to the N-1th capacitor layers, the cross-sectional area of ​​the connecting plugs 4 in the same capacitor layer is smaller than the cross-sectional area of ​​the capacitor.

[0082] In this embodiment, the capacitors in the storage structure are arranged in layers, and the first capacitor close to the substrate is directly connected to the first contact pad on the substrate, and the second capacitor far from the substrate is connected to the first contact pad through the connecting plug between the first capacitors. In this way, the number of capacitors in a single-layer capacitor layer can be reduced. Since the cross-sectional area of ​​the connecting plug is smaller than the cross-sectional area of ​​the first capacitor, there is a larger size space to accommodate the capacitor. Therefore, while avoiding short circuits between adjacent capacitors and short circuits of the capacitors themselves, the critical dimensions of the first capacitor and the second capacitor can be increased and the aspect ratio of the first capacitor and the second capacitor can be reduced, thereby increasing the capacitance, thereby improving the performance of the semiconductor structure while ensuring the yield of the semiconductor structure.

[0083] In some embodiments, reference Figure 2 and Figure 3 The projections of the first capacitor 201 and the second capacitor 202 on the substrate 1 are staggered or alternately arranged.

[0084] Among them, reference Figure 2 When the projections of the first capacitor 201 and the second capacitor 202 on the substrate 1 are offset from each other, the projection of the first capacitor 201 on the substrate 1 can be located on the center line of the two diagonally opposite projections of the second capacitor 202 on the substrate 1, or the projection of the second capacitor 202 on the substrate 1 is located on the center line of the two diagonally opposite projections of the first capacitor 201 on the substrate 1.

[0085] refer to Figure 3 When the projections of the first capacitor 201 and the second capacitor 202 on the substrate 1 are alternately arranged, the projection of the first capacitor 201 on the substrate 1 can be located on the center line of the projections of the two second capacitors 202 on the substrate 1 arranged in the same column or the same row, or the projection of the second capacitor 202 on the substrate 1 can be located on the center line of the projections of the two first capacitors 201 on the substrate 1 arranged in the same row or the same column.

[0086] In the present embodiment, the alternating arrangement of the first capacitor 201 and the second capacitor 202 can make good use of the space of the entire semiconductor structure, thereby preventing the first capacitor 201 from affecting the connection between the connecting plug 4 and the second capacitor 202, so that the second capacitor 202 can be electrically connected to the second type of contact pad 302 via the shortest connection path, thereby reducing the signal loss and signal transmission delay generated during the transmission process.

[0087] In some embodiments, the first contact pads 3 are arranged in an array. In a row of first contact pads 3 , at least one second contact pad 302 is disposed between adjacent first contact pads 301 . In a column of first contact pads 3 , at least one second contact pad 302 is disposed between adjacent first contact pads 301 .

[0088] For example, reference Fig.15 When the storage structure is a two-layer capacitor, for example, a second-type contact pad 302 may be disposed between adjacent first-type contact pads 301, and the number of first capacitors 201 and second capacitors 202 may be equal. Fig.24 The storage structure is a three-layer capacitor, and the storage structure also includes a third capacitor 203 arranged above the second capacitor 202. For example, two second-type contact pads 302 can be arranged between adjacent first-type contact pads 301, one of which can be electrically connected to the second capacitor 202, and the other second-type contact pad 302 can be electrically connected to the third capacitor 203.

[0089] In this embodiment, the first type of contact pads 301 and the second type of contact pads 302 are interspersed so that the capacitance of each layer can be evenly distributed. On the one hand, it is convenient for layout design and improves development efficiency. On the other hand, it can ensure the structural stability and reliability of each layer structure and avoid problems such as local collapse caused by connecting plugs 4 and uneven capacitance distribution.

[0090] In some embodiments of the present disclosure, reference Fig.15 The storage structure 2 also includes a first conductive layer 5 covering the first capacitor 201 and the connecting plug 4, and a second conductive layer 6 covering the second capacitor 202. The first conductive layer 5 and the second conductive layer 6 are in contact at the outermost periphery of the first capacitor 201 and the second capacitor 202.

[0091] In this embodiment, the first conductive layer 5 and the second conductive layer 6 arranged outside the storage structure 2 can control the uniform distribution of the electric field and provide electromagnetic shielding. At the same time, the first conductive layer 5 and the second conductive layer 6 serve as protective layers for the first capacitor 201 and the second capacitor 202. The capacitors are wrapped in conductive materials, which can effectively protect the storage structure 2 from damage by the external environment. For example, the first capacitor 201 and the second capacitor 202 can be prevented from being damaged by external impact or vibration. In addition, the first conductive layer 5 and the second conductive layer 6 provide a channel connecting the first capacitor 201 and the second capacitor 202. Such a setting can simplify the circuit layout of the storage structure 2 and ensure the stability of the electrical connection between the first capacitor 201 and the second capacitor 202. Among them, making the outermost periphery of the first conductive layer 5 and the second conductive layer 6 contact each other can ensure that the internal capacitor layout of the storage structure 2 is not disrupted, so as to further ensure the stability of the storage structure 2.

[0092] In some embodiments, continue to refer to Fig.15 An isolation layer 7 is provided between the first capacitor 201 and the second capacitor 202 , a second contact pad 8 is provided in the isolation layer 7 , and at least a portion of the second contact pad 8 connects the connecting plug 4 to the second capacitor 202 .

[0093] In this embodiment, the isolation layer 7 can achieve isolation between the first capacitor 201 and the second capacitor 202, avoid the capacitive coupling effect between the first capacitor 201 and the second capacitor 202, avoid mutual interference or short circuit between the first capacitor 201 and the second capacitor 202, ensure that the first capacitor 201 and the second capacitor 202 can work independently, and improve the reliability and performance of the storage structure 2.

[0094] It is understandable that the second contact pads 8 may correspond one to one with the connecting plugs 4. Fig.15 In the illustrated embodiment, all the second contact pads 8 are used to connect the second capacitor 202 and the connecting plug 4 .

[0095] In other embodiments, reference Fig.24 The storage structure 2 may include more than three layers of capacitors. For example, the storage structure 2 includes a first capacitor 201, a second capacitor 202, and a third capacitor 203. An isolation layer 7 may also be provided between the second capacitor 202 and the third capacitor 203. A third contact pad 22 is provided in the isolation layer 7. A connecting plug 4 may also be provided between adjacent second capacitors 202. Fig.24 , the second contact pad 8 may include a third type contact 801 and a fourth type contact pad 802, the third type contact pad 801 is electrically connected to the second capacitor 202, and the fourth type contact pad 802 is electrically connected to the third capacitor 203 through the connecting plug 4. The storage structure 2 may also include a fourth capacitor (not shown in the figure), a fifth capacitor (not shown in the figure), etc., wherein the connection and arrangement of the third capacitor 203 and the fourth capacitor may be the same as the connection and arrangement of the third capacitor 203 and the second capacitor 202, and so on, and this embodiment will not be repeated here.

[0096] In some embodiments, reference 13, in combination with Fig.11 and Fig.13 The isolation layer 7 includes a first isolation material layer 701 and a second isolation material layer 702. Fig. 9 and Fig.10 , a through hole 14 is provided between the first capacitor 201, the first isolation material layer 701 covers the sidewall of the through hole 14 and the top surface of the first conductive layer 5, the conductive material layer 21 covers the top surface of the first isolation material layer 701 and fills the space enclosed by the first isolation material layer 701 in the through hole 14, the conductive material layer 21 and the part of the first isolation material layer 701 in the through hole 14 constitute the connecting plug 4, and the conductive material layer 21 covering the top surface of the first isolation material layer 701 is patterned to form the second contact pad 8. The second isolation material layer 702 covers the first isolation material layer 701 and exposes at least part of the top surface of the second contact pad 8.

[0097] Exemplarily, the conductive material layer 21 may be a single-layer structure or a multi-layer structure. The conductive material layer 21 of the single-layer structure may include, for example, a metal material layer filled in the space surrounded by the first isolation material layer 701. The conductive material layer 21 of the multi-layer structure may include, for example, a metal material layer and an anti-diffusion layer (not shown in the figure), wherein the anti-diffusion layer may cover the sidewall of the first isolation material layer 701, and the metal material layer may fill in the space formed by the anti-diffusion layer. The metal material layer is used to electrically connect the second type contact pad 302 and the second contact pad 8, and the anti-diffusion layer may be used to block the diffusion of elements between the metal material layer and the first isolation material layer 701.

[0098] In this embodiment, the first isolation material layer 701 can be used to achieve electrical isolation between the first capacitor 201 and the adjacent connecting plug 4, thereby avoiding a short circuit between the first capacitor 201 and the connecting plug 4. The second isolation material layer 702 can be used to isolate the adjacent second contact pad 8, and can also achieve isolation between the first capacitor 201 and the second capacitor 202.

[0099] In some embodiments, reference Fig.15 , the top surface of the second contact pad 8 is flush with the top surface of the isolation layer 7. Specifically, the top surface of the second contact pad 8 is flush with the top surface of the second isolation material layer 702.

[0100] In this embodiment, Fig.11 As shown, the second isolation material layer 702 covers the top surface of the first isolation material layer 701 and the conductive material layer 21, and then a planarization process, such as chemical mechanical polishing (CMP) technology, can be used to remove part of the second isolation material layer 702 to expose the top surface of the second contact pad 8. At this time, the top surface of the second contact pad 8 is flush with the top surface of the isolation layer 7, and the top surface of the second contact pad 8 is completely exposed. In this embodiment, the top surface of the second contact pad 8 is directly exposed through the planarization process for contact with the second capacitor 202, which can effectively improve the processing efficiency of the semiconductor structure, and the process is simple and easy to operate.

[0101] In other embodiments, the top surface of the second contact pad 8 is lower than the top surface of the isolation layer 7, an opening is provided on the isolation layer 7 at a position corresponding to the second contact pad 8, and at least part of the top surface of the second contact pad 8 is exposed through the corresponding opening.

[0102] In this embodiment, the second isolation material layer 702 in the area where the second contact pad 8 is located can be removed by a patterned etching process, and a portion of the top surface of the second contact pad 8 is exposed. In this embodiment, since the top surface of the second contact pad 8 is located within the above-mentioned opening, and the top surface of the second contact pad 8 is lower than the top surface of the isolation layer 7, the isolation layer 7 in the area above the top surface of the second contact pad 8 can play a good isolation role for the adjacent second contact pads 8, thereby avoiding problems such as short circuits between the second contact pads 8.

[0103] In some embodiments, reference Figure 7-Figure 15 ,as well as Figure 18-Figure 23 The first capacitor 201 includes a first upper plate 2011, a first dielectric layer 2012 and a first lower plate 2013. The first lower plate 2013 contacts the top surface of the first contact pad 3. The first dielectric layer 2012 covers the first lower plate 2013 and the first dielectric layer 2012 is laid between adjacent first capacitors 201. The first upper plate 2011 covers the first dielectric layer 2012. The connecting plug 4 passes through the first dielectric layer 2012 and the first upper plate 2011 between adjacent first capacitors 201 to connect with the second type contact pad 302.

[0104] refer to Fig.12 as well as Fig.15 The second capacitor 202 includes a second upper plate 2021, a second dielectric layer 2022 and a second lower plate 2023, the second upper plate 2021 contacts the top surface of the second contact pad 8, the second dielectric layer 2022 covers the second lower plate 2023 and the second dielectric layer 2022 is laid between adjacent second capacitors 202, and the second upper plate 2021 covers the second dielectric layer 2022.

[0105] Exemplarily, the first lower electrode plate 2013 and the second lower electrode plate 2023 may be columnar or in other shapes, which is not limited in this embodiment.

[0106] In some embodiments, reference Figure 16-Figure 23 The first capacitor 201 further includes at least one support structure 9, at least one support structure 9 is located on the side wall of the lower electrode plate 2013, and the first dielectric layer 2012 covers the first lower electrode plate 2013 and the support structure 9. In this embodiment, the support structure 9 is used to support the first capacitor 201 and enhance the overall structural stability of the first capacitor 201.

[0107] In other embodiments, at least one support structure 9 is located between the first lower plates 2013 of two adjacent first capacitors 201, and the first dielectric layer 2012 covers the first lower plate 2013 and the support structure 9, wherein the connecting plug 4 passes through the support structure 9 between the adjacent first capacitors 201 to achieve the purpose of electrical connection with the second type contact pad 302.

[0108] The capacitance of the first capacitor 201 and the second capacitor 202 can be calculated using the following formula:

[0109] C=ε2πRH / A

[0110] Among them, ε is the dielectric constant; R is the critical dimension of the first capacitor 201 or the second capacitor 202. In this formula, the critical dimension is the radius of the first capacitor 201 or the second capacitor 202; H is the height of the first capacitor 201 or the second capacitor 202, and A is the distance between adjacent first upper plates 2011 or adjacent second upper plates 2021.

[0111] It can be seen from the above formula that the capacitance is proportional to the critical size and the height of the capacitor, and inversely proportional to the distance between adjacent first upper plates 2011 or adjacent second upper plates 2021 .

[0112] Exemplarily, the heights of the first capacitor 201 and the second capacitor 202 can be equal, which can reduce the difference in capacitance and the difference in electric field concentration between the first capacitor 201 and the second capacitor 202 to improve the overall stability of the storage structure 2. In addition, during the manufacturing process of the storage structure 2, the second capacitor 202 is formed above the first capacitor 201, that is, the second capacitor 202 is formed after the first capacitor 201. When the height of the second capacitor 202 is equal to that of the first capacitor 201, the various process parameters in the manufacturing process of the second capacitor 202 can be consistent with those of the first capacitor 201. This can simplify the production design process of the second capacitor 202 and improve development efficiency.

[0113] Exemplarily, the height of the first capacitor 201 or the second capacitor 202 is 800-1080nm, and the overall height of the first capacitor 201 and the second capacitor 202 is 800-2160nm. The height of the capacitor 201 and the second capacitor 202 provided in the present disclosure is significantly reduced compared to the capacitor in the prior art, and the height of the capacitor 201 and the second capacitor 202 in the present disclosure is 265-540nm higher than half the height of the capacitor in the prior art.

[0114] Exemplarily, the diameters of the first capacitor 201 and the second capacitor 202 can be equal, and the diameters of the first capacitor 201 and the second capacitor 202 can be, for example, both 40-75 nm. The diameters of the first capacitor 201 and the second capacitor 202 of the present disclosure are improved by 10-15 nm compared with the prior art, that is, in the present disclosure, the key dimensions of the first capacitor 201 and the second capacitor 202 are also significantly improved, so as to achieve the purpose of effectively increasing the capacitance of the first capacitor 201 and the second capacitor 202.

[0115] Exemplarily, the aspect ratio of the first capacitor 201 or the second capacitor 202 is 16-32, the aspect ratio of the first capacitor 201 is the ratio of the height to the diameter of the first capacitor 201 , and the aspect ratio of the second capacitor 202 is the ratio of the height to the diameter of the second capacitor 202 .

[0116] Furthermore, the aspect ratio of the first capacitor 201 and the second capacitor 202 may be 16-28.

[0117] An exemplary embodiment of the present disclosure also provides a method for manufacturing a semiconductor structure, referring to Fig.25 , the preparation method comprises:

[0118] Step S100: providing a substrate, on which first contact pads are arranged, and the first contact pads include first-type contact pads and second-type contact pads.

[0119] The substrate 1 may be, for example, a silicon (Si) substrate, a germanium (Ge) substrate, a SiGe substrate, a silicon on insulator (SOI) or a germanium on insulator (GOI), etc., for supporting the storage structure 2 thereon. The substrate 1 may also be a semiconductor substrate having a device structure, for example, a transistor may be formed on the substrate 1. The first type of contact pad 301 and the second type of contact pad 302 may be electrically connected to the source / drain in the transistor, and the materials of the first type of contact pad 301 and the second type of contact pad 302 may be the same, for example, they may be conductive materials such as metal copper and tungsten.

[0120] A first contact pad 3 is formed in the substrate 1 so as to be electrically connected to the first capacitor 201 and the connecting plug 4 formed thereon. The material of the first contact pad 3 can be a conductive material such as metal tungsten. The first contact pad 3 can be electrically connected to the source / drain of the transistor in the substrate 1 through the conductive plug 16.

[0121] Step S200: forming a first capacitor and a second capacitor stacked in sequence on a substrate, wherein connecting plugs are provided between adjacent first capacitors, the first capacitors are connected to a first type of contact pad, and the second capacitors are connected to a second type of contact pad via the connecting plugs.

[0122] refer to Figure 2 and Figure 3 The first type contact pads 301 and the second type contact pads 302 may be arranged in an array, at least one second type contact pad 302 is disposed between adjacent first type contact pads 301 , and the cross-sectional area of ​​the connecting plug 4 is smaller than the cross-sectional area of ​​the first capacitor 201 .

[0123] In this embodiment, the capacitors of the semiconductor structure formed by the manufacturing method are arranged in layers, and the first capacitor 201 close to the substrate 1 is directly connected to the first contact pad 3 on the substrate 1, and the second capacitor 202 far from the substrate 1 is connected to the first contact pad 3 through the connecting plug 4 between the first capacitors 201. In this way, the number of capacitors in a single-layer capacitor layer can be reduced, and the cross-sectional area of ​​the connecting plug 4 is smaller than the cross-sectional area of ​​the first capacitor 201. Therefore, while avoiding short circuits between adjacent capacitors and short circuits of the capacitors themselves, the critical dimensions of the first capacitor 201 and the second capacitor 202 can be increased and the aspect ratio of the first capacitor 201 and the second capacitor 202 can be reduced, thereby increasing the capacitor size, and then improving the performance of the semiconductor structure while ensuring the yield of the semiconductor structure.

[0124] In an exemplary embodiment of the present disclosure, Fig.26 As shown, step S200 includes the following steps:

[0125] Step S210: forming a first capacitor on the substrate and contacting the first type of contact pad.

[0126] Before forming the first capacitor 201, refer to Figure 4 , an initial support layer 10 and an initial sacrificial layer 11 stacked and arranged on the surface of the substrate 1 can be formed. Figure 5 As shown, a portion of the initial sacrificial layer 11 and a portion of the initial support layer 10 can be removed by dry etching or wet etching to obtain a plurality of capacitor holes 15 corresponding to the first type of contact pads 301. Figure 6 and Figure 7 , a first capacitor 201 can be formed in the capacitor hole 15, and after the first capacitor 201 is formed, the above-mentioned sacrificial layers 13 are removed.

[0127] Step S220: forming a first conductive layer covering the first capacitor.

[0128] refer to Figure 8 For example, the first conductive layer 5 may be formed by an atomic layer deposition process (ALD) or a chemical vapor deposition process (CVD), and the first conductive layer 5 covers each first capacitor 201 .

[0129] By way of example, the material of the first conductive layer 5 may include, for example, doped polysilicon, polyethylene terephthalate (PET), polyethylene terephthalate glycol-modified (PETG), and the like.

[0130] Step S230: forming a through hole in the first conductive layer, wherein the through hole exposes the top surface of the second type contact pad.

[0131] refer to Fig. 9 , part of the first conductive layer 5 can be removed by dry etching or wet etching without affecting the stability of the first capacitor 201 , and the through hole 14 is used to form the connection plug 4 described below.

[0132] Step S240: forming a connecting plug in the through hole, wherein the bottom end of the connecting plug contacts the second type contact pad.

[0133] Among them, reference Fig.13 The connecting plug 4 is filled in the through hole 14 and is used to connect the second type of contact pad 302 with the second capacitor 202 formed subsequently, wherein the connecting plug 4 plays a role of electrical connection, and the cross-sectional area of ​​the connecting plug 4 can be set smaller. Therefore, the storage structure 2 can have more space to arrange the first capacitor 201, and the cross-sectional area of ​​the first capacitor 201 can be set larger, and the aspect ratio of the first capacitor 201 is reduced, thereby increasing the capacitance of the first capacitor 201, and then improving the performance of the semiconductor structure.

[0134] Step S250: forming a second capacitor on the first capacitor, and connecting the second capacitor to the connecting plug.

[0135] Reference Fig.15 As shown, the second capacitor 202 is connected to the second type contact pad 302 through the connecting plug 4 .

[0136] Of course, it is understandable that the key dimensions, height and other parameters of the first capacitor 201 and the second capacitor 202 may be the same or different, and this embodiment does not limit this.

[0137] Step S260: forming a second conductive layer covering the second capacitor, wherein the second conductive layer and the first conductive layer are in contact at the outermost peripheries of the first capacitor and the second capacitor.

[0138] Reference Fig.15 For example, the second conductive layer 6 covering each second capacitor 202 may be formed by using an atomic layer deposition process (ALD) or a chemical vapor deposition process (CVD).

[0139] Exemplarily, the material of the second conductive layer 6 may be the same as or different from that of the first conductive layer 5 , and may include, for example, polyethylene terephthalate (PET) and polyethylene terephthalate glycol-modified (PETG).

[0140] In the present embodiment, the first capacitor 201 and the second capacitor 202 are formed by stacking in sequence, and a connecting plug 4 is formed between the first capacitor 201 to realize the connection between the second capacitor 202 and the first contact pad 3, thereby effectively reducing the number of capacitors in the single-layer capacitor layer, and the cross-sectional area of ​​the connecting plug 4 is smaller than the cross-sectional area of ​​the first capacitor 201. Therefore, while avoiding short circuits between adjacent capacitors and short circuits of the capacitors themselves, the critical dimensions of the first capacitor 201 and the second capacitor 202 can be increased and the aspect ratio of the first capacitor 201 and the second capacitor 202 can be reduced, thereby increasing the capacitance, thereby improving the performance of the semiconductor structure while ensuring the yield of the semiconductor structure.

[0141] It can be understood that the formed semiconductor structure can be a two-layer capacitor, namely a first capacitor 201 and a second capacitor 202, or can be Fig.24 As shown, after the second capacitor 202 is formed, the third capacitor 203 is stacked on the second capacitor 202, wherein the formation process of the second capacitor 202 and the third capacitor 203 can refer to the formation process of the first capacitor 201. Before stacking the third capacitor 203, it is also necessary to set a connecting plug 4 between the second capacitors 202. The specific manufacturing process can refer to the manufacturing process of the connecting plug 4 between the first capacitors 201, which will not be repeated here.

[0142] In an exemplary embodiment of the present disclosure, step S210 specifically includes the following steps:

[0143] Step S211A: forming a stacked initial support layer and an initial sacrificial layer.

[0144] like Figure 4 As shown, the initial sacrificial layer 11 and the initial supporting layer 10 can be provided with multiple layers, and they can be arranged alternately. For example, a layer of initial sacrificial layer 11 can be formed on the surface of the substrate 1 by a deposition process, and then the initial supporting layer 10 can be formed on the surface of the initial sacrificial layer 11, and so on, to form multiple layers of initial sacrificial layers 11 and multiple layers of initial supporting layers 10.

[0145] Step S212A: removing a portion of the initial support layer and a portion of the initial sacrificial layer to form a capacitor hole.

[0146] In this step, refer to Figure 5, a portion of the initial support layer 10 and a portion of the initial sacrificial layer 11 may be removed by etching to form a capacitor hole 15 , wherein the capacitor hole exposes the top surface of the first type contact pad 301 .

[0147] Step S213A: forming a first lower electrode plate, wherein the first lower electrode plate covers the sidewalls of the capacitor hole and the top surface of the first type of contact pad.

[0148] refer to Figure 6 The first lower electrode plate 2013 can be formed by an atomic layer deposition process (ALD) or a chemical vapor deposition process (CVD). The first lower electrode plate 2013 covers the side walls of the capacitor hole 15 and covers the top surface of the first type contact pad 301 exposed by the capacitor hole 15.

[0149] Step S214A: removing the sacrificial layer.

[0150] In this step, the sacrificial layer 13 may be dissolved by an acid solution to completely remove the sacrificial layer 13 , and the supporting layer 12 is retained. The supporting layer 12 constitutes the supporting structure 9 .

[0151] Step S215A: forming a first dielectric layer, wherein the first dielectric layer covers the first lower electrode plates and is laid between adjacent first lower electrode plates.

[0152] refer to Figure 7 The first dielectric layer 2012 may be formed by atomic layer deposition (ALD). The material of the first dielectric layer 2012 is a high-k material, and the dielectric constant of the high-k material is greater than the dielectric constant of silicon dioxide.

[0153] Step S216A: forming a first upper electrode plate, wherein the first upper electrode plate covers the first dielectric layer.

[0154] refer to Figure 7 The first upper plate 2011 may be formed by deposition using an atomic layer deposition process (ALD), and the material of the first upper plate 2011 includes a compound formed by one or both of metal nitride and metal silicide. Exemplarily, the material of the first upper plate 2011 may include one or both of titanium nitride, titanium silicide, nickel silicide, and titanium nitride silicon (TiSixNy).

[0155] In another embodiment, step S210 includes the following steps:

[0156] Step S211B: forming a stacked initial support layer and an initial sacrificial layer.

[0157] Step S212 B: removing a portion of the initial support layer and a portion of the initial sacrificial layer to form a capacitor hole.

[0158] Step S213 B: forming a first lower electrode plate, wherein the first lower electrode plate covers the sidewalls of the capacitor hole and the top surface of the first type of contact pad.

[0159] Step S214 B: removing the sacrificial layer.

[0160] Step 215B: removing part of the support layer to form a support structure.

[0161] refer to Fig.16 , a dry or wet etching method can be used to remove part of the support layer 12 and form a support structure 9 located on the side wall of the first lower electrode plate 2013 , with a gap between the support structure 9 and the adjacent first lower electrode plate 2013 .

[0162] Step S216 B: forming a first dielectric layer, wherein the first dielectric layer covers the first lower electrode plates and the support structure, and is laid between adjacent first lower electrode plates.

[0163] refer to Fig.17 The first dielectric layer 2012 may be formed by deposition using an atomic layer deposition (ALD) process.

[0164] Step S217 B: forming a first upper electrode plate, wherein the first upper electrode plate covers the first dielectric layer.

[0165] Among them, step S211B, step S212B, step S213B, step S214B, and step S217B are similar to step S211A, step S212A, step S213A, step S214A, and step S216A, respectively, and will not be repeated in this embodiment.

[0166] In this embodiment, the finally formed support structure 9 can also provide good support for the first capacitor 201. In addition, the support structure 9 occupies a relatively small space, which helps to improve the overall integration of the storage structure 2 and ensure that the first capacitor 201 can achieve a more compact layout.

[0167] In an exemplary embodiment of the present disclosure, step S240 includes the following steps:

[0168] Step S241 : forming a first isolation material layer on the first conductive layer, wherein the first isolation material layer covers the sidewalls of the through hole and the top surface of the first conductive layer.

[0169] For example, reference Fig.10 as well as Fig. 20 The first isolation material layer 701 can be formed by an atomic layer deposition process or a chemical vapor deposition process. The first isolation material layer 701 can include, for example, silicon nitride (SiN), silicon oxide (SiO2), etc., to achieve a good insulation effect between the connecting plug 4 and the first conductive layer 5 and the first capacitor 201, so as to effectively prevent the connecting plug 4, the first capacitor 201, etc. from current leakage and short circuit problems.

[0170] Step S242: forming a conductive material layer 21 on the first isolation material layer.

[0171] The conductive material layer 21 covers the top surface of the first isolation material layer 701 and fills the space enclosed by the first isolation material layer 701 in the through hole 14 . The first isolation material layer 701 and the conductive material layer 21 in the through hole 14 constitute a connecting plug 4 .

[0172] For example, reference Fig.11 as well as Fig.21 The conductive material layer 21 may be formed by atomic layer deposition (ALD) deposition. The material of the conductive material layer 21 may be, for example, conductive materials such as metal copper and metal tungsten.

[0173] Step S243: patterning the conductive material layer 21 covering the top surface of the first isolation material layer to form a second contact pad.

[0174] Among them, reference Fig.12 , Fig.13 as well as Fig. 22 The conductive material layer 21 can be patterned by dry or wet etching to form a plurality of second contact pads 8 , and the second contact pads 8 correspond to the connection plugs 4 one by one.

[0175] Step S244: forming a second isolation material layer, wherein the second isolation material layer covers the first isolation material layer and exposes at least a portion of the top surface of the second contact pad.

[0176] The first isolation material layer 701 and the second isolation material layer 702 constitute an isolation layer 7 , wherein the second contact pad 8 is located in the isolation layer 7 , and at least a portion of the second contact pad 8 is used to connect the connecting plug 4 to the second capacitor 202 .

[0177] After forming the second contact pad 8, for example, an atomic layer deposition process (ALD) can be used to deposit a second isolation material layer 702 covering the first isolation material layer 701 and the second contact pad 8, and then a planarization process such as chemical mechanical polishing (CMP) is used to remove a portion of the second isolation material layer 702 to expose the top surface of the second contact pad 8. At this time, the top surface of the formed second contact pad 8 is flush with the top surface of the isolation layer 7, and the top surface of the second contact pad 8 is completely exposed.

[0178] For another example, after forming the second isolation material layer 702, the second isolation material layer 702 in the area where the second contact pad 8 is located can be removed by a patterned etching process, and a portion of the top surface of the second contact pad 8 is exposed. In this embodiment, the top surface of the formed second contact pad 8 is lower than the top surface of the isolation layer 7. Therefore, the isolation layer 7 in the area above the top surface of the second contact pad 8 can play a good isolation role for the adjacent second contact pads 8, thereby avoiding problems such as short circuits between the second contact pads 8.

[0179] In this embodiment, the first isolation material layer 701 can provide good electrical isolation for the adjacent first capacitor 201, and the second isolation material layer 702 can provide good electrical isolation for the adjacent second contact pad 8. In addition, the conductive material layer 21 is used to form both the contact plug 4 and the second contact pad 8, thereby simplifying the manufacturing process of the semiconductor structure and improving production efficiency.

[0180] The various embodiments or implementation methods in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referenced to each other.

[0181] In the description of this specification, reference to the terms "embodiment", "exemplary embodiment", "some embodiments", "illustrative embodiment", "example", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure.

[0182] In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0183] In the description of the present disclosure, it should be noted that the terms "center", "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0184] It is to be understood that the terms "first", "second", etc. used in the present disclosure can be used to describe various structures in the present disclosure, but these structures are not limited by these terms. These terms are only used to distinguish a first structure from another structure.

[0185] In one or more of the accompanying drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown. For the sake of simplicity, the structure obtained after several steps can be described in one figure. Many specific details of the present disclosure, such as the structure, materials, dimensions, processing technology and technology of the device are described below to more clearly understand the present disclosure. However, as those skilled in the art will appreciate, the present disclosure may not be implemented in accordance with these specific details.

[0186] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A semiconductor structure, It is characterized in that The semiconductor structure comprises: A substrate, on which a first contact pad is disposed, wherein the first contact pad includes a first type of contact pad and a second type of contact pad; A storage structure is arranged on the substrate, the storage structure comprises a first capacitor and a second capacitor which are stacked, wherein a connection plug is arranged between adjacent first capacitors, the first capacitor is connected to the first type of contact pad, and the second capacitor is connected to the second type of contact pad through the connection plug; A cross-sectional area of ​​the connecting plug is smaller than a cross-sectional area of ​​the first capacitor.

2. The semiconductor structure according to claim 1, It is characterized in that Projections of the first capacitor and the second capacitor on the substrate are arranged staggered or alternately.

3. The semiconductor structure according to claim 1, It is characterized in that The first contact pads are arranged in an array, In a row of first contact pads, at least one second-type contact pad is disposed between adjacent first-type contact pads; In a column of first contact pads, at least one second-type contact pad is disposed between adjacent first-type contact pads.

4. The semiconductor structure according to claim 1, It is characterized in that The storage structure further includes a first conductive layer covering the first capacitor and the connection plug, and a second conductive layer covering the second capacitor, wherein the first conductive layer and the second conductive layer are in contact at the outermost peripheries of the first capacitor and the second capacitor.

5. The semiconductor structure according to claim 1, It is characterized in that An isolation layer is provided between the first capacitor and the second capacitor, a second contact pad is provided in the isolation layer, and at least a portion of the second contact pad connects the connection plug to the second capacitor.

6. The semiconductor structure according to claim 5, It is characterized in that The top surface of the second contact pad is flush with the top surface of the isolation layer; or, The top surface of the second contact pad is lower than the top surface of the isolation layer. An opening is provided at a position of the isolation layer corresponding to the second contact pad, and at least a portion of the top surface of the second contact pad is exposed through the corresponding opening.

7. The semiconductor structure according to any one of claims 1 to 6, It is characterized in that The aspect ratio of the first capacitor and the second capacitor is 16-32; and / or, The first capacitor and the second capacitor have the same height; and / or, The heights of the first capacitor and the second capacitor are both 800-1080 nm; The diameters of the first capacitor and the second capacitor are both 40-75 nm.

8. A method for manufacturing a semiconductor structure, It is characterized in that The method for manufacturing the semiconductor structure comprises: Providing a substrate, on which a first contact pad is disposed, wherein the first contact pad includes a first type of contact pad and a second type of contact pad; Forming a first capacitor and a second capacitor stacked in sequence on the substrate, wherein a connecting plug is provided between adjacent first capacitors, the first capacitor is connected to the first type of contact pad, and the second capacitor is connected to the second type of contact pad through the connecting plug; A cross-sectional area of ​​the connecting plug is smaller than a cross-sectional area of ​​the first capacitor.

9. The method according to claim 8, It is characterized in that The first contact pads are arranged in an array, at least one second contact pad is disposed between adjacent first contact pads, and the first capacitor and the second capacitor stacked in sequence are formed on the substrate, comprising: forming a first capacitor on the substrate in contact with the first type of contact pad; forming a first conductive layer covering the first capacitor; forming a through hole in the first conductive layer, wherein the through hole exposes a top surface of the second-type contact pad; forming the connecting plug in the through hole, wherein the bottom end of the connecting plug contacts the second-type contact pad; forming the second capacitor on the first capacitor, wherein the second capacitor is connected to the connection plug; A second conductive layer covering the second capacitor is formed, and the second conductive layer and the first conductive layer are in contact at the outermost peripheries of the first capacitor and the second capacitor.

10. The method according to claim 9, It is characterized in that Before forming the connecting plug in the through hole, the manufacturing method further includes: forming a first isolation material layer on the first conductive layer, wherein the first isolation material layer covers the sidewalls of the through hole and the top surface of the first conductive layer; The connecting plug is formed in the through hole, comprising: forming a conductive material layer on the first isolation material layer, wherein the conductive material layer covers the top surface of the first isolation material layer and fills the space enclosed by the first isolation material layer in the through hole, and the first isolation material layer and the conductive material layer in the through hole constitute the connecting plug; Before forming the second capacitor on the first capacitor, the manufacturing method further includes: Patterning the conductive material layer covering the top surface of the first isolation material layer to form a second contact pad; A second isolation material layer is formed, wherein the second isolation material layer covers the first isolation material layer and exposes at least a portion of the top surface of the second contact pad, and the first isolation material layer and the second isolation material layer constitute an isolation layer, wherein: The second contact pad is located in the isolation layer, and at least a portion of the second contact pad is used to connect the connecting plug to the second capacitor.

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