48results about How to "Reduce the number of capacitors" patented technology

The invention discloses a single-phase circuit topology structure used for a suppressing-typed convertor with multilevel and belongs to the electric and electronic technical field of the convertor with multilevel. The single-phase circuit topology structure is characterized in that a DC side is provided with three capacitors, the capacitors close to the DC side have a voltage of 4Vdc while the capacitor at the middle has a voltage of 2V dc; four diode suppressed parts are arranged at an input side and a capacitor suppressed part is arranged at an output side; through the adoption of the combination of switches, each switch has 1V dc voltage and five electric output levels can be obtained. The single-phase circuit topology structure of the invention has the advantages of much simplified structure and low voltage withstanding capacity and direct connection in series can occur in the circuit without involving with other elements and has no problem of synchronous connection and disconnection.

The invention relates to an automobile composite energy storage start-stop system capable of recycling braking energy. The system comprises a storage battery, a motor subsystem, a super capacitor and a two-way buck converter. The motor subsystem comprises a motor and a motor controller. When an automobile performs braking, the automobile start-stop system can recycle and regenerate the braking energy. When the motor operates as a starter, namely a BSG mode, the motor controller can output electric energy in a two-way mode, an engine is started depending on the motor subsystem, electric energy of the super capacitor flows toward the motor subsystem, the motor controller works in an inversion state, and the motor outputs mechanical energy in an electric operation mode. According to the system, the super capacitor takes charge of a large-current discharge function needed for starting the engine, and large-current discharge of the storage battery is not needed, so that service life of the storage battery is greatly prolonged. In addition, due to the fact that the storage battery does not have the large-current discharge state, voltage is more stable and response time is shorter.

The invention discloses a medium-voltage capacitive energy storage welding machine, which comprises a three-phase power source, a step-up transformer, a three-phase rectifier module, an energy storage module and a welding transformation module, wherein the step-up transformer is connected with three-phase alternate current to perform step-up treatment on input alternate current; the three-phase rectifier module is connected with the step-up transformer and the energy storage module respectively; the alternate current which is stepped up is rectified into direct current by the three-phase rectifier module and is charged to the energy storage module; the voltage value of the direct current is 500-1,000V; the energy storage module comprises a plurality of energy storage capacitors; the energy storage capacitors are metal thin film non-polar capacitors, and the withstand voltage of the energy storage capacitors is more than 1,000V; and the welding transformation module is connected with an output end of the energy storage module. The medium-voltage capacitive energy storage welding machine provided by the invention is safe in operation and is cost-saving.

The invention relates to the simulation integrated circuit design field and provides a switching strategy for a successive approximation register digital-to-analogue converter (SAR ADC) based on charge discharge and three-level reference voltage, greatly reduces dynamic power consumption of capacitor discharge of a DAC module in the SAR ADC because of switch switching and can dramatically reduce integral SAR ADC power consumption. The technical scheme of the digital-to-analogue conversion module is that: the digital-to-analogue conversion module for SAR ADC is connected to upper polar plates of all capacitors of the anode end of DAC and upper polar plates of all capacitors of the cathode end of the DAC through a switch S1 and a switch S2; the upper polar plates of the capacitors of the DAC anode end are connected to an input terminal of a comparator and are connected to a switch S3 at the same time; and the output terminal of the comparator is connected to input of a logical module; and output of the logical module controls switching-on and switching-off of a DAC switch. The digital-to-analogue conversion module is mainly used in a simulation integrated circuit design manufacture occasion.

The invention discloses an alternating-current side cascaded hybrid MMC topology resistant to alternating-current and direct-current faults and a control method thereof, and belongs to the field of power transmission and distribution of power systems. The alternating-current side cascaded hybrid MMC topology is composed of a direct-current side main branch and an alternating-current side auxiliarybranch, and the main branch is composed of half-bridge type sub-modules and used for power transmission during normal operation of a system; and the auxiliary branch is formed by cascading full-bridge sub-modules on the alternating current side, and is used for operation optimization in a steady state of the system and voltage support in alternating current and direct current fault ride-through.During steady-state operation, the auxiliary branch outputs the finer voltage to smooth the step wave voltage output by the main branch of the low sub-module, so that the grid-connected point voltageis closer to sine waveform; when a DC fault occurs, the main branch bypasses part of the half-bridge sub-modules in the bridge arm to suppress a DC fault current, and the auxiliary branch supports a grid-connected point AC voltage. When an alternating-current fault occurs, the auxiliary branch outputs an alternating-current voltage with a certain phase and amplitude so as to reduce the voltage ofa grid-connected point and suppress an alternating-current fault current.

The invention discloses a modular multilevel high-power alternating-current/alternating-current converter based on a high-frequency transformer. The converter comprises a first bridge arm, a second bridge arm and a third bridge arm, and each of the first bridge arm, the second bridge arm and the third bridge arm is formed by cascading n sub-modules, wherein each sub-module includes two H-bridge converters, a high-frequency transformer and a cycle converter which are connected in sequence. The converter has a modular design, is easy to expand, and has good output voltage waveform quality, no loop current, high power density and low cost, and has advantages of few bridge arms, a small IGBT total capacity, a small capacitor number and a high direct current voltage minimum harmonic component frequency.

The invention provides a capacitive touch sensor. A single sensing unit structure of the capacitive touch sensor is triangular, and is composed of an upper polar plate, a lower polar plate and a dielectric layer. The upper polar plate and the lower polar plate are correspondingly arranged; the upper polar plate comprises three first polar plates, the lower polar plate comprises three second polarplates, the first polar plates and the second polar plates are isosceles triangles with vertex angles of 120 degrees, the vertex angles of the three first polar plates are oppositely arranged, top ends of the three second polar plates are connected with one another, and the three first polar plates and the three second polar plates jointly form three independent capacitors; and through a structural arrangement, the number of polar plates and the number of capacitors are reduced, and a measurement circuit is greatly simplified so that accurate measurement and decoupling of a three-dimensional force are realized.

The invention provides a method for reducing radiation intensity between a chip and a memory. The method specifically comprises the following steps of equally dividing multiple data lines into M firstsignal line groups according to a data bit sequence; equally dividing multiple instruction lines and multiple address lines into N second signal line groups according to instruction bit and address bit sequences; transmitting instruction signals and address signals to the memory according to a sequence of the second signal line groups through the N second signal line groups by the chip, wherein each group of second signal lines have a transmission interval of first predetermined time; and transmitting data to the memory according to a sequence of the first signal line groups through the M first signal line groups by the chip, wherein each group of first signal lines have a transmission interval of second predetermined time. The technical scheme has the beneficial effects that the demand of a high-frequency current of a power end can be reduced, a capacitor quantity of a power part of the memory is reduced, and excessive transient current is avoided.

Provided are a charge pump device and a control method of the charge pump device. The charge pump device comprises a first-stage charge pump circuit and a second-stage charge pump circuit. The first-stage charge pump circuit is suitable for outputting a first-stage voltage according to input voltages, according to the voltage value Vout1 of the first-stage voltage, Vout1= m*Vin, and Vin is the voltage value of the input voltage of the first-stage charge pump circuit. The second-stage charge pump circuit is suitable for generating a second-stage first voltage and a second-stage second voltage according to the first-stage voltage, according to the voltage value Vout21 of the second-stage first voltage, Vout21=(p+m)*Vin, according to the voltage value Vout22 of the second-stage second voltage, Vout22=(q-m)*Vin, and m, q and p are arbitrary numbers.

The invention relates to a five-level clamping cross type sub-module topological structure of a modular multilevel converter, and belongs to the technical field of flexible direct-current power transmission. The MMC sub-module topology comprises an MMC sub-module topology, the MMC sub-module topology comprises sub-module output ends, the sub-module output ends are a voltage anode output end and a voltage cathode output end, the MMC sub-module topology further comprises a left half-bridge and a right half-bridge which are the same in structure, and the two half-bridges are connected through a power switch group S7 and a power switch group S8 which are crossed. The method has the rapid DC fault clearing capability, an AC switch does not need to be tripped off, the problems of capacitor voltage divergence possibly caused by long-time locking and action of an AC circuit breaker are avoided, and the non-locking mode is beneficial to rapid recovery of stable operation after the MMC breaks down.

The invention discloses a hundred-nanosecond-level trapezoidal wave pulse forming network and a design method. The network circuit structure comprises a shaping inductor and no more than three LC series branches, and the LC series branches are connected in parallel and then connected to the shaping inductor in series. The capacitor is a pulse film inductor; and capacitance and inductance values are determined through a predetermined method. The design method comprises the steps of building a network circuit structure and determining an initial value of a component, simulating the circuit, and adjusting the parameters of the component according to the output waveform of the circuit. The network structure is simple, the network level is low, the output waveform quality is good, and the research on the high-power microwave technology is facilitated. The design steps are high in operability and wide in application range. The miniaturization of the pulse device can be realized, and the service life of the network is greatly prolonged.

The invention provides a half-bridge modular multi-level single-phase inverter and a modulation method. The half-bridge modular multi-level single-phase inverter comprises a capacitor bridge arm and amodular multi-level bridge arm, the modular multi-level bridge arm comprises a two-port sub-module and a multi-port sub-module, each of the capacitor bridge arm and the modular multilevel bridge armcomprises a direct-current positive end point, a direct-current negative end point and an alternating-current end point; the direct-current positive electrode end point of the capacitor bridge arm isconnected with the direct-current positive electrode end point of the modular multi-level bridge arm and is connected with the positive electrode of the direct-current power supply; the direct currentnegative terminal of the capacitor bridge arm is connected with the direct current negative terminal of the modular multilevel bridge arm and is connected with the negative electrode of the direct current power supply; the alternating-current endpoints of the capacitor bridge arms and the alternating-current endpoints of the modular multilevel bridge arms jointly form an alternating-current output port of the single-phase inverter. According to the novel nearest level approximation modulation strategy provided for the topology, accurate topology output can be achieved, and effective work of the system is maintained.

The invention relates to a power supply circuit and an electronic device. The power supply circuit comprises N power supply modules, N first switch modules and a first capacitor module, and the powersupply modules are used for providing power supply signals. The first end of each first switch module is correspondingly connected with one power supply module. The first end of the first capacitor module is connected with the second ends of the N switch modules, and the second end of the first capacitor module is grounded, wherein N is an integer greater than or equal to 2. The first switch module is conducted in response to the first control signal, to transmit the power signal of the corresponding power module to the first end of the first capacitor module, and the first switch module is turned off in response to the second control signal to isolate the corresponding power module from the first capacitor module, so that the wiring space on the mainboard of the electronic device can be saved.

The present invention discloses a capacitance error measurement circuit, a measurement method, a chip and a household electrical appliance, the capacitance error measurement circuit comprising: a comparator, the first input end of which is configured to input an analog signal and the second input end of which is connected to a correction signal line and is configured to input a correction signal;a first capacitor matrix which comprises a plurality of first capacitors, wherein one ends of the plurality of first capacitors are connected with the correction signal line, and the other end of at least one first capacitor is configured to receive a reference signal and input a correction signal to the correction signal line; a second capacitance matrix, wherein one end of the second capacitancematrix is connected with the correction signal line, and the other end of the second capacitance matrix is configured to receive the reference signal, change the total capacitance value of the secondcapacitance matrix and adjust the correction signal; and a controller which is connected with the output end of the comparator and the second capacitor matrix, and is configured to determine the total capacitance value of the second capacitor matrix when the output signal of the comparator is reversed, and determine the error of the capacitor to be measured according to the total capacitance value. In this way, capacitance error measurement can be achieved.

The invention relates to the field of neural networks, in particular to a digital-analog hybrid neuron circuit, and aims to solve the problem that a large amount of time and energy are consumed duringdata access in the prior art. The circuit comprises an input layer circuit, a plurality of convolution layer circuits and an output layer circuit, wherein the input layer circuit comprises a data memory, a D/A conversion circuit and a weight memory; the data memory is used for storing multi-bit activation values; the D/A conversion circuit is used for converting the activation value of the digital quantity into an analog quantity; the weight memory is used for storing binary weight values in one-to-one correspondence with the activation values; the convolution layer circuits are used for performing multiple convolution operations based on the activation value of the analog quantity and the binary weight value corresponding to the activation value to obtain an analog voltage value; and theoutput layer circuit is used for outputting the digital quantity of the analog voltage value. According to the method, the data value is converted into the analog quantity before the convolution operation, and the activation value participates in the convolution operation with the analog quantity, so the problems of time delay and energy consumption during data access are solved.