Capacitance error measurement circuit, measurement method, chip and household electrical appliance

Abstract

The present invention discloses a capacitance error measurement circuit, a measurement method, a chip and a household electrical appliance, the capacitance error measurement circuit comprising: a comparator, the first input end of which is configured to input an analog signal and the second input end of which is connected to a correction signal line and is configured to input a correction signal;a first capacitor matrix which comprises a plurality of first capacitors, wherein one ends of the plurality of first capacitors are connected with the correction signal line, and the other end of at least one first capacitor is configured to receive a reference signal and input a correction signal to the correction signal line; a second capacitance matrix, wherein one end of the second capacitancematrix is connected with the correction signal line, and the other end of the second capacitance matrix is configured to receive the reference signal, change the total capacitance value of the secondcapacitance matrix and adjust the correction signal; and a controller which is connected with the output end of the comparator and the second capacitor matrix, and is configured to determine the total capacitance value of the second capacitor matrix when the output signal of the comparator is reversed, and determine the error of the capacitor to be measured according to the total capacitance value. In this way, capacitance error measurement can be achieved.

Description

technical field [0001] The present application relates to the technical field of capacitance error measurement, in particular to a capacitance error measurement circuit, a measurement method, a chip and household appliances. Background technique [0002] SAR ADC (successive approximation register analog to digital converter, successive approximation analog-to-digital converter) is a commonly used data converter with a medium sampling rate (up to about 15MSPS) and medium resolution (up to about 18 bits). These structures are efficient and easy to understand. Unlike pipelined ADCs, the SAR architecture has no latency. The relatively high sampling rate and zero latency make SAR ADCs suitable for multiplexed data acquisition. [0003] Because of its high speed, high precision and low power consumption, SAR ADC has been widely used in industry. In order to reduce power consumption, modern SAR ADCs use a capacitor matrix structure. In order to reduce the area of ​​the capacito...

AI Technical Summary

Problems solved by technology

Due to the deviation of the production process, there is a certain error

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