87 results about "Capacitance ratio" patented technology

The invention relates to the technical field of on-line monitoring, in particular to an insulation fault on-line monitoring method and system for a medical IT system control cabinet. The method comprises the following steps: selecting a non-integer frequency multiplication detection frequency according to equivalent ground distributed capacitance in a previous monitoring period, and superposing the non-integer frequency multiplication detection frequency with a fundamental frequency to form a composite signal injection system; collecting signals to calculate a voltage instantaneous harmonic distortion rate change gradient, and selecting a time window to split the leakage current according to the change gradient; on the basis of dispersion estimation signal-to-noise ratio weighted fusion current vectors, insulation resistance and distributed capacitance are calculated; constructing a four-dimensional original feature vector composed of the insulation parameter, the phase difference and the intermodulation component energy; constructing a diagonal weighting matrix based on the resistance-capacitance ratio and the gradient to transform a feature vector, and determining the fault attribution through the Mahalanobis distance calculation with the fault template library. According to the scheme, harmonic interference can be avoided, calculation stability can be improved, insulation instantaneous sudden change can be quickly responded, and different fault types can be accurately distinguished to guide maintenance.

The invention discloses a peak current sampling circuit suitable for a DC / DC converter with a wide load range, and belongs to the field of switching power supply DC / DC converter control. The circuit comprises a power PMOS switch tube P1, a power NMOS tube N1, an inductor L1, a sensing resistor RS, a sensing capacitor CS, an output capacitor COUT, divider resistors RFB1 and RFB2, a sampling circuit, a low-pass filter, a differential amplifier, an adder / subtractor, a transconductance amplifier, a compensation resistor RC, a compensation capacitor CC, a PWM comparator, a slope compensation circuit, an oscillator, an RS trigger and a logic and driving circuit. An equivalent series resistor DCR of an inductor is utilized, and a low-pass RC sensing network is connected to two ends of the inductor in parallel to sense an inductive current, so that power consumption caused by a traditional sampling resistor RSENSE is eliminated, and the efficiency of the DC / DC converter is improved; through reasonable arrangement of the values of the sensing resistor RS and the sensing capacitor CS and an internal signal processing circuit, an inductance ripple current signal is amplified on the basis of retaining the inductance average current, the sampling signal-to-noise ratio is improved, and noise interference is reduced.

The invention discloses a control method of a multi-branch energy storage system and a terminal. The control method comprises the following steps: acquiring the number of sub energy storage systems in an energy storage architecture and rated output power of each sub energy storage system; detecting required power, and distributing planned output power according to the capacitance ratio of each sub energy storage system; detecting whether the sub energy storage systems with the planned output power greater than or equal to the rated output power exist or not, and if yes, calculating to obtain additional complement power according to the number of the sub energy storage systems and the rated output power; and controlling the sub-energy storage systems with the rated output power greater than the planned output power to provide additional complement power. According to the method, the power supply capabilities of the sub energy storage systems are compared and analyzed, the sub energy storage systems which cannot meet the power supply requirements are screened out, and other sub energy storage systems are arranged to additionally complement the deficient parts, so that disordered power regulation and control among multiple branch energy storage systems under one EMS system is avoided, and orderly power supply regulation of the multiple sub energy storage systems is realized.

The utility model discloses a 2b / cycle successive approximation analog-to-digital converter of double comparators. The digital-to-analog converter comprises a DAC module, a comparator module, a recoding module and a successive approximation logic module, the DAC module comprises a main DAC capacitor array and an auxiliary DAC capacitor array, the main DAC capacitor array comprises a main quantization capacitor and a main C0 capacitor, the auxiliary DAC capacitor array adopts a differential structure to generate reference voltage, the auxiliary DAC capacitor array comprises an auxiliary capacitor and an auxiliary C0 capacitor, and the auxiliary C0 capacitor is used for generating reference voltage. The comparator module is composed of a comparator CMP1, a comparator CMP2 and two NOR gates, the comparator CMP1 is connected with the main DAC capacitor array, and the comparator CMP2 is connected with the main DAC capacitor array. The SAR ADC has the advantages of playing an important role in improving the linearity of the ADC, reducing the power consumption and the area of the SAR ADC, ensuring the stability of an asynchronous time sequence, having higher linearity and lower power consumption, realizing analog-to-digital conversion of high-speed data, and improving the conversion accuracy.

A semiconductor structure is provided that includes a tunable and shared non-conductive layer as part of a gate stack of at least a pair of nanosheet GAA transistors with a shared metal gate electrode. The semiconductor structure has a tunable non-conductive material / gate dielectric area ratio where the non-conductive material is not constrained to a periphery of the nanosheet stack cross section.

An image sensor includes a pixel-circuit and circuitry. The pixel-circuit includes a PD that accumulates charge responsively to incident light and a FD that stores the charge. The circuitry serially (i) connects the PD and a supply rail to the FD and sends a first FD voltage, (ii) disconnects the supply rail from the FD and sends a second FD voltage, (iii) disconnects the PD from the FD and sends a third FD voltage, (iv) waits a preset exposure time, (v) connects the supply rail to the FD and sends a fourth FD voltage, (vi) disconnects the supply rail from the FD and sends a fifth FD voltage, and (vii) connects the PD to the FD and sends a sixth FD voltage. The circuitry estimates incident light energy responsively to (i) the FD voltages, and (ii) a capacitance ratio defined over at least capacitances of the FD and the PD.

The invention relates to a circuit board backdrill capacitance testing method, device and equipment and a storage medium, and the method comprises the steps: obtaining a capacitance detection instruction, and obtaining the image information of a to-be-detected circuit board according to the capacitance detection instruction; carrying out clustering analysis on the image information of the to-be-detected circuit board by adopting a k-means algorithm to obtain a feature image of the to-be-detected circuit board, and carrying out analysis according to the feature image to obtain a displacement distance and an angle of the probe; adjusting the position of the probe according to the displacement distance and the angle of the probe, and generating a capacitance measurement message after the adjustment of the probe is completed; according to the capacitance measurement message, calculating a capacitance value of the circuit board to be detected through a capacitance method, and comparing the capacitance value of the circuit board to be detected with a preset capacitance value to obtain a capacitance comparison result; and generating a quality evaluation result of the back drilling hole of the circuit board according to the capacitance comparison result, and transmitting the quality evaluation result of the back drilling hole of the circuit board to the user side. The method has the effect of improving the precision and efficiency of back drilling hole quality detection.

In accordance with some embodiments of the present disclosure, an analog-to-digital-converter (ADC) is provided. The ADC may include a capacitive DAC (CDAC), a comparator, and a successive approximation register (SAR) logic configured to control the CDAC and the comparator to perform a successive approximation conversion of an analog input into a digital output signal. The CDAC includes a plurality of unary-weighted capacitors having the same capacitor value and a plurality of binary-weighted capacitors. In some embodiments, the CDAC includes a first capacitor array and a second capacitor array. Each of the first capacitor array and the second capacitor array may include a plurality of unary-weighted capacitors and a plurality of binary-weighted capacitors.

The invention discloses a switched capacitor circuit, a signal receiving chip and an Ethernet transceiver. The switched capacitor circuit comprises a first group of capacitors, a second group of capacitors, a third group of capacitors, a fully differential operational amplifier and a switch assembly. According to the technical scheme, on one hand, the switched capacitor circuit is controlled under the external clock signal to achieve the alternating process of the sampling phase state and the amplification phase state, a negative feedback loop is formed in the amplification phase state, and the frequency response and amplitude balance of the signal are ensured through the negative feedback loop. And on the other hand, compared with a traditional linear equalizer, the transfer function of the switched capacitor circuit in the technical scheme is only related to the capacitance ratio theoretically and is not easily influenced by process deviation, power supply voltage or temperature change, so that stable equalization frequency range and equalization strength are achieved, the stability of equalization capability is ensured, and the service life of the equalizer is prolonged. And the method is applied to an Ethernet receiving channel to omit CTLE, so that the structural design can be simplified.

The invention discloses a variable capacitance diode with a large variable capacitance ratio and a preparation method thereof in the field of variable capacitance diodes. The variable capacitance diode sequentially comprises an N + type substrate, an N-type epitaxial layer, an oxide layer and a passivation layer from bottom to top, wherein the back surface of the N + type substrate is provided with a back surface metal electrode; the main junction region is arranged in the middle of the N-type epitaxial layer, and the main junction region is provided with a doped N region and a doped P region from bottom to top; a plurality of vertical grooves are formed in the N-type epitaxial layer, the vertical grooves are located on the outer side of the main junction region, and polycrystalline silicon is filled in the vertical grooves; the oxide layer is provided with a window of a main junction region; the passivation layer comprises a glass layer and a Si3N4 layer which are sequentially arranged from bottom to top; and a front metal electrode and an electroplated layer are sequentially arranged above the main junction region from bottom to top. The variable capacitance diode has a large capacitance ratio, a good C-V curve and low parasitic capacitance and series resistance. And the variable capacitance diode is high in reliability and long in service life.

Aspects of the embodiments disclosed herein include electrical systems that reduce crosstalk, such as far-end crosstalk (FEXT) between two or more signal paths of a memory system by electromagnetically coupling the two or more signal paths each comprising a respective trace. Electromagnetically coupling the two or more respective traces includes positioning at least two traces in close proximity with each other such that a mutual-to-self-inductance ratio (Lm / L) between the at least two signal paths matches or substantially matches the mutual-to-self-capacitance ratio (Cm / C) of the at least two signal paths. Certain embodiments of this disclosure are directed to a passive manner of reducing FEXT between any number of signal paths without adding traces with the sole purpose of reducing crosstalk, thereby reducing or maintaining a signal density between designs of a component of an IC package.

A method comprises discharging electrical energy from an intermediate circuit comprised in the apparatus, measuring a direct current voltage, and inputting measured values to a parameter estimator for the intermediate circuit. The parameter estimator comprises at least a first parameter and a second parameter whose values are determined based on an equivalent capacitance value of the intermediate circuit, an equivalent resistance value of the intermediate circuit and an electrical load power value of the intermediate circuit, the parameter estimator outputting values for time constant and values for power-to-capacitance ratio of the intermediate circuit. The method further comprises storing values at least temporarily for condition monitoring.

The invention relates to the technical field of semiconductor integrated circuits, in particular to a high-voltage LDO (Low Dropout Regulator) power supply circuit which comprises an output Vout, an overshoot optimization module, an MOS (Metal Oxide Semiconductor) tube MP2 and a transient optimization module, the transient optimization module comprises a transconductance amplifier A2, a capacitor C3, a comparator A3, a transient suppression sub-module and a transient recovery sub-module; one end of the capacitor C3 is connected to the output Vout; the other end of the capacitor C3 is connected to the positive input end of the transconductance amplifier A2; the output end of the transconductance amplifier A2 is connected with the positive input end of the comparator A3; the negative input end of the transconductance amplifier A2 is grounded; the negative input end of the comparator A3 is connected with reference current Iref; the input end of the transient suppression sub-module and the input end of the transient recovery sub-module are respectively connected with the output end of the comparator A3; the output end of the transient suppression sub-module and the output end of the transient recovery sub-module are respectively connected with the grid electrode of the MOS tube MP2; and the transient response performance and reliability are improved.

The application relates to the technical field of metrological calibration, and discloses a multi-voltage-grade capacitor current tester calibration method based on unified transformation ratio. The method comprises the following steps: screening unified transformation ratio parameters meeting range constraints and error constraints, obtaining a ratio difference parameter of a corresponding electromagnetic voltage transformer, obtaining a capacitance ratio difference correction factor, calculating conversion coefficients under each voltage grade, determining a primary side capacitance setting value according to a preset primary side calibration capacitance value and the conversion coefficients, obtaining a secondary side output capacitance value of a standard capacitance tank, and collecting a displayed capacitance value and a displayed capacitance current value. The conversion coefficients between the unified transformation ratio and the theoretical transformation ratios of each voltage grade are established, single transformation ratio is used to cover multi-voltage-grade calibration, error components introduced by the ratio difference of the electromagnetic voltage transformer in the capacitance calibration process are reduced, and different transformation ratio equipment needs to be frequently replaced.

A power supply modulator and a wireless communication device including the same are provided. The supply modulator is configured to provide a supply voltage for the power amplifier. The power supply modulator includes: a converter configured to output the power supply voltage to a power amplifier; the switch is connected to the first capacitor and the second capacitor, the first end of the first capacitor is connected to the converter, the second end of the first capacitor is connected to the switch, the first end of the second capacitor is connected to the converter, and the second end of the second capacitor is connected to the ground and the switch; the capacitance of the second capacitor is smaller than that of the first capacitor; and a driver connected to the switch, the driver configured to turn off the switch based on occurrence of a transition of the supply voltage.

The application provides a capacitor array applied to a SAR auxiliary ramp ADC, an analog-to-digital converter and a conversion method, and belongs to the technical field of integrated circuits. The capacitor array comprises a first output end, a second output end, a first bridge capacitor, a second bridge capacitor, a first SAR capacitor subarray, a second SAR capacitor subarray, a low-bit SAR capacitor, a first to third ramp capacitor subarray and a fixed level capacitor subarray. Each capacitor is connected to a switch network through a specific connection relationship, and the capacitance ratio between each SAR capacitor and the capacitance ratio between the low-bit SAR capacitor and the bridge capacitor and the unit capacitor are configured to form a non-binary weight relationship. The application also provides a conversion method based on the capacitor array. By adopting a segmented capacitor structure and a non-binary weight design, the application can significantly reduce the capacitor array area, reduce the switch power consumption and comparator load, speed up the establishment time, and improve the linearity of the CDAC, thereby improving the overall performance of the ADC in speed, area and power consumption.

This application relates to the field of power electronics technology and discloses a method, device, equipment, and storage medium for detecting the aging of DC capacitors in a three-level inverter. The method includes: obtaining a simplified topology model of the three-level inverter; based on the working principle of the three-level inverter, controlling the midpoint current to zero by injecting a zero-sequence voltage into the three-phase reference voltage; under the state of midpoint potential balance, monitoring a first current and a second current using the correlation between capacitor current and capacitance value, calculating the current ratio of the first current and the second current, and deriving the capacitance ratio of the first capacitor and the second capacitor based on the current ratio; and identifying the aging state of the capacitor online based on the capacitance ratio. The device, equipment, and storage medium all correspond to this method. This application achieves online aging identification of capacitors by monitoring the current changes of the upper and lower DC capacitors of a three-level inverter, under the premise that the midpoint potential balance of the three-level inverter is controlled.

A 2-bit fast flash analog-to-digital converter circuit and related methods designed for use with multi-level converters in particular to achieve: high conversion speed, high resolution, small layout area, low power, and the ability to meet the requirements for properly balancing fly capacitor voltages. One embodiment includes a voltage input configured to be coupled to a multi-level converter fly capacitor; a comparator coupled to the voltage input and a first reference voltage input and having a first binary output indicating whether the input voltage is higher or lower than a voltage on the first reference voltage input; and a circuit coupled to the voltage input and to second and third reference voltage inputs, the circuit configured to provide a second binary output indicating whether the input voltage is inside or outside a voltage window defined by respective voltages on the second reference and third reference voltage inputs.

The application discloses a method for measuring error of low-frequency voltage transformer under high voltage by using standard capacitor, which comprises the following steps: connecting the measured low-frequency voltage transformer and low-frequency standard voltage transformer into a difference loop under preset low voltage to measure low-voltage ratio error and low-voltage phase error; introducing high-voltage standard capacitor and low-voltage standard capacitor under preset high voltage to connect with the measured low-frequency voltage transformer into an equal power loop to measure first capacitor ratio and first dielectric loss and second capacitor ratio and second dielectric loss; measuring high-voltage capacitor voltage coefficient, high-voltage dielectric loss voltage coefficient, low-voltage capacitor voltage coefficient and low-voltage dielectric loss voltage coefficient by using comparison method; measuring low-voltage capacitor ratio measurement error, low-voltage dielectric loss measurement error, high-voltage capacitor ratio measurement error and high-voltage dielectric loss measurement error by using capacitor rotation method; and calculating high-voltage ratio error and high-voltage phase error of the measured low-frequency voltage transformer under preset high voltage according to the above parameters.

The invention provides a temperature sensor, a circuit system and electronic equipment, and the system comprises a temperature voltage generation module which is used for temperature detection voltage; the temperature voltage comparator is used for comparing a first voltage and an analog voltage and outputting a comparison result signal, and the first voltage is equal to the sum of the temperature detection voltage and the input offset voltage of the temperature voltage comparator; the input offset voltage and the temperature detection voltage are both in direct proportion to the temperature to be detected, the load capacitance ratio of the input offset voltage and the temperature voltage comparator is in a logarithmic linear relation, and input geminate transistors in the temperature voltage comparator work in a sub-threshold region; the N-bit logic control module is used for outputting a corresponding temperature detection digital signal according to the comparison result signal; and the N-bit digital-to-analog conversion module is used for outputting a corresponding analog voltage according to the temperature detection digital signal, the temperature detection digital signal after N times of comparison is used for representing a first voltage, and the first voltage is used for representing the temperature to be detected.

The invention discloses a method and system for improving the linearity of an ADC, and relates to the technical field of analog-to-digital conversion, and the method comprises the steps: calibrating and recording capacitance ratio mismatch information, creating a correction table, and generating a correction coefficient; implementing a correction algorithm and dynamically adjusting a correction coefficient; the temperature of the working environment of the ADC is monitored in real time, a temperature compensation algorithm is implemented, and the influence of the temperature on the capacitor performance is compensated. According to the method, the accuracy of the subsequent correction process is ensured, the problem of capacitance ratio mismatch is solved in a targeted manner, ADC linearity errors caused by capacitance inconsistency are reduced, the initial linearity of the ADC is improved, the ADC can better adapt to the change of signal amplitude, high linearity is maintained, nonlinear errors are reduced, and the accuracy of the ADC is improved. According to the invention, the overall conversion precision of the ADC is improved, the influence of temperature on the performance of the capacitor is compensated, the capacitance change caused by temperature fluctuation is reduced, the linearity of the ADC is stabilized, and high-precision conversion under different temperature conditions is ensured.

According to certain embodiments, a microelectromechanical system (MEMS) device has a MEMS mirror structure with a rotatable mirror. Rotation of the mirror produces a change in measured capacitance corresponding to the angle of rotation. The MEMS structure is located on an oxide layer deposited on a substrate. A parasitic capacitance exists between the MEMS mirror structure and the substrate. An additional capacitance is provided between the substrate and a DC voltage source. The additional capacitance is much larger than the parasitic capacitance and shunts the parasitic capacitance to ground to minimize its effect on the measured capacitance.

Provided is a product sum calculator which consumes little energy and has high calculation accuracy. A product sum arithmetic unit (1) is configured from: a resistive digital-to-analog conversion unit (11) that is provided with a plurality of RDACs and that converts digital values of each element of an input vector into analog voltages and outputs the analog voltages; a capacitive digital-to-analog conversion unit (12), which is provided with a plurality of CDACs, to which the analog voltage output from the resistive digital-to-analog conversion unit (11) is inputted, and which sets a capacitance ratio corresponding to the digital value of each element of the matrix between input and output terminals and between the output terminal and ground; a successive approximation-type analog-to-digital conversion unit (13) provided with a plurality of successive approximation-type ADCs for converting the voltage of a node commonly connected to each output terminal of the capacitive digital-to-analog conversion unit (12) into a digital value and outputting the digital value; and a consumption current control unit (14) for controlling the consumption current of the resistive digital-to-analog conversion unit (11), the output from the successive comparison analog-to-digital conversion unit (13) being an output vector.

The invention relates to the technical field of inverters, in particular to an inverter system, a power distribution method and device thereof, a control device, a storage medium and a photovoltaic power station. Wherein the inverter system comprises a plurality of inverters, the direct current side of each inverter in the plurality of inverters is connected with a photovoltaic module, the alternating current sides of the plurality of inverters are connected in parallel, and the method comprises the following steps: obtaining the overload power of each inverter in the plurality of inverters in a running state and the capacitance ratio of the corresponding photovoltaic module; and distributing the total target active power of the inverter system based on the overload power of each inverter and the capacitance ratio of the corresponding photovoltaic module to obtain the target active power of each inverter. Therefore, the loss of active power generation caused by non-uniform installation of the photovoltaic module can be reduced.

The invention provides a negative single-particle transient reinforcing circuit and method based on a comparator and a resistance network, the negative single-particle transient reinforcing circuit comprises the comparator, the resistance network, a transistor and a capacitor, the positive electrode input end of the comparator is connected with the output end of a BGR, the negative electrode input end of the comparator is connected with the resistance network, and the transistor is connected with the capacitor. The output end of the comparator is connected with the grid electrode of the transistor, the drain electrode of the transistor is connected with the positive electrode input end of the comparator, the source electrode of the transistor is connected with one end of the capacitor and the voltage output end, and the other end of the capacitor is grounded. The plurality of resistors comprise a fifth resistor, a sixth resistor and an Nth resistor RN (N is an integer greater than 5). According to the negative single-particle transient reinforcing circuit based on the comparator and the resistance network, the Vref voltage output by the BGR subjected to SET is adjusted in real time based on the comparator, the circuit can be effectively reinforced, and the output voltage can be stabilized within a certain range.

The vacuum welding and detecting device comprises a vacuum machine, a vacuum chamber is arranged on the vacuum machine and used for enabling an inner cavity to be in a vacuum state, a placing frame is arranged in the vacuum chamber, a positioning ring is arranged on the placing frame and used for positioning and placing the vacuum cup, a plugging hole is formed in the bottom of the vacuum cup, and the plugging hole is used for plugging the vacuum cup. A cap is welded in the vacuum layer of the vacuum cup and covers the plugging hole, and a welding device is arranged on the positioning frame. The invention provides a vacuum welding and detecting device for a vacuum cup, which can be used for judging the sealing state of a vacuum layer by implanting a guide sheet into a vacuum layer of the vacuum cup, detecting capacitance for a vacuum chamber at the outside and detecting capacitance when the outside is normal pressure in the vacuum welding and packaging process of the vacuum cup and comparing the capacitance of the guide sheet and the capacitance of the vacuum chamber. Therefore, leakage products can be directly and clearly distinguished in the production process, the product quality is improved, and meanwhile the production efficiency is improved.

In accordance with some embodiments of the present disclosure, an analog-to-digital- converter (ADC) is provided. The ADC may include a capacitive DAC (CDAC), a comparator, and a successive approximation register (SAR) logic configured to control the CDAC and the comparator to perform a successive approximation conversion of an analog input into a digital output signal. The CDAC includes a plurality of unary-weighted capacitors having the same capacitor value and a plurality of binary-weighted capacitors. In some embodiments, the CDAC includes a first capacitor array and a second capacitor array. Each of the first capacitor array and the second capacitor array may include a plurality of unary-weighted capacitors and a plurality of binary-weighted capacitors.

The invention discloses an axial magnetic flux motor and a method for limiting shaft voltage and improving electric corrosion of a bearing, and the axial magnetic flux motor comprises a motor housing which is enclosed by at least one end cover; the stator is arranged in the motor shell; one end of the rotor is rotationally arranged in a bearing chamber through a bearing, and the bearing chamber is arranged in the motor shell; the bearing chamber and the end cover are arranged in a split mode. The bearing chamber and the end cover are connected in a non-conducting mode and are provided with at least one first adjustable capacitor. The stator and the end cover are in non-conducting connection and are provided with at least one second adjustable capacitor; by adjusting the capacitance values of the first adjustable capacitor and the second adjustable capacitor, the specific value of each bridge arm capacitor in the motor shaft voltage equivalent circuit is adjusted. According to the invention, accurate adjustment of the capacitance ratio of each bridge arm in the motor shaft voltage equivalent Wheatstone bridge arm circuit is realized. By adjusting the capacitance value of the capacitor, the bridge arm capacitance meets the balance condition, and electric corrosion of the bearing is avoided from the source.

The invention relates to a parameter design method of a bidirectional CLLC resonant converter, and discloses a parameter design method taking a voltage gain curve derivative as a target function based on the influence of three parameters of an inductance ratio, a capacitance ratio and a quality factor on a voltage gain curve. According to the method, parameters with small influence factors are assumed preferentially, parameters with large influence factors are analyzed, the slope of a voltage gain function is solved by adopting a first-order derivative method, linear processing is performed on a resonant frequency point of a voltage gain curve, and the slope corresponding to an intermediate value of frequency change is made to be equal to that of the intermediate value; according to the method, three related parameters including the inductance ratio, the capacitance ratio and the quality factor are obtained, and then specific numerical values of primary and secondary side resonant inductance, primary and secondary side resonant capacitance and excitation inductance are obtained, so that the parameter design is more reasonable, and forward and reverse voltage gain curves of the bidirectional CLLC resonant converter are in a monotonically decreasing section; the soft switching characteristic of the converter is ensured, the converter control strategy is simplified, and the robustness and dynamic response of the system are improved.

The embodiment of the present disclosure provides a quasi-fixed frequency constant on-time architecture buck converter and an on-time timing circuit. The on-time timing circuit comprises a current generating module, a flip delay cancellation module, a capacitor and a comparator. The current generating module is configured to generate a charging current proportional to the voltage of a switching node after the upper power tube is turned on. The flip delay cancellation module is configured to generate a first delay for canceling the flip delay of the comparator according to a variable resistance unit and the capacitor. The resistance value of the variable resistance unit is controlled by an input voltage. The capacitor is configured to be charged by the charging current after the upper power tube is turned on. The comparator is configured to compare the size of the slope voltage corresponding to the slope voltage node and the first voltage, and generate an off signal. The first voltage is a reference voltage in proportional relationship with the output voltage. The problem of large variation of working frequency in the quasi-fixed frequency constant on-time architecture buck converter is solved.