53 results about "Capacitance ratio" patented technology

The invention relates to the technical field of on-line monitoring, in particular to an insulation fault on-line monitoring method and system for a medical IT system control cabinet. The method comprises the following steps: selecting a non-integer frequency multiplication detection frequency according to equivalent ground distributed capacitance in a previous monitoring period, and superposing the non-integer frequency multiplication detection frequency with a fundamental frequency to form a composite signal injection system; collecting signals to calculate a voltage instantaneous harmonic distortion rate change gradient, and selecting a time window to split the leakage current according to the change gradient; on the basis of dispersion estimation signal-to-noise ratio weighted fusion current vectors, insulation resistance and distributed capacitance are calculated; constructing a four-dimensional original feature vector composed of the insulation parameter, the phase difference and the intermodulation component energy; constructing a diagonal weighting matrix based on the resistance-capacitance ratio and the gradient to transform a feature vector, and determining the fault attribution through the Mahalanobis distance calculation with the fault template library. According to the scheme, harmonic interference can be avoided, calculation stability can be improved, insulation instantaneous sudden change can be quickly responded, and different fault types can be accurately distinguished to guide maintenance.

In accordance with some embodiments of the present disclosure, an analog-to-digital-converter (ADC) is provided. The ADC may include a capacitive DAC (CDAC), a comparator, and a successive approximation register (SAR) logic configured to control the CDAC and the comparator to perform a successive approximation conversion of an analog input into a digital output signal. The CDAC includes a plurality of unary-weighted capacitors having the same capacitor value and a plurality of binary-weighted capacitors. In some embodiments, the CDAC includes a first capacitor array and a second capacitor array. Each of the first capacitor array and the second capacitor array may include a plurality of unary-weighted capacitors and a plurality of binary-weighted capacitors.

A method comprises discharging electrical energy from an intermediate circuit comprised in the apparatus, measuring a direct current voltage, and inputting measured values to a parameter estimator for the intermediate circuit. The parameter estimator comprises at least a first parameter and a second parameter whose values are determined based on an equivalent capacitance value of the intermediate circuit, an equivalent resistance value of the intermediate circuit and an electrical load power value of the intermediate circuit, the parameter estimator outputting values for time constant and values for power-to-capacitance ratio of the intermediate circuit. The method further comprises storing values at least temporarily for condition monitoring.

The application relates to the technical field of metrological calibration, and discloses a multi-voltage-grade capacitor current tester calibration method based on unified transformation ratio. The method comprises the following steps: screening unified transformation ratio parameters meeting range constraints and error constraints, obtaining a ratio difference parameter of a corresponding electromagnetic voltage transformer, obtaining a capacitance ratio difference correction factor, calculating conversion coefficients under each voltage grade, determining a primary side capacitance setting value according to a preset primary side calibration capacitance value and the conversion coefficients, obtaining a secondary side output capacitance value of a standard capacitance tank, and collecting a displayed capacitance value and a displayed capacitance current value. The conversion coefficients between the unified transformation ratio and the theoretical transformation ratios of each voltage grade are established, single transformation ratio is used to cover multi-voltage-grade calibration, error components introduced by the ratio difference of the electromagnetic voltage transformer in the capacitance calibration process are reduced, and different transformation ratio equipment needs to be frequently replaced.

The application provides a capacitor array applied to a SAR auxiliary ramp ADC, an analog-to-digital converter and a conversion method, and belongs to the technical field of integrated circuits. The capacitor array comprises a first output end, a second output end, a first bridge capacitor, a second bridge capacitor, a first SAR capacitor subarray, a second SAR capacitor subarray, a low-bit SAR capacitor, a first to third ramp capacitor subarray and a fixed level capacitor subarray. Each capacitor is connected to a switch network through a specific connection relationship, and the capacitance ratio between each SAR capacitor and the capacitance ratio between the low-bit SAR capacitor and the bridge capacitor and the unit capacitor are configured to form a non-binary weight relationship. The application also provides a conversion method based on the capacitor array. By adopting a segmented capacitor structure and a non-binary weight design, the application can significantly reduce the capacitor array area, reduce the switch power consumption and comparator load, speed up the establishment time, and improve the linearity of the CDAC, thereby improving the overall performance of the ADC in speed, area and power consumption.

This application relates to the field of power electronics technology and discloses a method, device, equipment, and storage medium for detecting the aging of DC capacitors in a three-level inverter. The method includes: obtaining a simplified topology model of the three-level inverter; based on the working principle of the three-level inverter, controlling the midpoint current to zero by injecting a zero-sequence voltage into the three-phase reference voltage; under the state of midpoint potential balance, monitoring a first current and a second current using the correlation between capacitor current and capacitance value, calculating the current ratio of the first current and the second current, and deriving the capacitance ratio of the first capacitor and the second capacitor based on the current ratio; and identifying the aging state of the capacitor online based on the capacitance ratio. The device, equipment, and storage medium all correspond to this method. This application achieves online aging identification of capacitors by monitoring the current changes of the upper and lower DC capacitors of a three-level inverter, under the premise that the midpoint potential balance of the three-level inverter is controlled.

A 2-bit fast flash analog-to-digital converter circuit and related methods designed for use with multi-level converters in particular to achieve: high conversion speed, high resolution, small layout area, low power, and the ability to meet the requirements for properly balancing fly capacitor voltages. One embodiment includes a voltage input configured to be coupled to a multi-level converter fly capacitor; a comparator coupled to the voltage input and a first reference voltage input and having a first binary output indicating whether the input voltage is higher or lower than a voltage on the first reference voltage input; and a circuit coupled to the voltage input and to second and third reference voltage inputs, the circuit configured to provide a second binary output indicating whether the input voltage is inside or outside a voltage window defined by respective voltages on the second reference and third reference voltage inputs.

The application discloses a method for measuring error of low-frequency voltage transformer under high voltage by using standard capacitor, which comprises the following steps: connecting the measured low-frequency voltage transformer and low-frequency standard voltage transformer into a difference loop under preset low voltage to measure low-voltage ratio error and low-voltage phase error; introducing high-voltage standard capacitor and low-voltage standard capacitor under preset high voltage to connect with the measured low-frequency voltage transformer into an equal power loop to measure first capacitor ratio and first dielectric loss and second capacitor ratio and second dielectric loss; measuring high-voltage capacitor voltage coefficient, high-voltage dielectric loss voltage coefficient, low-voltage capacitor voltage coefficient and low-voltage dielectric loss voltage coefficient by using comparison method; measuring low-voltage capacitor ratio measurement error, low-voltage dielectric loss measurement error, high-voltage capacitor ratio measurement error and high-voltage dielectric loss measurement error by using capacitor rotation method; and calculating high-voltage ratio error and high-voltage phase error of the measured low-frequency voltage transformer under preset high voltage according to the above parameters.

The invention relates to the technical field of inverters, in particular to an inverter system, a power distribution method and device thereof, a control device, a storage medium and a photovoltaic power station. Wherein the inverter system comprises a plurality of inverters, the direct current side of each inverter in the plurality of inverters is connected with a photovoltaic module, the alternating current sides of the plurality of inverters are connected in parallel, and the method comprises the following steps: obtaining the overload power of each inverter in the plurality of inverters in a running state and the capacitance ratio of the corresponding photovoltaic module; and distributing the total target active power of the inverter system based on the overload power of each inverter and the capacitance ratio of the corresponding photovoltaic module to obtain the target active power of each inverter. Therefore, the loss of active power generation caused by non-uniform installation of the photovoltaic module can be reduced.

The vacuum welding and detecting device comprises a vacuum machine, a vacuum chamber is arranged on the vacuum machine and used for enabling an inner cavity to be in a vacuum state, a placing frame is arranged in the vacuum chamber, a positioning ring is arranged on the placing frame and used for positioning and placing the vacuum cup, a plugging hole is formed in the bottom of the vacuum cup, and the plugging hole is used for plugging the vacuum cup. A cap is welded in the vacuum layer of the vacuum cup and covers the plugging hole, and a welding device is arranged on the positioning frame. The invention provides a vacuum welding and detecting device for a vacuum cup, which can be used for judging the sealing state of a vacuum layer by implanting a guide sheet into a vacuum layer of the vacuum cup, detecting capacitance for a vacuum chamber at the outside and detecting capacitance when the outside is normal pressure in the vacuum welding and packaging process of the vacuum cup and comparing the capacitance of the guide sheet and the capacitance of the vacuum chamber. Therefore, leakage products can be directly and clearly distinguished in the production process, the product quality is improved, and meanwhile the production efficiency is improved.

In accordance with some embodiments of the present disclosure, an analog-to-digital- converter (ADC) is provided. The ADC may include a capacitive DAC (CDAC), a comparator, and a successive approximation register (SAR) logic configured to control the CDAC and the comparator to perform a successive approximation conversion of an analog input into a digital output signal. The CDAC includes a plurality of unary-weighted capacitors having the same capacitor value and a plurality of binary-weighted capacitors. In some embodiments, the CDAC includes a first capacitor array and a second capacitor array. Each of the first capacitor array and the second capacitor array may include a plurality of unary-weighted capacitors and a plurality of binary-weighted capacitors.

The invention discloses an axial magnetic flux motor and a method for limiting shaft voltage and improving electric corrosion of a bearing, and the axial magnetic flux motor comprises a motor housing which is enclosed by at least one end cover; the stator is arranged in the motor shell; one end of the rotor is rotationally arranged in a bearing chamber through a bearing, and the bearing chamber is arranged in the motor shell; the bearing chamber and the end cover are arranged in a split mode. The bearing chamber and the end cover are connected in a non-conducting mode and are provided with at least one first adjustable capacitor. The stator and the end cover are in non-conducting connection and are provided with at least one second adjustable capacitor; by adjusting the capacitance values of the first adjustable capacitor and the second adjustable capacitor, the specific value of each bridge arm capacitor in the motor shaft voltage equivalent circuit is adjusted. According to the invention, accurate adjustment of the capacitance ratio of each bridge arm in the motor shaft voltage equivalent Wheatstone bridge arm circuit is realized. By adjusting the capacitance value of the capacitor, the bridge arm capacitance meets the balance condition, and electric corrosion of the bearing is avoided from the source.

The invention relates to a parameter design method of a bidirectional CLLC resonant converter, and discloses a parameter design method taking a voltage gain curve derivative as a target function based on the influence of three parameters of an inductance ratio, a capacitance ratio and a quality factor on a voltage gain curve. According to the method, parameters with small influence factors are assumed preferentially, parameters with large influence factors are analyzed, the slope of a voltage gain function is solved by adopting a first-order derivative method, linear processing is performed on a resonant frequency point of a voltage gain curve, and the slope corresponding to an intermediate value of frequency change is made to be equal to that of the intermediate value; according to the method, three related parameters including the inductance ratio, the capacitance ratio and the quality factor are obtained, and then specific numerical values of primary and secondary side resonant inductance, primary and secondary side resonant capacitance and excitation inductance are obtained, so that the parameter design is more reasonable, and forward and reverse voltage gain curves of the bidirectional CLLC resonant converter are in a monotonically decreasing section; the soft switching characteristic of the converter is ensured, the converter control strategy is simplified, and the robustness and dynamic response of the system are improved.

The embodiment of the present disclosure provides a quasi-fixed frequency constant on-time architecture buck converter and an on-time timing circuit. The on-time timing circuit comprises a current generating module, a flip delay cancellation module, a capacitor and a comparator. The current generating module is configured to generate a charging current proportional to the voltage of a switching node after the upper power tube is turned on. The flip delay cancellation module is configured to generate a first delay for canceling the flip delay of the comparator according to a variable resistance unit and the capacitor. The resistance value of the variable resistance unit is controlled by an input voltage. The capacitor is configured to be charged by the charging current after the upper power tube is turned on. The comparator is configured to compare the size of the slope voltage corresponding to the slope voltage node and the first voltage, and generate an off signal. The first voltage is a reference voltage in proportional relationship with the output voltage. The problem of large variation of working frequency in the quasi-fixed frequency constant on-time architecture buck converter is solved.

The embodiment of the invention provides a switch control circuit, an MOS tube control circuit and a control circuit, and relates to the technical field of electronics, the switch control circuit is connected with a PGD pin and a UVLO pin of a target chip, and the switch control circuit comprises a first controller, a first capacitor, a comparator, a second controller and a delay control chip; a first pin of the first controller is connected with the PGD pin, a second pin is connected with the anode of the first capacitor, and a third pin is connected with the cathode of the first capacitor; the positive electrode of the first capacitor is connected with charging voltage and is connected with the UVLO pin through a discharging link; the positive-phase input end of the comparator is connected with the positive electrode of the first capacitor, the negative-phase input end is connected with reference voltage, and the output end is connected with the fourth pin of the second controller; a fifth pin of the second controller is connected with an MR pin of the delay control chip, and a RESET pin of the delay control chip is connected with a UVLO pin. By applying the scheme provided by the embodiment of the invention, the MOS tube can be protected during full-load starting, overcurrent or short circuit.

The application discloses a foreground analog calibration method applied to a capacitive bridging type DAC, and comprises the following steps: inputting a sinusoidal signal into a SAR ADC to obtain a current digital code output by the SAR ADC; performing histogram distribution statistics on the current digital code; detecting whether the current digital code satisfies preset monotonicity based on N(i), and determining a connection mode of a calibration capacitor of a current capacitor in an LSB array of the bridging DAC according to a detection result; determining a calibration capacitor to be connected from all calibration capacitors of the current capacitor; returning to the step of inputting the sinusoidal signal into the SAR ADC after connecting the calibration capacitor to be connected to the bridging DAC according to the connection mode, and gradually reducing a quantization error of the DAC, so that INL and DNL satisfy error requirements. Meanwhile, the application takes a protection isolation capacitor filled around the LSB array as the calibration capacitor, adjusts a bit capacitor ratio of the capacitor array through a series-parallel calibration capacitor mode, reduces a proportion mismatch of the capacitor array as a whole, and reduces a non-linear error of the circuit.

The invention relates to the technical field of touch screens, and discloses a touch screen multi-point recognition method, system and equipment, and the method comprises the steps: detecting touch candidate nodes of a touch screen, carrying out the connectivity clustering of the touch candidate nodes, positioning a touch region, calculating a peak capacitance ratio, a radial attenuation coefficient and a symmetry index, and carrying out the combination to obtain a capacitance signature; calculating the position offset of the centroid coordinates between the adjacent frames and the time sequence fluctuation ratio of the capacitance signature, and screening out stable touch points of which the position offset and the time sequence fluctuation ratio meet the stability condition; the mass center distance and the capacitance signature difference degree between any two stable touch points are calculated, when the mass center distance is larger than the preset separation distance and the capacitance signature difference degree is larger than the preset difference threshold value, it is judged that the touch points are two target touch points, and then electromagnetic interference and water drop mistaken touch with abnormal capacitance distribution are effectively restrained; the influence of instantaneous interference on touch recognition is reduced, and it is ensured that the number and positions of output touch points are consistent with those of actual operation of a user.

The embodiment of the present application provides a micro electro mechanical system switch and a preparation method of the micro electro mechanical system switch. The micro electro mechanical system switch comprises a substrate, a signal line arranged on one side of the substrate, a switch beam located on the side, away from the substrate, of the signal line, the switch beam being provided with a containing hole, the orthographic projection of the containing hole on the substrate being located in the orthographic projection of the signal line on the substrate, and a conductive part connected with the signal line and located between the signal line and the switch beam, the orthographic projection of the conductive part on the substrate being located in the orthographic projection of the containing hole on the substrate. The embodiment of the present application can effectively improve the capacitance ratio of the off-state capacitance and the on-state capacitance, thereby improving the radio frequency performance of the micro electro mechanical system switch.

The solid-state imaging device has a plurality of pixel circuits (1) arranged in a matrix, wherein the pixel circuit (1) comprises: a photodiode (APD); a first charge storage unit (C1) for storing charge; a floating diffusion region (FD) for storing charge; a second charge storage unit (C2) for storing charge; a first transfer transistor (2) for transferring charge from the photodiode (APD) to the first charge storage unit (C1); a second transfer transistor (3) for transferring charge from the first charge storage unit (C1) to the floating diffusion region (FD); a first reset transistor (4) for resetting the floating diffusion region (FD); and an accumulation transistor (7) for accumulating charge of the floating diffusion region (FD) in the second charge storage unit (C2), wherein the capacitance of the first charge storage unit (C1) is larger than the capacitance of the floating diffusion region (FD), and the capacitance of the second charge storage unit (C2) is larger than the capacitance of the floating diffusion region (FD).

The invention relates to a method for determining a state of a capacitive voltage transformer (50) comprising a capacitive voltage divider with a first capacitor (C1) and a second capacitor (C2) on its primary side. The first capacitor (C1) has a high voltage connection (HV) for connecting to a high voltage (60) and the second capacitor (C2) has a ground connection (NHF). A first resonance frequency (ω e ) is determined by a plurality of first short circuit impedance measurements at different frequencies on the secondary side of the capacitive voltage transformer (50) with the high voltage connection (HV) grounded (70). A second resonance frequency (ω2) is determined by a plurality of second short circuit impedance measurements at different frequencies on the secondary side of the capacitive voltage transformer (50) with the high voltage connection (HV) open. A capacitance ratio (K e ) of the capacitive voltage divider (50) is determined based on the first resonance frequency (ω C ) and the second resonance frequency (ω2).

The invention discloses a high-switch-ratio inverted ferroelectric capacitance type memory based on a silicon-on-insulator substrate and a preparation method thereof. The device sequentially comprises a bottom buried oxide layer, a top channel, a ferroelectric layer covering the left side of the top of the top channel, a top electrode covering the top of the ferroelectric layer, and a bottom electrode covering the right side of the top of the top channel from bottom to top in the vertical direction. The ferroelectric layer is not in contact with the bottom electrode; a heavily doped N + region is arranged in the top channel below the bottom electrode, and lightly doped thin silicon is arranged in the top channel below the ferroelectric layer; according to the invention, the ultra-thin top silicon is used to precisely compress the low capacitance state, the EOT limitation is broken through, the capacitance ratio is significantly improved, high integration and low power consumption are considered, the device is significantly superior to the existing MFM and conventional MFS devices, and a feasible path is provided for a multi-valued storage and high-energy-efficiency storage chip.

The application is suitable for the technical field of over-voltage protection device of super-high voltage and extra-high voltage transmission system, and provides a controllable arrester based on self-triggering air-gap switch, which comprises an arrester fixed part, an arrester controllable part, a bypass capacitor high-voltage part, a bypass capacitor low-voltage part, an air-gap switch and an intermediate bridge valve group; the arrester fixed part, the arrester controllable part, the bypass capacitor high-voltage part, the bypass capacitor low-voltage part and the intermediate bridge valve group form an electric bridge structure, and the air-gap switch is connected in parallel with the bypass low-voltage part; the capacitance ratio of the bypass capacitor low-voltage part to the bypass capacitor high-voltage part is less than the rated voltage ratio of the arrester fixed part and the arrester controllable part. The short circuit of the arrester controllable part is realized through the cooperation of electrical parameters, the over-voltage can be protected in time, the influence caused by the dispersion of the air-gap switch action is avoided, a complex control system is not needed, and the device is less and the structure is simple.

The printed circuit board is configured to have: a base material formed of an insulator; and a pattern which is formed on the base material and on which a DC voltage unit connected to the rectifier and the inverter in the power conversion device is mounted, the pattern having, mounted as the DC voltage unit, either a first setting provided with a plurality of first electrolytic capacitors and a second setting provided with a plurality of second electrolytic capacitors. The second setting includes a second electrolytic capacitor and a small capacitance capacitor having a smaller capacitance than the plurality of first electrolytic capacitors and a smaller capacitance than the second electrolytic capacitor.

The invention belongs to the technical field of detection, and discloses a water volume continuous detection system and method based on a micro-pitch capacitor array, and the system comprises a micro-pitch capacitor array sensor and a processing module. The sensor adopts a comb-shaped crossed electrode structure, the distance between electrodes is within a millimeter-level range, and the surface is covered with a hydrophobic protection layer. And the processing module compares the charging and discharging times of the induction capacitor with the reference capacitor through a capacitance relative change measurement algorithm, judges a water drop event according to the change rate, immediately resets the current capacitance value as a new reference after triggering, realizes continuous detection under water film coverage, and judges the water stop state by monitoring the slow recovery trend of the capacitor. According to the invention, the detection sensitivity of tiny water drops is improved, the slow drift interference of environment temperature and humidity is effectively inhibited, the water film locking problem of a traditional sensor is solved, the electrodes do not need to be exposed, the detection reliability is improved, and the service life is prolonged.

A semiconductor structure is provided that includes a tunable and shared non-conductive layer as part of a gate stack of at least a pair of nanosheet GAA transistors with a shared metal gate electrode. The semiconductor structure has a tunable non-conductive material / gate dielectric area ratio where the non-conductive material is not constrained to a periphery of the nanosheet stack cross section.

An image sensor includes a pixel-circuit and circuitry. The pixel-circuit includes a PD that accumulates charge responsively to incident light and a FD that stores the charge. The circuitry serially (i) connects the PD and a supply rail to the FD and sends a first FD voltage, (ii) disconnects the supply rail from the FD and sends a second FD voltage, (iii) disconnects the PD from the FD and sends a third FD voltage, (iv) waits a preset exposure time, (v) connects the supply rail to the FD and sends a fourth FD voltage, (vi) disconnects the supply rail from the FD and sends a fifth FD voltage, and (vii) connects the PD to the FD and sends a sixth FD voltage. The circuitry estimates incident light energy responsively to (i) the FD voltages, and (ii) a capacitance ratio defined over at least capacitances of the FD and the PD.

This invention discloses a power converter with a multi-slope compensation mechanism. The multi-slope compensation circuit of the power converter includes multiple first capacitors, a comparator, and multiple first resistors. An inductor is connected to the node between the first terminals of the multiple first capacitors and the second terminal of the upper bridge switch and the first terminal of the lower bridge switch. Multiple first input terminals of the comparator are respectively connected to the second terminals of the multiple first capacitors and to the first terminals of the multiple first resistors. The second terminals of the multiple first resistors are coupled to a second reference voltage. The second input terminal of the comparator is coupled to a first reference voltage. The output terminal of the comparator is connected to the input terminal of a drive circuit.

A semiconductor field effect transistor device and its manufacturing method, the present invention relates to in power semiconductor device, the semiconductor device also includes the active region for providing the current conduction area when the device is turned on, the terminal trench region makes the electric field between the source-drain in the active region to prevent the breakdown of the device peripheral region, the gate-source capacitance region provides additional Cgs for the device and improves the switching characteristic, the stress release region for reducing the stress generated by the periodic arrangement of the device trench and the electric field cutoff region, compared with the traditional structure and process, the gate-source capacitance-gate-drain capacitance ratio can be improved, and the device terminal structure with high reliability is provided.

This disclosure provides a switched-capacitor comparator, an analog-to-digital converter, and an electronic device, relating to the field of integrated circuit technology. The switched-capacitor comparator includes a switched-capacitor comparator unit and a common-mode stabilization unit. The switched-capacitor comparator unit integrates a sampling capacitor and a comparator. Its inputs include a forward reference voltage, a reverse reference voltage, a forward input voltage, a reverse input voltage, and a common-mode bias voltage of the comparator. Its output is a comparison of the difference between the forward and reverse input voltages, and the difference between the forward and reverse reference voltages. The common-mode stabilization unit simulates the sampling state of the switched-capacitor comparator unit, ensuring that the actual common-mode input voltage of the comparator equals the ideal common-mode input voltage. Its inputs include the common-mode reference voltage, the forward input voltage, the reverse input voltage, and the ideal common-mode input voltage. Its output is the common-mode bias voltage. This switched-capacitor comparator features a wide common-mode input range and fast response.