36 results about "Capacitance ratio" patented technology

The invention relates to the technical field of on-line monitoring, in particular to an insulation fault on-line monitoring method and system for a medical IT system control cabinet. The method comprises the following steps: selecting a non-integer frequency multiplication detection frequency according to equivalent ground distributed capacitance in a previous monitoring period, and superposing the non-integer frequency multiplication detection frequency with a fundamental frequency to form a composite signal injection system; collecting signals to calculate a voltage instantaneous harmonic distortion rate change gradient, and selecting a time window to split the leakage current according to the change gradient; on the basis of dispersion estimation signal-to-noise ratio weighted fusion current vectors, insulation resistance and distributed capacitance are calculated; constructing a four-dimensional original feature vector composed of the insulation parameter, the phase difference and the intermodulation component energy; constructing a diagonal weighting matrix based on the resistance-capacitance ratio and the gradient to transform a feature vector, and determining the fault attribution through the Mahalanobis distance calculation with the fault template library. According to the scheme, harmonic interference can be avoided, calculation stability can be improved, insulation instantaneous sudden change can be quickly responded, and different fault types can be accurately distinguished to guide maintenance.

A method comprises discharging electrical energy from an intermediate circuit comprised in the apparatus, measuring a direct current voltage, and inputting measured values to a parameter estimator for the intermediate circuit. The parameter estimator comprises at least a first parameter and a second parameter whose values are determined based on an equivalent capacitance value of the intermediate circuit, an equivalent resistance value of the intermediate circuit and an electrical load power value of the intermediate circuit, the parameter estimator outputting values for time constant and values for power-to-capacitance ratio of the intermediate circuit. The method further comprises storing values at least temporarily for condition monitoring.

The application relates to the technical field of metrological calibration, and discloses a multi-voltage-grade capacitor current tester calibration method based on unified transformation ratio. The method comprises the following steps: screening unified transformation ratio parameters meeting range constraints and error constraints, obtaining a ratio difference parameter of a corresponding electromagnetic voltage transformer, obtaining a capacitance ratio difference correction factor, calculating conversion coefficients under each voltage grade, determining a primary side capacitance setting value according to a preset primary side calibration capacitance value and the conversion coefficients, obtaining a secondary side output capacitance value of a standard capacitance tank, and collecting a displayed capacitance value and a displayed capacitance current value. The conversion coefficients between the unified transformation ratio and the theoretical transformation ratios of each voltage grade are established, single transformation ratio is used to cover multi-voltage-grade calibration, error components introduced by the ratio difference of the electromagnetic voltage transformer in the capacitance calibration process are reduced, and different transformation ratio equipment needs to be frequently replaced.

The application provides a capacitor array applied to a SAR auxiliary ramp ADC, an analog-to-digital converter and a conversion method, and belongs to the technical field of integrated circuits. The capacitor array comprises a first output end, a second output end, a first bridge capacitor, a second bridge capacitor, a first SAR capacitor subarray, a second SAR capacitor subarray, a low-bit SAR capacitor, a first to third ramp capacitor subarray and a fixed level capacitor subarray. Each capacitor is connected to a switch network through a specific connection relationship, and the capacitance ratio between each SAR capacitor and the capacitance ratio between the low-bit SAR capacitor and the bridge capacitor and the unit capacitor are configured to form a non-binary weight relationship. The application also provides a conversion method based on the capacitor array. By adopting a segmented capacitor structure and a non-binary weight design, the application can significantly reduce the capacitor array area, reduce the switch power consumption and comparator load, speed up the establishment time, and improve the linearity of the CDAC, thereby improving the overall performance of the ADC in speed, area and power consumption.

This application relates to the field of power electronics technology and discloses a method, device, equipment, and storage medium for detecting the aging of DC capacitors in a three-level inverter. The method includes: obtaining a simplified topology model of the three-level inverter; based on the working principle of the three-level inverter, controlling the midpoint current to zero by injecting a zero-sequence voltage into the three-phase reference voltage; under the state of midpoint potential balance, monitoring a first current and a second current using the correlation between capacitor current and capacitance value, calculating the current ratio of the first current and the second current, and deriving the capacitance ratio of the first capacitor and the second capacitor based on the current ratio; and identifying the aging state of the capacitor online based on the capacitance ratio. The device, equipment, and storage medium all correspond to this method. This application achieves online aging identification of capacitors by monitoring the current changes of the upper and lower DC capacitors of a three-level inverter, under the premise that the midpoint potential balance of the three-level inverter is controlled.

A 2-bit fast flash analog-to-digital converter circuit and related methods designed for use with multi-level converters in particular to achieve: high conversion speed, high resolution, small layout area, low power, and the ability to meet the requirements for properly balancing fly capacitor voltages. One embodiment includes a voltage input configured to be coupled to a multi-level converter fly capacitor; a comparator coupled to the voltage input and a first reference voltage input and having a first binary output indicating whether the input voltage is higher or lower than a voltage on the first reference voltage input; and a circuit coupled to the voltage input and to second and third reference voltage inputs, the circuit configured to provide a second binary output indicating whether the input voltage is inside or outside a voltage window defined by respective voltages on the second reference and third reference voltage inputs.

The invention relates to the technical field of inverters, in particular to an inverter system, a power distribution method and device thereof, a control device, a storage medium and a photovoltaic power station. Wherein the inverter system comprises a plurality of inverters, the direct current side of each inverter in the plurality of inverters is connected with a photovoltaic module, the alternating current sides of the plurality of inverters are connected in parallel, and the method comprises the following steps: obtaining the overload power of each inverter in the plurality of inverters in a running state and the capacitance ratio of the corresponding photovoltaic module; and distributing the total target active power of the inverter system based on the overload power of each inverter and the capacitance ratio of the corresponding photovoltaic module to obtain the target active power of each inverter. Therefore, the loss of active power generation caused by non-uniform installation of the photovoltaic module can be reduced.

The embodiment of the present disclosure provides a quasi-fixed frequency constant on-time architecture buck converter and an on-time timing circuit. The on-time timing circuit comprises a current generating module, a flip delay cancellation module, a capacitor and a comparator. The current generating module is configured to generate a charging current proportional to the voltage of a switching node after the upper power tube is turned on. The flip delay cancellation module is configured to generate a first delay for canceling the flip delay of the comparator according to a variable resistance unit and the capacitor. The resistance value of the variable resistance unit is controlled by an input voltage. The capacitor is configured to be charged by the charging current after the upper power tube is turned on. The comparator is configured to compare the size of the slope voltage corresponding to the slope voltage node and the first voltage, and generate an off signal. The first voltage is a reference voltage in proportional relationship with the output voltage. The problem of large variation of working frequency in the quasi-fixed frequency constant on-time architecture buck converter is solved.

The application discloses a foreground analog calibration method applied to a capacitive bridging type DAC, and comprises the following steps: inputting a sinusoidal signal into a SAR ADC to obtain a current digital code output by the SAR ADC; performing histogram distribution statistics on the current digital code; detecting whether the current digital code satisfies preset monotonicity based on N(i), and determining a connection mode of a calibration capacitor of a current capacitor in an LSB array of the bridging DAC according to a detection result; determining a calibration capacitor to be connected from all calibration capacitors of the current capacitor; returning to the step of inputting the sinusoidal signal into the SAR ADC after connecting the calibration capacitor to be connected to the bridging DAC according to the connection mode, and gradually reducing a quantization error of the DAC, so that INL and DNL satisfy error requirements. Meanwhile, the application takes a protection isolation capacitor filled around the LSB array as the calibration capacitor, adjusts a bit capacitor ratio of the capacitor array through a series-parallel calibration capacitor mode, reduces a proportion mismatch of the capacitor array as a whole, and reduces a non-linear error of the circuit.

The invention relates to the technical field of touch screens, and discloses a touch screen multi-point recognition method, system and equipment, and the method comprises the steps: detecting touch candidate nodes of a touch screen, carrying out the connectivity clustering of the touch candidate nodes, positioning a touch region, calculating a peak capacitance ratio, a radial attenuation coefficient and a symmetry index, and carrying out the combination to obtain a capacitance signature; calculating the position offset of the centroid coordinates between the adjacent frames and the time sequence fluctuation ratio of the capacitance signature, and screening out stable touch points of which the position offset and the time sequence fluctuation ratio meet the stability condition; the mass center distance and the capacitance signature difference degree between any two stable touch points are calculated, when the mass center distance is larger than the preset separation distance and the capacitance signature difference degree is larger than the preset difference threshold value, it is judged that the touch points are two target touch points, and then electromagnetic interference and water drop mistaken touch with abnormal capacitance distribution are effectively restrained; the influence of instantaneous interference on touch recognition is reduced, and it is ensured that the number and positions of output touch points are consistent with those of actual operation of a user.

The embodiment of the present application provides a micro electro mechanical system switch and a preparation method of the micro electro mechanical system switch. The micro electro mechanical system switch comprises a substrate, a signal line arranged on one side of the substrate, a switch beam located on the side, away from the substrate, of the signal line, the switch beam being provided with a containing hole, the orthographic projection of the containing hole on the substrate being located in the orthographic projection of the signal line on the substrate, and a conductive part connected with the signal line and located between the signal line and the switch beam, the orthographic projection of the conductive part on the substrate being located in the orthographic projection of the containing hole on the substrate. The embodiment of the present application can effectively improve the capacitance ratio of the off-state capacitance and the on-state capacitance, thereby improving the radio frequency performance of the micro electro mechanical system switch.

The application is suitable for the technical field of over-voltage protection device of super-high voltage and extra-high voltage transmission system, and provides a controllable arrester based on self-triggering air-gap switch, which comprises an arrester fixed part, an arrester controllable part, a bypass capacitor high-voltage part, a bypass capacitor low-voltage part, an air-gap switch and an intermediate bridge valve group; the arrester fixed part, the arrester controllable part, the bypass capacitor high-voltage part, the bypass capacitor low-voltage part and the intermediate bridge valve group form an electric bridge structure, and the air-gap switch is connected in parallel with the bypass low-voltage part; the capacitance ratio of the bypass capacitor low-voltage part to the bypass capacitor high-voltage part is less than the rated voltage ratio of the arrester fixed part and the arrester controllable part. The short circuit of the arrester controllable part is realized through the cooperation of electrical parameters, the over-voltage can be protected in time, the influence caused by the dispersion of the air-gap switch action is avoided, a complex control system is not needed, and the device is less and the structure is simple.

The invention belongs to the technical field of detection, and discloses a water volume continuous detection system and method based on a micro-pitch capacitor array, and the system comprises a micro-pitch capacitor array sensor and a processing module. The sensor adopts a comb-shaped crossed electrode structure, the distance between electrodes is within a millimeter-level range, and the surface is covered with a hydrophobic protection layer. And the processing module compares the charging and discharging times of the induction capacitor with the reference capacitor through a capacitance relative change measurement algorithm, judges a water drop event according to the change rate, immediately resets the current capacitance value as a new reference after triggering, realizes continuous detection under water film coverage, and judges the water stop state by monitoring the slow recovery trend of the capacitor. According to the invention, the detection sensitivity of tiny water drops is improved, the slow drift interference of environment temperature and humidity is effectively inhibited, the water film locking problem of a traditional sensor is solved, the electrodes do not need to be exposed, the detection reliability is improved, and the service life is prolonged.

A semiconductor structure is provided that includes a tunable and shared non-conductive layer as part of a gate stack of at least a pair of nanosheet GAA transistors with a shared metal gate electrode. The semiconductor structure has a tunable non-conductive material / gate dielectric area ratio where the non-conductive material is not constrained to a periphery of the nanosheet stack cross section.

An image sensor includes a pixel-circuit and circuitry. The pixel-circuit includes a PD that accumulates charge responsively to incident light and a FD that stores the charge. The circuitry serially (i) connects the PD and a supply rail to the FD and sends a first FD voltage, (ii) disconnects the supply rail from the FD and sends a second FD voltage, (iii) disconnects the PD from the FD and sends a third FD voltage, (iv) waits a preset exposure time, (v) connects the supply rail to the FD and sends a fourth FD voltage, (vi) disconnects the supply rail from the FD and sends a fifth FD voltage, and (vii) connects the PD to the FD and sends a sixth FD voltage. The circuitry estimates incident light energy responsively to (i) the FD voltages, and (ii) a capacitance ratio defined over at least capacitances of the FD and the PD.

This invention discloses a power converter with a multi-slope compensation mechanism. The multi-slope compensation circuit of the power converter includes multiple first capacitors, a comparator, and multiple first resistors. An inductor is connected to the node between the first terminals of the multiple first capacitors and the second terminal of the upper bridge switch and the first terminal of the lower bridge switch. Multiple first input terminals of the comparator are respectively connected to the second terminals of the multiple first capacitors and to the first terminals of the multiple first resistors. The second terminals of the multiple first resistors are coupled to a second reference voltage. The second input terminal of the comparator is coupled to a first reference voltage. The output terminal of the comparator is connected to the input terminal of a drive circuit.

This disclosure provides a switched-capacitor comparator, an analog-to-digital converter, and an electronic device, relating to the field of integrated circuit technology. The switched-capacitor comparator includes a switched-capacitor comparator unit and a common-mode stabilization unit. The switched-capacitor comparator unit integrates a sampling capacitor and a comparator. Its inputs include a forward reference voltage, a reverse reference voltage, a forward input voltage, a reverse input voltage, and a common-mode bias voltage of the comparator. Its output is a comparison of the difference between the forward and reverse input voltages, and the difference between the forward and reverse reference voltages. The common-mode stabilization unit simulates the sampling state of the switched-capacitor comparator unit, ensuring that the actual common-mode input voltage of the comparator equals the ideal common-mode input voltage. Its inputs include the common-mode reference voltage, the forward input voltage, the reverse input voltage, and the ideal common-mode input voltage. Its output is the common-mode bias voltage. This switched-capacitor comparator features a wide common-mode input range and fast response.

A comparison circuit is provided with: an adder that generates an output voltage by means of a plurality of capacitors; a comparator that performs a comparison operation using the output voltage generated by the adder; and an input voltage change-over switch that switches an input voltage input to one of the plurality of capacitors, and the comparator performs the following operations: a reference voltage for a comparison operation is determined by a capacitance ratio of the plurality of capacitors; an input voltage input to one capacitor is switched by an input voltage change-over switch, thereby switching a reference voltage for a comparison operation.

The invention relates to the technical field of metering calibration, and discloses a multi-voltage-class capacitance current tester calibration method based on a unified transformation ratio. The method comprises the following steps: screening a unified transformation ratio parameter satisfying a range constraint and an error constraint, obtaining a ratio error parameter of a corresponding electromagnetic voltage transformer to obtain a capacitance ratio error correction factor, and calculating a conversion coefficient under each voltage grade, and determining a primary side capacitance set value according to a preset primary side calibration capacitance value and the conversion coefficient, obtaining a secondary side output capacitance value of the standard capacitance box, and collecting a display capacitance value and a display capacitance current value. According to the invention, the conversion coefficient between the unified transformation ratio and the theoretical transformation ratio of each voltage grade is established, so that multi-voltage-grade calibration is covered by a single transformation ratio, the error component introduced by the ratio difference of the electromagnetic voltage transformer in the capacitance calibration process is reduced, and frequent replacement of equipment with different transformation ratios is avoided.

The invention relates to a control and sensor device (1) for controlling a door driven by a motor, comprising a first and a second sensor group comprising sensor electrodes (2a, 2b), a sensor strip element (3), in which the sensor electrodes (2a, 2b) are arranged, an actuating means (4) for actuating the sensor electrodes, wherein the actuated sensor electrodes form sensor regions, a measuring device (5), which is configured to detect capacitance values within the sensor regions and to create capacitance comparison values, a control device (6) which is configured to transmit a control signal as a function of the capacitance comparison values, wherein the sensor electrodes (2a, 2b) of the two sensor groups are each arranged spaced apart from one another without overlap along a longitudinal extent of the sensor strip element (3).

The application provides a kind of capacitance measurement circuit and system, circuit includes: switch circuit, switch circuit connects the capacitance to be measured and power supply, switch circuit is used to control the capacitance to be measured and charges through the output voltage of power supply.Comparison circuit, the first input end of comparison circuit is connected to the capacitance to be measured, the second input end of comparison circuit receives reference voltage, comparison circuit is used to output trigger signal in response to the voltage of the capacitance to be measured greater than or equal to reference voltage.Time counting circuit, time counting circuit is connected to comparison circuit, time counting circuit is used to determine charging duration in response to trigger signal.Control circuit, control circuit is used to determine the capacitance value of the capacitance to be measured according to charging duration, the output voltage of power supply, reference voltage.Thereby, the precision and efficiency of the application provided can be improved capacitance value measurement.

A semiconductor device includes a junction field effect transistor (JFET) including a source electrode, a drain electrode, and a gate electrode, and a metal oxide semiconductor field effect transistor (MOSFET) including a source electrode, a drain electrode, and a gate electrode. The JFET and the MOSFET are cascode-connected such that the source electrode of the JFET and the drain electrode of the MOSFET are electrically connected. A gate voltage dependency of the JFET or a capacitance ratio of a mirror capacitance of the MOSFET to an input capacitance of the MOSFET is adjusted in a predetermined range.

The invention belongs to the field of temperature detection, and particularly provides a switched capacitor amplifier sampling circuit for converting differential voltage into common-mode voltage, which has the advantages of high precision and low distortion and is used for replacing a fully differential amplifier module in a temperature detection circuit. The sampling circuit of the switched capacitor amplifier comprises a sampling stage and a holding (amplifying) stage, the sampling stage synchronously stores signals and imbalance, the amplifying stage reversely superposes and counteracts, equivalent imbalance is greatly reduced, drift can be neglected, additional calibration is not needed, imbalance is prevented from covering weak signals, and precision is greatly improved; meanwhile, non-overlapping clock control is adopted, switch cross conduction is avoided through an accurate time sequence, and non-ideal factor interference is reduced; moreover, the fixed gain is realized through the capacitance proportion, a precise resistor is not needed, the linearity depends on capacitance matching, the wide gain range is realized, and the performance is stable. And in cooperation with rail-to-rail output, a wider signal range can be covered, and the requirement for full-scene signal amplification is met.

The utility model provides a voltage control circuit which is coupled between an input voltage end and an amplifying circuit. The voltage control circuit comprises a comparator, a first transistor, an inductor and a first capacitor. The output end of the comparator is used for outputting control voltage. The first transistor is used for outputting a regulation voltage according to a control voltage. The first end of the first transistor is coupled with an input voltage end and is used for receiving an input voltage. The control end of the first transistor is coupled with the output end of the comparator and is used for receiving the control voltage. The second end of the first transistor is coupled to the amplifying circuit and is used for outputting a regulated voltage. The inductor is coupled between the second end of the first transistor and the amplifying circuit. The first capacitor is coupled to the second end of the first transistor. The voltage control circuit provided by the utility model can effectively reduce the misjudgment of the comparator in the voltage control circuit.

Embodiments of the present disclosure relate to estimating parameter values of an intermediate circuit. A method is disclosed, comprising: releasing electrical energy from an intermediate circuit comprised in an apparatus; measuring a direct current voltage; inputting the measured value to a parameter estimator for the intermediate circuit, wherein the parameter estimator comprises at least a first parameter and a second parameter, the value of the first parameter and the value of the second parameter being determined based on an equivalent capacitance value of the intermediate circuit, an equivalent resistance value of the intermediate circuit and an electrical load power value of the intermediate circuit, the parameter estimator outputting a value of a time constant of the intermediate circuit and a value of a power capacitance ratio; and storing the values at least temporarily for condition monitoring.

The application provides a multi-bit gallium oxide floating gate memory, a preparation method and application thereof. The memory comprises a gallium oxide layer, a source electrode and a drain electrode, a gate dielectric layer, a plurality of floating gates, a plurality of control gates, and a tunneling layer. The gallium oxide layer comprises a plurality of gallium oxide channels. The plurality of floating gates are arranged correspondingly to the gallium oxide channels. The plurality of control gates are arranged correspondingly on the plurality of floating gates. The tunneling layer is arranged between the control gates and the floating gates. The control gate-tunneling layer-floating gate forms a first capacitor. The floating gate-gate dielectric layer-gallium oxide channel forms a second capacitor. The capacitance ratios of the plurality of first-second capacitor groups are different. The plurality of control gates are in equal potential and are connected in parallel. The application uses a floating gate structure to control the opening of the channel, stabilizes the storage of the tunneling of electrons, accurately controls the tunneling voltage by adjusting the capacitance ratio, controls the step-by-step opening of the channel, realizes the accurate programming of multi-bit, changes the voltage size of the parallel control gate, and obtains different storage windows, and the complexity of the circuit is significantly reduced.

This invention relates to the field of novel graphene technology, and more particularly to a patterned zinc cobalt fluoride-doped fluorinated graphene, its preparation method, and its application. The patterned zinc cobalt fluoride-doped fluorinated graphene is prepared by this method. The method includes obtaining a zinc cobalt fluoride-doped fluorinated polyamic acid composite resin; coating the composite resin onto a carrier to form a coating layer; subjecting the coating layer to a stepped heating heat treatment to obtain a zinc cobalt fluoride-doped fluorinated polyimide film; cooling the film, then immersing it in water, and peeling it off from the carrier; and laser-processing the peeled film to form patterned zinc cobalt fluoride-doped fluorinated graphene. The application is that this patterned zinc cobalt fluoride-doped fluorinated graphene is used as an electrode material in the fabrication of micro supercapacitors. This invention can prepare patterned zinc cobalt fluoride-doped fluorinated graphene electrode materials with good capacitance characteristics and a large area-to-capacitance ratio.

The invention belongs to the technical field of semiconductor power devices, and provides a variable capacitance diode and a preparation method. The variable capacitance diode comprises an N + substrate, an N-epitaxial layer, a first P + doped region, a second P + doped region, a dielectric layer, a front metal layer and a back metal layer, wherein the first P + doped region is annularly arranged above the N-epitaxial layer; the second P + doped region is circularly arranged above the N-epitaxial layer and is concentric with the first P + doped region, the diameter of the second P + doped region is larger than the outer diameter of the first P + doped region, and the depth of the second P + doped region is smaller than that of the first P + doped region; the first P + doped region and the second P + doped region are formed through two times of injection and annealing, and the injection energy and the injection dosage of the first P + doped region are larger than those of the second P + doped region. The depletion layer is widened along with the increase of voltage, the depletion layer of the second P + doped region and the depletion layer of the first P + doped region tend to be consistent, so that the capacitance reduction effect is obvious, and the capacitance ratio of the variable capacitance diode is effectively increased.

A flash voltage-time converter based on reference voltage dynamic generation comprises a plurality of VTC sub-circuits working in parallel, each stage of VTC sub-circuit comprises a p structure circuit and an n structure circuit which are oppositely arranged and are the same in structure, a capacitor in each VTC structure is charged to high and low reference voltage in the sampling stage, and the voltage of each VTC sub-circuit is equal to that of each VTC sub-circuit. In the redistribution stage, charge redistribution is achieved through upper pole plate short circuit, all sub-circuits work at the same time, input signals are input into the input ends, and finally a set of time signals are output. The multi-path reference voltage is dynamically generated in a capacitor charge redistribution mode, a switched capacitor charge redistribution mode is adopted, quiescent current is not needed, all reference voltage path capacitor loads are consistent, the established characteristics are uniform, and bandwidth mismatch does not exist; charge operation is synchronous with a sampling process, and extra time sequence overhead is not introduced; the reference voltage value is accurately controlled through the capacitance proportion, the precision is high, the mismatch influence is small, and the method is particularly suitable for scenes with high requirements for the reference voltage establishment speed and precision of the flash voltage-time converter.