Method for reducing radiation intensity between chip and memory

Abstract

The invention provides a method for reducing radiation intensity between a chip and a memory. The method specifically comprises the following steps of equally dividing multiple data lines into M firstsignal line groups according to a data bit sequence; equally dividing multiple instruction lines and multiple address lines into N second signal line groups according to instruction bit and address bit sequences; transmitting instruction signals and address signals to the memory according to a sequence of the second signal line groups through the N second signal line groups by the chip, wherein each group of second signal lines have a transmission interval of first predetermined time; and transmitting data to the memory according to a sequence of the first signal line groups through the M first signal line groups by the chip, wherein each group of first signal lines have a transmission interval of second predetermined time. The technical scheme has the beneficial effects that the demand of a high-frequency current of a power end can be reduced, a capacitor quantity of a power part of the memory is reduced, and excessive transient current is avoided.

Description

Technical field [0001] The invention relates to the field of chip circuits, and in particular to a method for reducing the radiation intensity between a chip and a memory. Background technique [0002] Signal lines are generally connected between SOC chips (chips of integrated circuits) and DDR memory (double-rate synchronous dynamic random access memory), which specifically include command lines, address lines, and data lines. The instruction signal, address signal and data line data corresponding to the instruction line and address line are all output from the SOC chip at the same time, so the power supply capability is high, and the high-energy signal generated from this will radiate to the space, resulting in excessive radiation emission Or the margin is insufficient. In order to overcome the above shortcomings, the existing method is to strengthen the power supply area of ​​the chip and increase the power supply capacitance, series resistance on the signal line, and increas...

AI Technical Summary

Problems solved by technology

However, the above-mentioned methods have the following defects, high requirements on power supply performance, need to increase wiring space, and need to increase filter capacitors; DDR wiring area increases PCB (printed circuit board) can not be suitable for small structures; increase shielding cover cost

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