Semiconductor device and data storage system

Abstract

The invention relates to a semiconductor device and a data storage system. The semiconductor device includes: a plate layer; gate electrodes stacked in a first direction on the plate layer and spaced apart from each other, the gate electrodes including a first gate electrode and a second gate electrode on the first gate electrode; a horizontal insulating layer between the first gate electrode and the second gate electrode; a first channel structure extending through the first gate electrode in a first direction; second channel structures extending through the second gate electrodes in the first direction and electrically connected to the first channel structures, respectively; contact plugs extending through the horizontal insulating layer in the first direction and connected to the gate electrodes, respectively; a dummy vertical structure extending through the horizontal insulating layer in the first direction and surrounding the contact plug; and a cell region insulating layer covering an upper surface of the dummy vertical structure.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device having improved reliability and a data storage system including the semiconductor device having improved reliability. Background Art

[0002] Semiconductor devices capable of storing large amounts of data are required in data storage systems. Therefore, research has been conducted on methods for increasing the data storage capacity of semiconductor devices. For example, as a method for increasing the data storage capacity of semiconductor devices, a semiconductor device including three-dimensionally arranged storage cells rather than two-dimensionally arranged storage cells has been proposed. Summary of the invention

[0003] In general, according to some aspects, the subject matter of the present disclosure relates to a semiconductor device, the semiconductor device comprising: a first semiconductor structure, the first semiconductor structure comprising a substrate, a circuit device located on the substrate, and a circuit interconnection line located on the circuit device; and a second semiconductor structure located on the first semiconductor structure, the second semiconductor structure having a first region and a second region, wherein the second semiconductor structure comprises: a plate layer; a gate electrode, the gate electrode comprising a lower selection gate electrode, a storage gate electrode, and an upper selection gate electrode stacked in sequence from the plate layer along a first direction perpendicular to an upper surface of the plate layer and spaced apart from each other; a horizontal insulating layer, the horizontal insulating layer being located between the storage gate electrode and the upper selection gate electrode; a first channel structure, the first channel structure being located in the first region along a first direction perpendicular to an upper surface of the plate layer A first direction extends through the lower selection gate electrode and the storage gate electrode; a connection pad, which penetrates the horizontal insulating layer and is connected to the first channel structure; a second channel structure, which penetrates the upper selection gate electrode in the first region, is connected to the connection pad, and is electrically connected to the first channel structure respectively; a contact plug, which extends in the first direction through at least a portion of the gate electrodes in the second region and electrically connects the gate electrodes to a portion of the circuit interconnects; and a dummy vertical structure, which surrounds the contact plug in the second region and extends through the horizontal insulating layer in the first direction, and wherein the lower end of the dummy vertical structure is at a first height, and the lower end of the contact plug is at a second height lower than the first height.

[0004] In general, according to some other aspects, the subject matter of the present disclosure relates to a semiconductor device, which includes: a board layer; gate electrodes, which are stacked on the board layer along a first direction perpendicular to the upper surface of the board layer and spaced apart from each other, and include a first gate electrode and a second gate electrode located on the first gate electrode; a horizontal insulating layer, which is located between the first gate electrode and the second gate electrode and includes a nitride; a first channel structure, which extends through the first gate electrode in the first direction; a second channel structure, which extends through the second gate electrode in the first direction and is electrically connected to the first channel structure, respectively; contact plugs, which extend through the horizontal insulating layer in the first direction and are respectively connected to the gate electrodes; dummy vertical structures, which extend through the horizontal insulating layer in the first direction and surround the contact plugs; and a cell area insulating layer, which covers the upper surface of the dummy vertical structure.

[0005] In general, in some other aspects, the subject matter of the present disclosure relates to a data storage system, the data storage system comprising: a semiconductor storage device, the semiconductor storage device comprising a first semiconductor structure, a second semiconductor structure and an input / output pad, the first semiconductor structure comprising a circuit device, the second semiconductor structure being located on a surface of the first semiconductor structure, the input / output pad being electrically connected to the circuit device; and a controller, the controller being electrically connected to the semiconductor storage device through the input / output pad and controlling the semiconductor storage device, wherein the second semiconductor structure comprises: a board layer; gate electrodes, the gate electrodes being stacked on the board layer in a first direction perpendicular to an upper surface of the board layer and spaced apart from each other, and comprising a first gate electrode and a second gate electrode located on the first gate electrode; a horizontally insulated an insulating layer, a horizontal insulating layer located between the first gate electrode and the second gate electrode and including a nitride; a first channel structure, the first channel structure extending through the first gate electrode in a first direction; a second channel structure, the second channel structure extending through the second gate electrode in the first direction and being electrically connected to the first channel structure, respectively; contact plugs, a plurality of contact plugs extending through the horizontal insulating layer in the first direction and being connected to the gate electrodes, respectively; dummy vertical structures, the dummy vertical structures extending through the horizontal insulating layer in the first direction and surrounding the contact plugs; and a cell area insulating layer, the cell area insulating layer covering an upper surface of the dummy vertical structure, wherein the dummy vertical structure includes a material that is the same as that of the contact plug and has a length different from that of the contact plug. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The above and other aspects, features and advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0007] Figure 1A and Figure 1Bis a plan view illustrating an example of a semiconductor device.

[0008] Figure 2A and Figure 2B is a cross-sectional view illustrating an example of a semiconductor device.

[0009] FIG. 3A to FIG. 3C is an enlarged view of a portion illustrating an example of a semiconductor device.

[0010] FIG. 4A to FIG. 4C is an enlarged view of a portion illustrating another example of a semiconductor device.

[0011] Figure 5A and Figure 5B is a cross-sectional view illustrating another example of a semiconductor device.

[0012] Figure 6 is a cross-sectional view illustrating another example of a semiconductor device.

[0013] 7A to 7J is a cross-sectional view illustrating an example of a method of manufacturing a semiconductor device.

[0014] Figure 8 is a view illustrating an example of a data storage system including a semiconductor device.

[0015] Fig. 9 is a perspective view illustrating an example of a data storage system including a semiconductor device.

[0016] Fig.10 is a cross-sectional view illustrating an example of a semiconductor package. DETAILED DESCRIPTION

[0017] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings as follows.

[0018] Figure 1A and Figure 1B is a plan view illustrating an example of a semiconductor device. Figure 1B It's a picture. Figure 1A Magnified view of the “A” area.

[0019] Figure 2A and Figure 2B 1 are cross-sectional views illustrating an example of the semiconductor device taken along lines II′ and II-II′ in FIG. 1 .

[0020] FIG. 3A to FIG. 3C is an enlarged view of a portion illustrating an example of a semiconductor device. Figure 3A It's a picture. Figure 2A A magnified view of the "B" area in Figure 3B It's a picture. Figure 2B A magnified view of the "C" region in FIG. Figure 3C It's a picture. Figure 2B Magnified view of the “D” area.

[0021] refer to Figures 1A to 3C , the semiconductor device 100 includes a peripheral circuit region PERI and a memory cell region CELL, the peripheral circuit region PERI is a first semiconductor structure including a substrate 201, and the memory cell region CELL is a second semiconductor structure including a board layer 101. The memory cell region CELL may be disposed on the peripheral circuit region PERI. On the contrary, in some embodiments, the memory cell region CELL is disposed below the peripheral circuit region PERI.

[0022] The peripheral circuit region PERI may include a substrate 201 , an impurity region 205 and a device isolation layer 210 in the substrate 201 , a circuit device 220 disposed on the substrate 201 , a peripheral region insulating layer 290 , a circuit contact plug 270 , and a circuit interconnection line 280 .

[0023] The substrate 201 may have an upper surface extending in the X direction and the Y direction. In the substrate 201, the active region may be defined by the device isolation layer 210. An impurity region 205 including impurities may be provided in a portion of the active region. The substrate 201 may include a semiconductor material such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. The substrate 201 may be provided as a bulk wafer or an epitaxial layer.

[0024] The circuit devices 220 may include planar transistors. Each circuit device 220 may include a circuit gate dielectric layer 222, a spacer layer 224, and a circuit gate electrode 225. On both sides of the circuit gate electrode 225, impurity regions 205 may be provided in the substrate 201 as source / drain regions.

[0025] The peripheral region insulating layer 290 may be disposed on the circuit device 220 on the substrate 201. The peripheral region insulating layer 290 may include a plurality of insulating layers formed in different processes. The peripheral region insulating layer 290 may be formed of an insulating material.

[0026] The circuit contact plug 270 and the circuit interconnection line 280 may form a circuit interconnection structure electrically connected to the circuit device 220 and the impurity region 205. The circuit contact plug 270 may be cylindrical, and the circuit interconnection line 280 may be linear. An electrical signal may be applied to the circuit device 220 by the circuit contact plug 270 and the circuit interconnection line 280. In an area not shown, the circuit contact plug 270 may also be connected to the circuit gate electrode 225. The circuit interconnection line 280 may be connected to the circuit contact plug 270, may be linear, and may be arranged in multiple layers. The circuit contact plug 270 and the circuit interconnection line 280 may include a conductive material, such as tungsten (W), copper (Cu), aluminum (Al), etc., and each component may also include a diffusion barrier layer. In some embodiments, the number of layers of the circuit contact plug 270 and the circuit interconnection line 280 varies.

[0027] The memory cell region CELL may have a first region R1 and a second region R2, and may include: a source structure SS; a gate electrode 130, stacked on the source structure SS and forming a gate structure GS; an interlayer insulating layer 120, alternately stacked with the gate electrode 130; a first channel structure CH and a second channel structure SCH, arranged to penetrate the gate structure GS in the first region R1; a first isolation region MS, extending by partially penetrating the gate structure GS; a second isolation region US, penetrating a portion arranged in an upper portion of the gate electrode 130; a horizontal insulating layer 150 and a connecting pad 151, arranged between the first channel structure CH and the second channel structure SCH; a contact plug 170, connected to the gate electrode 130 in the second region R2 and extending vertically; and a dummy vertical structure 180, arranged around the contact plug 170 and penetrating the horizontal insulating layer 150. The memory cell region CELL may also include a horizontal sacrificial layer 110 arranged below the gate electrode 130 in the second region R2, a substrate insulating layer 121 arranged to penetrate the plate layer 101, an upper contact plug 172, a short pillar 185 located on the second channel structure SCH and the contact plug 170, and a first cell region insulating layer 192, a second cell region insulating layer 194, and a third cell region insulating layer 196 covering the gate electrode 130.

[0028] In the memory cell region CELL, in the first region R1, the gate electrode 130 may be vertically stacked and the first channel structure CH may be provided, and the memory cell may be provided in the first region R1. In the second region R2, the gate electrode 130 may extend to different lengths, and the second region R2 may be configured to electrically connect the memory cell to the peripheral circuit region PERI. The second region R2 may be provided on at least one end of the first region R1 along at least one direction (e.g., X direction).

[0029] The source structure SS may include a plate layer 101, a first horizontal conductive layer 102, and a second horizontal conductive layer 104 sequentially stacked in the first region R1. However, in some embodiments, the number of conductive layers included in the source structure SS is varied.

[0030] The plate layer 101 may be in a plate shape and may be used as at least a portion of a common source line of the semiconductor device 100. The plate layer 101 may have an upper surface extending in the X direction and the Y direction. The plate layer 101 may include a conductive material. For example, the plate layer 101 may include a semiconductor material such as a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI compound semiconductor. For example, the Group IV semiconductor may include silicon, germanium, or silicon germanium. The plate layer 101 may also include impurities. The plate layer 101 may be provided as a polycrystalline semiconductor layer such as a polysilicon layer or an epitaxial layer.

[0031] The first horizontal conductive layer 102 and the second horizontal conductive layer 104 may be sequentially stacked on the upper surface of the plate layer 101 in the first region R1. The first horizontal conductive layer 102 may not extend to the second region R2, and the second horizontal conductive layer 104 may extend to the second region R2. The first horizontal conductive layer 102 may be used as part of a common source line of the semiconductor device 100, and, for example, the first horizontal conductive layer 102 may be used as a common source line together with the plate layer 101. Figure 3C As illustrated, the first horizontal conductive layer 102 may be directly connected to the channel layer 140 around the channel layer 140. The second horizontal conductive layer 104 may contact the plate layer 101 in a partial region of the second region R2 where the first horizontal conductive layer 102 and the horizontal sacrificial layer 110 are not disposed.

[0032] The first horizontal conductive layer 102 and the second horizontal conductive layer 104 may include a semiconductor material such as polysilicon. In this case, at least the first horizontal conductive layer 102 may be doped with impurities having the same conductivity as that of the plate layer 101, and the second horizontal conductive layer 104 may be a doped layer or a layer including impurities diffused from the first horizontal conductive layer 102. However, the material of the second horizontal conductive layer 104 is not limited to a semiconductor material, and may be replaced with an insulating layer.

[0033] The horizontal sacrificial layer 110 may be disposed on the plate layer 101 at the same height as the first horizontal conductive layer 102 in at least a portion of the second region R2. The horizontal sacrificial layer 110 may include first horizontal sacrificial layers 111 and second horizontal sacrificial layers 112 alternately stacked on the second region R2 of the plate layer 101. The horizontal sacrificial layer 110 may be a layer remaining after a portion is replaced with the first horizontal conductive layer 102 in a process of manufacturing the semiconductor device 100.

[0034] The horizontal sacrificial layer 110 may include silicon oxide, silicon nitride, silicon carbide, or silicon oxynitride. The first horizontal sacrificial layer 111 and the second horizontal sacrificial layer 112 may include different insulating materials. For example, the first horizontal sacrificial layer 111 may be formed of the same material as the interlayer insulating layer 120, and the second horizontal sacrificial layer 112 may be formed of a material different from the material of the interlayer insulating layer 120.

[0035] The substrate insulating layer 121 may be disposed to penetrate the plate layer 101, the horizontal sacrificial layer 110, and the second horizontal conductive layer 104 in a portion of the second region R2. The substrate insulating layer 121 may be further disposed in the first region R1, and, for example, may be disposed in a region in which a through-path extending from the memory cell region CELL to the peripheral circuit region PERI is disposed. The upper surface of the substrate insulating layer 121 may be coplanar with the upper surface of the second horizontal conductive layer 104. The substrate insulating layer 121 may include an insulating material such as silicon oxide, silicon nitride, silicon carbide, or silicon oxynitride.

[0036] The gate electrodes 130 may be stacked vertically on the plate layer 101 and spaced apart from each other, and may form a gate structure GS together with the interlayer insulating layer 120. The gate structure GS may include a first stacking structure GS1 and a second stacking structure GS2 that may be stacked vertically. However, in some embodiments, the number of stacking structures included in the gate structure GS varies. For example, in some embodiments, the gate structure GS includes three or more stacking structures or may include a single stacking structure. The number of gate electrodes 130 included in the first stacking structure GS1 and the number of gate electrodes 130 included in the second stacking structure GS2 may be the same or different.

[0037] The gate electrode 130 may include a first upper gate electrode 130U1 forming a string selection transistor, a second upper gate electrode 130U2 forming an erase transistor, a storage gate electrode 130M forming a plurality of memory cells, and a lower gate electrode 130L forming an erase transistor and a ground selection transistor. The number of storage gate electrodes 130M included in the memory cell may be determined according to the capacity of the semiconductor device 100. In this specification, the second upper gate electrode 130U2, the storage gate electrode 130M, and the lower gate electrode 130L may be referred to as a first gate electrode, and the first upper gate electrode 130U1 may be referred to as a second gate electrode. One of the lower gate electrodes 130L and the first upper gate electrode 130U1 may also be referred to as a lower selection gate electrode and an upper selection gate electrode, respectively. In some embodiments, each of the number of the first upper gate electrodes 130U1, the number of the second upper gate electrodes 130U2, and the number of the lower gate electrodes 130L is 1 to 4 or more, and may have a structure that is the same as or different from that of the storage gate electrode 130M. In some embodiments, the second upper gate electrode 130U2 and / or the at least one lower gate electrode 130L are not provided. Portions of the gate electrode 130 (eg, the memory gate electrode 130M adjacent to the second upper gate electrode 130U2 or the lower gate electrode 130L) may be dummy gate electrodes.

[0038] The gate electrodes 130 may be vertically stacked and spaced apart from each other on the first region R1, may extend to different lengths from the first region R1 to the second region R2, and may form a step structure in a staircase form in the gate pad region GP. Figure 2A As shown, the gate electrode 130 may have a shape in which a predetermined depth is removed from the upper portion of one of the first stacked structure GS1 and the second stacked structure GS2 in the gate pad region GP. The gate pad region GP may be arranged not to overlap each other in the Z direction. On the gate pad region GP of the first stacked structure GS1, at least a portion of the gate electrode 130 included in the second stacked structure GS2 above and below may extend horizontally. In some embodiments, the gate pad region GP is sequentially arranged in the second stacked structure GS2, the first stacked structure GS1, and the second stacked structure GS2 along the X direction from the first region R1. However, in some embodiments, the arrangement type, arrangement order, and depth of the gate pad region GP vary. In some embodiments, the gate electrode 130 is not arranged on the gate pad region GP.

[0039] The gate electrode 130 may form a first step structure and a second step structure in an asymmetric form along the X direction in each gate pad region GP. The first step structure may be a step structure relatively adjacent to the first region R1 and may be a step structure whose height decreases in the X direction, while the second step structure may be set to be spaced a relatively large distance from the first region R1 and may be a step structure whose height increases in the X direction. For example, in each gate pad region GP, ​​the slope of the first step structure may be smaller than the slope of the second step structure in the first region R1. However, in some embodiments, the first step structure and the second step structure are symmetrically shaped. In the first step structure, the gate electrode 130 may be connected to the contact plug 170, and in the second step structure, the gate electrode 130 may form a dummy region or a dummy structure that is not connected to the contact plug 170. In some embodiments, the specific shape of the step structure and the number of gate electrodes 130 included in each step structure are not limited to Figure 2A In some embodiments, the gate electrode 130 is provided to have a step structure even in the Y direction.

[0040] like Figure 3A As illustrated, by the first step structure, among the gate electrodes 130, the lower gate electrode 130 may extend farther than the upper gate electrode 130, and each may have a contact region 130P exposed upward from the interlayer insulating layer 120. The gate electrode 130 may be connected to the contact plug 170 in the contact region 130P as an end region. The gate electrodes 130 other than the first upper gate electrode 130U1 may have an increased thickness in the contact region 130P. The thickness T2 of the gate electrode 130 in the contact region 130P may be greater than the thickness T1 in the region including the first region R1 where the other gate electrodes 130 are disposed on the upper surface.

[0041] The gate electrode 130 may include a metal material such as tungsten (W). In some embodiments, the gate electrode 130 may include polysilicon or a metal silicide material. In some embodiments, the gate electrode 130 may also include a diffusion barrier layer, and for example, the diffusion barrier layer may include tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), or a combination thereof.

[0042] The interlayer insulating layer 120 may be disposed between the gate electrodes 130. Similar to the gate electrodes 130, the interlayer insulating layers 120 may be spaced apart from each other in a direction perpendicular to the upper surface of the plate layer 101 and may extend in the X direction. The interlayer insulating layer 120 may include an insulating material such as silicon oxide or silicon nitride. In some embodiments, the thickness of each interlayer insulating layer 120 may vary.

[0043] The first channel structure CH may extend through the gate electrode 130 other than the first upper gate electrode 130U1 in the Z direction and may be connected to the plate layer 101. The first channel structure CH may form a memory cell string together with the second channel structure SCH and may be spaced apart from each other while forming rows and columns on the plate layer 101 in the first region R1. The first channel structure CH may be arranged to form a lattice pattern on the XY plane, or may be arranged in a zigzag pattern in one direction. The first channel structure CH may be columnar in shape and may have an inclined side surface whose width decreases toward the plate layer 101. Among the first channel structures CH, at least a portion of the first channel structure CH including the end portion of the first region R1 may be a dummy channel structure.

[0044] The first channel structure CH may include a lower channel structure CH1 and an upper channel structure CH2 that may be vertically stacked. The first channel structure CH may have a form in which the lower channel structure CH1 and the upper channel structure CH2 are connected to each other, and may have a curved portion due to a difference in width in a connection region. However, in some embodiments, the number of channel structures stacked in the Z direction varies.

[0045] Each of the first channel structures CH may include a first channel layer 140, a first gate dielectric layer 145, a first channel buried insulating layer 147, and a first channel pad 149 disposed in the lower channel hole. Figure 3C , the first channel layer 140 forms a ring shape around the inner first channel buried insulating layer 147, but in some embodiments, the first channel layer 140 has a columnar shape, such as a column or a prism column without the first channel buried insulating layer 147. The first channel layer 140 may be connected to the first horizontal conductive layer 102 in a lower portion. The first channel layer 140 may include a semiconductor material such as polysilicon or single crystal silicon.

[0046] The first gate dielectric layer 145 may be disposed between the gate electrode 130 and the first channel layer 140. Although not specifically illustrated, the first gate dielectric layer 145 may include a tunnel layer, a charge storage layer, and a blocking layer stacked in order from the first channel layer 140. The tunnel layer may tunnel charges into the charge storage layer, and may include, for example, silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiON), or a combination thereof. The charge storage layer may be a charge trapping layer or a floating gate conductive layer. The blocking layer may include silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4), silicon oxynitride (SiON), a high-k dielectric material, or a combination thereof. In some embodiments, at least a portion of the gate dielectric layer 145 extends along the gate electrode 130 in a horizontal direction.

[0047] The first channel pad 149 may be disposed only on an upper end portion of the upper channel structure CH2. The first channel pad 149 may include, for example, doped polysilicon.

[0048] The first channel layer 140, the first gate dielectric layer 145, and the first channel buried insulating layer 147 may be connected to each other between the lower channel structure CH1 and the upper channel structure CH2. A region where the lower channel structure CH1 and the upper channel structure CH2 are connected to each other may be a region where the interlayer insulating layer 120 is disposed.

[0049] The second channel structures SCH may penetrate the first upper gate electrode 130U1 , may extend in the Z direction, and may be connected to the first channel structures CH, respectively. The second channel structures SCH may be disposed on the first channel structures CH, respectively, and may be horizontally shifted from the first channel structures CH, but are not limited thereto.

[0050] like Figure 3B As shown, each second channel structure SCH includes a second channel layer 160, a second gate dielectric layer 165, a second channel buried insulating layer 167, and a second channel pad 169 disposed in the upper channel hole. The second channel layer 160 may be formed in a ring shape surrounding the second channel buried insulating layer 167 therein. The second channel layer 160 may be connected to the connection pad 151 in the lower portion, and may be electrically connected to the first channel layer 140 of the first channel structure CH through the connection pad 151.

[0051] The description of the material of each of the above-mentioned first channel layer 140, first gate dielectric layer 145, first channel buried insulating layer 147 and first channel pad 149 can be applied to the materials of the second channel layer 160, second gate dielectric layer 165, second channel buried insulating layer 167 and second channel pad 169, respectively.

[0052] The horizontal insulating layer 150 may be disposed between the first channel structure CH and the second channel structure SCH, and may extend horizontally in the first region R1 and the second region R2. The horizontal insulating layer 150 may be disposed between the first upper gate electrode 130U1 and the second upper gate electrode 130U2. The horizontal insulating layer 150 may be used as an etching stop layer when forming the second channel structure SCH, and may also be used when forming the connection pad 151.

[0053] The horizontal insulating layer 150 may include an insulating material and may include a material different from that of the second cell region insulating layer 194 and the third cell region insulating layer 196. The horizontal insulating layer 150 may be a hydrogen barrier layer and may include a material that blocks or reduces the diffusion of hydrogen (H). The horizontal insulating layer 150 may include a nitride and may include, for example, at least one of SiN, SiON, SiCN, and SiOCN.

[0054] The connection pad 151 may penetrate the horizontal insulating layer 150 between the first channel structure CH and the second channel structure SCH, and may electrically connect the first channel layer 140 to the second channel layer 160. The connection pad 151 may be formed by partially removing the horizontal insulating layer 150, and may have an upper surface coplanar with an upper surface of the horizontal insulating layer 150. The connection pad 151 may be disposed to be partially recessed into the first channel pad 149. However, in some embodiments, the specific arrangement of the connection pad 151 may vary. The connection pad 151 may include a conductive material, such as polysilicon.

[0055] The first isolation region MS may penetrate at least a portion of the gate electrode 130 and may extend in the X direction. The first isolation region MS may be disposed to penetrate the gate electrode 130 except for the first upper gate electrode 130U1. Figure 1A As shown, the first isolation regions MS may be arranged parallel to each other. Figure 2B As shown, the first isolation region MS may penetrate the gate electrode 130 stacked on the plate layer 101, may further penetrate the first horizontal conductive layer 102 and the second horizontal conductive layer 104 below, and may be connected to the plate layer 101. A portion of the isolation region MS may extend along the first region R1 and the second region R2 as an integrated region, and another portion may extend only to a portion of the second region R2, or may be intermittently disposed in the first region R1 and the second region R2. However, in some embodiments, the arrangement type and number of the first isolation region MS are not limited to Figure 1A An example is shown in the figure.

[0056] A gate isolation insulating layer 105 may be disposed in each first isolation region MS. The gate isolation insulating layer 105 may have a shape whose width may decrease toward the plate layer 101 due to a high aspect ratio. The gate isolation insulating layer 105 may include an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0057] like Figure 1AAs shown, the second isolation region US may extend in the X direction between the first isolation regions MS adjacent to each other. The second isolation region US may be disposed in a portion of the second region R2 and the first region R1. The second isolation region US may penetrate the first upper gate electrode 130U1 which is the uppermost gate electrode among the gate electrodes 130. Figure 2B As illustrated, the second isolation region US may divide the first upper gate electrode 130U1 in the Y direction. Portions of the second isolation region US may be disposed on the first isolation region MS.

[0058] Each second isolation region US may include an upper isolation insulating layer 103. The upper isolation insulating layer 103 may include an insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride.

[0059] The contact plug 170 may be connected to the contact region 130P of the gate electrode 130 in the gate pad region GP of the second region R2. The contact plug 170 may penetrate at least a portion of the first cell region insulating layer 192, the second cell region insulating layer 194, and the third cell region insulating layer 196, and may be respectively connected to the upwardly exposed contact regions 130P of the gate electrode 130. The contact plug 170 may penetrate the gate electrode 130 below the contact region 130P, may penetrate the second horizontal conductive layer 104, the horizontal sacrificial layer 110, and the board layer 101, and may be connected to the circuit interconnection line 280 in the peripheral circuit region PERI. The contact plug 170 may be spaced apart from the gate electrode 130 below the contact region 130P by the contact insulating layer 125. The contact plug 170 may be spaced apart from the board layer 101, the horizontal sacrificial layer 110, and the second horizontal conductive layer 104 by the substrate insulating layer 121. However, in some embodiments, the contact plug 170 is provided so as not to penetrate the gate electrode 130 , and in this case, the contact plug 170 may be connected to each of the contact regions 130P of the gate electrode 130 that are exposed upward.

[0060] The contact plugs 170 may have a shape corresponding to that of the channel structure CH. Each of the contact plugs 170 may include a lower region and an upper region that penetrate the first stack structure GS1 and the second stack structure GS2, respectively. Figure 3A As illustrated, the upper region has a bent portion BE whose width may be discontinuously changed below the horizontal insulating layer 150. The height of the bent portion BE may correspond to the height of the lower end of the dummy vertical structure 180. The lower region may further penetrate the substrate insulating layer 121. The lower region and the upper region may be in a cylindrical shape whose width may decrease toward the substrate 201 due to the aspect ratio. Each contact plug 170 may also include a landing region whose width may extend below the substrate insulating layer 121. However, in some embodiments, the contact plug 170 does not include a landing region.

[0061] like Figure 3A As shown, each contact plug 170 has a horizontally extending form in the contact region 130P. The contact plug 170 may include a vertical extension portion 170V extending in the Z direction and a horizontal extension portion 170H extending horizontally from the vertical extension portion 170V and contacting the gate electrode 130. The horizontal extension portion 170H may be arranged along the circumference of the vertical extension portion 170V, and the entire side surface may be surrounded by the gate electrode 130. The length from the side surface of the vertical extension portion 170V to the end of the horizontal extension portion 170H may be less than the length from the side surface of the vertical extension portion 170V to the outer side surface of the contact insulation layer 125. The contact plug 170 may be spaced apart from the gate electrode 130 (i.e., the gate electrode 130 that is not electrically connected) below the contact region 130P by the contact insulation layer 125.

[0062] The contact plug 170 may include at least one of the following conductive materials: for example, tungsten (W), copper (Cu), aluminum (Al), and alloys thereof. In some embodiments, the contact plug 170 includes a barrier layer extending along side and bottom surfaces, or may have an air gap therein.

[0063] The contact insulating layer 125 may be disposed to surround the side surface of each contact plug 170 below the contact region 130P. The contact insulating layer 125 may be disposed to be spaced apart from each other in the Z direction around each contact plug 170. The contact insulating layer 125 may be disposed at a height substantially the same as that of the gate electrode 130. The contact insulating layer 125 may include an insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride.

[0064] The upper contact plug 172 may be connected to the first upper gate electrode 130U1. Unlike the contact plug 170, the upper contact plug 172 may not penetrate the first upper gate electrode 130U1. The upper contact plug 172 may be provided to be partially recessed from the upper surface into the first upper gate electrode 130U1, or may be provided to contact the upper surface. The upper contact plug 172 may include a conductive material, and may include the same material as that of the contact plug 170, but the embodiment is not limited thereto.

[0065] The dummy vertical structure 180 may be disposed to surround the contact plug 170. Figure 1A and Figure 1BAs illustrated, the dummy vertical structure 180 may be disposed in the second region R2 in a circular shape in a plan view, and may be disposed to surround the contact plug 170 in a regular form. For example, four dummy vertical structures 180 may be disposed to surround the contact plug 170, but the embodiment is not limited thereto. Even in a region where the contact plugs 170 are spaced apart from each other in the X direction, the dummy vertical structures 180 may be regularly and continuously disposed. In some embodiments, the dummy vertical structure 180 is further disposed on the first isolation region MS1. The dummy vertical structure 180 is not limited to a circular shape in a plan view, and may be in various shapes such as a polygonal shape and an elliptical shape. As shown in FIG. Figure 3A As illustrated, the diameter D2 of the dummy vertical structure 180 is equal to or smaller than the diameter D1 of the contact plug 170 .

[0066] The dummy vertical structure 180 may be disposed on the gate electrode 130 other than the first upper gate electrode 130U1 and the first isolation region MS1 ​​outside the first upper gate electrode 130U1. Therefore, regardless of the arrangement of the gate electrode 130 and the first isolation region MS1, the arrangement form of the dummy vertical structure 180 on a plan view may vary within a range spaced apart from the contact plug 170.

[0067] like Figure 2A and Figure 3A As illustrated, the dummy vertical structure 180 may be disposed to penetrate the horizontal insulating layer 150. The upper end of the dummy vertical structure 180 may be disposed at a height substantially the same as the height of the upper end of the contact plug 170. The upper end of the dummy vertical structure 180 may be disposed at a height higher than the height of the upper surface of the first upper gate electrode 130U1. The dummy vertical structure 180 may have a second length L2 that is less than the first length L1 of the contact plug 170 in the Z direction. The lower end of the dummy vertical structure 180 may be disposed at a height higher than the height of the lower end of the contact plug 170. The lower end of the dummy vertical structure 180 may be disposed at a height equal to or lower than the height of the lower surface of the horizontal insulating layer 150, and may be disposed at a height higher than the height of the upper surface of the second upper gate electrode 130U2. The lower end of the dummy vertical structure 180 may be disposed at a height lower than the height of the lower end of the second channel structure SCH. The lower end of the dummy vertical structure 180 may be disposed at a height higher than the height of the uppermost surface of the storage gate electrode 130M. The dummy vertical structure 180 may overlap the first upper gate electrode 130U1 in a horizontal direction.

[0068] The upper surface of the dummy vertical structure 180 may be completely covered by the third cell region insulating layer 196. The entire surface of the dummy vertical structure 180 may be covered by an insulating material. The dummy vertical structure 180 may be disposed not to be connected to the conductive structure and may not perform an electrical function in the semiconductor device 100.

[0069] The dummy vertical structure 180 may include a conductive material, such as at least one of tungsten (W), copper (Cu), aluminum (Al), and alloys thereof. The dummy vertical structure 180 may be formed by the same deposition process as the deposition process for the contact plug 170, and may include the same material as the contact plug 170, such as a metal material. For example, when the contact plug 170 includes a barrier layer, the dummy vertical structure 180 may also include a barrier layer. However, in some embodiments, the dummy vertical structure 180 may be formed by a deposition process different from the deposition process for the contact plug 170, and in this case, the dummy vertical structure 180 may be formed of an insulating material.

[0070] In some embodiments, the dummy vertical structure 180 is disposed to penetrate the horizontal insulating layer 150, so that during the process of manufacturing the semiconductor device 100, a movement path of hydrogen (H) can be formed from above the horizontal insulating layer 150 to below the horizontal insulating layer 150. Therefore, hydrogen passivation can be performed on the lower structure including the first channel structure CH, so that defects such as dangling bonds and traps can be solved, and the reliability and electrical properties of the semiconductor device 100 can be improved.

[0071] The short column 185 may be included in a cell interconnect structure electrically connected to a memory cell in the memory cell region CELL. The short column 185 may be connected to the second channel structure SCH and the contact plug 170, and may be electrically connected to the first channel structure CH and the second channel structure SCH and the gate electrode 130. The short column 185 may not be disposed on the dummy vertical structure 180. In the illustrated example, the short column 185 may be in the shape of a plug, but the embodiment is not limited thereto, and the short column 185 may be in the shape of a line. In some embodiments, the number of plugs and interconnect lines included in the cell interconnect structure varies. The short column 185 may include a metal, such as tungsten (W), copper (Cu), or aluminum (Al).

[0072] The first cell region insulating layer 192, the second cell region insulating layer 194, and the third cell region insulating layer 196 may be disposed to cover the first stacked structure GS1 and the second stacked structure GS2. The first cell region insulating layer 192 may cover the first stacked structure GS1, the second cell region insulating layer 194 may cover a portion of the second stacked structure GS2 disposed below the horizontal insulating layer 150, and the third cell region insulating layer 196 may be disposed on the horizontal insulating layer 150 and may cover the side surface of the first upper gate electrode 130U1. The first cell region insulating layer 192, the second cell region insulating layer 194, and the third cell region insulating layer 196 may be formed of an insulating material or may include a plurality of insulating layers. When the first cell region insulating layer 192, the second cell region insulating layer 194, and the third cell region insulating layer 196 include the same material as the material of the interlayer insulating layer 120, the interface surface with the interlayer insulating layer 120 may not be obvious.

[0073] FIG. 4A to FIG. 4C is an enlarged view of a portion illustrating another example of a semiconductor device, which illustrates Figure 1B The corresponding plane.

[0074] refer to Figure 4A In the semiconductor device 100a, the arrangement of the dummy vertical structure 180 is different from Figure 1B In a plan view, the dummy vertical structure 180 is disposed on an end portion of the gate electrode 130. In some embodiments, the dummy vertical structure 180 may be disposed on the first isolation region MS1 ​​in the same form.

[0075] refer to Figure 4B In the semiconductor device 100b, the dummy vertical structure 180b is in a line shape extending in the X direction. However, in some embodiments, the length of the dummy vertical structure 180b in the X direction may vary. In some embodiments, the dummy vertical structure 180b may be further disposed on the first isolation region MS1.

[0076] refer to Figure 4C In the semiconductor device 100c, the dummy vertical structure 180c is in a line shape extending in the Y direction. The dummy vertical structure 180c may also extend to a region above the first isolation region MS1. However, in some embodiments, the length of the dummy vertical structure 180c in the Y direction may vary.

[0077] Figure 5A and Figure 5B is a cross-sectional view illustrating another example of a semiconductor device, which illustrates Figure 2A The corresponding cross section.

[0078] refer to Figure 5A , in the semiconductor device 100 d , the dummy vertical structure 180 d has a relatively long length.

[0079] The dummy vertical structure 180d may penetrate a portion of the gate electrode 130 and may extend downward. For example, the dummy vertical structure 180d may penetrate a portion of the gate electrode 130 included in the second stacked structure GS2 and may extend downward. However, in some embodiments, the number of gate electrodes 130 penetrated by the dummy vertical structure 180d may vary. Even in this case, the length of the dummy vertical structure 180d may be smaller than the length of the contact plug 170. The diameter of the dummy vertical structure 180d may be smaller than the diameter of the contact plug 170, but example embodiments thereof are not limited thereto.

[0080] In some embodiments, the dummy vertical structure 180d is connected to the plurality of gate electrodes 130, so that the dummy vertical structure 180d may be formed of an insulating material. In some embodiments, the dummy vertical structure 180d is disposed to penetrate only the second upper gate electrode 130U2 or to be recessed into only the second upper gate electrode 130U2. In this case, the dummy vertical structure 180d may include a conductive material or an insulating material.

[0081] refer to Figure 5B , in the semiconductor device 100e, the memory cell region CELL further includes a support structure DCH.

[0082] The support structure DCH may be disposed under the horizontal insulating layer 150 and may be configured to support the mold structure MS including the interlayer insulating layer 120 during the process of manufacturing the semiconductor device 100e (see Fig. 7E ). An upper end of the support structure DCH may be disposed at substantially the same height as that of an upper end of the first channel structure CH.

[0083] In some embodiments, at least a portion of the support structure DCH may be arranged to overlap the dummy vertical structure 180 in the Z direction. Figure 5B As shown in the enlarged view in FIG. 1 , the dummy vertical structure 180 can be configured to be partially recessed into the upper portion of the support structure DCH. In some embodiments, the relative sizes of the dummy vertical structure 180 and the support structure DCH vary. In some embodiments, the support structure DCH does not overlap with the dummy vertical structure 180 in the Z direction.

[0084] The support structure DCH may include an insulating material and may include, for example, silicon oxide, silicon nitride, silicon carbide or silicon oxynitride.

[0085] Figure 6 is a cross-sectional view illustrating another example of a semiconductor device.

[0086] refer to Figure 6 , the semiconductor device 100f includes a first semiconductor structure S1 and a second semiconductor structure S2 bonded to each other by a wafer bonding method.

[0087] For the above reference Figures 1A to 2B The description of the peripheral circuit region PERI described may be applicable to the first semiconductor structure S1. However, the first semiconductor structure S1 may also include a first bonding path 295, a first bonding metal layer 298, and a first bonding insulating layer 299 as a bonding structure. The first bonding path 295 may be disposed above the uppermost circuit interconnection line 280 and may be connected to the circuit interconnection line 280. At least a portion of the first bonding metal layer 298 may be connected to the first bonding path 295 on the first bonding path 295. The first bonding metal layer 298 may be connected to the second bonding metal layer 198 of the second semiconductor structure S2. The first bonding metal layer 298 may provide an electrical connection path according to the bonding between the first semiconductor structure S1 and the second semiconductor structure S2 together with the second bonding metal layer 198. A portion of the first bonding metal layer 298 may be provided only for bonding without being connected to the circuit interconnection line 280 below. The first bonding path 295 and the first bonding metal layer 298 may include a conductive material such as copper (Cu). The first bonding insulating layer 299 may be disposed to surround the first bonding metal layer 298. The first bonding insulating layer 299 may also serve as a diffusion barrier layer of the first bonding metal layer 298 , and may include, for example, at least one of SiN, SiON, SiCN, SiOC, SiOCN, and SiO.

[0088] As for the second semiconductor structure S2, unless otherwise indicated, Figures 1A to 3C The description of the memory cell region CELL described above may be applicable. The second semiconductor structure S2 may further include a cell interconnection line 187 as a cell interconnection structure, and may further include a second bonding via 195, a second bonding metal layer 198, and a second bonding insulating layer 199 as a bonding structure. The second semiconductor structure S2 may further include a passivation layer 106 covering the upper surface of the plate layer 101.

[0089] The cell interconnection line 187 may be connected to the short pillar 185. However, in some embodiments, the number of layers included in the cell interconnection structure and the arrangement of the plug and the interconnection line are varied. The cell interconnection line 187 may be formed of a conductive material and may include, for example, at least one of tungsten (W), aluminum (Al), and copper (Cu).

[0090] The second bonding via 195 and the second bonding metal layer 198 may be disposed under the cell interconnection line 187. The second bonding via 195 may connect the cell interconnection line 187 to the second bonding metal layer 198, and the second bonding metal layer 198 may be bonded to the first bonding metal layer 298 of the first semiconductor structure S1. The second bonding insulating layer 199 may be bonded and connected to the first bonding insulating layer 299 of the first semiconductor structure S1. The second bonding via 195 and the second bonding metal layer 198 may include a conductive material such as copper (Cu). The second bonding insulating layer 199 may include, for example, at least one of SiO, SiN, SiCN, SiOC, SiON, and SiOCN.

[0091] The first semiconductor structure S1 and the second semiconductor structure S2 may be bonded to each other through bonding between the first bonding metal layer 298 and the second bonding metal layer 198 and bonding between the first bonding insulating layer 299 and the second bonding insulating layer 199. The bonding between the first bonding metal layer 298 and the second bonding metal layer 198 may be, for example, copper (Cu) to copper (Cu) bonding, and the bonding between the first bonding insulating layer 299 and the second bonding insulating layer 199 may be, for example, dielectric to dielectric bonding, such as SiCN to SiCN bonding. The first semiconductor structure S1 and the second semiconductor structure S2 may be bonded to each other through hybrid bonding including copper (Cu) to copper (Cu) bonding and dielectric to dielectric bonding.

[0092] The passivation layer 106 may be disposed on the upper surface of the plate layer 101 and may protect the semiconductor device 100f. The passivation layer 106 may include an insulating material such as at least one of silicon oxide, silicon nitride, and silicon carbide. The substrate insulating layer 121 may be relatively widely disposed in the second region R2 to cover the upper end of the contact plug 170. However, in some embodiments, the arrangement form of the substrate insulating layer 121 varies within a range that electrically isolates the contact plug 170 from the plate layer 101.

[0093] In some embodiments, the second semiconductor structure S2 does not include the first horizontal conductive layer 102 and the second horizontal conductive layer 104 (see Figure 2A The first channel structure CHf may be formed in the first channel layer 140 (see Figure 3C ) is directly connected to the board layer 101 through the upper end when it is exposed. However, in some embodiments, the form of the electrical connection between the first channel structure CHf and the common source line may be varied, and the first channel structure and the source structure may have the same Figure 2A The same structure as in the example implementation.

[0094] 7A to 7J is a cross-sectional view illustrating an example of a method of manufacturing a semiconductor device, and illustrates Figure 2AThe corresponding area.

[0095] refer to Fig. 7A , the circuit device 220 , the circuit interconnection structure and the peripheral region insulating layer 290 included in the peripheral circuit region PERI are formed on the substrate 201 .

[0096] First, a device isolation layer 210 may be formed in the substrate 201, and a circuit gate dielectric layer 222 and a circuit gate electrode 225 may be sequentially formed on the substrate 201. The device isolation layer 210 may be formed by, for example, a shallow trench isolation (STI) process. The circuit gate dielectric layer 222 and the circuit gate electrode 225 may be formed using atomic layer deposition (ALD) or chemical vapor deposition (CVD). The circuit gate dielectric layer 222 may be formed of silicon oxide, and the circuit gate electrode 225 may be formed of at least one of polysilicon or a metal silicide layer, but the embodiment is not limited thereto. Thereafter, a spacer layer 224 and an impurity region 205 may be formed on both sidewalls of the circuit gate dielectric layer 222 and the circuit gate electrode 225. In some embodiments, the spacer layer 224 includes a plurality of layers. The impurity region 205 may be formed by performing an ion implantation process.

[0097] The circuit contact plug 270 of the circuit interconnection structure may be formed by forming part of the peripheral region insulating layer 290, removing the part of the peripheral region insulating layer 290 by etching, and filling a conductive material therein. The circuit interconnection line 280 may be formed, for example, by depositing a conductive material and patterning the line.

[0098] The peripheral region insulating layer 290 may include a plurality of insulating layers. The peripheral region insulating layer 290 may be provided as a part in each process of forming a circuit interconnection structure. Thus, a peripheral circuit region PERI may be formed.

[0099] refer to Figure 7B A plate layer 101, a horizontal sacrificial layer 110, a second horizontal conductive layer 104, and a substrate insulating layer 121 on which a memory cell region CELL is disposed are formed on the peripheral circuit region PERI, and a mold structure MS, first and second channel sacrificial layers 116a and 116b, and first and second contact sacrificial layers 119a and 119b are formed.

[0100] The plate layer 101 may be formed on the peripheral region insulating layer 290. The plate layer 101 may be formed of, for example, polysilicon and may be formed through a CVD process. The polysilicon included in the plate layer 101 may include impurities.

[0101] When the board layer 101 is formed, the landing pad 171 may be formed together on the uppermost circuit interconnection line 280. The landing pad 171 may be formed in a region where the contact plug 170 (see FIG. 1 ) is disposed. Figure 2A ). First, before forming the board layer 101, an opening may be formed by partially removing the peripheral region insulating layer 290 on the uppermost circuit interconnection line 280. When the board layer 101 is formed, the landing pad 171 may be formed by filling the opening with a material included in the board layer 101. These openings may be formed together with, for example, a ground via for connecting the board layer 101 and the circuit interconnection structure.

[0102] The first horizontal sacrificial layer 111 and the second horizontal sacrificial layer 112 included in the horizontal sacrificial layer 110 may be alternately stacked on the board layer 101. Parts of the horizontal sacrificial layer 110 may be replaced by subsequent processes. Figure 2B The first horizontal conductive layer 102 in the first horizontal conductive layer 102. The first horizontal sacrificial layer 111 may include a material different from that of the second horizontal sacrificial layer 112. For example, the first horizontal sacrificial layer 111 may be formed of the same material as that of the interlayer insulating layer 120, and the second horizontal sacrificial layer 112 may be formed of the same material as that of the subsequent sacrificial insulating layer 118. Portions of the horizontal sacrificial layer 110 may be removed by a patterning process in a partial region (e.g., the second region R2).

[0103] The second horizontal conductive layer 104 may be formed on the horizontal sacrificial layer 110 , and may contact the board layer 101 from a region where the horizontal sacrificial layer 110 is removed.

[0104] The substrate insulating layer 121 may be formed to penetrate the board layer 101 in partial regions including the regions where the contact plugs 170 (see Figure 2A ) region. The substrate insulating layer 121 may be formed by removing portions of the plate layer 101, the horizontal sacrificial layer 110, and the second horizontal conductive layer 104 and filling an insulating material therein. After the insulating material is filled, a planarization process may be further performed using a chemical mechanical polishing or CMP process. Thus, the upper surface of the substrate insulating layer 121 may be substantially coplanar with the upper surface of the second horizontal conductive layer 104.

[0105] Thereafter, a first mold structure MS1 of the mold structure MS may be formed, and a first channel sacrificial layer 116 a and a first contact sacrificial layer 119 a penetrating the first mold structure MS1 may be formed.

[0106] The first mold structure MS1 may be provided with the first stack structure GS1 (see Figure 2A ) is formed on the second horizontal conductive layer 104 and the substrate insulating layer 121.

[0107] At least a portion of the sacrificial insulating layer 118 may be replaced by the gate electrode 130 through a subsequent process (see Figure 2A ) portion. The sacrificial insulating layer 118 may be formed of a material different from that of the interlayer insulating layer 120, and may be formed of a material having an etching selectivity to the interlayer insulating layer 120 under specific etching conditions. For example, the interlayer insulating layer 120 may be formed of at least one of silicon oxide and silicon nitride, and the sacrificial insulating layer 118 may be formed of a material different from that of the interlayer insulating layer 120 selected from silicon, silicon oxide, silicon carbide, and silicon nitride. The number of interlayer insulating layers 120 and sacrificial insulating layers 118 may vary from the illustrated example.

[0108] The gate pad region GP may be formed by repeatedly performing a photolithography process and an etching process on the sacrificial insulating layer 118 and the interlayer insulating layer 120. The gate pad region GP may be formed in the second region R2, and the upper sacrificial insulating layer 118 may include a region extending shorter than the lower sacrificial insulating layer 118. In the gate pad region GP, ​​an asymmetric step structure may be formed so that the upper surfaces and ends of the plurality of sacrificial insulating layers 118 may be exposed upward. However, in some embodiments, the specific form of the gate pad region GP varies. By further forming a sacrificial insulating layer 118 on the step structure of the gate pad region GP, ​​the sacrificial insulating layer 118 disposed on each region may be formed to have a relatively large thickness.

[0109] Thereafter, a first cell region insulating layer 192 covering the first mold structure MS1 may be formed. A first channel sacrificial layer 116a may be formed in the first region R1 at a position adjacent to the channel structure CH (see Figure 2A ) corresponding to the position. The first contact sacrificial layer 119a may be formed in the second region R2 at a position corresponding to the contact plug 170 (see Figure 2A The first channel sacrificial layer 116a and the first contact sacrificial layer 119a may be formed at the same time.

[0110] The first channel sacrificial layer 116a and the first contact sacrificial layer 119a may be formed by forming a first hole penetrating the first mold structure MS1, depositing a sacrificial layer material on the first hole, and performing a planarization process. The first channel sacrificial layer 116a and the first contact sacrificial layer 119a may include, for example, at least one of TiN and polysilicon.

[0111] The second mold structure MS2 , the second channel sacrificial layer 116 b , and the second contact sacrificial layer 119 b may be formed on the first mold structure MS1 in the same manner as in a process for forming each of the first mold structure MS1 , the first channel sacrificial layer 116 a , and the first contact sacrificial layer 119 a .

[0112] refer to Figure 7C , a first channel structure CH penetrating the mold structure MS is formed.

[0113] The first channel structure CH may be formed by forming a lower channel hole by removing the first channel sacrificial layer 116a and the second channel sacrificial layer 116b, and sequentially depositing at least a portion of the first gate dielectric layer 145, the first channel layer 140, the first channel buried insulating layer 147, and the first channel pad 149 in the lower channel hole.

[0114] The first gate dielectric layer 145 may be formed to have a uniform thickness using an ALD or CVD process. In this process, all or part of the first gate dielectric layer 145 may be formed, and in this process, a portion extending perpendicularly to the plate layer 101 along the first channel structure CH may be formed. The first channel layer 140 may be formed on the first gate dielectric layer 145 within the lower channel hole. The first channel buried insulating layer 147 may be formed to fill the lower channel hole and may be an insulating material. The first channel pad 149 may be formed of a conductive material (e.g., polysilicon).

[0115] refer to Fig.7D , the first contact hole OH is formed by removing the first contact sacrificial layer 119a and the second contact sacrificial layer 119b.

[0116] The first contact hole OH may be formed by selectively removing the first contact sacrificial layer 119a and the second contact sacrificial layer 119b and further removing the exposed landing pad 171. The circuit interconnection line 280 may be exposed through the bottom surface of the first contact hole OH. In some embodiments, the landing pad 171 is not removed in this process but may be removed in a subsequent process.

[0117] refer to Fig. 7E , a preliminary contact insulating layer 125P and a vertical sacrificial layer 191 are formed on the first contact hole OH, and the sacrificial insulating layer 118 may be removed.

[0118] First, a portion of the sacrificial insulating layer 118 exposed by the first contact hole OH may be removed. A contact tunnel portion may be formed by removing the sacrificial insulating layer 118 to a predetermined length around the first contact hole OH. The contact tunnel portion may be formed to have a relatively short length in the uppermost sacrificial insulating layer 118 and a relatively long length in the lower sacrificial insulating layer 118.

[0119] Specifically, first, on the contrary, the contact tunnel portion can be formed relatively long in the uppermost sacrificial insulating layer 118, which may be because the uppermost sacrificial insulating layer 118 may include an area with a relatively faster etching rate than the lower sacrificial insulating layer 118. Thereafter, a sacrificial layer may be formed in the first contact hole OH and the contact tunnel portion. The sacrificial layer may be formed of a material having an etching rate slower than that of the sacrificial insulating layer 118. Thereafter, a portion of the sacrificial layer and the sacrificial insulating layer 118 may be removed. In this case, the sacrificial layer may remain in the uppermost portion, the sacrificial layer may be removed from the lower portion, and a portion of the sacrificial insulating layer 118 may be removed. Therefore, in the end, the contact tunnel portion may be formed to have a relatively short length in the uppermost sacrificial insulating layer 118.

[0120] The preliminary contact insulating layer 125P may be formed by depositing an insulating material in the first contact hole OH and the contact channel portion. The preliminary contact insulating layer 125P may be formed on the sidewall of the first contact hole OH and may fill the contact tunnel portion. In the uppermost sacrificial insulating layer 118, the preliminary contact insulating layer 125P may not completely fill the contact tunnel portion.

[0121] The vertical sacrificial layer 191 may fill the first contact hole OH and the uppermost contact tunnel portion. The vertical sacrificial layer 191 may include a material different from that of the preliminary contact insulating layer 125P, and may include, for example, polysilicon.

[0122] Thereafter, the first isolation region MS (see Figure 1A and Figure 2B ) is formed in a position of the first region R1 through the sacrificial insulating layer 118 and the interlayer insulating layer 120 and extending to the plate layer 101. Thereafter, the horizontal sacrificial layer 110 may be selectively removed from the first region R1 by performing an etch-back process while forming a sacrificial spacer layer in the opening, and the exposed portion of the first gate dielectric layer 145 may be removed together. After forming the first horizontal conductive layer 102 by depositing a conductive material on the region from which the horizontal sacrificial layer 110 is removed, the sacrificial spacer layer may be removed from the opening. Through this process, the first horizontal conductive layer 102 may be formed in the first region R1.

[0123] Thereafter, the sacrificial insulating layer 118 may be removed selectively with respect to the interlayer insulating layer 120 , the second horizontal conductive layer 104 , and the preliminary contact insulating layer 125P using, for example, wet etching.

[0124] refer to Figure 7F , a portion of the gate electrode 130 is formed.

[0125] The gate electrode 130 may be formed by depositing a conductive material in the region from which the sacrificial insulating layer 118 is removed. The conductive material may include a metal, polysilicon, or a metal silicide material. In some embodiments, a portion of the first gate dielectric layer 145 is preferentially formed before forming the gate electrode 130.

[0126] After forming the gate electrode 130, a gate isolation insulating layer 105 may be formed in the opening formed to correspond to the first isolation region MS (see Figure 2B ).

[0127] refer to Figure 7G , the horizontal insulating layer 150 and the first upper gate electrode 130U1 are formed, and the second channel structure SCH penetrating the first upper gate electrode 130U1 is formed.

[0128] A horizontal insulating layer 150 may be formed on the first channel structure CH. Thereafter, a third cell region insulating layer 196 may be partially formed, and the first upper gate electrode 130U1 may be patterned. The first upper gate electrode 130U1 may include a material different from other gate electrodes 130, but the embodiment is not limited thereto. For example, the first upper gate electrode 130U1 may include polysilicon. Thereafter, a third cell region insulating layer 196 may be further formed.

[0129] In order to form the second channel structure SCH, first, an upper channel hole penetrating the first upper gate electrode 130U1 may be formed, and a second channel dielectric layer 165 and a sacrificial layer may be formed in order. Thereafter, a lower hole penetrating the second channel dielectric layer 165 and the sacrificial layer and extending from the bottom surface of the upper channel hole to the horizontal insulating layer 150 may be formed, and the first channel pad 149 may be exposed by partially removing the horizontal insulating layer 150 exposed by the lower hole. A connecting pad 151 may be formed in the region from which the horizontal insulating layer 150 is removed, the sacrificial layer may be removed, and a second channel layer 160, a second channel buried insulating layer 167, and a second channel pad 169 may be formed in order in each upper channel hole, thereby forming the second channel structure SCH. Each layer may be formed in the same manner as in the first channel structure CH. The lower end of the second channel layer 160 may be connected to the connecting pad 151.

[0130] refer to Figure 7H , a first opening OP1 , a second opening OP2 , and a third opening OP3 are formed.

[0131] The first opening OP1, the second opening OP2, and the third opening OP3 may be formed to penetrate at least a portion of the third cell region insulating layer 196. The first opening OP1 may be formed at a position corresponding to the third cell region insulating layer 196. Figure 2AThe position corresponding to the dummy vertical structure 180 in the third unit area insulating layer 196 and the horizontal insulating layer 150 is penetrated. The second opening OP2 can be formed to penetrate the third unit area insulating layer 196 and the horizontal insulating layer 150 so that the preliminary contact insulating layer 125P and the vertical sacrificial layer 191 can be exposed. The third opening OP3 can be formed so that the first upper gate electrode 130U1 can be exposed. The first opening OP1 and the second opening OP2 can be formed at the same time, and the third opening OP3 can be formed at the same time as the first opening OP1 and the second opening OP2 or can be formed in a separate process. In some embodiments, the third opening OP3 is formed in a subsequent process.

[0132] refer to Fig.7I , the second contact hole OH′ is formed by removing the vertical sacrificial layer 191 exposed through the second opening OP2 and partially removing the preliminary contact insulating layer 125P.

[0133] The vertical sacrificial layer 191 may be selectively removed relative to the interlayer insulating layer 120 and the gate electrode 130. After removing the vertical sacrificial layer 191, the exposed portion of the preliminary contact insulating layer 125P may also be removed. In this case, the entire preliminary contact insulating layer 125P may be removed from the contact region 130P (see Figure 3A ) is removed from the uppermost gate electrode 130 corresponding to the preliminary contact insulating layer 125P, and may remain thereunder and a contact insulating layer 125 may be formed. In the contact region 130P, when the first gate dielectric layer 145 is exposed after the preliminary contact insulating layer 125P is removed, the first gate dielectric layer 145 may also be removed so that the side surface of the gate electrode 130 may be exposed.

[0134] refer to Figure 7J , the contact plug 170 , the dummy vertical structure 180 , and the upper contact plug 172 are formed.

[0135] The contact plug 170, the dummy vertical structure 180, and the upper contact plug 172 may be formed by depositing a conductive material in the second contact hole OH' and the first and third openings OP1 and OP3. The contact plug 170 may be formed to have a horizontal extension portion 170H extending horizontally from the contact region 130P (see Figure 3A ), thereby being physically and electrically connected to the gate electrode 130. The dummy vertical structure 180 may be spaced apart from the gate electrode 130 and may form an electrically floating state. The contact plug 170 and the dummy vertical structure 180 may be formed together and may include the same material. The upper contact plug 172 may be deposited together with the contact plug 170 and the dummy vertical structure 180, or may be deposited in a separate process.

[0136] After that, refer to Figure 2AThe semiconductor device 100 may be manufactured by forming a contact plug 170 and a short pillar 185 connected to the upper end of the second channel structure SCH. The short pillar 185 may not be formed on the dummy vertical structure 180, and the upper surface of the dummy vertical structure 180 may be covered by a third cell region insulating layer 196 formed additionally.

[0137] When forming an insulating layer such as the third cell region insulating layer 196, hydrogen may exist in the insulating layer. When forming a cell interconnect structure including the short pillar 185, such hydrogen may diffuse to the area below the horizontal insulating layer 150 and may hydrogen-passivate the lower structure disposed below the horizontal insulating layer 150. In the semiconductor device 100, by forming a dummy vertical structure 180 penetrating the horizontal insulating layer 150 as a hydrogen barrier layer, a hydrogen diffusion path can be secured. Therefore, defects in the lower structure including the first channel structure CH can be resolved.

[0138] Figure 8 is a view illustrating an example of a data storage system including a semiconductor device.

[0139] refer to Figure 8 , the data storage system 1000 includes a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100. The data storage system 1000 may be implemented as a storage device including one or more semiconductor devices 1100 or an electronic device including a storage device. For example, the data storage system 1000 may be implemented as a solid state drive (SSD) device, a universal serial bus (USB), a computing system, a medical device, or a communication device including one or more semiconductor devices 1100.

[0140] The semiconductor device 1100 may be implemented as a nonvolatile memory device, such as, for example, the nonvolatile memory device described in the foregoing example embodiments with reference to FIGS. 1 to 13 . Figure 6 The NAND flash memory device described. The semiconductor device 1100 may include a first structure 1100F and a second structure 1100S located on the first structure 1100F. In some embodiments, the first structure 1100F is disposed on one side of the second structure 1100S. The first structure 1100F may be implemented as a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and a logic circuit 1130. The second structure 1100S may be implemented as a memory cell structure including: a bit line BL; a common source line CSL; a word line WL disposed between the bit line BL and the common source line CSL, a first gate upper line UL1 and a second gate upper line UL2, a first gate lower line LL1 and a second gate lower line LL2, and a memory cell string CSTR.

[0141] In the second structure 1100S, each memory cell string CSTR may include lower transistors LT1 and LT2 adjacent to a common source line CSL, upper transistors UT1 and UT2 adjacent to a bit line BL, and a plurality of memory cell transistors MCT disposed between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. The number of the lower transistors LT1 and LT2 and the number of the upper transistors UT1 and UT2 may vary.

[0142] In some embodiments, the upper transistors UT1 and UT2 include string selection transistors, and the lower transistors LT1 and LT2 may include ground selection transistors. The gate lower lines LL1 and LL2 may be configured as gate electrodes of the lower transistors LT1 and LT2, respectively. The word line WL may be configured as a gate electrode of the memory cell transistor MCT, and the gate upper lines UL1 and UL2 may be configured as gate electrodes of the upper transistors UT1 and UT2, respectively.

[0143] In some embodiments, the lower transistors LT1 and LT2 include a lower erase control transistor LT1 and a ground selection transistor LT2 connected in series to each other. The upper transistors UT1 and UT2 may include a string selection transistor UT1 and an upper erase control transistor UT2 connected in series to each other. At least one of the lower erase control transistor LT1 and the upper erase control transistor UT2 may be used in an erase operation to erase data stored in the memory cell transistor MCT using a GIDL phenomenon.

[0144] The common source line CSL, the first and second gate lower lines LL1 and LL2, the word lines WL, and the first and second gate upper lines UL1 and UL2 may be electrically connected to the decoder circuit 1110 through a first connection interconnect 1115 extending from the first structure 1100F to the second structure 1100S. The bit line BL may be electrically connected to the page buffer 1120 through a second connection interconnect 1125 extending from the first structure 110F to the second structure 1100S.

[0145] In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 may perform a control operation on at least one selected memory cell transistor among the plurality of memory cell transistors MCT. The decoder circuit 1110 and the page buffer 1120 may be controlled by a logic circuit 1130. The semiconductor device 1100 may communicate with the controller 1200 through an input / output pad 1101 electrically connected to the logic circuit 1130. The input / output pad 1101 may be electrically connected to the logic circuit 1130 through an input / output connection line 1135 extending from the first structure 1100F to the second structure 1100S.

[0146] The controller 1200 may include a processor 1210 , a NAND controller 1220 , and a host interface 1230 . In some embodiments, the data storage system 1000 includes a plurality of semiconductor devices 1100 , and in this case, the controller 1200 may control the plurality of semiconductor devices 1100 .

[0147] The processor 1210 may control the overall operation of the data storage system 1000 including the controller 1200. The processor 1210 may operate according to a predetermined firmware, and may access the semiconductor device 1100 by controlling the NAND controller 1220. The NAND controller 1220 may include a controller interface 1221 that processes communication with the semiconductor device 1100. Through the controller interface 1221, a control command for controlling the semiconductor device 1100, data to be written to the memory cell transistor MCT of the semiconductor device 1100, and data to be read from the memory cell transistor MCT of the semiconductor device 1100 may be sent. The host interface 1230 may provide a communication function between the data storage system 1000 and an external host. When a control command from an external host is received through the host interface 1230, the processor 1210 may control the semiconductor device 1100 in response to the control command.

[0148] Fig. 9 is a perspective view illustrating an example of a data storage system including a semiconductor device.

[0149] refer to Fig. 9 , the data storage system 2000 includes a main board 2001, a controller 2002 mounted on the main board 2001, one or more semiconductor packages 2003, and a DRAM 2004. The semiconductor package 2003 and the DRAM 2004 are connected to the controller 2002 through an interconnection pattern 2005 formed on the main board 2001.

[0150] The mainboard 2001 may include a connector 2006 having a plurality of pins coupled to an external host. The number and arrangement of the plurality of pins in the connector 2006 may vary depending on the communication interface between the data storage system 2000 and the external host. In some embodiments, the data storage system 2000 communicates with the external host according to one of the interfaces among the Universal Serial Bus (USB), the Peripheral Component Interconnect Express (PCI-Express), the Serial Advanced Technology Attachment (SATA), and the M-Phy for Universal Flash Memory (UFS). In some embodiments, the data storage system 2000 operates by power supplied from the external host by the connector 2006. The data storage system 2000 may also include a power management integrated circuit (PMIC) for distributing the power supplied from the external host to the controller 2002 and the semiconductor package 2003.

[0151] The controller 2002 may write data to or read data from the semiconductor package 2003 , and may improve the operation speed of the data storage system 2000 .

[0152] The DRAM 2004 may be configured as a buffer memory for alleviating a speed difference between the semiconductor package 2003 as a data storage space and an external host. The DRAM 2004 included in the data storage system 2000 may operate as a cache memory and may provide a space for temporarily storing data in a control operation for the semiconductor package 2003. When the data storage system 2000 may include the DRAM 2004, the controller 2002 may further include a DRAM controller for controlling the DRAM 2004 in addition to the NAND controller for controlling the semiconductor package 2003.

[0153] The semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may be configured as a semiconductor package including a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a package substrate 2100, a semiconductor chip 2200 located on the package substrate 2100, an adhesive layer 2300 respectively disposed on the lower surface of the semiconductor chip 2200, a connection structure 2400 electrically connecting the semiconductor chip 2200 to the package substrate 2100, and a mold layer 2500 covering the semiconductor chip 2200 and the connection structure 2400 on the package substrate 2100.

[0154] The package substrate 2100 may be configured as a printed circuit board including the package pads 2130. Each semiconductor chip 2200 may include an input / output pad 2210. The input / output pad 2210 may correspond to Figure 8 Each semiconductor chip 2200 may include a gate stack structure 3210 and a channel structure 3220. Each semiconductor chip 2200 may include the gate stack structure 3210 and the channel structure 3220 described in the foregoing example embodiments with reference to FIGS. 1 to 3. Figure 6 A semiconductor device is described.

[0155] In some embodiments, the connection structure 2400 is configured as a bonding wire that electrically connects the input / output pad 2210 to the package on-pad 2130. Therefore, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other by a bonding wire method, and may be electrically connected to the package on-pad 2130 of the package substrate 2100. In some embodiments, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 are electrically connected to each other by a connection structure including a through-hole electrode (TSV) instead of the connection structure 2400 of the bonding wire method.

[0156] In some embodiments, the controller 2002 and the semiconductor chip 2200 are included in a single package. In some embodiments, the controller 2002 and the semiconductor chip 2200 are mounted on an interposer substrate different from the mainboard 2001, and the controller 2002 and the semiconductor chip 2200 can be connected to each other through interconnections formed on the interposer substrate.

[0157] Fig.10 is a cross-sectional view illustrating an example of a semiconductor package. Fig. 9 FIG. 2 is an example implementation of a semiconductor package 2003 taken along line III-III′ in FIG.

[0158] refer to Fig.10 In the semiconductor package 2003, the package substrate 2100 is implemented as a printed circuit substrate. The package substrate 2100 includes a package substrate main body 2120, a package upper pad 2130 (see FIG. 213 ) disposed on the upper surface of the package substrate main body 2120, and a package upper pad 2130 (see FIG. 214 ). Fig. 9 ), a lower pad 2125 disposed on or exposed through the lower surface of the package substrate main body portion 2120, and an internal interconnect 2135 in the package substrate main body portion 2120 that electrically connects the upper pad 2130 to the lower pad 2125. Fig. 9 As illustrated, the lower pad 2125 is connected to the interconnection pattern 2005 of the main board 2001 of the data storage system 2000 through the conductive connection portion 2800 .

[0159] Each semiconductor chip 2200 may include a semiconductor substrate 3010 and a first structure 3100 and a second structure 3200 sequentially stacked on the semiconductor substrate 3010. The first structure 3100 may include a peripheral circuit region having a peripheral interconnect 3110. The second structure 3200 may include a common source line 3205, a gate stack structure 3210 located on the common source line 3205, a channel structure 3220 penetrating the gate stack structure 3210, a bit line 3240 electrically connected to the channel structure 3220, and a word line WL electrically connected to the gate stack structure 3210 (see Figure 8 ) of the contact plug 3235. As shown in FIG. 1 to FIG. Figure 6 As described, in each semiconductor chip 2200 , the dummy vertical structure 180 penetrating the horizontal insulating layer 150 may be disposed to surround the contact plug 170 .

[0160] Each semiconductor chip 2200 may include a through interconnect 3245 electrically connected to the peripheral interconnect 3110 of the first structure 3100 and extending into the second structure 3200. The through interconnect 3245 may be disposed outside the gate stack structure 3210, and may be further disposed to penetrate the gate stack structure 3210. Each semiconductor chip 2200 may also include an input / output pad 2210 electrically connected to the peripheral interconnect 3110 of the first structure 3100 (see Fig. 9 ).

[0161] According to the aforementioned example embodiments, by including a dummy vertical structure penetrating a horizontal insulating layer disposed between a memory gate electrode and an upper selection gate electrode, a semiconductor device having improved reliability and a data storage system including the same may be provided.

[0162] Although this specification contains a variety of specific implementation details, these should not be interpreted as limitations on the scope of possible claims, but rather as descriptions of features that may be specific to a specific embodiment of a specific invention. Certain features described in this specification in the context of a separate implementation can also be implemented in combination in a single implementation. Conversely, the various features described in a single implementation can also be implemented individually or in any suitable sub-combination in multiple implementations. In addition, although features may be described above as working in certain combinations and even initially claimed as such, one or more features from the claimed combination may be removed from the combination in some cases, and the claimed combination may be directed to a sub-combination or a variation of the sub-combination.

[0163] While example embodiments have been illustrated and described above, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the scope of the present disclosure as defined by the appended claims.

Claims

1. A semiconductor device, the semiconductor device include: a first semiconductor structure, the first semiconductor structure comprising a substrate, a plurality of circuit devices located on the substrate, and a plurality of circuit interconnection lines located on the plurality of circuit devices; as well as a second semiconductor structure, the second semiconductor structure being located on the first semiconductor structure and comprising a first region and a second region, Wherein, the second semiconductor structure comprises: Lamellar; a plurality of gate electrodes, the plurality of gate electrodes comprising a lower selection gate electrode, a storage gate electrode, and an upper selection gate electrode stacked in order from the plate layer along a first direction perpendicular to an upper surface of the plate layer, wherein the lower selection gate electrode, the storage gate electrode, and the upper selection gate electrode are spaced apart from each other; a horizontal insulating layer, the horizontal insulating layer being located between the storage gate electrode and the upper selection gate electrode; a plurality of first channel structures extending through the lower selection gate electrode and the storage gate electrode in the first region along the first direction; a plurality of connection pads extending through the horizontal insulating layer and connected to the plurality of first channel structures; a plurality of second channel structures extending through the upper selection gate electrode in the first region, connected to the plurality of connection pads, and electrically connected to the plurality of first channel structures, respectively; a plurality of contact plugs extending through at least a portion of the plurality of gate electrodes along the first direction in the second region and electrically connecting the plurality of gate electrodes to a portion of the plurality of circuit interconnection lines; and a plurality of dummy vertical structures, the plurality of dummy vertical structures surrounding the plurality of contact plugs in the second region, the plurality of dummy vertical structures extending through the horizontal insulating layer in the first direction, The lower ends of the plurality of dummy vertical structures are at a first height, and the lower ends of the plurality of contact plugs are at a second height lower than the first height.

2. The semiconductor device according to claim 1, in, The second semiconductor structure further includes: a plurality of cell interconnect structures connected to the plurality of contact plugs; and A cell region insulating layer covers upper surfaces of the plurality of dummy vertical structures.

3. The semiconductor device according to claim 1, in, Upper ends of the plurality of dummy vertical structures and upper ends of the plurality of contact plugs are at substantially the same height.

4. The semiconductor device according to claim 1, in, The first height is higher than a third height of an uppermost surface of the storage gate electrode.

5. The semiconductor device according to claim 1, in, The first height is between a lower surface of the horizontal insulating layer and an uppermost surface of the storage gate electrode.

6. The semiconductor device according to claim 1, in, The plurality of dummy vertical structures extend through portions of the memory gate electrodes.

7. The semiconductor device according to claim 1, in, The plurality of dummy vertical structures include a conductive material.

8. The semiconductor device according to claim 1, in, The plurality of dummy vertical structures and the plurality of contact plugs include a same material.

9. The semiconductor device according to claim 1, in, A diameter of each of the plurality of dummy vertical structures is equal to or smaller than a diameter of each of the plurality of contact plugs.

10. The semiconductor device according to claim 1, in, The horizontal insulating layer includes nitride.

11. The semiconductor device according to claim 1, in, Each of the plurality of contact plugs includes a vertical extending portion extending in the first direction and at least one horizontal extending portion extending horizontally from the vertical extending portion, and each of the plurality of contact plugs contacts one of the plurality of gate electrodes.

12. The semiconductor device according to claim 1, in, The plurality of gate electrodes form a first step structure whose height decreases in the first direction and a second step structure whose height increases in the first direction in the second region, and Wherein, the plurality of contact plugs extend through the first stepped structure.

13. A semiconductor device, the semiconductor device include: Lamellar; a plurality of gate electrodes, wherein the plurality of gate electrodes are stacked on the plate layer along a first direction perpendicular to an upper surface of the plate layer and are spaced apart from each other, and the plurality of gate electrodes include a first gate electrode and a second gate electrode located on the first gate electrode; a horizontal insulating layer, the horizontal insulating layer being located between the first gate electrode and the second gate electrode, the horizontal insulating layer comprising nitride; a plurality of first channel structures extending through the first gate electrode in the first direction; a plurality of second channel structures, the plurality of second channel structures extending through the second gate electrode in the first direction, the plurality of second channel structures being electrically connected to the plurality of first channel structures respectively; a plurality of contact plugs extending through the horizontal insulating layer in the first direction, the plurality of contact plugs being respectively connected to the plurality of gate electrodes; a plurality of dummy vertical structures extending through the horizontal insulating layer in the first direction and surrounding the plurality of contact plugs; and A cell region insulating layer covers upper surfaces of the plurality of dummy vertical structures.

14. The semiconductor device according to claim 13, in, A length of each of the plurality of dummy vertical structures in the first direction is smaller than a length of each of the plurality of contact plugs in the first direction.

15. The semiconductor device according to claim 13, in, Lower ends of the plurality of dummy vertical structures are at a height equal to or lower than a height of a lower surface of the horizontal insulating layer.

16. The semiconductor device according to claim 13, in, Lower ends of the plurality of dummy vertical structures are at a height lower than that of lower ends of the plurality of second channel structures.

17. The semiconductor device according to claim 13, in, Upper ends of the plurality of dummy vertical structures are at a height higher than a height of an upper surface of the second gate electrode.

18. The semiconductor device according to claim 13, in, Each of the plurality of contact plugs has a bent portion whose width changes under the horizontal insulating layer.

19. A data storage system, the data storage system include: A semiconductor memory device, the semiconductor memory device comprising a first semiconductor structure, a second semiconductor structure and an input / output pad, the first semiconductor structure comprising a plurality of circuit devices, the second semiconductor structure being located on a surface of the first semiconductor structure, and the input / output pad being electrically connected to the plurality of circuit devices; as well as a controller electrically connected to the semiconductor memory device through the input / output pad, the controller being configured to control the semiconductor memory device, Wherein, the second semiconductor structure comprises: Lamellar; a plurality of gate electrodes, the plurality of gate electrodes being stacked on the plate layer along a first direction perpendicular to an upper surface of the plate layer and spaced apart from each other, and the plurality of gate electrodes comprising a first gate electrode and a second gate electrode located on the first gate electrode; a horizontal insulating layer, the horizontal insulating layer being located between the first gate electrode and the second gate electrode, the horizontal insulating layer comprising nitride; a plurality of first channel structures extending through the first gate electrode in the first direction; a plurality of second channel structures, the plurality of second channel structures extending through the second gate electrode in the first direction, the plurality of second channel structures being electrically connected to the plurality of first channel structures respectively; a plurality of contact plugs extending through the horizontal insulating layer in the first direction, the plurality of contact plugs being respectively connected to the plurality of gate electrodes; a plurality of dummy vertical structures extending through the horizontal insulating layer in the first direction and surrounding the plurality of contact plugs; and a cell region insulating layer, wherein the cell region insulating layer covers upper surfaces of the plurality of dummy vertical structures, The plurality of dummy vertical structures and the plurality of contact plugs include a same material, and the plurality of dummy vertical structures have a length different from that of the plurality of contact plugs.

20. The data storage system according to claim 19, in, Lower ends of the plurality of dummy vertical structures are at a height between the second gate electrode and the horizontal insulating layer.

Images