Semiconductor device and preparation method thereof

Abstract

The invention discloses a semiconductor device and a preparation method thereof, the semiconductor device comprises a cellular region, a gate bus and a transition region, the transition region is located between the cellular region and the gate bus, the transition region comprises a substrate, an epitaxial layer, a main junction layer, a gate oxide layer and a gate dielectric layer, the epitaxial layer is arranged on one side of the substrate, the main junction layer is arranged on one side, away from the substrate, of the epitaxial layer, and the gate oxide layer is arranged on the other side of the epitaxial layer. The main junction layer comprises an adjusting region, the adjusting region is located on the side, away from the substrate, of the main junction layer, and the adjusting region and the main junction layer are opposite in conduction type; the gate oxide layer is arranged on the side, away from the substrate, of the main junction layer and comprises a first gate oxide structure close to the cellular area and a second gate oxide structure close to the gate bus, and the thickness of the first gate oxide structure is larger than that of the second gate oxide structure; the gate dielectric layer is arranged on the side, away from the substrate, of the gate oxide layer. Wherein the second gate oxide structure is in contact with the adjusting region, and the orthographic projection of the second gate oxide structure on the substrate falls into the orthographic projection range of the adjusting region on the substrate.

Description

Technical Field

[0001] The present application belongs to the field of power semiconductor technology, and in particular, relates to a semiconductor device and a method for manufacturing the same. Background Art

[0002] In the field of power semiconductors, silicon carbide MOSFET is widely used in high-voltage scenarios due to its many advantages such as high breakdown voltage, high power, low on-resistance and high temperature resistance.

[0003] For silicon carbide MOSFET devices, electric field concentration is prone to occur in the transition region, which in turn causes oxide layer breakdown in this region, resulting in device failure and adversely affecting device reliability. Summary of the invention

[0004] An embodiment of the present application provides a semiconductor device and a method for preparing the same. The semiconductor device introduces an adjustment region of opposite conductivity type in the main junction layer. The adjustment region can reduce the electric field strength of the gate oxide layer in the transition region, thereby improving the reliability of the semiconductor device.

[0005] In a first aspect, an embodiment of the present application provides a semiconductor device, including a cell region, a gate bus and a transition region, wherein the transition region is located between the cell region and the gate bus, and the transition region includes a substrate, an epitaxial layer, a main junction layer, a gate oxide layer and a gate dielectric layer arranged in sequence, wherein the epitaxial layer is arranged on one side of the substrate; the main junction layer is arranged on a side of the epitaxial layer away from the substrate, the main junction layer includes an adjustment region, the adjustment region is located on a side of the main junction layer away from the substrate, and the conductivity type of the adjustment region is opposite to that of the main junction layer; the gate oxide layer is arranged on a side of the main junction layer away from the substrate, and includes a first gate oxide structure close to the cell region and a second gate oxide structure close to the gate bus, wherein the thickness of the first gate oxide structure is greater than the thickness of the second gate oxide structure; the gate dielectric layer is arranged on a side of the gate oxide layer away from the substrate;

[0006] The second gate oxide structure is in contact with the adjustment region, and the orthographic projection of the second gate oxide structure on the substrate falls within the range of the orthographic projection of the adjustment region on the substrate.

[0007] In some embodiments, the gate oxide layer further includes a third gate oxide structure, which is located between the first gate oxide structure and the second gate oxide structure, and the thickness of the third gate oxide structure gradually decreases along the direction from the cell region to the gate bus line.

[0008] In some of the embodiments, the orthographic projection of the third gate oxide structure on the substrate at least partially falls within the orthographic projection range of the adjustment region on the substrate.

[0009] In some of the embodiments, the conductive ion concentration of the adjustment region is greater than the conductive ion concentration of the epitaxial layer.

[0010] In some of these embodiments, the transition zone further comprises:

[0011] An isolation dielectric layer, located on a side of the gate dielectric layer facing away from the substrate;

[0012] A gate metal is located on a side of the isolation dielectric layer facing away from the substrate and in contact with the gate dielectric layer;

[0013] A source metal is located on a side of the isolation dielectric layer facing away from the substrate and in contact with the main junction layer;

[0014] The source metal and the gate metal are separated by an isolation dielectric layer, and the source metal and the gate dielectric layer channel are separated by an isolation dielectric layer.

[0015] In some of the embodiments, along the direction from the cell region to the gate bus, the orthographic projection of the source metal on the substrate and the orthographic projection of the first gate oxide structure on the substrate are spaced apart from each other.

[0016] In some of the embodiments, an orthographic projection of the source metal on the substrate partially overlaps with an orthographic projection of the second gate oxide structure on the substrate.

[0017] In a second aspect, an embodiment of the present application provides a method for preparing a semiconductor device, the method comprising:

[0018] providing a substrate and growing a drift region on one side of the substrate;

[0019] Implanting ions of the first conductivity type into a side of the drift region facing away from the substrate to obtain an epitaxial layer and a main junction layer located in the drift region;

[0020] Setting a first mask, and injecting ions of the second conductivity type into a side of the main junction layer away from the substrate to obtain an adjustment area;

[0021] forming a gate oxide layer on a side of the main junction layer facing away from the substrate;

[0022] A gate dielectric layer is formed on a side of the gate oxide layer facing away from the substrate.

[0023] In some embodiments, the step of forming a gate oxide layer on a side of the main junction layer facing away from the substrate includes:

[0024] A thick oxide layer is deposited on the side of the main junction layer facing away from the substrate, a second mask is set, and the thick oxide layer is etched to obtain a first gate oxide structure;

[0025] A thin oxide layer is grown on the side of the main junction layer away from the substrate, a third mask is set, and the thin oxide layer is etched to obtain a second gate oxide structure.

[0026] In some embodiments, the preparation method further comprises:

[0027] Depositing an isolation dielectric layer on the side of the gate dielectric layer away from the substrate, setting a fourth mask, and etching the isolation dielectric layer to obtain a gate contact hole and a source contact hole;

[0028] The gate metal is obtained by metal deposition in the gate contact hole, and the source metal is obtained by metal deposition in the source contact hole.

[0029] The embodiment of the present application introduces a regulation region of opposite conductivity type into the main junction layer of the transition region of the semiconductor device, which can increase the growth rate of the second gate oxide structure above the regulation region, so that a thicker gate oxide layer can be grown in the same time, thereby improving the voltage resistance performance of the device. In addition, the regulation region covering the second gate oxide structure can also weaken the electric field strength above the second gate oxide structure, reduce the probability of device failure caused by breakdown of the second gate oxide structure, and improve the reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present application. Moreover, the same reference numerals are used throughout the drawings to represent the same components. In the drawings:

[0031] Figure 1 A schematic diagram of the layout of a semiconductor device according to some embodiments of the present application;

[0032] Figure 2 for Figure 1 A schematic structural diagram of the semiconductor device shown;

[0033] Figures 3a to 3e A schematic diagram of a method for preparing a semiconductor device according to some embodiments of the present application;

[0034] Figure 4 A schematic diagram of a process for preparing a semiconductor device according to some embodiments of the present application;

[0035] Figure 5 A schematic diagram of a sub-process of a method for preparing a semiconductor device according to some embodiments of the present application;

[0036] Figure 6 A schematic diagram of the transition region structure of a semiconductor device with a traditional structure;

[0037] Figures 7a to 7b This is the electric field intensity distribution diagram of the traditional structure under experimental conditions;

[0038] Figures 8a to 8b This is a diagram of the electric field intensity distribution of the embodiment of the present application under experimental conditions;

[0039] Fig. 9The electric field intensity distribution characteristic curve diagram of the thin gate oxide layer region of the traditional structure and the embodiment of the present application under experimental conditions.

[0040] The reference numerals in the specific implementation manner are as follows:

[0041] 11. Cell region; 12. Transition region; 13. Gate bus; 14. Gate region; 15. Terminal region;

[0042] 110, substrate; 120, epitaxial layer; 200, main junction layer; 210, adjustment region; 300, gate oxide layer; 310, first gate oxide structure; 320, second gate oxide structure; 330, third gate oxide structure; 400, gate dielectric layer; 500, isolation dielectric layer; 610, gate metal; 620, source metal; 630, drain metal. DETAILED DESCRIPTION

[0043] The following embodiments of the technical solution of the present application are described in detail in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present application, and are therefore only used as examples, and cannot be used to limit the scope of protection of the present application.

[0044] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by technicians in the technical field to which this application belongs; the terms used herein are only for the purpose of describing specific embodiments and are not intended to limit this application; the terms "including" and "having" in the specification and claims of this application and the above-mentioned figure descriptions and any variations thereof are intended to cover non-exclusive inclusions.

[0045] In the description of the embodiments of the present application, the technical terms "first", "second", etc. are only used to distinguish different objects, and cannot be understood as indicating or implying relative importance or implicitly indicating the number, specific order or primary and secondary relationship of the indicated technical features. In the description of the embodiments of the present application, the meaning of "multiple" is more than two, unless otherwise clearly and specifically defined.

[0046] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0047] In the description of the embodiments of the present application, the term "and / or" is only a description of the association relationship of the associated objects, indicating that there may be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0048] In the description of the embodiments of the present application, the term "multiple" refers to more than two (including two). Similarly, "multiple groups" refers to more than two groups (including two groups), and "multiple pieces" refers to more than two pieces (including two pieces).

[0049] In the description of the embodiments of the present application, the technical terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, which are only for the convenience of describing the embodiments of the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the embodiments of the present application.

[0050] In the description of the embodiments of the present application, unless otherwise clearly specified and limited, technical terms such as "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, and it can be the internal connection of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present application can be understood according to the specific circumstances.

[0051] In the field of power semiconductors, silicon carbide MOSFET is widely used in high-voltage scenarios of power electronic systems due to its many advantages such as high breakdown voltage, high power, low on-resistance and high temperature resistance.

[0052] For silicon carbide MOSFET devices, electric field concentration is prone to occur in the transition region, which in turn causes oxide layer breakdown in this region, resulting in device failure and adversely affecting device reliability.

[0053] In order to solve the problems in the prior art, the present invention provides a semiconductor device and a method for manufacturing the same. The semiconductor device provided by the present invention is first introduced below.

[0054] See also Figure 1 to Figure 2The present application provides a semiconductor device in an embodiment. The semiconductor device includes a cell region 11, a gate bus 13 and a transition region 12. The transition region 12 is located between the cell region 11 and the gate bus 13. The transition region 12 includes a substrate 110, an epitaxial layer 120, a main junction layer 200, a gate oxide layer 300 and a gate dielectric layer 400 arranged in sequence. The epitaxial layer 120 is arranged on one side of the substrate 110; the main junction layer 200 is arranged on the side of the epitaxial layer 120 away from the substrate 110. The main junction layer 200 includes an adjustment region 210. The adjustment region 210 includes a gate oxide layer 300 and a gate dielectric layer 400. The node region 210 is located on the side of the main junction layer 200 away from the substrate 110, and the conductivity type of the adjustment region 210 is opposite to that of the main junction layer 200; the gate oxide layer 300 is arranged on the side of the main junction layer 200 away from the substrate 110, and the gate oxide layer 300 includes a first gate oxide structure 310 close to the cell region 11 and a second gate oxide structure 320 close to the gate bus 13, and the thickness of the first gate oxide structure 310 is greater than the thickness of the second gate oxide structure 320; the gate dielectric layer 400 is arranged on the side of the gate oxide layer 300 away from the substrate 110. The second gate oxide structure 320 is in contact with the adjustment region 210, and the orthographic projection of the second gate oxide structure 320 on the substrate 110 falls within the orthographic projection of the adjustment region 210 on the substrate 110.

[0055] Specifically, the conductivity type of the substrate 110 and the epitaxial layer 120 is the same, and the conductivity type of the epitaxial layer 120 and the main junction layer 200 is opposite.

[0056] Exemplarily, the main junction layer 200 is doped with P-type ions, and the adjustment region 210 is doped with N-type ions.

[0057] Exemplarily, the material of the gate dielectric layer 400 includes polysilicon.

[0058] In some of these embodiments, see Figure 1 The semiconductor device further includes a gate region 14, and the gate region 14 is connected to the gate bus 13. Exemplarily, in a horizontal plane, along the circumference of the gate region 14 and the gate bus 13, the cell region 11 is surrounded on the outside.

[0059] In some of these embodiments, please continue to refer to Figure 1 The semiconductor device further includes a terminal region 15. Exemplarily, in a horizontal plane, along the circumference of the cell region 11, the terminal region 15 is disposed on the outside.

[0060] It is understood that the “thickness” here refers to the minimum size of the first gate oxide structure 310 and the second gate oxide structure 320 in a direction perpendicular to their coverage surface. For example, along the direction perpendicular to the coverage surface, the first gate oxide structure 310 has a first portion with a smaller size and a second portion with a larger size, wherein the size of the first portion is larger than the size of the second gate oxide structure 320; or, along the direction perpendicular to the coverage surface, the second gate oxide structure 320 has a third portion with a larger size and a fourth portion with a smaller size, wherein the size of the third portion is smaller than the size of the first gate oxide structure 310. Of course, in some embodiments, the first gate oxide structure 310 has the same size in the direction perpendicular to its coverage surface, or the second gate oxide structure 320 has the same size in the direction perpendicular to its coverage surface.

[0061] Therefore, the adjustment region 210 with the opposite conductivity type is arranged in the main junction layer 200, which can accelerate the growth of the second gate oxide structure 320 above the adjustment region 210, so that the second gate oxide structure 320 has a greater thickness within the same growth time, and reduces the probability of the transition region 12 having a device at the second gate oxide structure 320. In addition, the adjustment region 210 covering the second gate oxide structure 320 can also weaken the electric field strength at the second gate oxide structure 320, further improving the withstand voltage performance of the transition region 12, thereby improving the reliability of the semiconductor device.

[0062] According to certain embodiments of the present application, the gate oxide layer 300 also includes a third gate oxide structure 330, which is located between the first gate oxide structure 310 and the second gate oxide structure 320, and the thickness of the third gate oxide structure 330 is less than or equal to the first gate oxide structure 310, and the thickness of the third gate oxide structure 330 is greater than or equal to the second gate oxide structure 320.

[0063] Optionally, the third gate oxide structure 330 is made of the same material as the first gate oxide structure 310 and the second gate oxide structure 320, or the third gate oxide structure 330 is made of a material different from the first gate oxide structure 310 and the second gate oxide structure 320. Exemplarily, the third gate oxide structure 330 is made of silicon dioxide.

[0064] Optionally, along the direction from the cell region 11 to the gate bus 13 , the thickness of the third gate oxide structure 330 gradually decreases.

[0065] Further optionally, the maximum thickness of the third gate oxide structure 330 is the same as the thickness of the first gate oxide structure 310 .

[0066] Further optionally, the minimum thickness of the third gate oxide structure 330 is the same as the thickness of the second gate oxide structure 320 .

[0067] Exemplarily, a cross section of the third gate oxide structure 330 in the height direction is distributed in an inclined straight line, or a cross section of the third gate oxide structure 330 in the height direction is distributed in a curve.

[0068] Therefore, the third gate oxide structure 330 can serve as a transition between the first gate oxide structure 310 and the second gate oxide structure 320 having a thickness difference, adapt to the changes in the electric field above the first gate oxide structure 310 and the electric field above the second gate oxide structure 320, so as to protect the junction between the first gate oxide structure 310 and the second gate oxide structure 320, and reduce the probability of device failure caused by breakdown in this area.

[0069] According to some embodiments of the present application, the orthographic projection of the third gate oxide structure 330 on the substrate 110 at least partially falls within the orthographic projection range of the adjustment region 210 on the substrate 110 .

[0070] Optionally, an orthographic projection of the third gate oxide structure 330 on the substrate 110 falls within a range of an orthographic projection of the adjustment region 210 on the substrate 110 .

[0071] Optionally, the orthographic projections of the third gate oxide structure 330 on the substrate 110 all fall within the range of the orthographic projections of the adjustment region 210 on the substrate 110 .

[0072] Therefore, on the one hand, it helps the third gate oxide structure 330 to grow thicker during preparation so as to have better voltage resistance performance. On the other hand, the adjustment region 210 can at least form protection for part of the third gate oxide structure 330 to reduce the probability of device failure due to breakdown at the third gate oxide structure 330.

[0073] According to some embodiments of the present application, the conductive ion concentration of the adjustment region 210 is greater than the conductive ion concentration of the epitaxial layer 120 .

[0074] Optionally, the conductive ion concentration of the adjustment region 210 is greater than the conductive ion concentration of the substrate 110 .

[0075] Exemplarily, the substrate 110 , the epitaxial layer 120 , and the adjustment region 210 are all N-type ion doped.

[0076] Therefore, the adjustment region 210 with a higher ion doping concentration is provided to accelerate the growth of the second gate oxide structure 320 and at least a portion of the third gate oxide structure 330 above the adjustment region 210 , and to thicken the second gate oxide structure 320 and the third gate oxide structure 330 to improve the withstand voltage performance of the semiconductor device.

[0077] According to certain embodiments of the present application, the transition region 12 also includes an isolation dielectric layer 500, a gate metal 610 and a source metal 620, the isolation dielectric layer 500 is located on the side of the gate dielectric layer 400 away from the substrate 110, the gate metal 610 is located on the side of the isolation dielectric layer 500 away from the substrate 110 and in contact with the gate dielectric layer 400, and the source metal 620 is located on the side of the isolation dielectric layer 500 away from the substrate 110 and in contact with the main junction layer 200.

[0078] See also Figure 2 It can be understood that the transition region 12 further includes a drain metal 630 , and the drain metal 630 is disposed on a side of the substrate 110 away from the epitaxial layer 120 .

[0079] It is understandable that the source metal 620 is separated from the gate metal 610 by the isolation dielectric layer 500 , and the source metal 620 is separated from the gate dielectric layer 400 by the isolation dielectric layer 500 to prevent a short circuit between the source metal 620 and the gate metal 610 .

[0080] Optionally, along the direction from the cell region 11 to the gate bus 13 , the orthographic projection of the source metal 620 on the substrate 110 and the orthographic projection of the gate metal 610 on the substrate 110 are distributed at intervals.

[0081] Optionally, an isolation dielectric layer 500 is disposed between the source metal 620 and the gate metal 610 along the direction from the cell region 11 to the gate bus 13 .

[0082] According to some embodiments of the present application, along the direction from the cell region 11 to the gate bus 13 , the orthographic projection of the source metal 620 on the substrate 110 and the orthographic projection of the first gate oxide structure 310 on the substrate 110 are spaced apart from each other.

[0083] Optionally, an orthographic projection of the source metal 620 on the substrate 110 and an orthographic projection of the third gate oxide structure 330 on the substrate 110 are spaced apart from each other.

[0084] Further optionally, the orthographic projection of the source metal 620 on the substrate 110 partially overlaps with the orthographic projection of the second gate oxide structure 320 on the substrate 110 .

[0085] Therefore, on the one hand, the distance between the source metal 620 and the gate metal 610 is extended to improve the safety of the device, and on the other hand, the electric field strength in the thin gate oxide layer 300 area is significantly reduced, reducing the probability of failure due to device breakdown and improving device reliability.

[0086] Second, see Figure 4 and Figures 3a to 3e The present application provides a method for preparing a semiconductor device, which is used to prepare the semiconductor device provided by any of the above embodiments. The preparation method includes:

[0087] S100, providing a substrate 110, and growing a drift region on one side of the substrate 110;

[0088] S200, implanting ions of the first conductivity type into a side of the drift region away from the substrate 110 to obtain an epitaxial layer 120 and a main junction layer 200 located in the drift region;

[0089] S300, setting a first mask, and injecting ions of the second conductivity type into the side of the main junction layer 200 away from the substrate 110 to obtain an adjustment region 210;

[0090] S400, forming a gate oxide layer 300 on a side of the main junction layer 200 facing away from the substrate 110;

[0091] S500 , forming a gate dielectric layer 400 on a side of the gate oxide layer 300 facing away from the substrate 110 .

[0092] Optionally, the ions of the first conductivity type are P-type ions, and the ions of the second conductivity type are N-type ions.

[0093] Optionally, in step S300, after the second conductive type ions are implanted, high temperature annealing is performed to activate the impurities.

[0094] See also Figure 5 According to some embodiments of the present application, step S400 includes:

[0095] S410, depositing a thick oxide layer on the side of the main junction layer 200 away from the substrate 110, setting a second mask, and etching the thick oxide layer to obtain a first gate oxide structure 310;

[0096] S420 , growing a thin oxide layer on the side of the main junction layer 200 facing away from the substrate 110 , setting a third mask, and etching the thin oxide layer to obtain a second gate oxide structure 320 .

[0097] Optionally, in step S420 , the thin oxide layer is prepared by low-temperature growth to improve the quality of the second gate oxide structure 320 .

[0098] According to certain embodiments of the present application, the preparation method further comprises:

[0099] S610, depositing an isolation dielectric layer 500 on the side of the gate dielectric layer 400 facing away from the substrate 110, setting a fourth mask, and etching the isolation dielectric layer 500 to obtain a gate contact hole and a source contact hole;

[0100] S620 , obtaining a gate metal 610 by metal deposition in the gate contact hole, and obtaining a source metal 620 by metal deposition in the source metal 620 hole.

[0101] In order to further verify the protective effect of the structure of the present application on the thin gate oxide layer area, TACD simulation verification is performed on the transition region structure of the present application and the prior art. GS =20V, source-drain voltage V DS =0V.

[0102] The traditional structure used in the experiment sets a shielding layer with the same conductivity type as the main junction layer between the main junction layer and the gate oxide layer in the transition region. For the specific structure, please refer to Figure 6 For the structure of the embodiment of the present application selected for the experiment, please refer to Figure 2 Compared with the conventional structure, the embodiment of the present application does not introduce a P-type high-concentration doped region in the main junction layer, but sets a high-concentration N-type doped region below the thin gate oxide layer, and shortens the length of the source metal to above the thin gate oxide layer so that it no longer covers the thick oxide layer area.

[0103] Figure 7a is the electric field intensity distribution diagram of the traditional structure under experimental conditions. Figure 7b for Figure 7a A partial enlarged view of the local electric field intensity distribution in the thin gate oxide layer area.

[0104] Figure 8a This is the electric field intensity distribution diagram of the embodiment of this application under experimental conditions, Figure 8b for Figure 8a A local enlarged view of the electric field strength distribution of the second gate oxide structure.

[0105] Fig. 9 Based on Figure 7b and Figure 8b The obtained electric field intensity distribution characteristic curve diagram of the traditional structure and the embodiment of the present application in the thin gate oxide layer area. Figure 7b and Figure 8b Combined with Fig. 9 It is easy to see that compared with the traditional structure, the present application significantly weakens the electric field strength in the thin gate oxide layer area, wherein the peak intensity of the traditional structure in the thin gate oxide layer is about 4.9MV / cm, and the peak intensity of the embodiment of the present application in the thin gate oxide layer is about 3.8MV / cm.

[0106] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them; although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application, and they should all be included in the scope of the claims and specification of the present application. In particular, as long as there is no structural conflict, the various technical features mentioned in the various embodiments can be combined in any way. The present application is not limited to the specific embodiments disclosed herein, but includes all technical solutions that fall within the scope of the claims.

Claims

1. A semiconductor device, characterized in that: It includes a cell region, a gate bus and a transition region, wherein the transition region is located between the cell region and the gate bus, and the transition region includes: substrate; An epitaxial layer is disposed on one side of the substrate; A main junction layer is arranged on a side of the epitaxial layer away from the substrate, the main junction layer comprises an adjustment region, the adjustment region is located on a side of the main junction layer away from the substrate, and the conductivity type of the adjustment region is opposite to that of the main junction layer; A gate oxide layer, disposed on a side of the main junction layer away from the substrate, comprising a first gate oxide structure close to the cell region and a second gate oxide structure close to the gate bus, wherein the thickness of the first gate oxide structure is greater than the thickness of the second gate oxide structure; A gate dielectric layer, disposed on a side of the gate oxide layer facing away from the substrate; The second gate oxide structure is in contact with the adjustment region, and the orthographic projection of the second gate oxide structure on the substrate falls within the orthographic projection range of the adjustment region on the substrate.

2. The semiconductor device according to claim 1, wherein: The gate oxide layer further includes a third gate oxide structure, which is located between the first gate oxide structure and the second gate oxide structure. The thickness of the third gate oxide structure gradually decreases along the direction from the cell region to the gate bus line.

3. The semiconductor device according to claim 2, characterized in that The orthographic projection of the third gate oxide structure on the substrate at least partially falls within the orthographic projection range of the adjustment region on the substrate.

4. The semiconductor device according to claim 1, wherein: The conductive ion concentration of the adjustment region is greater than the conductive ion concentration of the epitaxial layer.

5. The semiconductor device according to claim 1, wherein: The transition zone also includes: an isolation dielectric layer, located on a side of the gate dielectric layer facing away from the substrate; A gate metal, located on a side of the isolation dielectric layer away from the substrate and in contact with the gate dielectric layer; A source metal, located on a side of the isolation dielectric layer away from the substrate and in contact with the main junction layer; The source metal and the gate metal are separated by the isolation dielectric layer, and the source metal and the gate dielectric layer channel are separated by the isolation dielectric layer.

6. The semiconductor device according to claim 5, characterized in that Along the direction from the cell region to the gate bus, the orthographic projection of the source metal on the substrate and the orthographic projection of the first gate oxide structure on the substrate are distributed at intervals.

7. The semiconductor device according to claim 5, characterized in that The orthographic projection of the source metal on the substrate partially overlaps with the orthographic projection of the second gate oxide structure on the substrate.

8. A method for preparing a semiconductor device, characterized in that: The preparation method comprises: providing a substrate and growing a drift region on one side of the substrate; Implanting ions of the first conductivity type into a side of the drift region facing away from the substrate to obtain an epitaxial layer and a main junction layer located in the drift region; Setting a first mask, and injecting ions of the second conductivity type into a side of the main junction layer away from the substrate to obtain an adjustment area; forming a gate oxide layer on a side of the main junction layer facing away from the substrate; A gate dielectric layer is formed on the side of the gate oxide layer facing away from the substrate.

9. The method for preparing a semiconductor device according to claim 8, characterized in that: The step of forming a gate oxide layer on a side of the main junction layer away from the substrate comprises: A thick oxide layer is deposited on the side of the main junction layer facing away from the substrate, a second mask is set, and the thick oxide layer is etched to obtain a first gate oxide structure; A thin oxide layer is grown on the side of the main junction layer away from the substrate, a third mask is set, and the thin oxide layer is etched to obtain a second gate oxide structure.

10. The method for preparing a semiconductor device according to claim 8, characterized in that: The preparation method also includes: Depositing an isolation dielectric layer on the side of the gate dielectric layer away from the substrate, setting a fourth mask, and etching the isolation dielectric layer to obtain a gate contact hole and a source contact hole; The gate metal is obtained by metal deposition in the gate contact hole, and the source metal is obtained by metal deposition in the source contact hole.

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