LDMOS device and preparation method thereof

Abstract

The invention relates to an LDMOS device and a preparation method thereof. The LDMOS device comprises a semiconductor substrate, a first drift region, a first well region, a first source-drain region, a second source-drain region and an embedded field plate unit. The first drift region and the first well region are formed in the semiconductor substrate and adjacent to each other. The first source-drain region is disposed in the first drift region. The second source-drain region is disposed in the first well region. The embedded field plate unit comprises a first shallow trench isolation structure and a conductive layer. The first shallow trench isolation structure is arranged in the first drift region and located between the first source-drain region and the second source-drain region. The conductive layer is embedded in the first shallow trench isolation structure.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to an LDMOS device and a method for preparing the same. Background Art

[0002] In the field of semiconductor devices such as power devices, laterally-diffused metal-oxide semiconductor (LDMOS) devices have been widely used.

[0003] Power devices often need to cope with high voltage and high current conditions, which requires LDMOS devices to have good voltage resistance. In related technologies, in order to improve the voltage resistance of LDMOS devices, the channel length of LDMOS devices is generally adjusted. However, such methods are difficult to meet the requirements of device miniaturization.

[0004] Therefore, how to design an optimized LDMOS device to improve its withstand voltage characteristics has become a technical problem that needs to be solved urgently. Summary of the invention

[0005] The present application provides an LDMOS device and a method for manufacturing the same, so as to enhance the voltage resistance of the LDMOS device without increasing its size.

[0006] To achieve the above technical objectives, the first aspect of the present application provides an LDMOS device. The LDMOS device includes: a semiconductor substrate, a first drift region, a first well region, a first source-drain region, a second source-drain region, and a buried field plate unit. The first drift region and the first well region are formed in the semiconductor substrate and are adjacent to each other. The first source-drain region is arranged in the first drift region. The second source-drain region is arranged in the first well region. The buried field plate unit includes a first shallow trench isolation structure and a conductive layer. The first shallow trench isolation structure is arranged in the first drift region and is located between the first source-drain region and the second source-drain region. The conductive layer is buried in the first shallow trench isolation structure.

[0007] In order to achieve the above technical objectives, the second aspect of the present application provides a method for preparing an LDMOS device. The preparation method includes: making a buried field plate unit in a semiconductor substrate, wherein the buried field plate unit includes: a first shallow trench isolation structure, and a conductive layer buried in the first shallow trench isolation structure; forming a first drift region and a first well region adjacent to each other in the semiconductor substrate by doping, wherein the first drift region is configured as a continuous region surrounding and adjacent to the buried field plate unit; and doping in the first drift region to form a first source-drain region, and doping in the first well region to form a second source-drain region, wherein the first source-drain region is located on a side of the buried field plate unit away from the first well region.

[0008] In the present application, an LDMOS device and a method for preparing the same are provided. The LDMOS device comprises: a semiconductor substrate, a first drift region, a first well region, a first source-drain region, a second source-drain region, and a buried field plate unit. The first drift region and the first well region are formed in the semiconductor substrate and are adjacent to each other. The first source-drain region is arranged in the first drift region. The second source-drain region is arranged in the first well region. The buried field plate unit comprises a first shallow trench isolation structure and a conductive layer. The first shallow trench isolation structure is arranged in the first drift region and is located between the first source-drain region and the second source-drain region. The conductive layer is buried in the first shallow trench isolation structure. By burying the conductive layer in the first shallow trench isolation structure, the conductive layer can form a large-area field plate of the drift region close to the bottom side and both sides of the first shallow trench isolation structure. By applying a reverse voltage to the conductive layer, the electric field distribution of the drift region of the LDMOS device can be better adjusted, thereby increasing the breakdown voltage of the LDMOS tube without increasing the on-resistance of the LDMOS, thereby improving its withstand voltage performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The present application will illustrate the implementation methods in conjunction with the accompanying drawings. The accompanying drawings of the present application are only used to describe the embodiments for the purpose of demonstration. Without departing from the principles of the present application, those skilled in the art can easily make other embodiments according to the steps described below through the following description.

[0010] Figure 1 is a schematic diagram of a top view of an LDMOS device according to some embodiments of the present application;

[0011] Figure 2 According to some embodiments of the present application, the LDMOS device Figure 1 A schematic diagram of the cross-sectional structure of the A-A' section;

[0012] Figure 3 is a flow chart of a preparation method according to some embodiments of the present application;

[0013] Figure 4 According to some embodiments of the present application Figure 3 A schematic flow chart of operation S31 in FIG.

[0014] Figure 5 is a first structural schematic diagram of a process for preparing a buried field plate unit according to some embodiments of the present application;

[0015] Figure 6 is a second structural schematic diagram of a process for preparing a buried field plate unit according to some embodiments of the present application;

[0016] Figure 7 is a third structural schematic diagram of a process for preparing a buried field plate unit according to some embodiments of the present application;

[0017] Figure 8 is a fourth structural schematic diagram of a process for preparing a buried field plate unit according to some embodiments of the present application;

[0018] Fig. 9 is a fifth structural schematic diagram of a process for preparing a buried field plate unit according to some embodiments of the present application;

[0019] Fig.10 is a sixth structural schematic diagram of a preparation process of a buried field plate unit according to some embodiments of the present application;

[0020] Fig.11 is a TCAD simulation result of an LDMOS device according to some embodiments of the present application;

[0021] Fig.12 It is the simulation result of the impact ionization intensity of the LDMOS device when the buried field plate unit is not set;

[0022] Fig.13 is a simulation result of the impact ionization intensity of the LDMOS device when a reverse voltage of 10V is applied to the buried field plate unit according to some embodiments of the present application;

[0023] Fig.14 is the simulation result of the current density of the LDMOS device when the buried field plate unit is not provided;

[0024] Fig.15 The following are simulation results of the current density of the LDMOS device when a reverse voltage of 10V is applied to the buried field plate unit according to some embodiments of the present application. DETAILED DESCRIPTION

[0025] The scheme of the embodiment of the present application is described in detail below in conjunction with the drawings of the specification.

[0026] In the following description, for the purpose of explanation rather than limitation, specific details such as specific system structures, interfaces, and technologies are provided to facilitate a thorough understanding of the present application.

[0027] The term "and / or" in this article is only a description of the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship. In addition, "many" in this article means two or more than two.

[0028] The terms "first", "second", and "third" in this application are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined as "first", "second", and "third" can expressly or implicitly include at least one of the features. In the description of this application, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise specified in some embodiments. In the embodiments of this application, all directional indications (such as up, down, left, right, front, back...) are only used to explain the relative position relationship, movement, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication also changes accordingly. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but optionally also includes steps or units that are not listed, or optionally also includes other steps or units inherent to these processes, methods, products, or devices.

[0029] refer to Figure 1 and Figure 2 , Figure 1 is a schematic diagram of a top view of an LDMOS device 1 according to some embodiments of the present application, and Figure 2 According to some embodiments of the present application, the LDMOS device 1 is Figure 1 Schematic diagram of the cross-sectional structure of the A-A' section.

[0030] Figure 1 and Figure 2 In the description, two transistors with a common drain region are used as an example. Specifically, the LDMOS device 1 includes two adjacent transistors. The two transistors have a common drain region. The two source regions of the two adjacent transistors are respectively arranged on a side away from the common drain region to serve as the source regions of the respective transistors. In some embodiments, the LDMOS device 1 may also include only a single transistor structure, and the present application does not make specific restrictions on this.

[0031] like Figure 1 and Figure 2 As shown, the LDMOS device 1 includes a semiconductor substrate 10 , a first drift region 12 , a first well region 14 , a first source-drain region 22 , a second source-drain region 24 and a buried field plate unit 30 .

[0032] In some embodiments, the material of the semiconductor substrate 10 can be a semiconductor material such as Si, SiGe, SiGeC, SiC, GaAs, InAs, InP, other III / V or II / VI compound semiconductors, etc., and can also include a layered substrate such as Si / SiGe, Si / SiC, silicon on insulator (SOI) or silicon germanium on insulator, which is not limited in the present application.

[0033] In some embodiments, the first drift region 12 and the first well region 14 may be formed in the semiconductor substrate 10 and adjacent to each other. Figure 1 and Figure 2 As shown, in the case of two transistors with a common drain region, the LDMOS device 1 may include a first drift region 12 formed between two first well regions 14 .

[0034] In some embodiments, the first drift region 12 and the first well region 14 have opposite doping types. Figure 2 The doping type of the first drift region 12 shown in the figure can be P-type, and the doping type of the first well region 14 can be N-type, and the present application does not make specific restrictions. In P-type doping, a P-type doping element (also called an acceptor impurity) is introduced into the semiconductor material, so that in the doped semiconductor material, holes serve as the majority carriers, and the semiconductor material exhibits P-type conductive characteristics. Acceptor impurities are, for example, boron (B), gallium (Ga), etc. In N-type doping, an N-type doping element (also called a donor impurity) is introduced into the semiconductor material, so that in the doped semiconductor material, electrons serve as the majority carriers, and the semiconductor material exhibits N-type conductive characteristics. Donor impurities are, for example, phosphorus (P), arsenic (As), etc.

[0035] In some embodiments, the first source-drain region 22 is disposed in the first drift region 12, and the second source-drain region 24 is disposed in the first well region 14. Figure 1 and Figure 2 In the two transistor structures with a common drain region shown in FIG, the first source-drain region 22 is a drain region, and the second source-drain region 24 is a source region. The first source-drain region 22 and the second source-drain region 24 can be formed by doping materials at corresponding positions of the semiconductor substrate 10, and the doping concentrations of the first source-drain region 22 and the second source-drain region 24 can be higher than the doping concentrations of the first drift region 12 and the first well region 14. Figure 2 In the embodiment of the present invention, the first source-drain region 22 and the second source-drain region 24 may both be formed by N-type doping, and the present application does not impose any specific limitation thereto.

[0036] In some embodiments, the buried field plate unit 30 may include a first shallow trench isolation structure 32 and a conductive layer 34. The first shallow trench isolation structure 32 is disposed in the first drift region 12 and is located between the first source-drain region 22 and the second source-drain region 24. The conductive layer 34 is buried in the first shallow trench isolation structure 32. In the technical solution of the present application, a voltage may be applied to the conductive layer 34, and the voltage may generate an electric field in the first drift region 12, thereby adjusting the electric field distribution of the first drift region 12 of the LDMOS device 1.

[0037] In the technical solution of the present application, the conductive layer 34 is buried in the first shallow trench isolation structure 32, and the conductive layer 34 can form a large-area field plate of the first drift region 12 close to the bottom and both sides of the first shallow trench isolation structure 32. By applying a voltage, especially a reverse voltage, to the conductive layer 34, the electric field distribution of the first drift region 12 of the LDMOS device 1 can be better adjusted, and the impact ionization intensity of the first drift region 12 can be improved. Through this configuration, the breakdown voltage of the LDMOS device 1 can be increased without increasing the on-resistance of the LDMOS device 1, thereby improving its withstand voltage performance.

[0038] In some embodiments, the buried field plate unit 30 further includes a contact hole 36. Figure 1 and Figure 2 , the contact hole 36 is shown as a black filled portion. The contact hole 36 is configured to be electrically connected to the conductive layer 34. The contact hole 36 is also called a contact plug, which is a conductive structure connecting different layers of a semiconductor device. The contact hole 36 may include a hole defined in a semiconductor material and a conductive material filled in the hole. The conductive material may be, for example, a metal or polysilicon, etc., and the present application does not make specific restrictions. The contact hole 36 may be configured to provide a voltage to the conductive layer 34. The contact hole 36 itself may also generate a corresponding electric field, which may cooperate with the electric field generated by the conductive layer 34 to better adjust the electric field distribution of the first drift region 12 of the LDMOS device 1 and enhance the voltage resistance performance of the LDMOS device 1.

[0039] In some embodiments, the conductive layer 34 may be in the shape of a thin film. The conductive layer 34 includes a conductive material. In this embodiment, the conductive layer 34 includes a TiN material as the conductive material. The TiN material has good conductivity, excellent stability and corrosion resistance, and high mechanical hardness, which can ensure the integrity of the conductive layer 34 during the manufacturing process and increase the yield of the LDMOS device 1 of the present application. Furthermore, the TiN material has excellent diffusion barrier properties and can be used as a stop layer (stoplayer) in the process of making a jack or plug. In addition, TiN has good adhesion to the conductive material, which can improve the connection reliability between the conductive layer 34 and the contact hole 36.

[0040] like Figure 2As shown, the first shallow trench isolation structure 32 may include a trench 322 and an insulating material 324 filled in the trench 322. The insulating material 324 may be, for example, SiO2, etc., and this application does not make any specific restrictions. Specifically, the first shallow trench isolation structure 32 may be formed based on shallow trench isolation (STI) technology. Figure 2 The groove 322 shown is a trapezoidal groove 322 that is wide at the top and narrow at the bottom. The groove 322 can also be a rectangular groove 322, an inverted trapezoidal groove 322 that is narrow at the top and wide at the bottom, a U-shaped groove 322 with an arc-shaped bottom, etc. The present application does not impose any specific restrictions on this.

[0041] In some embodiments, the conductive layer 34 is close to the wall of the trench 322 and is buried in the insulating material 324. Figure 2 As shown, the conductive layer 34 may extend substantially along the bottom wall and the side wall of the trench 322. Preferably, the conductive layer 34 may completely cover the trench wall of the trench 322, thereby increasing the extension area of ​​the conductive layer 34 as much as possible and improving the electric field adjustment efficiency of the first drift region 12 outside the first shallow trench isolation structure 32.

[0042] In some embodiments, Figure 2 As shown, the conductive layer 34 can divide the insulating material 324 into a first insulating material portion 3241 adjacent to the groove wall and a second insulating material portion 3242 away from the groove wall. The contact hole 36 can be configured to pass through the second insulating material portion 3242 and connect to the conductive layer 34. The first insulating material portion 3241 can isolate the conductive layer 34 from the first drift region 12, thereby preventing the conductive layer 34 from generating leakage current. Through this arrangement, the first insulating material portion 3241 and the second insulating material portion 3242 can jointly fix the conductive layer 34 firmly in the first shallow trench isolation structure 32.

[0043] In some embodiments, the LDMOS device 1 may further include a gate structure 26. The gate structure 26 may be located between the first source-drain region 22 and the second source-drain region 24, and located on a portion of the first drift region 12, a portion of the first well region 14, and a portion of the surface of the buried field plate unit 30.

[0044] The gate structure 26 includes a gate insulating layer 262 and a gate electrode layer 264. The gate insulating layer 262 is located between the gate electrode layer 264 and the semiconductor substrate 10. That is, the gate insulating layer 262 may be located on the surface of a portion of the first drift region 12, a portion of the first well region 14, and a portion of the buried field plate unit 30. The gate insulating layer 262 is used to isolate the gate electrode layer 264 from the semiconductor substrate 10. In other words, the gate electrode layer 264 may be located on the surface of a portion of the first drift region 12, a portion of the first well region 14, and a portion of the buried field plate unit 30, and is separated from these portions by the gate insulating layer 262. The gate insulating layer 262 may be formed, for example, of silicon oxide, silicon oxynitride, a high-κ dielectric, or other insulating materials, and the gate electrode layer 264 may be formed, for example, of polysilicon, metal, or other materials, and the present application does not make specific restrictions.

[0045] The gate structure 26 also includes a spacer. The spacer may include one or more wall layers. The spacer includes one or more dielectric layers, such as SiO2, SiN, and SiO2, disposed on both sides of the gate electrode layer 264. The spacer may isolate and protect the gate electrode layer 264, which will not be described in detail in this application.

[0046] In some embodiments, the LDMOS device 1 may further include a second shallow trench isolation structure 16. The second shallow trench isolation structure 16 is disposed in the first well region 14 and is located on a side of the second source-drain region 24 away from the first source-drain region 22. Figure 2 As shown, the second shallow trench isolation structure 16 is disposed on both sides of the transistor in the common drain region to separate the transistor in the common drain region from other parts. The second shallow trench isolation structure 16 can be a common shallow trench isolation structure, which will not be described in detail here.

[0047] refer to Figure 3 , Figure 3 is a flow chart of the preparation method according to some embodiments of the present application. Figure 3 As shown, combined Figure 2 and Figures 5 to 10 The present application provides a method for preparing an LDMOS device 1, comprising the following steps.

[0048] S31 : manufacturing a buried field plate unit 30 in the semiconductor substrate 10 .

[0049] In some embodiments, as described above, the buried field plate unit 30 includes a first shallow trench isolation structure 32 and a conductive layer 34. The conductive layer 34 is configured to be buried in the first shallow trench isolation structure 32.

[0050] In the case where the LDMOS device 1 is a transistor with a common drain region, two spaced-apart buried field plate units 30 may be fabricated in the semiconductor substrate 10 .

[0051] In some embodiments, two second shallow trench isolation structures 16 distributed on both sides of the LDMOS device 1 may be fabricated in the semiconductor substrate 10. The second shallow trench isolation structure 16 may be used to separate the transistor from other parts of the LDMOS device 1. The second shallow trench isolation structure 16 may be a common shallow trench isolation structure, which will not be described in detail in this application.

[0052] As described above, the material of the semiconductor substrate 10 can be a semiconductor material such as Si, SiGe, SiGeC, SiC, GaAs, InAs, InP, other III / V or II / VI compound semiconductors, etc., and can also include a layered substrate such as Si / SiGe, Si / SiC, silicon on insulator (SOI) or silicon germanium on insulator, and the present application does not impose any restrictions on this.

[0053] refer to Figure 4 , Figure 4 According to some embodiments of the present application Figure 3 The schematic diagram of the structure of the LDMOS device 1 in the process of preparing the buried field plate unit 30 according to an embodiment of the present application can be specifically referred to Figure 5-Figure 10 .

[0054] refer to Figure 4 The operation of manufacturing the buried field plate unit 30 in the semiconductor substrate 10 includes the following steps.

[0055] S311 : defining a trench 322 in the semiconductor substrate 10 .

[0056] In some embodiments, a groove 322 of a predetermined depth is defined in the semiconductor substrate 10 by photolithography or etching. The depth of the groove 322 can be set according to the specific application scenario, and this application will not repeat it here. The shape of the groove 322 can be a trapezoidal groove 322 with a wide top and a narrow bottom, the groove 322 can also be a rectangular groove 322, an inverted trapezoidal groove 322 with a narrow top and a wide bottom, a U-shaped groove 322 with an arc at the bottom, etc., and this application does not make specific restrictions on this.

[0057] The following uses a hard mask as an example to introduce the method for defining the groove 322. The hard mask has the characteristics of high hardness, strong chemical inertness, high melting point, and high etching selectivity. It can be used to etch a deeper target depth with a very thin thickness, which can improve the etching resolution, the stability of the etching process, and the product yield.

[0058] First, a hard mask layer may be formed on the semiconductor substrate 10. Before forming the hard mask, an oxide layer (e.g., SiO2) may be deposited on the semiconductor substrate 10 as a buffer layer. The hard mask may, for example, include silicon nitride (Si3N4), and the present application does not limit the specific material of the hard mask.

[0059] Next, the hard mask and / or oxide layer may be patterned to expose an exposed area corresponding to the trench 322. In some embodiments, a photolithography process may be used to define an exposed position above the trench 322 on the hard mask, and then the hard mask and / or oxide layer in the exposed area may be removed by etching.

[0060] Next, the semiconductor substrate 10 below the exposed region is etched away to form a trench 322 with a predetermined depth.

[0061] In some embodiments, after etching to form the trench 322, the trench walls, including the sidewalls and the bottom wall, of the trench 322 may be oxidized to form a silicon oxide layer. This operation may reduce the defect density at the interface between the trench 322 and the semiconductor substrate 10 and reduce the risk of leakage.

[0062] S312 : Filling the first insulating material portion 3241 in the trench 322 .

[0063] refer to Figure 5 , Figure 5 It is a first structural schematic diagram of the preparation process of the buried field plate unit according to some embodiments of the present application. Figure 5 The retained hard mask 3222 is also shown in bold black lines. A layer of silicon oxide or other insulating material type may be deposited on the bottom wall and sidewall of the trench 322 by a process such as chemical vapor deposition (CVD) as the first insulating material portion 3241 .

[0064] The first insulating material portion 3241 can isolate the conductive layer 34 from the first drift region 12 , thereby preventing the conductive layer 34 from generating leakage current.

[0065] S313 : forming a conductive layer 34 on the surface of the first insulating material portion 3241 .

[0066] In some embodiments, the conductive layer 34 may include TiN material as the conductive material. That is, a TiN material layer is formed on the surface of the first insulating material portion 3241. The TiN material has good conductivity, excellent stability and corrosion resistance, and high mechanical hardness, which can ensure the integrity of the conductive layer 34 during the manufacturing process and increase the yield of the LDMOS device 1 of the present application. Furthermore, the TiN material has excellent diffusion barrier properties and can be used as a barrier layer in the process of making the contact hole 36. In addition, TiN has good adhesion to the conductive material, which can improve the connection reliability between the conductive layer 34 and the socket. The present application does not limit the specific type of the conductive material of the conductive layer.

[0067] refer to Figure 6 , Figure 63 is a second structural schematic diagram of the preparation process of the buried field plate unit according to some embodiments of the present application. A conductive material film layer 342 may be first deposited on the surface of the LDMOS device 1. The conductive material film layer 342 may be, for example, a TiN layer. Specifically, a TiN layer may be deposited on the surface of the LDMOS device 1 by physical vapor deposition or chemical vapor deposition.

[0068] refer to Figure 7 , Figure 7 FIG. 1 is a third structural schematic diagram of a process for preparing a buried field plate unit according to some embodiments of the present application. Figure 7 As shown, next, the trench 322 is filled with photoresist 344 .

[0069] refer to Figure 8 , Figure 8 FIG. 4 is a fourth structural schematic diagram of a process for preparing a buried field plate unit according to some embodiments of the present application. Figure 8 As shown, next, the other parts of the conductive material film layer 342 are etched away, leaving only the conductive material film layer 342 in the groove 322 as the conductive layer 34 in the buried field plate unit 30 , and then the remaining photoresist 344 is removed.

[0070] S314 : Filling the second insulating material portion 3242 in the trench 322 .

[0071] refer to Fig. 9 , Fig. 9 FIG. 5 is a fifth structural diagram of a process for preparing a buried field plate unit according to some embodiments of the present application. Fig. 9 As shown, silicon oxide or other insulating material types can be filled in the trench 322 by chemical vapor deposition (CVD) and other processes to serve as the second insulating material portion 3242. The first insulating material portion 3241 and the second insulating material portion 3242 sandwich the conductive layer 34. The first insulating material portion 3241 and the second insulating material portion 3242 together constitute the insulating material 324 of the first shallow trench isolation structure 32.

[0072] After the insulating material is filled in the trench 322, an insulating material layer covering at least a portion of the surface of the LDMOS device 1 may be further filled. The excess insulating material layer may ensure that the surface of the LDMOS device 1 is sufficiently flat, thereby facilitating a subsequent chemical mechanical polishing (CMP) process.

[0073] S315 : removing the insulating material layer and the hard mask 3222 on the surface of the semiconductor substrate 10 to expose the buried field plate unit 30 .

[0074] In some embodiments, the excess insulating material layer on the surface of the semiconductor substrate 10 is polished away by a chemical mechanical polishing process. The chemical mechanical polishing process can use the hard mask 3222 as a stop layer. The embodiments of the present application can continue to remove the hard mask 3222 and / or the oxide layer on the surface of the semiconductor substrate 10 by etching or other methods.

[0075] refer to Fig.10 , Fig.10 FIG. 6 is a sixth structural diagram of a process for preparing a buried field plate unit according to some embodiments of the present application. Fig.10 As shown, the preparation of the first shallow trench isolation structure 32 is completed, and the excess insulating material layer, the hard mask 3222 and / or the oxide layer on the surface of the semiconductor substrate 10 have been completely removed.

[0076] S32 : forming a first drift region 12 and a first well region 14 adjacent to each other in the semiconductor substrate 10 by doping.

[0077] The position of the first drift region 12 may be arranged corresponding to the position of the buried field plate unit 30. Specifically, the first drift region 12 may be arranged as a continuous region surrounding and adjacent to the buried field plate unit 30. In other words, the buried field plate unit 30 is arranged in the first drift region 12.

[0078] refer to Figure 2 In the case where the LDMOS device 1 is a transistor with two shared drain regions and there are two spaced-apart buried field plate units 30 , the first drift region 12 may be configured as a continuous region surrounding and adjacent to the two spaced-apart buried field plate units 30 .

[0079] In some embodiments, the first drift region 12 and the first well region 14 have opposite doping types. Figure 2 The doping type of the first drift region 12 shown in the figure may be P-type, and the doping type of the first well region 14 may be N-type, which is not specifically limited in the present application.

[0080] In the case where the LDMOS device 1 is a transistor with two shared drain regions, the LDMOS device 1 may include a first drift region 12 formed between two first well regions 14 .

[0081] In some embodiments, in the case where there are two second shallow trench isolation structures 16 , the first well region 14 and the first drift region 12 may be formed between the two second shallow trench isolation structures 16 .

[0082] S33: doping the first drift region 12 to form a first source-drain region 22, and doping the first well region 14 to form a second source-drain region 24. The first source-drain region 22 is located on a side of the buried field plate unit 30 away from the first well region 14.

[0083] In some embodiments, the preparation method of the present application may further include manufacturing a gate structure 26. The gate structure 26 is located between the first source-drain region 22 and the second source-drain region 24, and is located on a portion of the first drift region 12, a portion of the first well region 14, and a portion of the surface of the buried field plate unit 30. The gate structure 26 can be manufactured by a gate-first process or a gate-last process, which is not specifically limited in the present application and will not be described in detail herein.

[0084] S34 : making a contact hole 36 connected to the conductive layer 34 .

[0085] In some embodiments, a contact window exposing the conductive layer 34 may be formed through the second insulating material portion 3242, and a conductive material may be filled in the contact window to form a contact hole 36. The conductive material may be, for example, metal or other conductive materials, and the present application does not impose any specific limitation.

[0086] In some embodiments, an interlayer dielectric layer (not shown) may be formed to cover the gate structure 26 . A contact window may be formed through the interlayer dielectric layer and the second insulating material portion 3242 , and a conductive material may be filled in the contact window to form a contact hole 36 .

[0087] When forming a contact window, the conductive layer 34 of the buried field plate unit 30 can be used as a stop layer or a barrier layer. TiN material has excellent diffusion barrier properties and is suitable for being used as a stop layer.

[0088] The contact hole 36 may be configured to connect the conductive layer 34 to a control terminal. The control terminal may be configured to apply a predetermined voltage to the conductive layer 34 to adjust the electric field distribution around the first drift region 12 of the buried field plate unit 30, thereby enhancing the durability of the LDMOS device 1.

[0089] The embodiment of the present application provides a method for preparing an LDMOS device 1. The LDMOS device 1 includes a buried field plate unit 30 disposed in a first drift region 12. The buried field plate unit 30 includes a conductive layer 34 buried in a first shallow trench isolation structure 32. The conductive layer 34 can form a large-area field plate of the first drift region 12 close to the bottom wall and side wall of the first shallow trench isolation structure 32. By applying a voltage, especially a reverse voltage, to the conductive layer 34, the electric field distribution of the first drift region 12 of the LDMOS device 1 can be better adjusted, and the impact ionization intensity of the first drift region 12 can be improved. Through this configuration, the breakdown voltage of the LDMOS device 1 can be increased without increasing the on-resistance of the LDMOS device 1, thereby improving its withstand voltage performance.

[0090] refer to Fig.11 , Fig.11It is a TCAD simulation result of the LDMOS device 1 according to some embodiments of the present application. Those skilled in the art should know that TCAD (Technology Computer-Aided Design) is a computer-aided design tool for designing and analyzing semiconductor devices, which will not be described in detail here.

[0091] Specifically, Fig.11 The IdVd curve of the LDMOS device 1 is shown. The IdVd curve is also called the drain current-voltage curve. The horizontal axis of the curve is Vd (Drain-Source Voltage, drain voltage), and the unit is volt (V). The vertical axis of the curve is I d (Drain Current, drain current), and the unit is ampere (A). Fig.11 Three I dVd curves are shown, corresponding to the I dVd curves under the reference voltage (i.e., no reverse voltage is applied to the buried field plate unit 30), the reverse voltage of 5V is applied to the buried field plate unit 30, and the reverse voltage of 10V is applied to the buried field plate unit 30. The reverse voltage is a voltage with a polarity opposite to the voltage at the drain end of the transistor, also known as a reverse bias voltage. For example, when the voltage at the drain end is a positive voltage, the reverse voltage is a negative voltage, and vice versa.

[0092] like Fig.11 As shown, when the drain voltage Vd is the same, the greater the reverse voltage, the smaller the drain current Id.

[0093] The breakdown voltage of the LDMOS device 1 is characterized by a voltage threshold that causes the drain current to increase rapidly when the voltage applied between the drain and source of the LDMOS device 1 reaches a certain value. Fig.11 In the graph, when no reverse voltage (reference voltage curve) is applied to the buried field plate unit 30, the breakdown voltage corresponding to the rapid increase of the drain current is 30.6V. When a reverse voltage of 10V is applied to the buried field plate unit 30, the breakdown voltage corresponding to the rapid increase of the drain current is 33.1V. It can be seen that the breakdown voltage of the latter is 8.2% higher than that of the former. Therefore, applying a reverse voltage to the buried field plate unit 30 can effectively increase the breakdown voltage of the LDMOS device 1.

[0094] refer to Figures 12 to 15 , Fig.12 is a simulation result of the impact ionization intensity of the LDMOS device 1 when the buried field plate unit 30 is not provided. Fig.13 It is a simulation result of the impact ionization intensity of the LDMOS device 1 when a reverse voltage of 10V is applied to the buried field plate unit 30 according to some embodiments of the present application. Fig.14 is a simulation result of the current density of the LDMOS device 1 when the buried field plate unit 30 is not provided. Fig.15 1 is a simulation result of the current density of the LDMOS device 1 when a reverse voltage of 10V is applied to the buried field plate unit 30 according to some embodiments of the present application.

[0095] exist Figure 12-Figure 15 In the figure, the drain voltage Vd (or the reference drain voltage, shown as Ref@Vd) is 25V, and the LDMOS device 1 is not broken down.

[0096] like Fig.12 As shown, when the buried field plate unit 30 is not provided, there is a portion with a high impact ionization intensity in the first drift region 12 adjacent to the first shallow trench isolation structure 32, especially at the corner of the first shallow trench isolation structure 32. Fig.13 As shown, when the buried field plate unit 30 is provided and a reverse voltage of 10 V is applied, the high impact ionization region near the first shallow trench isolation structure 32 is significantly eliminated.

[0097] like Fig.14 As shown, when the buried field plate unit 30 is not provided, there is a portion with a high current density in the first drift region 12 adjacent to the first shallow trench isolation structure 32, especially at the corner of the first shallow trench isolation structure 32. Fig.15 As shown, when the buried field plate unit 30 is provided and a reverse voltage of 10V is applied, the high current density region near the first shallow trench isolation structure 32 is significantly eliminated.

[0098] In summary, Figure 12-Figure 15 It can be seen that when a buried field plate unit 30 is set in the LDMOS device 1 and a reverse voltage is applied, the electric field formed by the conductive layer 34 and the contact hole 36 can effectively reduce the collision ionization intensity and current density in the surrounding first drift region 12, thereby enhancing the breakdown voltage of the first drift region 12 and improving the durability of the LDMOS device 1. The technical effect of the technical solution of the present application is significant.

[0099] The above description of various embodiments tends to emphasize the differences between the various embodiments. The same or similar aspects can be referenced to each other, and for the sake of brevity, they will not be repeated herein.

Claims

1. An LDMOS device, characterized in that: include: Semiconductor substrate; A first drift region and a first well region are formed in the semiconductor substrate and are adjacent to each other; a first source-drain region, disposed in the first drift region; a second source-drain region, disposed in the first well region; The buried field plate unit comprises: A first shallow trench isolation structure is disposed in the first drift region and between the first source-drain region and the second source-drain region; as well as A conductive layer is buried in the first shallow trench isolation structure.

2. The LDMOS device according to claim 1, characterized in that: The buried field plate unit further includes a contact hole configured to be connected to the conductive layer.

3. The LDMOS device according to claim 1, characterized in that: The gate structure is located between the first source-drain region and the second source-drain region, and is located on a surface of a portion of the first drift region, a portion of the first well region, and a portion of the buried field plate unit.

4. The LDMOS device according to claim 1, characterized in that: The conductive layer includes TiN material.

5. The LDMOS device according to claim 2, characterized in that: The first shallow trench isolation structure includes a trench and an insulating material filled in the trench; and The conductive layer is close to the groove wall of the groove and buried in the insulating material.

6. The LDMOS device according to claim 5, characterized in that: The conductive layer divides the insulating material into a first insulating material portion adjacent to the slot wall and a second insulating material portion away from the slot wall; and The contact hole is configured to pass through the second insulating material portion and connect to the conductive layer.

7. The LDMOS device according to claim 1, characterized in that: The first drift region and the first well region have opposite doping types.

8. The LDMOS device according to claim 1, characterized in that: Also includes: The second shallow trench isolation structure is arranged in the first well region and is located on a side of the second source-drain region away from the first source-drain region.

9. A method for preparing an LDMOS device, characterized in that: include: A buried field plate unit is fabricated in a semiconductor substrate, wherein the buried field plate unit comprises: a first shallow trench isolation structure, and a conductive layer buried in the first shallow trench isolation structure; By doping, forming a first drift region and a first well region adjacent to each other in the semiconductor substrate, wherein the first drift region is configured as a continuous region surrounding and adjacent to the buried field plate unit; and A first source-drain region is doped in the first drift region, and a second source-drain region is doped in the first well region, wherein the first source-drain region is located on a side of the buried field plate unit away from the first well region.

10. The method according to claim 9, characterized in that Also includes: Making the gate structure, The gate structure is located between the first source-drain region and the second source-drain region, and is located on a portion of the first drift region, a portion of the first well region, and a portion of the surface of the buried field plate unit.

11. The method according to claim 10, characterized in that Also includes: A contact hole connected to the conductive layer is made.

12. The method according to claim 9, characterized in that The method of manufacturing a buried field plate unit in a semiconductor substrate comprises: defining a trench in the semiconductor substrate; Filling a first insulating material portion in the trench; forming the conductive layer on the surface of the first insulating material portion; and A second insulating material portion is filled in the trench.

13. The method according to claim 12, characterized in that The forming of the conductive layer on the surface of the first insulating material portion comprises: A TiN material layer is formed on the surface of the first insulating material portion.

14. The method according to claim 12, characterized in that Also includes: forming a contact window through the second insulating material to partially expose the conductive layer; as well as A conductive material is filled in the contact window to form a contact hole.

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