P-type horizontal gallium oxide diode device and preparation method thereof

Abstract

The invention discloses a P-type gallium oxide horizontal diode device structure and a preparation method thereof, and mainly solves the problems of small current and poor voltage endurance capability of the existing similar device. The device structure comprises a gallium oxide insulating substrate (1), a gallium oxide P-type layer (2), cathode metal (3) and anode metal (4). Wherein the nickel oxide P-type layer is realized by performing ion implantation and annealing activation processes on the surface of the gallium oxide insulating substrate, and compared with the existing heterogeneous material deposition process, the implantation process has no interface defect, and the voltage endurance capability of the device can be improved. As the extension performance improvement of the device structure, a nickel oxide layer (5) can be additionally arranged between the gallium oxide P-type layer and the cathode to improve the conductivity of the device, or a field plate structure (6) is additionally arranged on the anode metal to further improve the voltage endurance capability of the device. The invention has the advantages of good conductivity and strong voltage endurance capability, and can be used for high-voltage high-power circuits such as high-voltage power grids, current inverters and data center power.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and specifically relates to a P-type horizontal gallium oxide diode device, which can be used in circuits such as high-voltage power grids, current inverters, and data center power supplies. Background Art

[0002] Gallium oxide has a relatively high bandgap of 4.5-4.9 eV and a 2 / Vs and a high critical breakdown field strength of ~8MV / cm make it have great potential in the application field of power electronics, which also makes gallium oxide one of the current research hotspots. Compared with traditional semiconductor materials, gallium oxide devices can achieve a larger power figure of merit at the same size, which means that the device performance of gallium oxide far exceeds that of traditional semiconductor devices. However, due to the crystal structure, oxygen vacancy defects, and valence band structure of the gallium oxide material itself, gallium oxide currently only has N-type devices, which greatly limits the application of gallium oxide in functional circuits such as amplifiers, oscillators, filters, etc., and limits the further improvement of the performance of gallium oxide devices.

[0003] For gallium oxide materials, due to the impurity defects introduced during the growth process, gallium oxide single crystals usually become N-type semiconductors, mainly because the electronegativity of oxygen is higher than that of possible P-type dopants, and the acceptor energy level is mostly located at the bottom of the band gap, so it is difficult for the doped element to ionize to form free holes. In addition, the N-type background impurities existing in the gallium oxide material itself will also form a self-compensation effect, which makes it difficult to achieve P-type gallium oxide materials. Therefore, in order to obtain effective P-type materials, a P-type dopant with a higher electronegativity should be found, and the formation of natural oxygen vacancy defects in gallium oxide should be suppressed. There are currently two doping methods for this, namely single doping method and co-doping method. Single doping current research shows that effective single elements are mainly Mg, Cu, Zn, Fe, N, etc. In addition to doping the above metal elements, co-doping will also select F, Cl, P and other non-metallic elements for co-doping.

[0004] Patent document with application number CN202411108620.7 discloses a lateral gallium oxide high-voltage Schottky diode and its preparation method, the structural diagram of which is shown in Figure 1 As shown, the anode and cathode electrodes are directly deposited on the gallium oxide material to form a horizontal Schottky diode device, but it is an N-type device, and its majority carriers are electrons.

[0005] Patent document with application number CN202410958170.4 discloses a p-type organic material, a self-driven gallium oxide ultraviolet photodetector and a preparation method thereof, which prepares a detection device by depositing a layer of p-type organic material on the surface of gallium oxide as the P-type layer of gallium oxide. However, the crystal structure of the P-type organic material is complex, which is not conducive to the power device's demand for high power and high current. The doping concentration is also difficult to adjust, and there are many defects at the interface of heterogeneous materials, which is not conducive to the device's voltage resistance characteristics. Summary of the invention

[0006] The purpose of the present invention is to address the shortcomings and deficiencies of the prior art and propose a P-type horizontal gallium oxide diode device and a preparation method. By adopting ion implantation and annealing processes to form a homogeneous P-type layer on the surface of an insulating gallium oxide substrate, the oxygen vacancy defects of the N-type gallium oxide are suppressed, and the activation rate of the P-type impurities is increased, so that the gallium oxide device has a larger current and better voltage resistance.

[0007] According to the above ideas, the technical solutions of the present invention include the following:

[0008] Technical solution 1:

[0009] 1. A P-type horizontal gallium oxide diode device, comprising a gallium oxide insulating substrate, a cathode metal and an anode metal, characterized in that a gallium oxide P-type layer is provided on the gallium oxide insulating substrate to increase the device current and improve the withstand voltage capability.

[0010] Preferably, the gallium oxide P-type layer has a depth of 10 nm-10 μm, an injection angle of 0°-14°, and a target injection concentration of 1×10 16 ~1×10 19 cm -3 .

[0011] Preferably, the ions implanted into the gallium oxide P-type layer are any one of Mg, Cu, Zn, Fe, and N, or any combination of elements such as Mg, Cu, Zn, Fe, N, F, Cl, and P.

[0012] Preferably, the gallium oxide insulating substrate has a thickness of 100 μm-3 mm and a doping concentration of 1×10 15 ~1×10 17 cm -3 .

[0013] 2. A method for manufacturing the P-type horizontal gallium oxide diode device, characterized in that it comprises the following steps:

[0014] 1) Selecting a gallium oxide insulating substrate and pre-treating it;

[0015] 2) Preparation of gallium oxide P-type layer:

[0016] 2a) A concentration of 1×10 16 ~1×10 19 cm -3 Ion implantation is performed to form an ion implantation region with a depth of 10 nm-10 μm, and the element selected for the ion implantation is one or any combination of Mg, Cu, Zn, Fe, N, F, Cl, and P;

[0017] 2b) placing the sample after ion implantation in a N2 environment and performing an activation treatment at a temperature of 800° C. to 1600° C. for 10 seconds to 10 hours, so that a gallium oxide P-type layer is formed in the ion implantation area;

[0018] 3) Evaporation electrode

[0019] 3a) depositing a Ti / Au or Ti / Al / Ni / Au cathode metal with a thickness of 20nm-800nm ​​on one end of the gallium oxide P-type layer by electron beam evaporation deposition process, and annealing at 400°C-800°C to form an ohmic contact;

[0020] 3b) Depositing Ni / Au, Mo / Au or Pt / Au anode metal with a thickness of 20nm-800nm ​​on the other end of the gallium oxide P-type layer to complete the device manufacturing.

[0021] Technical solution 2:

[0022] 1. A P-type horizontal gallium oxide diode device, comprising a gallium oxide insulating substrate (1), a cathode metal (3)

[0023] and an anode metal (4), characterized in that:

[0024] A gallium oxide P-type layer (2) is provided on the gallium oxide insulating substrate (1) to increase device current and improve voltage resistance;

[0025] A nickel oxide layer (5) is deposited on the upper part of the gallium oxide P-type layer (2) to reduce the ohmic contact resistance.

[0026] 2. A method for manufacturing a P-type horizontal gallium oxide diode device having a nickel oxide layer, characterized in that it comprises the following steps:

[0027] The first step is to select a gallium oxide insulating substrate and pre-treat it;

[0028] The second step is to prepare the gallium oxide P-type layer:

[0029] First, a 1×10 16 ~1×10 19 cm -3Ion implantation is performed to form an ion implantation region with a depth of 10 nm-10 μm, and the element selected for the ion implantation is one or any combination of Mg, Cu, Zn, Fe, N, F, Cl, and P;

[0030] Then, the sample after ion implantation is placed in a N2 environment and activated at a temperature of 800°C-1600°C for 10s-10h, so that a gallium oxide P-type layer is formed in the ion implantation area;

[0031] The third step is to use a photoresist to perform image processing on the surface of the gallium oxide P-type layer, and deposit a nickel oxide layer (5);

[0032] Step 4: Prepare electrodes:

[0033] Depositing Ti / Au or Ti / Al / Ni / Au cathode metal with a thickness of 20nm-800nm ​​on one end of the gallium oxide P-type layer by electron beam evaporation deposition process, and annealing at 400℃-800℃ to form an ohmic contact;

[0034] A Ni / Au, Mo / Au or Pt / Au anode metal with a thickness of 20nm-800nm ​​is deposited on the other end of the gallium oxide P-type layer not covered by the nickel oxide layer (5) to complete the device manufacturing.

[0035] Technical solution three:

[0036] 1 A P-type horizontal gallium oxide diode device, comprising a gallium oxide insulating substrate (1), a cathode metal (3)

[0037] and an anode metal (4), characterized in that:

[0038] A gallium oxide P-type layer (2) is provided on the gallium oxide insulating substrate (1) to increase device current and improve voltage resistance;

[0039] A field plate metal (6) is provided on the anode metal (3) to further improve the voltage resistance of the device.

[0040] 2. A method for preparing a P-type horizontal gallium oxide diode device with a field plate, characterized in that it comprises the following steps:

[0041] S1) selecting a gallium oxide insulating substrate and pre-treating it;

[0042] S2) preparing a gallium oxide P-type layer:

[0043] S2a) The concentration of 1×10 16 ~1×10 19 cm -3Ion implantation is performed to form an ion implantation region with a depth of 10 nm-10 μm, and the element selected for the ion implantation is one or any combination of Mg, Cu, Zn, Fe, N, F, Cl, and P;

[0044] S2b) placing the sample after ion implantation in a N2 environment and performing an activation treatment at a temperature of 800° C. to 1600° C. for 10 seconds to 10 hours, so that a gallium oxide P-type layer is formed in the ion implantation area;

[0045] S3) Evaporation electrode

[0046] Depositing Ti / Au or Ti / Al / Ni / Au cathode metal with a thickness of 20nm-800nm ​​on one end of the gallium oxide P-type layer by electron beam evaporation deposition process, and annealing at 400℃-800℃ to form an ohmic contact;

[0047] S4) depositing a field plate dielectric layer with a thickness of 100nm-500nm on the anode metal, and then depositing a field plate metal on the field plate dielectric by electron beam evaporation to complete the device preparation.

[0048] Compared with the prior art, the present invention has the following advantages.

[0049] Firstly, since the present invention prepares a P-type layer on a gallium oxide insulating substrate, the lower background carriers of the gallium oxide insulating substrate can suppress the impurity self-compensation effect of the P-type layer, thereby enhancing the conductivity of the P-type layer. In addition, the lower impurities and defects in the insulating substrate greatly improve the activation rate of the injected ions, thereby providing more carriers and further improving the conductivity of the P-type layer. Meanwhile, since the P-type layer is prepared on the surface of the insulating substrate by ion implantation and annealing processes, compared with depositing heterogeneous P-type materials on the surface of gallium oxide, there are no interface defects, thereby improving the withstand voltage capability of the device.

[0050] Secondly, the second technical solution of the present invention inserts a nickel oxide layer between the gallium oxide P-type layer and the cathode metal electrode, which can reduce the cathode contact resistance and increase the current of the device.

[0051] Thirdly, in the third technical solution of the present invention, a field plate is prepared on the anode metal to further improve the voltage resistance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0053] Figure 1 It is a structural diagram of the prior art;

[0054] Figure 2 It is a schematic cross-sectional structure diagram of a device according to a first technical solution of the present invention;

[0055] Figure 3 It is a schematic diagram of the cross-sectional structure of the device of the second technical solution of the present invention;

[0056] Figure 4 It is a schematic cross-sectional structure diagram of the third device of the technical solution of the present invention;

[0057] Figure 5 The present invention is prepared Figure 2 Schematic diagram of the device process;

[0058] Figure 6 The present invention is prepared Figure 3 Schematic diagram of the device process;

[0059] Figure 7 The present invention is prepared Figure 4 Schematic diagram of the device flow. DETAILED DESCRIPTION

[0060] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0061] Embodiment 1:

[0062] Reference Figure 2 The P-type horizontal gallium oxide diode device of this example includes a gallium oxide insulating substrate 1, a gallium oxide P-type layer 2, a cathode metal 3 and an anode metal 4, wherein:

[0063] The gallium oxide insulating substrate has a thickness of 100 μm-3 mm and a doping concentration of 1×10 15 ~1×10 17 cm -3 .

[0064] The gallium oxide P-type layer 2 is located on the upper part of the gallium oxide insulating substrate 1, has a depth of 10 nm-10 μm, an injection angle of 0°-14°, and a target injection concentration of 1×10 16 ~1×10 19 cm -3 The injected ions are any one of Mg, Cu, Zn, Fe, N or any combination of Mg, Cu, Zn, Fe, N, F, Cl, P and other elements.

[0065] The cathode metal 3 is located at one end of the surface of the gallium oxide P-type layer 2, and the cathode metal is Ti / Au or Ti / Al / Ni / Au, and the metal thickness is 20nm-800nm;

[0066] The anode metal 4 is located at the other end of the surface of the gallium oxide P-type layer. The anode metal is any one of Ni / Au, Mo / Au and Pt / Au, and the metal thickness is 20nm-800nm.

[0067] Embodiment 2:

[0068] Reference Figure 3 The P-type horizontal gallium oxide diode device of this example includes a gallium oxide insulating substrate 1, a gallium oxide P-type layer 2, a cathode metal 3, an anode metal 4, and a nickel oxide layer 5, wherein:

[0069] The gallium oxide insulating substrate 1 has a thickness of 100 μm-3 mm and a doping concentration of 1×10 15 ~1×10 17 cm -3 .

[0070] The gallium oxide P-type layer 2 is located on the upper part of the gallium oxide insulating substrate 1, has a depth of 10 nm-10 μm, an injection angle of 0°-14°, and a target injection concentration of 1×10 16 ~1×10 19 cm -3 ; The injected ions are any one of Mg, Cu, Zn, Fe, N or any combination of elements such as Mg, Cu, Zn, Fe, N, F, Cl, P, etc.

[0071] The nickel oxide layer 5 is located on the upper portion of the gallium oxide P-type layer 2 to reduce the ohmic contact resistance.

[0072] The cathode metal 3 is located at one end of the nickel oxide layer and has a thickness of 20nm-800nm ​​Ti / Au or Ti / Al / Ni / Au.

[0073] The anode metal is located at the other end of the gallium oxide P-type layer not covered by the nickel oxide layer 5, and has a thickness of 20nm-800nm ​​of Ni / Au, Mo / Au or Pt / Au.

[0074] Example 3

[0075] Reference Figure 4 The P-type horizontal gallium oxide diode device of this example includes a gallium oxide insulating substrate 1, a gallium oxide P-type layer 2, a cathode metal 3, an anode metal 4 and a field plate metal 6.

[0076] The gallium oxide insulating substrate has a thickness of 100 μm-3 mm and a doping concentration of 1×10 15 ~1×10 17 cm -3 .

[0077] The gallium oxide P-type layer 2 is located on the upper part of the gallium oxide insulating substrate 1, has a depth of 10 nm-10 μm, an injection angle of 0°-14°, and a target injection concentration of 1×10 16 ~1×10 19 cm -3 ; The injected ions are any one of Mg, Cu, Zn, Fe, N or any combination of elements such as Mg, Cu, Zn, Fe, N, F, Cl, P, etc.

[0078] The cathode metal 3 is located at one end of the surface of the gallium oxide P-type layer 2. The cathode metal is Ti / Au or Ti / Al / Ni / Au, and the metal thickness is 20nm-800nm.

[0079] The anode metal 4 is located at the other end of the surface of the gallium oxide P-type layer. The anode metal is any one of Ni / Au, Mo / Au and Pt / Au, and the metal thickness is 20nm-800nm.

[0080] The field plate metal 6 is located on the anode metal to further improve the voltage resistance of the device.

[0081] The following is an example of manufacturing the three P-type horizontal gallium oxide diode devices:

[0082] Example 4: A horizontal SBD device is prepared on a gallium oxide insulating substrate having a gallium oxide P-type layer.

[0083] Reference Figure 5 , the implementation steps of this example are as follows:

[0084] Step 1: Select a gallium oxide insulating sheet and pretreat it.

[0085] 1.1) The thickness of the gallium oxide insulating sheet is 100 μm and the doping concentration is 1×10 15 cm -3 ,like Figure 5 (a)

[0086] 1.2) Place the gallium oxide insulating sheet sample in an acetone solution and ultrasonically clean it for 5 minutes, then place it in an isopropanol solution or anhydrous ethanol and ultrasonically clean it for 5 minutes, and then place the substrate in deionized water and ultrasonically clean it for 5 minutes to remove organic impurities on the surface of the gallium oxide;

[0087] 1.3) After the organic cleaning, the sample was placed in piranha solution for 10 minutes of surface optimization treatment, and then washed with deionized water for 5 minutes.

[0088] Step 2: Prepare a gallium oxide P-type layer.

[0089] 2.1) Covering the surface of the pre-treated gallium oxide insulating sheet sample with a layer of photoresist or silicon oxide as a masking material for ion implantation, and exposing the area where ion implantation is required by developing or wet etching;

[0090] 2.2) Set the target ion implantation depth to 10 nm and the target concentration to 1×10 16 cm -3 , the ion implantation angle is 0°, and the implanted ions are Mg ions;

[0091] 2.3) After the ion implantation is completed, the photoresist or silicon oxide used as the ion implantation masking material is washed away, and the gallium oxide insulating sheet is organically cleaned after washing;

[0092] 2.4) After the organic cleaning, the gallium oxide insulating sheet is annealed to activate the implanted ions. The annealing temperature is set to 800° C. and the annealing time is 10 seconds. After the annealing activation, a gallium oxide P-type layer is formed on the surface of the gallium oxide insulating sheet. Figure 5 (b) as shown.

[0093] Step 3, Evaporation of Electrode

[0094] 3.1) Prepare a Ti / Au cathode with a thickness of 10nm / 10nm on the highly doped substrate surface of a gallium oxide epitaxial wafer sample by electron beam evaporation, such as Figure 5 (c)

[0095] 3.2) setting the annealing temperature to 400° C. and the annealing time to 1 min, and performing thermal annealing on the sample deposited with the cathode metal to form an ohmic contact;

[0096] 3.3) Deposit a Mo / Au metal anode with a thickness of 10nm / 10nm on the surface of the P-type gallium oxide layer, such as Figure 5 As shown in (d), the device fabrication is completed.

[0097] Example 5: A P-type horizontal SBD device having a nickel oxide layer is prepared on a gallium oxide insulating substrate having a gallium oxide P-type layer.

[0098] Reference Figure 6 , the implementation of this example is as follows:

[0099] Step 1: Select a gallium oxide insulating sheet and pretreat it.

[0100] The thickness of the gallium oxide insulating sheet is 3 mm and the doping concentration is 1×10 17 cm -3 ,like Figure 6 (a)

[0101] The gallium oxide insulating sheet sample is placed in an acetone solution for ultrasonic cleaning for 10 minutes, then placed in an isopropanol solution or anhydrous ethanol for ultrasonic cleaning for 10 minutes, and then the substrate is placed in deionized water for ultrasonic cleaning for 10 minutes to remove organic impurities on the surface of the gallium oxide;

[0102] After organic cleaning, the sample was placed in piranha solution for 30 minutes of surface optimization treatment, and then rinsed with deionized water for 10 minutes.

[0103] Step 2: Prepare a gallium oxide P-type layer.

[0104] A layer of photoresist or hard mask material such as silicon oxide is covered on the surface of the pre-treated gallium oxide epitaxial wafer sample as a masking material for ion implantation, and a patterning process of the ion implantation area is performed by a developing method or wet etching;

[0105] Set the target ion implantation depth to 10 μm and the target concentration to 1×10 19 cm -3 , the ion implantation angle is 14°, and the implanted ions are co-doped with N and P ions;

[0106] After the ion implantation, the photoresist or silicon oxide used as the ion implantation masking material is washed away, and then the gallium oxide insulating sheet is organically cleaned, and then the gallium oxide insulating sheet after organic cleaning is annealed to activate the implanted ions. The annealing temperature is set to 1600°C, and the annealing time is 10 hours. After annealing activation, a gallium oxide P-type layer is formed on the surface of the gallium oxide insulating sheet, such as Figure 6 (b) as shown.

[0107] Step three: depositing a nickel oxide layer.

[0108] Since the gallium oxide P-type layer usually has a low doping concentration, the resistance of the ohmic contact is larger than that of the highly doped substrate. Therefore, a layer of highly doped heterogeneous P-type material can be deposited to reduce the resistance of the ohmic contact.

[0109] First, a nickel oxide layer is patterned on the surface of the gallium oxide P-type layer using a photoresist, and then a nickel oxide layer is deposited. Figure 6 (c)

[0110] After deposition is complete, the unnecessary nickel oxide material is stripped off and organic cleaning is performed.

[0111] Step 4: Prepare electrodes

[0112] A Ti / Au cathode with a thickness of 400 nm / 400 nm was prepared on the nickel oxide layer by electron beam evaporation, as Figure 6 (d)

[0113] The sample after evaporation of cathode metal was annealed to form ohmic contact. The annealing temperature was set to 800°C and the annealing time was 10 min. A Ni / Au metal anode with a thickness of 400nm / 400nm was deposited on the end of the gallium oxide P-type layer not covered by the nickel oxide layer to complete the device preparation. Figure 6 As shown in (e), the device fabrication is completed.

[0114] Example 6: A horizontal SBD device with a field plate is prepared on a gallium oxide insulating substrate with a gallium oxide P-type layer.

[0115] Reference Figure 7 , the implementation of this example is as follows:

[0116] Step A: Select gallium oxide insulating sheet and pre-treat it

[0117] A1) The thickness of the gallium oxide insulating sheet is 1 mm and the doping concentration is 3×10 16 cm -3 ,like Figure 7 (a)

[0118] A2) performing organic cleaning on the gallium oxide insulating sheet sample, ultrasonically cleaning the sample with acetone solution, isopropanol solution and anhydrous ethanol for 8 minutes respectively, and finally placing the substrate in deionized water for ultrasonic cleaning for 8 minutes to remove organic impurities on the surface of the gallium oxide;

[0119] A3) After the organic cleaning, the sample was placed in piranha solution for 20 minutes of surface optimization treatment, and then rinsed with deionized water for 8 minutes.

[0120] Step B, preparing a gallium oxide P-type layer.

[0121] B1) using photoresist or silicon oxide as a masking material for ion implantation on the pretreated gallium oxide insulating sheet sample, and performing patterning of the ion implantation area by a developing method or wet etching;

[0122] B2) Set the target ion implantation depth to 300nm and the target concentration to 1×10 18 cm -3 The ion implantation angle is 8°, and the implanted ions are co-doped with Mg, N, and P ions. After the ion implantation, the photoresist or silicon oxide used as the ion implantation masking material is washed away, and the gallium oxide insulating sheet is organically cleaned after washing;

[0123] B3) The gallium oxide insulating sheet after organic cleaning is annealed to activate the implanted ions. The annealing temperature is set to 900° C. and the annealing time is 1 hour. After annealing and activation, a gallium oxide P-type layer is formed on the surface of the gallium oxide insulating sheet. Figure 7 (b) as shown.

[0124] Step C, Evaporation of Electrode

[0125] C1) Prepare Ti / Al / Ni / Au cathodes with thickness of 50nm / 30nm / 20nm / 120nm on the surface of the P-type layer of the gallium oxide insulating sheet sample by electron beam evaporation, such as Figure 7 (c)

[0126] C2) performing thermal annealing on the gallium oxide insulating sheet sample after step C1) to form an ohmic contact, the annealing temperature is 600° C., and the duration is 3 minutes.

[0127] C3) A Ni / Au anode with a thickness of 100nm / 300nm is deposited on the epitaxial layer surface of the annealed sample, such as Figure 7 (d) as shown.

[0128] Step D, preparing the field plate.

[0129] D1) Deposit a layer of field plate dielectric 5 with a thickness of 500nm on the anode metal, such as Figure 7 As shown in (e), any one of silicon oxide, silicon nitride and aluminum oxide is usually used for deposition;

[0130] D2) Ni / Au with a thickness of 60nm / 200nm is deposited on the field plate medium by electron beam evaporation as the field plate metal. Figure 7 (e) Device preparation is completed.

[0131] The above descriptions are only a few specific examples of the present invention and do not constitute any limitation to the present invention. Obviously, for professionals in this field, after understanding the content and principles of the present invention, it is possible to make various modifications and changes in form and details without departing from the principles and structures of the present invention. For example, the elements of ion implantation can have other combinations besides those described in the embodiments, and the annealing activation process and the structural parameters of the device can be modified. However, these modifications and changes based on the ideas of the present invention are still within the scope of protection of the claims of the present invention.

Claims

1. A P-type horizontal gallium oxide diode device, comprising a gallium oxide insulating substrate (1), a cathode metal (3) and an anode metal (4), characterized in that: A gallium oxide P-type layer (2) is provided on a gallium oxide insulating substrate (1) to increase device current and improve voltage resistance.

2. The device according to claim 1, characterized in that: The gallium oxide P-type layer (2) has a depth of 10 nm-10 μm, an injection angle of 0°-14°, and a target injection concentration of 1×10 16 ~1×10 19 cm -3 .

3. The device according to claim 1, characterized in that: The gallium oxide P-type layer (2) has implanted ions of any one of Mg, Cu, Zn, Fe, and N, or any combination of elements such as Mg, Cu, Zn, Fe, N, F, Cl, and P.

4. The device according to claim 1, characterized in that: The gallium oxide insulating substrate (1) has a thickness of 100 μm-3 mm and a doping concentration of 1×10 15 ~1×10 17 cm -3 .

5. A P-type horizontal gallium oxide diode device, comprising a gallium oxide insulating substrate (1), a cathode metal (3) and an anode metal (4), characterized in that: A gallium oxide P-type layer (2) is provided on the gallium oxide insulating substrate (1) to increase device current and improve voltage resistance; A nickel oxide layer (5) is deposited on the upper part of the gallium oxide P-type layer (2) to reduce the ohmic contact resistance.

6. A P-type horizontal gallium oxide diode device, comprising a gallium oxide insulating substrate (1), a cathode metal (3) and an anode metal (4), characterized in that: A gallium oxide P-type layer (2) is provided on the gallium oxide insulating substrate (1) to increase device current and improve voltage resistance; A field plate metal (6) is provided on the anode metal (3) to improve the voltage resistance of the device.

7. A method for preparing the P-type horizontal gallium oxide diode device according to claim 1, characterized in that: The steps include: 1) Selecting a gallium oxide insulating substrate and pre-treating it; 2) Preparation of gallium oxide P-type layer: 2a) Ion implantation is performed on the surface of the pretreated gallium oxide insulating substrate to form an ion implantation region with a depth of 10 nm-10 μm, and the target implantation concentration is 1×10 16 ~1×10 19 cm -3 The selected element is any one of Mg, Cu, Zn, Fe, N or a combination of any several of the elements such as Mg, Cu, Zn, Fe, N, F, Cl, P, etc.; 2b) performing annealing activation treatment in a N2 environment, setting the annealing temperature to 800° C.-1600° C. and the annealing time to 10 s-10 h, so that a gallium oxide P-type layer is formed in the ion implantation area; 3) Evaporation electrode 3a) depositing a Ti / Au or Ti / Al / Ni / Au cathode metal with a thickness of 20nm-800nm ​​on one end of the gallium oxide P-type layer by electron beam evaporation deposition process, and annealing at 400°C-800°C to form an ohmic contact; 3b) Depositing Ni / Au, Mo / Au or Pt / Au anode metal with a thickness of 20nm-800nm ​​on the other end of the gallium oxide P-type layer to complete the device manufacturing.

8. The method according to claim 7, characterized in that: In step 1), the gallium oxide insulating substrate is pretreated, including organic cleaning and piranha treatment of the gallium oxide insulating substrate, wherein: The organic cleaning is to put the sample into an acetone solution for ultrasonic cleaning for 5-10 minutes, then put it into an isopropanol solution or anhydrous ethanol for ultrasonic cleaning for 5-10 minutes, and finally put the sample into deionized water for ultrasonic cleaning for 5-10 minutes to remove organic impurities on the sample surface; The piranha treatment is to place the sample after organic cleaning in a piranha solution for 10 minutes to 30 minutes for surface optimization treatment, and then wash it with deionized water for 5 minutes to complete the sample pretreatment.

9. A method for preparing the P-type horizontal gallium oxide diode device according to claim 5, characterized in that: The steps include: The first step is to select a gallium oxide insulating substrate and pre-treat it; The second step is to prepare the gallium oxide P-type layer: First, ion implantation is performed on the surface of the pretreated gallium oxide insulating substrate to form an ion implantation area with a depth of 10 nm-10 μm, and the target implantation concentration is 1×10 16 ~1×10 19 cm -3 The selected element is any one of Mg, Cu, Zn, Fe, N or a combination of any several of the elements such as Mg, Cu, Zn, Fe, N, F, Cl, P, etc.; Then, the sample after ion implantation is placed in a N2 environment for annealing activation treatment, the annealing temperature is set to 800°C-1600°C, and the annealing time is set to 10s-10h, so that a gallium oxide P-type layer is formed in the ion implantation area; The third step is to use a photoresist to perform image processing on the surface of the gallium oxide P-type layer, and deposit a nickel oxide layer (5); Step 4: Prepare electrodes: Depositing Ti / Au or Ti / Al / Ni / Au cathode metal with a thickness of 20nm-800nm ​​on one end of the nickel oxide layer by electron beam evaporation deposition process, and annealing at 400℃-800℃ to form an ohmic contact; A Ni / Au, Mo / Au or Pt / Au anode metal with a thickness of 20nm-800nm ​​is deposited on one end of the gallium oxide P-type layer not covered by the nickel oxide layer (5) to complete the device manufacturing.

10. A method for preparing the P-type horizontal gallium oxide diode device according to claim 6, characterized in that: The steps include: S1) selecting a gallium oxide insulating substrate and pre-treating it; S2) preparing a gallium oxide P-type layer: S2a) ion implantation is performed on the surface of the pretreated gallium oxide insulating substrate to form an ion implantation region with a depth of 10 nm-10 μm, and the target implantation concentration is 1×10 16 ~1×10 19 cm -3 The selected element is any one of Mg, Cu, Zn, Fe, N or a combination of any several of the elements such as Mg, Cu, Zn, Fe, N, F, Cl, P, etc.; S2b) performing annealing activation treatment in a N2 environment, setting the annealing temperature to 800° C.-1600° C. and the annealing time to 10 s-10 h, so that a gallium oxide P-type layer is formed in the ion implantation area; S3) Evaporation electrode Depositing Ti / Au or Ti / Al / Ni / Au cathode metal with a thickness of 20nm-800nm ​​on one end of the gallium oxide P-type layer by electron beam evaporation deposition process, and annealing at 400℃-800℃ to form an ohmic contact; S4) depositing a field plate dielectric layer with a thickness of 100nm-500nm on the anode metal, and then depositing a field plate metal on the field plate dielectric by electron beam evaporation to complete the device preparation.

11. The method according to claim 9, characterized in that The field plate dielectric deposited on the anode metal is any one of silicon oxide, silicon nitride and aluminum oxide.

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