Display panel and display device

Abstract

The application provides a display panel and a display device, which comprise: a shielding layer; a pixel driving circuit layer located on the shielding layer and comprising a plurality of pixel driving circuits at least partially overlapping the shielding layer; and a power line electrically connected to the shielding layer through a plurality of through holes arranged in the pixel driving circuit layer, wherein the converging traces between adjacent through holes are arranged according to the shortest distances between the adjacent through holes.

Description

[0001] This application is a divisional application of a patent application with the application date of March 11, 2022, the application number of 202210237733.1, and the invention name of "Display panel and display device". TECHNICAL FIELD

[0002] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0003] OLED (Organic Light-Emitting Diode) screens have been widely used at present, and have the advantages of lightness and high color gamut value. However, due to the use of organic flexible substrates for the substrate, the OLED screen is prone to screen residual image, initial drop, poor service life and other phenomena due to the influence of the interface between the substrate and the inorganic layer.

[0004] In order to weaken this influence, more and more OLED screens use bottom shielding metal to shield the pixel driving circuit at the interface between the substrate and the inorganic layer. However, in order to be connected with the power line, the edge of the bottom shielding metal is serrated, which is easy to cause ESD (Electro-Static Discharge) burn at the tip of the serration, thereby affecting the display effect. SUMMARY

[0005] The embodiments of the present application provide a display panel and a display device, which can improve the problem of ESD burn of the bottom shielding metal.

[0006] The embodiments of the present application provide a display panel, comprising a display area and a non-display area arranged on at least one side of the display area, the display panel comprising: a substrate; a shielding layer located on the substrate, comprising a plurality of shielding blocks and a convergence trace electrically connected to the plurality of shielding blocks, the convergence trace being located on at least one side of the plurality of shielding blocks; a pixel driving circuit layer located on the shielding layer, comprising a plurality of pixel driving circuits located in the display area, each pixel driving circuit at least partially overlapping with the corresponding shielding block; and a first conductive layer arranged on a side of the shielding layer away from the substrate, the first conductive layer comprising: a plurality of power lines, the plurality of power lines being electrically connected to the convergence trace through a plurality of through holes; wherein the convergence trace between adjacent through holes is arranged according to the shortest distance between adjacent through holes.

[0007] In some embodiments, the convergence trace between adjacent through holes is arranged in a straight line shape.

[0008] In some embodiments, the convergence trace is arranged in a straight line shape, and the plurality of through holes arranged overlapping the convergence trace are arranged in a straight line.

[0009] In some embodiments, the convergence trace includes a first convergence trace, the first convergence trace includes a plurality of first connection segments and a plurality of second connection segments, each of the second connection segments is connected between the middle of two adjacent first connection segments, the width of the first connection segment is greater than the width of the second connection segment, and the plurality of power lines are electrically connected to the plurality of first connection segments through the plurality of through holes.

[0010] In some embodiments, the pixel driving circuit layer includes a plurality of pixel driving circuits arranged in a first direction and a second direction, and each of the first connection segments is electrically connected to the corresponding shielding block of a column of pixel driving circuits arranged in the first direction.

[0011] In some embodiments, the outer periphery of the first connection segment is in a circular arc shape, the second connection segment is in a straight line shape, and the maximum width of the first connection segment is greater than the width of the second connection segment.

[0012] In some embodiments, the non-display area includes a first non-display area and a second non-display area arranged on both sides of the display area, the first non-display area includes a bending sub-area, and the display panel is arranged to be bent in the bending sub-area.

[0013] The convergence trace includes a first convergence trace arranged in the first non-display area, and the plurality of power lines are electrically connected to the first convergence trace through the plurality of through holes.

[0014] In some embodiments, the convergence trace includes a second convergence trace arranged in the second non-display area, and the plurality of power lines are electrically connected to the second convergence trace through the plurality of through holes.

[0015] In some embodiments, the pixel driving circuit layer includes a semiconductor layer arranged on the side of the shielding layer away from the substrate, a first insulating layer arranged on the side of the semiconductor layer away from the substrate, a first gate metal layer arranged on the side of the first insulating layer away from the substrate, a second insulating layer arranged on the side of the first gate metal layer away from the substrate, a second gate metal layer arranged on the side of the second insulating layer away from the substrate, a third insulating layer arranged on the side of the second gate metal layer away from the substrate, and the first conductive layer arranged on the side of the third insulating layer away from the substrate, the plurality of power lines of the first conductive layer are electrically connected to the convergence trace through the plurality of through holes, and the through holes pass through the first insulating layer, the second insulating layer, and the third insulating layer.

[0016] In some embodiments, the pixel driving circuit layer further comprises: a fourth insulating layer disposed between the second gate metal layer and the third insulating layer; a second conductive layer disposed between the fourth insulating layer and the third insulating layer; the via comprises a first via and a second via, the first via passes through the first insulating layer, the second insulating layer and the fourth insulating layer, the second via passes through the third insulating layer, the first via communicates with the second via and the diameter of the second via is greater than the diameter of the first via.

[0017] The embodiment of the present application further provides a display device comprising the display panel.

[0018] In the display panel and the display device provided by the embodiment of the present application, the plurality of shielding blocks of the shielding layer shield the plurality of thin film transistors of the pixel driving circuit layer, the power supply line and the converging trace of the shielding layer are electrically connected to each other through the via, wherein the converging trace between adjacent vias is arranged according to the shortest distance between the adjacent vias, so that the path of the expected current flowing through the converging trace is located within the boundary of the converging trace and conducts along the shortest distance between the adjacent vias, thereby the accumulation of the electric charge at the boundary of the shielding layer can be reduced, and the phenomenon of ESD burnout of the shielding layer can be reduced. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort.

[0020] Figure 1 is a cross-sectional schematic view of the display panel provided by the embodiment of the present application;

[0021] Figure 2 is a top view schematic view of the display panel provided by the embodiment of the present application;

[0022] Figure 3 is Figure 2 is an enlarged schematic view of part A in

[0023] Figure 4 is a top view schematic view of the display panel provided by the embodiment of the present application;

[0024] Figure 5 is Figure 4 is an enlarged schematic view of part B in DETAILED DESCRIPTION

[0025] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of the present application. In addition, it should be understood that the specific implementation described herein is only used to illustrate and explain the present application, and is not used to limit the present application. In the present application, the orientation words such as "upper" and "lower" generally refer to the upper and lower in the actual use or working state of the device, and specifically refer to the direction of the drawing surface in the drawings; and "inner" and "outer" refer to the outline of the device.

[0026] As shown in Figure 1 and Figure 2 Embodiments of the present application provide a display panel 1000, which can be an OLED display panel, a liquid crystal display panel, a micro light-emitting diode display panel, or a mini light-emitting diode display panel. Exemplarily, the display panel 1000 is an OLED display panel.

[0027] The display panel 1000 includes a display area DA and a non-display area NDA. The display area DA can be an area for setting sub-pixels 9 for displaying images. The non-display area NDA can be an area for setting a driving unit such as a gate driving circuit for providing driving signals to the pixel driving circuit 40 of the sub-pixels 9, and some connections of the driving unit. No sub-pixel 9 is set in the non-display area NDA. The non-display area NDA can be arranged on at least one side of the display area DA. The non-display area NDA can at least partially surround the periphery of the display area DA. The non-display area NDA includes a first non-display area and a second non-display area arranged on both sides of the display area DA, and the display panel is bent at a bent sub-area BA of the first non-display area.

[0028] The display panel 1000 includes a substrate 1, a shielding layer 2 located on the substrate 1, a bottom insulating layer 30 located on the shielding layer 2, a buffer layer 31 located on the bottom insulating layer 30, a pixel driving circuit layer 4 located on the buffer layer 31, a pixel definition layer 5 and a light-emitting device layer 6 located on the pixel driving circuit layer 4, and a power supply line 7. For ease of description, a plurality of sub-pixels 9 can include the light-emitting device layer 6.

[0029] Referring to Figure 1 , the substrate 1 can include a single-layer insulating material such as glass, quartz, and polymer resin, or a multi-layer insulating material such as double-layer polymer resin. The substrate 1 can be a rigid substrate 1 or a flexible substrate 1. The substrate 1 is used to carry the film layers arranged thereon.

[0030] The bottom insulating layer 30 and the buffer layer 31 can include a single layer of insulating film such as silicon nitride (SiNx) and silicon oxide (SiOx) or a multi-layer film of silicon nitride (SiNx) and silicon oxide (SiOx) stacked together. The buffer layer 31 prevents the penetration of impurities or moisture and the like.

[0031] Please refer to Figure 1 and Figure 2 , the shielding layer 2 can include a single layer or a multi-layer of metal material such as Mo, Ti, Ti / Al / Ti, or semiconductor material Si, or transparent conductive material such as ITO (Indium Tin Oxide). The shielding layer 2 is located between the bottom insulating layer 30 and the substrate 1 and is disposed below the pixel driving circuit layer 4 to shield the plurality of pixel driving circuits 40 of the pixel driving circuit layer 4. The shielding layer 2 includes converging traces 20, shielding portions 21 and common connection portions 22 connected to each other, wherein the converging traces 20 are located within the non-display area NDA and close to the display area DA, and the shielding portions 21 are located within the display area DA.

[0032] The converging traces 20 include opposite first converging traces 201 and second converging traces 202, wherein the first converging traces 201 are located within the first non-display area and the second converging traces 202 are located within the second non-display area, and the first converging traces 201 and the second converging traces 202 extend along a first direction, which is the extension direction of the scan lines of the pixel driving circuit layer 4 (the direction from left to right in the figure). The first converging traces 201 and the second converging traces 202 each include a plurality of first connection segments 203 and a plurality of second connection segments 204, wherein the outer periphery of the first connection segments 203 is in the shape of a circular arc, and exemplarily, the outer periphery of the first connection segments 203 can be approximately in the shape of an ellipse or a circle, and the second connection segments 204 are approximately in the shape of a straight line. Each of the second connection segments 204 is connected between the middle portions of two adjacent first connection segments 203, and the maximum width of the first connection segments 203 is greater than the width of the second connection segments 204.

[0033] The shielding part 21 is used to shield a plurality of thin film transistors 401 of a plurality of pixel driving circuits 40 arranged in a first direction and a second direction. The plurality of thin film transistors 401 includes a plurality of driving thin film transistors, and the shielding part 21 includes a plurality of shielding blocks 211 shielding the semiconductor patterns of the plurality of driving thin film transistors. Wherein the plurality of shielding blocks 211 are arranged in an array, and each column of the shielding blocks 211 shields the semiconductor patterns of the driving thin film transistors of the plurality of pixel driving circuits 40 driving a corresponding column of the sub-pixels 9, and is connected to the corresponding first connection section 203.

[0034] The common connection part 22 includes a plurality of common connection sections 221, wherein a first part of the plurality of common connection sections 221 is directly connected between the plurality of shielding blocks 211 and the first connection sections 203 on the outermost side in the row direction, and a second part of the plurality of common connection sections 221 is electrically connected between the plurality of shielding blocks 211.

[0035] Please continue to refer to Figure 1 The pixel driving circuit layer 4 includes a semiconductor layer 41, a first insulating layer 42 located on the semiconductor layer 41, a first gate metal layer 43 located on the first insulating layer 42, a second insulating layer 44 located on the first gate metal layer 43, a second gate metal layer 45 located on the second insulating layer 44, an interlayer insulating layer 46 (i.e. fourth insulating layer) located on the second gate metal layer 45, a third metal layer 47 (i.e. second conductive metal layer) located on the interlayer insulating layer 46, a first planar layer 481 (i.e. third insulating layer) located on the third metal layer 47, a fourth metal layer 49 (i.e. first conductive layer) located on the first planar layer 481, and a second planar layer 482 located on the fourth metal layer 49. Wherein the semiconductor layer 41, the first insulating layer 42, the first gate metal layer 43, the interlayer insulating layer 46 and the third metal layer 47 can jointly form a plurality of thin film transistors 401, and the first gate metal layer 43, the second insulating layer 44 and the second gate metal layer 45 can jointly form a plurality of capacitors 402. Wherein a plurality of pixel driving circuits 40 can include a plurality of capacitors 402 and a plurality of thin film transistors 401 to drive the sub-pixels 9 to emit light.

[0036] The semiconductor layer 41 can include polysilicon or an oxide semiconductor. In this case, the oxide semiconductor can include any one of oxides or composite oxides based on titanium (Ti), hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), germanium (Ge), zinc (Zn), gallium (Ga), tin (Sn), or indium (In). The semiconductor layer 41 can include the semiconductor pattern of the thin film transistor 401. The semiconductor pattern can include a channel region overlapping with a gate in a thickness direction, and first and second source / drain regions on one side and the other side of the channel region, respectively. The first and second source / drain regions are regions in which the conductivity is higher and the resistance is lower than that of the channel region.

[0037] The first and second insulating layers 42 and 44 can be a single layer film including silicon oxide (SiOx) or silicon nitride (SiNx), or a multi-layer film in which they are stacked.

[0038] The first gate metal layer 43 can include the gate of the thin film transistor 401 and a plurality of scan lines, and the gate can be formed of a low-resistance substance. The second gate metal layer 45 can include the upper plate of the capacitor 402, and the gate can serve as the lower plate of the capacitor 402. The materials of the first and second gate metal layers 43 and 45 can be the same or different, and for example, the first and second gate metal layers 43 and 45 can include one or more metals selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu), but are not limited thereto.

[0039] The interlayer insulating layer 46 can include a silicon compound, a metal oxide, or the like. For example, the interlayer insulating layer 46 can include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, or the like. These substances can be used alone or in combination with each other.

[0040] The third metal layer 47 can include the source and drain of the thin film transistor 401 and a plurality of data lines. The third metal layer 47 and the fourth metal layer 49 can be made of the same material. For example, the third metal layer 47 and the fourth metal layer 49 can include one or more metals selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The third metal layer 47 can be a single layer or a multi-layer film. For example, the third metal layer 47 can be formed as a laminated structure of Ti / Al / Ti, Mo / Al / Mo, Mo / AlGe / Mo, Ti / Cu, and the like.

[0041] The first planar layer 481 and the second planar layer 482 can be made of the same or different materials. For example, the first planar layer 481 and the second planar layer 482 can include an inorganic insulating material or an organic insulating material such as an acrylate-based resin, an epoxy resin, a phenol resin, a polyamide-based resin, a polyimide-based resin, an unsaturated polyester-based resin, a polyphenylene ether-based resin, a polyphenylene sulfide-based resin, or a benzocyclobutene. The first planar layer 481 can further include a photosensitive material, but is not limited thereto.

[0042] Please refer to Figures 1 to 3 The power supply line 7 is disposed in the fourth metal layer 49. The first power supply line 7 can be a power supply line having a fixed potential disposed in the non-display area NDA. The power supply line 7 includes a plurality of signal traces 71 disposed in the display area DA and electrically connected to the pixel driving circuit 40, and a peripheral trace 72 disposed in the non-display area NDA and electrically connected to a predetermined voltage source (e.g., a power supply chip). The peripheral trace 72 is electrically connected to the plurality of signal traces 71 to reduce signal differences among the plurality of signal traces 71. The plurality of signal traces 71 extend in a second direction, which is the direction of the data lines of the pixel driving circuit layer 4 (the direction from top to bottom in the figure). The peripheral trace 72 extends in the first direction and includes opposite first and second connecting portions 721 and 722. The first connecting portion 721 is adjacent to the bent sub-area BA, and the second connecting portion 722 is disposed in the second non-display area.

[0043] Exemplarily, the power line 7 is at least one of a high-voltage power line and a reset signal line. The third metal layer 47 and the fourth metal layer 49 can form the high-voltage power line, a low-voltage power line and the reset signal line. The drive thin-film transistor in the plurality of thin-film transistors 401 can be connected in series with the light-emitting layer of the sub-pixel 9 in a circuit loop formed by the high-voltage power line and the low-voltage power line to drive the light-emitting layer 61 of the sub-pixel 9 to emit light. The reset signal line can be electrically connected to at least one of the capacitor 402, the first electrode of the sub-pixel 9 and the drive thin-film transistor to reset them.

[0044] The power line 7 is electrically connected to the plurality of first connection segments 203 of the convergence trace 20 through the via hole 90 to be electrically connected to the shielding layer 2. The convergence trace 20 between adjacent via holes 90 is arranged according to the shortest distance between adjacent via holes 90. Since the shortest distance between adjacent via holes 90, i.e. the virtual line segment 107, can represent the expected current path between adjacent via holes 90, the expected current path in a substantially straight line type can be located within the boundary of the convergence trace 20. The via hole 90 passes through the first insulating layer 42, the second insulating layer 44 and the first planar layer 481. The via hole 90 includes a plurality of first via holes 91 and a plurality of second via holes 92. The first via hole 91 penetrates through the first insulating layer 42, the second insulating layer 44 and the interlayer insulating layer 46, and the second via hole 92 penetrates the first planar layer 481. The first via hole 91 communicates with the second via hole 92, and the diameter of the first via hole 91 is smaller than the diameter of the second via hole 92.

[0045] Please continue to refer to FIG. 1, the pixel definition layer 5 can include resins such as polyacrylates or polyimides, and inorganics such as silica series. The pixel definition layer 5 is provided with a plurality of openings to expose the first electrode 60 of the light-emitting device layer 6.

[0046] The light-emitting device layer 6 can include a first electrode 60, a light-emitting layer 61 and a second electrode 62.

[0047] The first electrode 60 can be an anode. The anode can have a laminated film structure of a higher work function material layer of indium-tin-oxide (ITO), indium-zinc-oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), and a reflective material layer of silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or a mixture thereof, but is not limited thereto. The higher work function layer can be disposed in an upper layer than the reflective material layer and disposed close to the light emitting layer 61EL. The anode can have a multi-layer structure of ITO / Mg, ITO / MgF2, ITO / Ag, ITO / Ag / ITO, but is not limited thereto.

[0048] The light emitting layer 61 can include an organic material layer. The organic material layer of the light emitting layer 61 can include an organic light emitting layer, and can further include a hole injection / transport layer and / or an electron injection / transport layer.

[0049] The second electrode 62 can be a cathode. The cathode can include a lower work function material layer of, for example, Li, Ca, LiF / Ca, LiF / Al, Al, Mg, Ag, Pt, Pd, Ni, Au, Nd, Ir, Cr, BaF2, Ba, or a compound or mixture thereof (e.g., a mixture of Ag and Mg, etc.). The cathode can further include a transparent metal oxide layer disposed on the lower work function material layer.

[0050] In the display panel 1000 of the present embodiment, the plurality of shielding blocks 211 of the shielding layer 2 shield the plurality of thin film transistors 401 of the pixel driving circuit layer 4, and the power supply line 7 and the converging trace 20 of the shielding layer 2 are electrically connected to each other through the via hole 90 provided in the pixel driving circuit layer 4, wherein the converging trace 20 between adjacent via holes 90 is arranged according to the shortest distance between the adjacent via holes 90, so that the expected current path flowing through the converging trace 20 is located within the boundary of the converging trace and conducts along the shortest distance between the adjacent via holes 90, thereby reducing the accumulation of electric charges at the boundary of the shielding layer 2 and reducing the phenomenon of ESD burnout of the shielding layer 2.

[0051] In other embodiments, please refer to Figure 4 and Figure 5The first and second converging traces 201 and 202 are linear, and the through holes 90 arranged in a linear manner overlap the first and second converging traces 201 and 202. Based on the same or similar principles, the ESD burn phenomenon occurring at the adjacent connection positions can be reduced.

[0052] In other embodiments, the shielding layer 2 can be located between the buffer layer 31 and the semiconductor layer 41, or below the substrate 1, and below the pixel driving circuit layer 4 for shielding.

[0053] In other embodiments, the power line 7 can also be located in other layers of the pixel driving circuit layer 4, or below the pixel driving circuit layer 4, and is not limited to a high-voltage power line or a reset signal line.

[0054] Embodiments of the present application also provide a display device comprising the display panel 1000 described in any one of the above. The display device as a device for displaying video or still images, can not only be a fixed terminal such as a television, a desktop computer, a monitor, an advertising board, but also a mobile terminal such as a mobile phone, a tablet computer, a mobile communication terminal, an electronic organizer, an electronic book, a multimedia player, a navigator, a notebook computer, and can also be a wearable electronic device such as a smart watch, smart glasses, virtual reality equipment, augmented reality equipment.

[0055] The above describes the embodiments of the present application in detail, and the principles and implementation modes of the present application are described by applying specific examples. The above description of the embodiments is only used to help understand the method of the present application and its core idea; at the same time, for those skilled in the art, according to the idea of the present application, the specific implementation mode and application range will be changed, and the above description should not be understood as a limitation of the present application.

Claims

1. A display panel, comprising a display area and a non-display area arranged at least one side of the display area, characterized in that, The display panel comprises: a substrate; a shielding layer located on the substrate, the shielding layer comprising at least two layers of structure, the shielding layer comprising a plurality of shielding blocks and a convergence trace electrically connected to the plurality of shielding blocks, the convergence trace being located on at least one side of the plurality of shielding blocks; a pixel driving circuit layer located on the shielding layer, comprising a plurality of pixel driving circuits located in the display area, each of the pixel driving circuits at least partially overlapping the corresponding shielding block; and a first conductive layer provided on a side of the shielding layer away from the substrate, the first conductive layer comprising a plurality of power lines, the plurality of power lines being electrically connected to the convergence trace through a plurality of through holes. The convergence trace between adjacent through holes is arranged in a straight line.

2. The display panel of claim 1, wherein, The material of the shielding layer comprises at least two of molybdenum, titanium, aluminum and indium tin oxide.

3. The display panel of claim 1, wherein, The convergence trace is arranged in a straight line, and the plurality of through holes arranged overlapping the convergence trace are arranged in a straight line.

4. The display panel of claim 1, wherein, The convergence trace comprises a first convergence trace, the first convergence trace comprising a plurality of first connection segments and a plurality of second connection segments, wherein each of the second connection segments is connected between the middle portions of two adjacent first connection segments, the width of the first connection segment is greater than the width of the second connection segment, and the plurality of power lines are electrically connected to the plurality of first connection segments through the plurality of through holes.

5. The display panel of claim 4, wherein, The pixel driving circuit layer comprises a plurality of pixel driving circuits arranged in a first direction and a second direction, each of the first connection segments being electrically connected to the shielding block corresponding to a column of pixel driving circuits arranged in the first direction.

6. The display panel of claim 5, wherein, The outer periphery of the first connection segment is in a circular arc shape, the second connection segment is in a straight line shape, and the maximum width of the first connection segment is greater than the width of the second connection segment.

7. The display panel of claim 1, wherein, The non-display area comprises: a first non-display area and a second non-display area provided on both sides of the display area, the first non-display area comprising a bending sub-area, and the display panel being arranged in a bending manner in the bending sub-area; The convergence trace comprises a first convergence trace provided in the first non-display area, and the plurality of power lines are electrically connected to the first convergence trace through the plurality of through holes.

8. The display panel of claim 7, wherein, The convergence trace comprises a second convergence trace provided in the second non-display area, and the plurality of power lines are electrically connected to the second convergence trace through the plurality of through holes.

9. The display panel of claim 1, wherein, The pixel driving circuit layer comprises: a semiconductor layer provided on a side of the shielding layer away from the substrate; a first insulating layer provided on a side of the semiconductor layer away from the substrate; a first gate metal layer provided on a side of the first insulating layer away from the substrate; a second insulating layer provided on a side of the first gate metal layer away from the substrate; a second gate metal layer provided on a side of the second insulating layer away from the substrate; a third insulating layer provided on a side of the second gate metal layer away from the substrate; The first conductive layer is disposed on a side of the third insulating layer away from the substrate, and a plurality of the power lines of the first conductive layer are electrically connected to the converging trace through a plurality of the through holes, the through holes penetrating the first insulating layer, the second insulating layer, and the third insulating layer.

10. The display panel of claim 9, wherein, The pixel driving circuit layer further comprises: A fourth insulating layer is disposed between the second gate metal layer and the third insulating layer. A second conductive layer is disposed between the fourth insulating layer and the third insulating layer. The through holes comprise first through holes and second through holes, the first through holes penetrating the first insulating layer, the second insulating layer, and the fourth insulating layer, the second through holes penetrating the third insulating layer, the first through holes being in communication with the second through holes and the diameter of the second through holes being greater than the diameter of the first through holes.

11. A display device, characterized by comprising: A display panel comprising any one of claims 1-10.

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