Logic analysis component and chip
Through centralized logic analysis circuit group and signal enhancement module, the problem of scattered circuits affecting chip performance is solved, efficient signal sampling and transmission is achieved, and the chip test coverage and performance is improved.
Patent Information
- Application Number
- CN202411177126.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-26
- Publication Date
- 2024-12-13
AI Technical Summary
In chip design, scattered logic analysis circuits will affect chip performance, and if there are too many, the performance loss will be large. If there are too many, the test coverage will be insufficient, making it difficult to locate the signal problem.
A centralized logic analysis circuit group and data connection lines are used to sample and store the test signals, and a signal enhancement module is used to reduce attenuation and distortion in signal transmission to ensure signal quality.
By centrally arranging logic analysis circuits, avoid excessive circuit dispersion, improve chip performance, enhance signal transmission accuracy and coverage, and simplify signal positioning and testing processes.
Smart Images
Figure CN119125857A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of chip signal transmission, and in particular to logic analysis components and chips. Background Art
[0002] In chip design, we have no way of knowing the changes of each signal, especially during analysis. If a function goes wrong, it is difficult to locate the problem point when we need to locate it. The on-chip logic analysis circuit is to solve this problem. It intercepts the signal from some or all signals and pulls it out through the circuit. When testing the chip, the signal can be observed separately. For each signal that needs to be observed, the signal is pulled out separately and output through the port for off-chip test observation. The embedded logic analysis circuit is such a functional circuit. For the back-end implementation stage of the digital circuit, relying on the assistance of EDA tools, the circuit will be scattered throughout the chip to achieve back-end timing convergence and tape-out. For the entire chip, when the number of scattered logic analysis circuits is too large, the performance of the chip will be greatly affected, but if the number of scattered logic analysis circuits is too small, the debug coverage during testing will be very small. Summary of the invention
[0003] The main purpose of this application is to provide a logic analysis component and chip, aiming to solve the technical problem that scattered logic analysis circuits affect chip performance.
[0004] To achieve the above-mentioned purpose, the present application proposes a logic analysis component, which is applied to a chip provided with a plurality of devices to be tested, and the logic analysis component comprises: a centralized logic analysis circuit group and a data connection line;
[0005] The centralized logic analysis circuit group is connected to each device under test via the data connection line;
[0006] The centralized logic analysis circuit group is used to sample the signals to be tested generated by each device to be tested.
[0007] In one embodiment, the logic analysis component further comprises: a memory; the memory is connected to the logic analysis circuit group via the data connection line;
[0008] The logic analysis circuit group is also used to send the sampled signal to be tested to the memory for storage.
[0009] In one embodiment, the logic analysis circuit group is further used to intercept the sampled signal according to the trigger condition, and send the intercepted sampled signal to be tested to the memory for storage.
[0010] In one embodiment, the centralized logic analysis circuit group includes a plurality of logic analysis circuits, and each logic analysis circuit is connected to a corresponding device under test via the data connection line.
[0011] Each of the logic analysis circuits is used to sample a signal under test generated by a corresponding device under test.
[0012] In one embodiment, the logic analysis component further includes a transmission component; the transmission component is connected to each logic analysis circuit via a data connection line; the transmission component is also connected to an external device;
[0013] The transmission component is used to send the sampled signals obtained by sampling the respective logic analysis circuits to the external device.
[0014] In one embodiment, the logic analysis circuit and the corresponding device under test further include: a signal enhancement module;
[0015] The signal enhancement module is respectively connected to the logic analysis circuit and the device to be tested corresponding to the logic analysis circuit through the data connection line;
[0016] The signal enhancement module is used to reduce the attenuation and distortion of the signal under test when it is transmitted from the device under test corresponding to the logic analysis circuit to the logic analysis circuit.
[0017] In one embodiment, the signal enhancement module includes a plurality of signal regenerators;
[0018] The signal regenerators are connected in sequence through the data connection lines, one end of the signal regenerators connected in sequence is connected to the logic analysis circuit, and the other end of the signal regenerators connected in sequence is connected to the device to be tested corresponding to the logic analysis circuit.
[0019] In one embodiment, the number of the signal regenerators is set according to a signal transmission distance between the logic analysis circuit and a device under test corresponding to the logic analysis circuit.
[0020] In addition, to achieve the above-mentioned purpose, the present application also proposes a chip, on which a plurality of devices to be tested are arranged, and the chip includes a logic analysis component as described above, and the logic analysis component establishes a connection with each of the devices to be tested.
[0021] One or more technical solutions proposed in this application have at least the following technical effects:
[0022] The logic analysis component includes: a centralized logic analysis circuit group and a data connection line; the centralized logic analysis circuit group is connected to each device under test through the data connection line; the centralized logic analysis circuit group is used to sample the test signal generated by each device under test. Since all logic analysis circuits are placed in a centralized manner, the signal processing and interaction are centralized, avoiding the circuit being too dispersed and affecting the performance. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.
[0024] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.
[0025] Figure 1 A schematic diagram of a module provided for the first embodiment of the logic analysis component of the present application;
[0026] Figure 2 A schematic diagram of a module provided for the second embodiment of the logic analysis component of the present application;
[0027] Figure 3 A schematic diagram of a module provided for the third embodiment of the logic analysis component of the present application;
[0028] Description of Figure Numbers:
[0029] 10. Centralized logic analysis circuit group; 20. Device to be tested; 30. Data connection line;
[0030] 40. Chip; 50. Memory; 60. Logic analysis circuit;
[0031] 70. Transmission component; 80. External device; 90. Signal enhancement module; 100. Signal regenerator.
[0032] The purpose, features and advantages of this application will be further described in conjunction with the embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION
[0033] It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.
[0034] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0035] It should be noted that all directional indications in the embodiments of the present application (such as up, down, left, right, front, back, etc.) are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.
[0036] In addition, the descriptions of "first", "second", etc. in this application are only for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in this field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by this application.
[0037] Reference Figure 1 , Figure 1 This is a module diagram of the first embodiment of the logic analysis component proposed in this application. Figure 1 The first embodiment of the logic analysis component of the present application is proposed.
[0038] In this embodiment, the logic analysis component includes: a centralized logic analysis circuit group 10 and a data connection line 30 ; the centralized logic analysis circuit group 10 is connected to each DUT 20 via the data connection line 30 .
[0039] It should be noted that the centralized logic analysis circuit group 10 fixes multiple logic analysis circuits 60 in a special range of the chip 40, which can be circular, rectangular or other shapes. The size of the area occupied by the chip 40 can be determined according to the number of logic analysis circuits placed. The shape and size of this range can be designed according to actual needs, and this embodiment does not limit it. The centralized logic analysis circuit group 10 is connected to each device under test 20 on the chip 40 through a data connection line 30. The device under test 20 is used to send a signal to be tested to the centralized logic analysis circuit group 10. The signal to be tested is a signal that needs to be observed in the end. The signal to be tested can be a bus signal, a register state signal or other important signal inside the chip 40. The centralized logic analysis circuit group 10 receives these signals to be tested through the data connection line 30. The data connection line 30 refers to the internal wiring resource, which is used to connect the logic analysis circuit group and the signal node in the device under test 20. These data connection lines 30 can be wires in the metal layer, and these wires constitute the interconnection network inside the chip 40. After receiving the test signal sent by the device under test 20, the logic analysis circuit group can perform sampling according to the clock signal. For example, the logic analysis circuit usually relies on a stable clock signal to synchronize the sampling operation. The clock signal defines the sampling frequency, that is, the signal is sampled once every clock cycle. For example, under a 10MHz clock, the logic analysis circuit will sample at a time interval of 100ns. In addition to the clock signal, the logic analysis circuit can also set a trigger condition to determine when to start sampling. The trigger condition can be a specific signal state, a combination of the states of a group of signals, or the occurrence of a certain event. For example, when the output of the device under test 20 reaches a certain specific mode, the logic analysis circuit will start sampling.
[0040] In another possible implementation, the logic analysis component further includes a memory 50 , and the memory 50 is connected to the logic analysis circuit group via the data connection line 30 .
[0041] It should be noted that after the logic analysis circuit group samples the signal to be tested, the sampled signal to be tested can be sent to the memory 50 for storage for subsequent analysis. The memory 50 is used to temporarily store the sampled data. This usually includes a form of volatile memory, such as SRAM (static random access memory) or DRAM (dynamic random access memory). Data organization: The memory 50 may also need to organize the data to a certain extent for more efficient storage and retrieval. Data formatting: The data in the memory 50 may need to undergo certain formatting processing to facilitate subsequent analysis. Data transmission: The logic analysis circuit group transmits the sampled data to the memory 50. This is usually done through an internal bus or other forms of data connection lines 30. Storage management: The memory 50 management logic is responsible for controlling the storage location and order of the data. This may include address pointer management, write control, etc. Data reading: When the stored data needs to be sent to an external debugging tool, the memory 50 reads the data back to the logic analysis circuit group or directly sends it to an external interface. Data collection and transmission process sampling and storage: The logic analysis circuit group samples the selected signal and stores the sampled data in the internal memory 50. Data organization: The memory 50 can organize the data in a certain way, such as arranging them in chronological order or storing them in a specific format.
[0042] In another feasible implementation, the logic analysis circuit group is also used to intercept the sampled signal according to the trigger condition, and send the intercepted sampled signal to be tested to the memory 50 for storage. Interception logic: When the trigger condition is met, the interception logic is responsible for selecting data within a specific time window from the sampled data for storage. Data selection: The interception logic can select data for a period of time before and after the trigger condition to capture important information before and after the trigger event, and the data storage logic is responsible for storing the intercepted data in the internal memory 50. This may involve the management of address pointers, write control, etc.
[0043] In this embodiment, there is a centralized logic analysis circuit group and a data connection line; the centralized logic analysis circuit group is connected to each device under test through the data connection line; the centralized logic analysis circuit group is used to sample the test signal generated by each device under test. The technical problem that scattered logic analysis circuits affect chip performance is solved. Compared with the prior art, since all logic analysis circuits are placed in a centralized manner, the signal processing and interaction are centralized, which avoids the circuit being too dispersed and affecting the performance.
[0044] Reference Figure 2 , Figure 2 This is a module diagram of the second embodiment of the logic analysis component proposed in this application. Figure 2 A second embodiment of the logic analysis component of the present application is proposed.
[0045] In this embodiment, the centralized logic analysis circuit group 10 includes a plurality of logic analysis circuits 60 , and each logic analysis circuit 60 is connected to a corresponding device under test 20 via the data connection line 30 .
[0046] It should be noted that the logic analysis circuit group includes a large number of logic analysis circuits 60, and the functions of these circuits are different and may test different signals. These logic analysis circuits 60 include but are not limited to: a logic analysis circuit for monitoring the CPU data bus, a logic analysis circuit for monitoring the control signal, and a logic analysis circuit for monitoring the access to the memory 50, etc. The logic analysis circuit for monitoring the CPU data bus is usually directly connected to the data bus of the CPU through the data connection line 30. The logic analysis circuit for monitoring the CPU data bus is used to monitor the data transmission on the CPU data bus, sample the data flow on the data bus, and intercept key data according to the trigger condition. The logic analysis circuit for monitoring the control signal is used to monitor specific control signals, such as clock signals, interrupt signals, etc., sample the state changes of the control signal, and record the time points before and after the trigger condition. The logic analysis circuit for monitoring the access to the memory 50 is used to monitor the read and write operations of the memory 50, sample the address and data of the memory 50, and related control signals.
[0047] In another feasible implementation manner, the logic analysis component further includes a transmission component 70; the transmission component 70 is connected to each logic analysis circuit 60 via a data connection line 30; the transmission component 70 is also connected to an external device 80;
[0048] It should be noted that the transmission component 70 plays a vital role in the logic analysis circuit group. It is responsible for aggregating the data collected by each logic analysis circuit 60 and sending it to the external device 80 for analysis.
[0049] The transmission component 70 is responsible for collecting sampled data from each logic analysis circuit 60. These data may have been processed by triggering and interception. The transmission component 70 can further process the collected data, such as data compression, formatting, etc., to reduce the amount of data and improve transmission efficiency. The transmission component 70 sends the processed data to an external device 80, such as a debugging tool or a computer, for further analysis. The transmission component 70 is usually equipped with one or more external interfaces for communicating with the external device 80. These interfaces may include JTAG / SWD, SPI, I2C or other proprietary interfaces. The components of the transmission component 70 may be as follows: Data collection logic: used to read data from each logic analysis circuit 60, and may merge the data into a larger data packet. Data processing logic: used to compress, format, etc. the data to reduce the transmission time and the required bandwidth. External interface logic: used to communicate with the external device 80 and support one or more external interface protocols. Control logic: used to control the data sending and receiving process, including synchronization and handshake mechanisms. The transmission component 70 plays a key role in the logic analysis circuit group. It is responsible for aggregating the data collected by each logic analysis circuit 60 and sending it to the external device 80. In this way, the logic analysis circuit group can effectively capture and store key signal data for subsequent analysis. The design of the transmission component 70 usually needs to consider the efficiency of data collection, processing and transmission to ensure that the data can be transmitted to the external debugging tool in a timely and accurate manner.
[0050] Reference Figure 3 , Figure 3 This is a module diagram of the third embodiment of the logic analysis component proposed in this application. Figure 3 A third embodiment of the logic analysis component of the present application is proposed.
[0051] In this embodiment, the logic analysis circuit 60 and the corresponding device under test 20 further include: a signal enhancement module 90; the signal enhancement module 90 is connected to the logic analysis circuit 60 and the device under test 20 corresponding to the logic analysis circuit 60 through the data connection line 30;
[0052] It should be noted that the main purpose of the signal enhancement module 90 is to ensure that the signal maintains good quality and strength during transmission, and to reduce the attenuation and distortion of the signal to be tested when it is transmitted from the device to be tested 20 corresponding to the logic analysis circuit 60 to the logic analysis circuit 60, so that it can be accurately captured and analyzed. The signal enhancement module 90 can amplify the signal to compensate for the attenuation of the signal during transmission. Signal regeneration is another important function of the signal enhancement module 90. It ensures that the signal maintains its original shape and integrity during transmission by shaping and regenerating the signal. The signal enhancement module 90 can also help suppress noise during transmission to improve the quality of the signal. The signal enhancement module 90 sometimes also includes an isolation function to avoid mutual interference between signals. Finally, the enhanced signal is sent to the integrated logic analysis circuit group for sampling and analysis.
[0053] In another feasible embodiment, the signal enhancement module 90 includes multiple signal regenerators 100; the signal regenerators 100 are connected in sequence through the data connection line 30, one end of the signal regenerators 100 connected in sequence is connected to the logic analysis circuit 60, and the other end of the signal regenerators 100 connected in sequence is connected to the device to be tested 20 corresponding to the logic analysis circuit 60.
[0054] It should be noted that the signal regenerator 100 is usually used to restore the original form of the signal, and its main function is to amplify, regenerate and shape the signal. The purpose of designing the signal regenerator 100 is to eliminate the distortion that may occur in the transmission process of the signal, such as signal attenuation, noise accumulation and waveform distortion. The number of signal regenerators 100 is usually proportional to the distance of signal transmission. The longer the transmission distance, the more serious the signal distortion, and more signal regenerators 100 are needed to shape and regenerate the signal. The specific number of signal regenerators 100 used between the logic analysis circuit 60 and the corresponding device to be tested 20 is not limited in this embodiment. For the device to be tested that is very close to the centralized logic analysis circuit group 10, the signal regenerator 100 may not be set.
[0055] In addition, the present application provides a chip, on which a plurality of devices to be tested are arranged, and the chip includes the logic analysis component in the above-mentioned embodiment, and the logic analysis component is connected to each of the devices to be tested, which can solve the technical problem that scattered logic analysis circuits affect chip performance. Compared with the prior art, the beneficial effects of the chip provided by the present application are the same as the beneficial effects of the logic analysis component provided by the above-mentioned embodiment, and will not be elaborated here.
[0056] The above descriptions are only some embodiments of the present application, and are not intended to limit the patent scope of the present application. All equivalent structural changes made using the contents of the present application specification and drawings under the technical concept of the present application, or direct / indirect applications in other related technical fields are included in the patent protection scope of the present application.
Claims
1. A logic analysis component, characterized in that: Applied to a chip with multiple devices to be tested, the logic analysis component includes: a centralized logic analysis circuit group and a data connection line; The centralized logic analysis circuit group is connected to each device under test via the data connection line; The centralized logic analysis circuit group is used to sample the signals to be tested generated by each device to be tested.
2. The logic analysis component according to claim 1, characterized in that The logic analysis component also includes: a memory; The memory is connected to the logic analysis circuit group via the data connection line; The logic analysis circuit group is also used to send the sampled signal to be tested to the memory for storage.
3. The logic analysis component according to claim 2, characterized in that The logic analysis circuit group is also used to intercept the sampled signal according to the trigger condition, and send the intercepted sampled signal to be tested to the memory for storage.
4. The logic analysis component of claim 1, wherein: The centralized logic analysis circuit group includes a plurality of logic analysis circuits, each of which is connected to a corresponding device under test via the data connection line; Each of the logic analysis circuits is used to sample a signal under test generated by a corresponding device under test.
5. The logic analysis component according to claim 4, characterized in that The logic analysis component also includes a transmission component; The transmission component is connected to each logic analysis circuit via a data connection line; the transmission component is also connected to an external device; The transmission component is used to send the sampled signals obtained by sampling the respective logic analysis circuits to the external device.
6. The logic analysis component of claim 4, wherein: The logic analysis circuit and the corresponding device under test also include: a signal enhancement module; The signal enhancement module is respectively connected to the logic analysis circuit and the device to be tested corresponding to the logic analysis circuit through the data connection line; The signal enhancement module is used to reduce the attenuation and distortion of the signal under test when it is transmitted from the device under test corresponding to the logic analysis circuit to the logic analysis circuit.
7. The logic analysis component of claim 6, wherein: The signal enhancement module includes a plurality of signal regenerators; The signal regenerators are connected in sequence through the data connection lines, one end of the signal regenerators connected in sequence is connected to the logic analysis circuit, and the other end of the signal regenerators connected in sequence is connected to the device to be tested corresponding to the logic analysis circuit.
8. The logic analysis component of claim 7, wherein: The number of the signal regenerators is set according to the signal transmission distance between the logic analysis circuit and the device under test corresponding to the logic analysis circuit.
9. A chip, characterized in that: The chip is provided with a plurality of devices under test and a logic analysis component as described in any one of claims 1 to 5, and the logic analysis component is connected to each of the devices under test.