A voltage regulation method, electronic equipment and related device

Abstract

The present application provides a voltage regulation method, an electronic device and a related device. The electronic device includes a universal flash storage (UFS) device. In the method, the electronic device can determine the amount of data indicated by the read command to read the UFS device by parsing the read command, and adjust the voltage according to the amount of data to set the target voltage. When the target voltage can satisfy the UFS device to perform a read operation, the voltage obtained by adjustment can reduce power consumption.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to a voltage regulation method, electronic equipment and related devices. Background Art

[0002] As electronic devices (such as mobile phones and tablets) have more and more functions, they will perform read and write operations on storage devices during use to meet different application scenarios. Generally speaking, power is supplied to storage devices so that they can perform read and write operations. However, power supply will generate power consumption, and how to adjust the voltage required by storage devices to reduce power consumption is a problem that needs to be studied at present. Summary of the invention

[0003] The embodiments of the present application provide a voltage regulation method, an electronic device, and related devices, which can adjust the voltage according to the amount of data to be read indicated by a read command, thereby reducing power consumption.

[0004] In a first aspect, the present application provides a voltage regulation method, the method being applied to an electronic device, the electronic device including a universal flash storage UFS device, the method comprising:

[0005] Get the read command;

[0006] Parsing and obtaining the memory address and memory length of the UFS device carried in the read command, wherein the amount of data corresponding to the memory address and memory length of the UFS device is the amount of data indicated by the read command to be read;

[0007] Setting a target voltage according to a memory address and a memory length of the UFS device;

[0008] The UFS device is powered using the target voltage, and a read operation is performed on the UFS device according to the read command at the target voltage.

[0009] In the embodiment of the present application, the electronic device adjusts the voltage of the storage device by identifying the amount of data to be read from the UFS storage device indicated by the read command, and uses the adjusted voltage to power the UFS device. Compared with the existing use of a fixed voltage, the embodiment of the present application reduces the power consumption of the UFS device while providing power that can satisfy the UFS device to perform a read operation, thereby achieving the purpose of reducing the power consumption of the electronic device.

[0010] In a possible implementation manner of the first aspect, determining the target voltage according to the memory address and the memory length of the UFS device includes:

[0011] When the amount of data corresponding to the memory address and the memory length of the UFS device is less than or equal to a preset threshold, setting the target voltage to include a first voltage;

[0012] When the amount of data corresponding to the memory address and the memory length of the UFS device is greater than the preset threshold, setting the target voltage includes the second voltage, wherein the second voltage is greater than the first voltage.

[0013] In an embodiment of the present application, when a read command is used to indicate that the amount of data read is less than or equal to a preset threshold, it indicates a small data volume scenario, and a voltage including a small voltage (i.e., a first voltage) can be used to power the UFS device; when a read command is used to indicate that the amount of data read is greater than a preset threshold, it indicates a large data volume scenario, and a voltage including a large voltage (i.e., a second voltage) can be used to power the UFS device. Optionally, the situation of "equal to the preset threshold" can be placed in another branch of the judgment. It can be seen that, compared with the existing fixed voltage, the use of a small voltage for a small amount of data can reduce power consumption and improve performance while satisfying the requirement of reading a small amount of data.

[0014] In a possible implementation of the first aspect, the electronic device further includes a power management chip PMIC, and the UFS device includes one or more of a control unit, a storage unit, a first power interface, a second power interface, and a third power interface;

[0015] The PMIC is used to input voltage to the first power interface so that the first power interface supplies power to the control unit;

[0016] The PMIC is used to input a voltage to the second power interface so that the second power interface supplies power to the control unit and / or the storage unit;

[0017] The PMIC is used to input voltage to the third power interface so that the third power interface supplies power to the storage unit.

[0018] In the embodiment of the present application, considering that the UFS device has three power signals reserved for the outside, these three power signals correspond to three power interfaces respectively, and the PMIC can supply power to the three power interfaces respectively by making full use of these three power signals. Exemplarily, the electronic device can select the voltage to supply power to the UFS device by reading the amount of data, so as to meet the work of the control unit and the storage unit in the UFS device.

[0019] In a possible implementation of the first aspect, when the first power interface and the second power interface supply power to the control unit, and the third power interface supplies power to the storage unit, the first voltage includes the voltage input through the second power interface, and the second voltage includes the voltage input through the first power interface; wherein the voltage input to the first power interface is greater than the voltage input to the second power interface.

[0020] In the embodiment of the present application, when the amount of data is small, the control unit is powered by the voltage (first voltage) input by the second power interface and the storage unit is powered by the voltage (fixed voltage) input by the third power interface, so as to satisfy the UFS device to perform a small number of read operations; when the amount is large, the control unit is powered by the voltage (second voltage) input by the first power interface and the storage unit is powered by the voltage (fixed voltage) input by the third power interface, so as to satisfy the UFS device to perform a large amount of read operations. It can be seen that the corresponding target voltage when reading a small amount of data includes the first voltage and the fixed voltage, and the corresponding target voltage when reading a large amount of data includes the second voltage and the fixed voltage. Since the first voltage is less than the second voltage, the power consumption can be reduced by reducing the voltage when reading a small amount of data.

[0021] In a possible implementation of the first aspect, when the first power interface is used to supply power to the control unit, and the second power interface and the third power interface are used to supply power to the storage unit, the first voltage includes a voltage input through the second power interface, and the second voltage includes a voltage input through the third power interface; wherein the voltage input to the third power interface is greater than the voltage input to the second power interface.

[0022] In the embodiment of the present application, when the amount of data is small, the control unit is powered by the voltage (fixed voltage) input by the first power interface and the storage unit is powered by the voltage (first voltage) input by the second power interface, so as to satisfy the UFS device to perform a small amount of read operations; when the amount is large, the control unit is powered by the voltage (fixed voltage) input by the first power interface and the storage unit is powered by the voltage (second voltage) input by the third power interface, so as to satisfy the UFS device to perform a large amount of read operations. It can be seen that the corresponding target voltage when reading a small amount of data includes the first voltage and the fixed voltage, and the corresponding target voltage when reading a large amount of data includes the second voltage and the fixed voltage. Since the first voltage is less than the second voltage, the power consumption can be reduced by reducing the voltage when reading a small amount of data.

[0023] In a possible implementation manner of the first aspect, the second power interface includes a first sub-interface and a second sub-interface;

[0024] When the first power interface and the first sub-interface are used to supply power to the control unit, and the second sub-interface and the third power interface are used to supply power to the storage unit, the first voltage includes a voltage input through the first sub-interface and a voltage input through the second sub-interface, and the second voltage includes a voltage input through the first power interface and a voltage input through the third power interface; wherein the voltage input to the first power interface is greater than the voltage input to the first sub-interface, and the voltage input to the third power interface is greater than the voltage input to the second sub-interface.

[0025] In the embodiment of the present application, when the amount of data is small, the storage unit is powered by the voltage (first voltage) input from the first sub-interface of the second power interface and the voltage (first voltage) input from the second sub-interface of the second power interface, so as to satisfy the UFS device to perform a small amount of read operations; when the amount is large, the control unit is powered by the voltage (second voltage) input from the first power interface and the storage unit is powered by the voltage (second voltage) input from the third power interface, so as to satisfy the UFS device to perform a large amount of read operations. It can be seen that the corresponding target voltage when reading a small amount of data includes the first voltage, and the corresponding target voltage when reading a large amount of data includes the second voltage. Since the first voltage is less than the second voltage, the power consumption can be reduced by reducing the voltage when reading a small amount of data.

[0026] In a possible implementation of the first aspect, the PMIC includes a register, and determining the target voltage according to the memory address and the memory length of the UFS device includes:

[0027] When the amount of data corresponding to the memory address and the memory length of the UFS device is less than a preset threshold, determining, by the register, that the first voltage is the target voltage;

[0028] When the amount of data corresponding to the memory address and the memory length of the UFS device is less than a preset threshold, the second voltage is determined as the target voltage through the register.

[0029] In an embodiment of the present application, the electronic device can determine the required amount of data based on the issued read command, and then write a value corresponding to the amount of data in the UFS register to select the first voltage or the second voltage, so that when the amount of data is small, the UFS device can be powered by a voltage including the first voltage, and when the amount of data is large, the UFS device can be powered by a voltage including the second voltage. Therefore, power consumption can be reduced by lowering the voltage when reading a small amount of data.

[0030] In a possible implementation manner of the first aspect, the UFS device includes a power regulator, and determining the target voltage according to the memory address and the memory length of the UFS device includes:

[0031] When the amount of data corresponding to the memory address and the memory length of the UFS device is less than a preset threshold, determining, by the power regulator, that the first voltage is the target voltage;

[0032] When the amount of data corresponding to the memory address and the memory length of the UFS device is less than a preset threshold, the second voltage is determined to be the target voltage by the power regulator.

[0033] In the embodiment of the present application, after receiving the read command, the UFS device can determine the required data amount according to the issued read command, and then select the first voltage or the second voltage through the power regulator, so that when the data amount is small, the UFS device can be powered by a voltage including the first voltage, and when the data amount is large, the UFS device can be powered by a voltage including the second voltage. Therefore, power consumption can be reduced by lowering the voltage when reading a small amount of data.

[0034] In a second aspect, an embodiment of the present application provides an electronic device, the electronic device comprising: one or more processors; a memory; wherein the memory is coupled to the one or more processors, the memory is used to store computer program code, the computer program code comprises computer instructions, and the one or more processors call the computer instructions to enable the electronic device to execute the voltage regulation method described in the first aspect or any possible implementation of the first aspect.

[0035] Optionally, the memory includes a UFS device.

[0036] In a third aspect, the present application provides a chip or a chip system, the chip or chip system includes at least one processor and a communication interface, the communication interface and the at least one processor are interconnected through a line, and the at least one processor is used to run a computer program or instruction to execute the voltage regulation method described in the first aspect or any possible implementation of the first aspect. The communication interface in the chip can be an input / output interface, a pin or a circuit, etc.

[0037] In a possible implementation, the chip or chip system described above in the embodiment of the present application further includes at least one memory, in which instructions are stored. The memory may be a storage unit inside the chip, such as a register, a cache, etc., or a storage unit of the chip (such as a read-only memory, a random access memory, etc.).

[0038] In a fourth aspect, an embodiment of the present application provides a computer storage medium, which stores a computer program. When the computer program is executed by a processor, the computer executes the voltage regulation method described in the first aspect or any possible implementation of the first aspect.

[0039] In a fifth aspect, an embodiment of the present application provides a computer program product. When the computer program product runs on a communication device, the communication device executes the voltage regulation method described in the first aspect or any possible implementation of the first aspect.

[0040] It should be understood that the description of technical features, technical solutions, beneficial effects or similar language in this application does not imply that all features and advantages can be realized in any single embodiment. On the contrary, it is understood that the description of features or beneficial effects means that specific technical features, technical solutions or beneficial effects are included in at least one embodiment. Therefore, the description of technical features, technical solutions or beneficial effects in this specification does not necessarily refer to the same embodiment. Furthermore, the technical features, technical solutions and beneficial effects described in the present embodiment can also be combined in any appropriate manner. Those skilled in the art will understand that the embodiment can be realized without one or more specific technical features, technical solutions or beneficial effects of a specific embodiment. In other embodiments, additional technical features and beneficial effects can also be identified in a specific embodiment that does not embody all embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The following is an introduction to the drawings used in the embodiments of the present application.

[0042] Figure 1 is a schematic diagram of the hardware structure of an electronic device 100 provided in an embodiment of the present application;

[0043] Figure 2 is a schematic diagram of the hardware structure of another electronic device 100 provided in an embodiment of the present application;

[0044] Figure 3 is a schematic diagram of the hardware structure of another electronic device 100 provided in an embodiment of the present application;

[0045] Figure 4A is a schematic diagram of the hardware structure of another electronic device 100 provided in an embodiment of the present application;

[0046] Figure 4B 1 is a schematic diagram of the hardware architecture of another electronic device 100 provided in an embodiment of the present application;

[0047] Figure 4C 1 is a schematic diagram of the hardware architecture of another electronic device 100 provided in an embodiment of the present application;

[0048] Figure 4D 1 is a schematic diagram of the hardware architecture of another electronic device 100 provided in an embodiment of the present application;

[0049] Figure 5A is a schematic diagram of the hardware structure of another electronic device 100 provided in an embodiment of the present application;

[0050] Figure 5B 1 is a schematic diagram of the hardware architecture of another electronic device 100 provided in an embodiment of the present application;

[0051] Figure 5C 1 is a schematic diagram of the hardware architecture of another electronic device 100 provided in an embodiment of the present application;

[0052] Figure 5D 1 is a schematic diagram of the hardware architecture of another electronic device 100 provided in an embodiment of the present application;

[0053] Figure 6 It is a flow chart of a voltage regulation method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0054] The terms used in the following embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to be used as limitations to the present application. As used in the specification and appended claims of the present application, the singular expressions "one", "a kind of", "said", "above", "the" and "this" are intended to also include plural expressions, unless there is a clear indication to the contrary in the context. It should also be understood that the term "and / or" used in the present application refers to and includes any or all possible combinations of one or more listed items.

[0055] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as suggesting or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features, and in the description of the embodiments of the present application, unless otherwise specified, "plurality" means two or more.

[0056] The electronic device 100 provided in the embodiment of the present application includes a display screen. The electronic device 100 may be, but is not limited to, a mobile phone, a tablet computer, a handheld computer, a desktop computer, a laptop computer, an ultra-mobile personal computer (UMPC), a netbook, a cellular phone, a personal digital assistant (PDA), and wearable devices such as smart bracelets, smart watches, and smart glasses, augmented reality (AR), virtual reality (VR), mixed reality (MR) and other extended reality (XR) devices, vehicle-mounted devices or smart city devices. The embodiment of the present application does not impose any special restrictions on the specific type of the electronic device 100.

[0057] Figure 1 It is a schematic diagram of the hardware structure of an electronic device 100 provided in an embodiment of the present application.

[0058] The electronic device 100 may include a processor 110, an external memory interface 120, an internal memory 121, a universal serial bus (USB) interface 130, a charging management module 140, a power management module 141, a battery 142, an antenna 1, an antenna 2, a mobile communication module 150, a wireless communication module 160, an audio module 170, a speaker 170A, a receiver 170B, a microphone 170C, an earphone interface 170D, a sensor module 180, a button 190, a motor 191, an indicator 192, a camera 193, a display screen 194, and a subscriber identification module (SIM) card interface 195, etc. The sensor module 180 may include a pressure sensor 180A, a gyroscope sensor 180B, an air pressure sensor 180C, a magnetic sensor 180D, an acceleration sensor 180E, a distance sensor 180F, a proximity light sensor 180G, a fingerprint sensor 180H, a temperature sensor 180J, a touch sensor 180K, an ambient light sensor 180L, a bone conduction sensor 180M, etc.

[0059] It is to be understood that the structure illustrated in the embodiment of the present invention does not constitute a specific limitation on the electronic device 100. In other embodiments of the present application, the electronic device 100 may include more or fewer components than shown in the figure, or combine some components, or separate some components, or arrange the components differently. The components shown in the figure may be implemented in hardware, software, or a combination of software and hardware.

[0060] The processor 110 may include one or more processing units, for example, the processor 110 may include an application processor (AP), a modem processor, a graphics processor (GPU), an image signal processor (ISP), a controller, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural-network processing unit (NPU), etc. Different processing units may be independent devices or integrated into one or more processors.

[0061] The controller can generate operation control signals according to the instruction operation code and timing signal to complete the control of instruction fetching and execution.

[0062] The processor 110 may also be provided with a memory for storing instructions and data. In some embodiments, the memory in the processor 110 is a cache memory. The memory may store instructions or data that the processor 110 has just used or cyclically used. If the processor 110 needs to use the instruction or data again, it may be directly called from the memory. This avoids repeated access, reduces the waiting time of the processor 110, and thus improves the efficiency of the system.

[0063] In some embodiments, the processor 110 may include one or more interfaces. The interface may include an inter-integrated circuit (I2C) interface, an inter-integrated circuit sound (I2S) interface, a pulse code modulation (PCM) interface, a universal asynchronous receiver / transmitter (UART) interface, a mobile industry processor interface (MIPI), a general-purpose input / output (GPIO) interface, a subscriber identity module (SIM) interface, and / or a universal serial bus (USB) interface, etc.

[0064] The charging management module 140 is used to receive charging input from a charger. The charger may be a wireless charger or a wired charger. In some wired charging embodiments, the charging management module 140 may receive charging input from a wired charger through the USB interface 130. In some wireless charging embodiments, the charging management module 140 may receive wireless charging input through a wireless charging coil of the electronic device 100. While the charging management module 140 is charging the battery 142, it may also power the electronic device through the power management module 141.

[0065] The power management module 141 is used to connect the battery 142, the charging management module 140 and the processor 110. The power management module 141 receives input from the battery 142 and / or the charging management module 140, and supplies power to the processor 110, the internal memory 121, the display screen 194, the camera 193, and the wireless communication module 160. The power management module 141 can also be used to monitor parameters such as battery capacity, battery cycle number, battery health status (leakage, impedance), etc. In some other embodiments, the power management module 141 can also be set in the processor 110. In other embodiments, the power management module 141 and the charging management module 140 can also be set in the same device. Optionally, the power management module 141 includes a power management chip (power management integrated circuit, PMIC).

[0066] The wireless communication function of the electronic device 100 can be implemented through the antenna 1, the antenna 2, the mobile communication module 150, the wireless communication module 160, the modem processor and the baseband processor.

[0067] Antenna 1 and antenna 2 are used to transmit and receive electromagnetic wave signals. Each antenna in electronic device 100 can be used to cover a single or multiple communication frequency bands. Different antennas can also be reused to improve the utilization of antennas. For example, antenna 1 can be reused as a diversity antenna for a wireless local area network. In some other embodiments, the antenna can be used in combination with a tuning switch.

[0068] The mobile communication module 150 can provide wireless communication solutions including second generation (2G) / third generation (3G) / fourth generation (4G) / fifth generation (5G) / sixth generation (6G) applied to the electronic device 100. The mobile communication module 150 may include at least one filter, switch, power amplifier, low noise amplifier (LNA), etc. The mobile communication module 150 can receive electromagnetic waves from the antenna 1, filter, amplify and process the received electromagnetic waves, and transmit them to the modulation and demodulation processor for demodulation. The mobile communication module 150 can also amplify the signal modulated by the modulation and demodulation processor, and convert it into electromagnetic waves for radiation through the antenna 1. In one embodiment, at least some of the functional modules of the mobile communication module 150 can be set in the processor 110. In one embodiment, at least some of the functional modules of the mobile communication module 150 can be set in the same device as at least some of the modules of the processor 110.

[0069] The modem processor may include a modulator and a demodulator. Among them, the modulator is used to modulate the low-frequency baseband signal to be sent into a medium-high frequency signal. The demodulator is used to demodulate the received electromagnetic wave signal into a low-frequency baseband signal. The demodulator then transmits the demodulated low-frequency baseband signal to the baseband processor for processing. After the low-frequency baseband signal is processed by the baseband processor, it is passed to the application processor. The application processor outputs a sound signal through an audio device (not limited to a speaker 170A, a receiver 170B, etc.), or displays an image or video through a display screen 194. In some embodiments, the modem processor may be an independent device. In other embodiments, the modem processor may be independent of the processor 110 and be set in the same device as the mobile communication module 150 or other functional modules.

[0070] The wireless communication module 160 can provide wireless communication solutions including wireless local area networks (WLAN) (such as wireless fidelity (Wi-Fi) networks), bluetooth (BT), global navigation satellite system (GNSS), frequency modulation (FM), near field communication (NFC), infrared (IR), and wireless communication technologies (such as SLE, SLB) specified by the SparkLink Alliance for application in the electronic device 100. The wireless communication module 160 can be one or more devices integrating at least one communication processing module. The wireless communication module 160 receives electromagnetic waves via the antenna 2, modulates the electromagnetic wave signal and filters it, and sends the processed signal to the processor 110. The wireless communication module 160 can also receive the signal to be sent from the processor 110, modulate the frequency, amplify it, and convert it into electromagnetic waves for radiation through the antenna 2.

[0071] In some embodiments, the antenna 1 of the electronic device 100 is coupled to the mobile communication module 150, and the antenna 2 is coupled to the wireless communication module 160, so that the electronic device 100 can communicate with the network and other devices through wireless communication technology. The wireless communication technology may include global system for mobile communications (GSM), general packet radio service (GPRS), code division multiple access (CDMA), wideband code division multiple access (WCDMA), time-division code division multiple access (TD-SCDMA), long term evolution (LTE), BT, GNSS, WLAN, NFC, FM, and / or IR technology. The GNSS may include a global positioning system (GPS), a global navigation satellite system (GLONASS), a Beidou navigation satellite system (BDS), a quasi-zenith satellite system (QZSS) and / or a satellite based augmentation system (SBAS).

[0072] The electronic device 100 implements the display function through a GPU, a display screen 194, and an application processor. The GPU is a microprocessor for image processing, which connects the display screen 194 and the application processor. The GPU is used to perform mathematical and geometric calculations for graphics rendering. The processor 110 may include one or more GPUs that execute program instructions to generate or change display information.

[0073] The display screen 194 is used to display images, videos, etc. The display screen 194 includes a display panel. The display panel can be a liquid crystal display (LCD), an organic light-emitting diode (OLED), an active-matrix organic light-emitting diode or an active-matrix organic light-emitting diode (AMOLED), a flexible light-emitting diode (FLED), Miniled, MicroLed, Micro-oLed, a quantum dot light-emitting diode (QLED), etc. In some embodiments, the electronic device 100 may include 1 or N display screens 194, where N is a positive integer greater than 1.

[0074] The electronic device 100 can realize the shooting function through ISP, camera 193, video codec, GPU, display screen 194 and application processor.

[0075] ISP is used to process the data fed back by camera 193. For example, when taking a photo, the shutter is opened, and the light is transmitted to the camera photosensitive element through the lens. The light signal is converted into an electrical signal, and the camera photosensitive element transmits the electrical signal to ISP for processing and converts it into an image visible to the naked eye. ISP can also perform algorithm optimization on the noise, brightness, color, etc. of the image. ISP can also optimize the exposure, color temperature and other parameters of the shooting scene. In some embodiments, ISP can be set in camera 193.

[0076] The camera 193 is used to capture still images or videos. The object generates an optical image through the lens and projects it onto the photosensitive element. The photosensitive element can be a charge coupled device (CCD) or a complementary metal-oxide-semiconductor (CMOS) phototransistor. The photosensitive element converts the optical signal into an electrical signal, and then passes the electrical signal to the ISP to be converted into a digital image signal. The ISP outputs the digital image signal to the DSP for processing. The DSP converts the digital image signal into an image signal in a standard RGB, YUV or other format. In some embodiments, the electronic device 100 may include 1 or N cameras 193, where N is a positive integer greater than 1.

[0077] The digital signal processor is used to process digital signals, and can process not only digital image signals but also other digital signals. For example, when the electronic device 100 is selecting a frequency point, the digital signal processor is used to perform Fourier transform on the frequency point energy.

[0078] Video codecs are used to compress or decompress digital videos. The electronic device 100 may support one or more video codecs. Thus, the electronic device 100 may play or record videos in a variety of coding formats, such as Moving Picture Experts Group (MPEG) 1, MPEG2, MPEG3, MPEG4, etc.

[0079] NPU is a neural network (NN) computing processor. By drawing on the structure of biological neural networks, such as the transmission mode between neurons in the human brain, it can quickly process input information and can also continuously self-learn. Through NPU, applications such as intelligent cognition of the electronic device 100 can be realized, such as image recognition, face recognition, voice recognition, text understanding, etc.

[0080] The external memory interface 120 can be used to connect an external memory card, such as a Micro SD card, to expand the storage capacity of the electronic device 100. The external memory card communicates with the processor 110 through the external memory interface 120 to implement a data storage function, such as storing music, video and other files in the external memory card.

[0081] The internal memory 121 can be used to store computer executable program codes, which include instructions. The internal memory 121 may include a program storage area and a data storage area. Among them, the program storage area may store an operating system, an application required for at least one function (such as a sound playback function, an image playback function, etc.), etc. The data storage area may store data created during the use of the electronic device 100 (such as audio data, a phone book, etc.), etc. In addition, the internal memory 121 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, a universal flash storage (UFS), etc. The processor 110 executes various functional applications and data processing of the electronic device 100 by running instructions stored in the internal memory 121, and / or instructions stored in a memory provided in the processor.

[0082] The electronic device 100 can implement audio functions such as music playing and recording through the audio module 170, the speaker 170A, the receiver 170B, the microphone 170C, the headphone jack 170D, and the application processor.

[0083] The audio module 170 is used to convert digital audio information into analog audio signal output, and is also used to convert analog audio input into digital audio signals. The audio module 170 can also be used to encode and decode audio signals. In some embodiments, the audio module 170 can be arranged in the processor 110, or some functional modules of the audio module 170 can be arranged in the processor 110.

[0084] The speaker 170A, also called a "speaker", is used to convert an audio electrical signal into a sound signal. The electronic device 100 can listen to music or listen to a hands-free call through the speaker 170A.

[0085] The receiver 170B, also called a "earpiece", is used to convert audio electrical signals into sound signals. When the electronic device 100 receives a call or voice message, the voice can be received by placing the receiver 170B close to the human ear.

[0086] Microphone 170C, also called "microphone" or "microphone", is used to convert sound signals into electrical signals. When making a call or sending a voice message, the user can speak by putting their mouth close to microphone 170C to input the sound signal into microphone 170C. The electronic device 100 can be provided with at least one microphone 170C. In other embodiments, the electronic device 100 can be provided with two microphones 170C, which can not only collect sound signals but also realize noise reduction function. In other embodiments, the electronic device 100 can also be provided with three, four or more microphones 170C to collect sound signals, reduce noise, identify the sound source, realize directional recording function, etc.

[0087] The earphone interface 170D is used to connect a wired earphone and can be a USB interface 130 or a 3.5 mm open mobile terminal platform (OMTP) standard interface or a cellular telecommunications industry association of the USA (CTIA) standard interface.

[0088] The pressure sensor 180A is used to sense the pressure signal and can convert the pressure signal into an electrical signal. In some embodiments, the pressure sensor 180A can be set on the display screen 194. There are many types of pressure sensors 180A, such as resistive pressure sensors, inductive pressure sensors, capacitive pressure sensors, etc. A capacitive pressure sensor can be a parallel plate including at least two conductive materials. When a force acts on the pressure sensor 180A, the capacitance between the electrodes changes. The electronic device 100 determines the intensity of the pressure based on the change in capacitance. When a touch operation acts on the display screen 194, the electronic device 100 detects the intensity of the touch operation based on the pressure sensor 180A. The electronic device 100 can also calculate the position of the touch based on the detection signal of the pressure sensor 180A.

[0089] The gyroscope sensor 180B can be used to determine the motion posture of the electronic device 100. The air pressure sensor 180C is used to measure air pressure. The acceleration sensor 180E can detect the magnitude of the acceleration of the electronic device 100 in all directions (generally three axes). The distance sensor 180F is used to measure the distance. The proximity light sensor 180G may include, for example, a light emitting diode (LED) and a light detector, such as a photodiode. The light emitting diode may be an infrared light emitting diode. The electronic device 100 emits infrared light outward through the light emitting diode. The electronic device 100 uses a photodiode to detect infrared reflected light from nearby objects. When sufficient reflected light is detected, it can be determined that there is an object near the electronic device 100. When insufficient reflected light is detected, the electronic device 100 can determine that there is no object near the electronic device 100. The ambient light sensor 180L is used to sense the brightness of the ambient light. The fingerprint sensor 180H is used to collect fingerprints. The electronic device 100 can use the collected fingerprint characteristics to realize fingerprint unlocking, access application locks, fingerprint photography, fingerprint answering calls, etc. The temperature sensor 180J is used to detect temperature. The touch sensor 180K is also called a "touch device". The touch sensor 180K can be set on the display screen 194, and the touch sensor 180K and the display screen 194 form a touch screen, also called a "touch screen". The touch sensor 180K is used to detect touch operations acting on or near it. The touch sensor can pass the detected touch operation to the application processor to determine the type of touch event. Visual output related to the touch operation can be provided through the display screen 194. In other embodiments, the touch sensor 180K can also be set on the surface of the electronic device 100, which is different from the position of the display screen 194. The bone conduction sensor 180M can obtain a vibration signal. The button 190 includes a power button, a volume button, etc. The motor 191 can generate a vibration prompt. The indicator 192 can be an indicator light, which can be used to indicate the charging status, power changes, messages, missed calls, notifications, etc. The SIM card interface 195 is used to connect a SIM card.

[0090] See also Figure 2 , Figure 2 FIG. 1 is a schematic diagram of the hardware structure of another electronic device 100 provided in an embodiment of the present application. Figure 2 As shown, the electronic device 100 includes but is not limited to: a system on chip (SoC) 101, a power management integrated circuit (PMIC) 102 and a universal flash storage (UFS) device 103.

[0091] SoC 101 may be used to implement a processing control process of electronic device 100. In some embodiments of the present application, SoC 101 may be connected to and communicate with PMIC 102. In some embodiments of the present application, SoC 101 may be connected to and communicate with UFS device 103.

[0092] The UFS device 103 includes a control unit 1031 and a storage unit 1032. Exemplarily, the control unit 1031 may include a UFS controller, and the storage unit 1032 includes non-volatile medium particles such as NAND Flash for storing data.

[0093] The PMIC 102 may be connected to the UFS device 103, and may input voltage to the UFS device 103 to support the read and write operations of the UFS device 103. Exemplarily, the UFS device 103 includes but is not limited to a first power interface 1033, a second power interface 1034, and a third power interface 1035, and the UFS device 103 may input different voltages to the UFS device 103 through the above different power interfaces.

[0094] In some embodiments, the UFS device 103 inputs voltage 1 to the UFS device 103 through the first power interface 1033. In some embodiments, the UFS device 103 inputs voltage 2 to the UFS device 103 through the second power interface 1034. In some embodiments, the UFS device 103 inputs voltage 3 to the UFS device 103 through the third power interface 1035. Optionally, voltage 1, voltage 2, and voltage 3 may be the same or different. Exemplarily, in actual use, for UFS devices of different specifications, two of the three power interfaces are used to receive the voltage input by the PMIC 102, for example, a UFS4.0 device or a UFS3.1 device uses the first power interface 1033 and the third power interface 1035, and a UFS2.2 device or a UFS2.1 device uses the second power interface 1034 and the third power interface 1035. Generally speaking, the electronic device 100 includes a UFS device of one specification, so there may be a situation where the power interface is vacant, for example, the second power interface 1034 of the UFS4.0 device or the UFS3.1 device is vacant, and the first power interface 1033 of the UFS2.2 device or the UFS2.1 device is vacant.

[0095] Exemplarily, the UFS device 103 uses the first power interface 1033 to input voltage 1 to the UFS device 103 , and uses the third power interface 1035 to input voltage 3 to the UFS device 103 , to illustrate the read and write operations of the UFS device 103 .

[0096] In some embodiments, in a scenario where the electronic device 100 starts an application program and reads a small amount of data, the SoC 101 may send a first read command to the UFS device 103, and the first read command carries the address of the logic block corresponding to the small amount of data and the length of the logic block. Under the action of the pre-set / selected voltage 1 and voltage 3, the control unit 1031 in the UFS device 103 reads the data of the small amount of data in the storage unit 1032 according to the first read command to achieve the corresponding task. In other embodiments, in a scenario where the electronic device 100 loads a large amount of data, such as loading a film and television resource, the SoC 101 may send a second read command to the UFS device 103, and the second read command carries the address of the logic block corresponding to the large amount of data and the length of the logic block. Under the action of the pre-set / selected voltage 1 and voltage 3, the control unit 1031 in the UFS device 103 reads the data of the large amount of data in the storage unit 1032 according to the second read command to achieve the corresponding task. Optionally, the small amount of data includes a data amount less than or equal to a preset threshold, and the large amount of data includes a data amount greater than a preset threshold. For example, the preset threshold includes 128 kilobytes (KB).

[0097] Exemplarily, in order to meet the needs of reading large amounts of data, it is necessary to provide sufficient voltage for the UFS device. Optionally, the voltage 1 input through the first power interface 1033 and the voltage 3 input through the third power interface 1035 can provide sufficient voltage for the UFS device so that the UFS device can read large amounts of data. Optionally, in the case where voltage 1 and voltage 3 can meet the needs of reading a large amount of data, the voltage can also meet the needs of reading a small amount of data. However, when the UFS device reads a small amount of data, it may not need the voltage values ​​corresponding to voltage 1 and voltage 3. For example, when the UFS device is powered by voltage 1 and voltage 3, the UFS device can also read a small amount of data. Therefore, when reading a small amount of data, the voltage required for reading a large amount of data is also used, which may cause additional power consumption waste.

[0098] In addition, the applicant found in the study that by statistically analyzing the data used by the electronic device within a preset time (for example, 24 hours), the proportion of small data volume carried in the read command is about 93%; the proportion of large data volume carried in the read command is about 7%, indicating that the electronic device 100 performs read and write access to the UFS device with small data volume in 93% of the scenarios, and performs read and write access to the UFS device with large data volume in 7% of the scenarios. When performing a read operation with a large data volume, the first current corresponding to the voltage 1 and the third current corresponding to the voltage 3 required by the UFS device will increase sharply, while when performing a read operation with a small data volume, the demand for the first current corresponding to the voltage 1 and the third current corresponding to the voltage 3 is relatively low. For example, the first current corresponding to the read operation with a large data volume is about 3 to 5 times the first current corresponding to the small data volume, and the third current corresponding to the read operation with a large data volume is about 1.5 times the third current corresponding to the small data volume. Therefore, in actual use, electronic devices read small amounts of data in most scenarios. If the voltage required for reading large amounts of data (for example, pre-set / selected voltage 1 and voltage 3) is continued to be used when reading small amounts of data, it may cause additional waste of power consumption.

[0099] In view of this, an embodiment of the present application proposes a voltage adjustment method, in which an electronic device can set / select a target voltage according to the address and length of the UFS device carried in the read command, for example, when the amount of data corresponding to the address and length of the UFS device is less than or equal to a preset threshold, a first voltage is set / selected as the target voltage; when the amount of data corresponding to the address and length of the UFS device is greater than the preset threshold, a second voltage is set / selected as the target voltage, and the second voltage is greater than the first voltage. When reading a small amount of data, a lower voltage is used to save power consumption, thereby reducing power consumption while ensuring normal data reading.

[0100] Not limited to the above-mentioned UFS device, the embodiments of the present application may also be applicable to a storage device having the same power supply scheme as the UFS device.

[0101] See also Figure 3 , Figure 3 FIG. 1 is a schematic diagram of the hardware structure of another electronic device 100 provided in an embodiment of the present application. Figure 3 As shown, the electronic device 100 includes but is not limited to: SoC 101, PMIC 102 and UFS device 103. For example, SoC 101 corresponds to Figure 1 The processor 110 and PMIC 102 shown correspond to Figure 1 The power management module 141 shown in FIG. 1 corresponds to the UFS device 103. Figure 1 The internal memory 121 is shown.

[0102] Exemplarily, the PMIC 102 includes but is not limited to a first interface 1021 , a second interface 1022 , and a third interface 1023 . The UFS device 103 includes but is not limited to a control unit 1031 , a storage unit 1032 , a first power interface 1033 , a second power interface 1034 , and a third power interface 1035 .

[0103] SoC 101 may be used to implement a processing control process of electronic device 100. In some embodiments of the present application, SoC 101 may be connected to and communicate with PMIC 102. In some embodiments of the present application, SoC 101 may be connected to and communicate with UFS device 103.

[0104] In some embodiments of the present application, the first interface 1021 of the PMIC 102 is connected to the first power interface 1033 of the UFS device 103, and the first power interface 1033 of the UFS device 103 is connected to the control unit 1031. Exemplarily, the PMIC 102 can provide voltage to the outside through the first interface 1021, and input voltage to the first power interface 1033 of the UFS device 103 through the first voltage path, so that the first power interface 1033 of the UFS device 103 can supply power to the control unit 1031.

[0105] Optionally, the first power interface 1033 of the UFS device 103 may supply power to a flash memory input and output interface (NAND I / O) and a controller core in the control unit 1031 .

[0106] Exemplarily, the voltage provided by the first interface 1021 of the PMIC 102 and the voltage received by the first power interface 1033 of the UFS device 103 may be referred to as a power supply voltage VCCQ. Optionally, VCCQ includes but is not limited to any voltage value less than or equal to 1.2 volts (V).

[0107] In some embodiments of the present application, the second interface 1022 of the PMIC 102 is connected to the second power interface 1034 of the UFS device 103, and the second power interface 1034 of the UFS device 103 is connected to the control unit 1031 or the storage unit 1032. Exemplarily, the PMIC 102 can provide voltage to the outside through the second interface 1022, and input voltage to the second power interface 1034 of the UFS device 103 through the second voltage path, so that the second power interface 1034 of the UFS device 103 can supply power to the control unit 1031 or the storage unit 1032.

[0108] Optionally, the second power interface 1034 of the UFS device 103 can supply power to a physical layer module in the control unit 1031. Exemplarily, the physical layer module includes a physical layer (physical, PHY) based on a mobile industry processor interface (Mobile Industry Processor Interface MIPI), which can be referred to as MIPI M-PHY.

[0109] Exemplarily, the voltage provided by the second interface 1022 of the PMIC 102 and the voltage received by the second power interface 1034 of the UFS device 103 may be referred to as the supply voltage VCCQ2. Optionally, VCCQ2 includes the minimum voltage value recorded in the specification or a voltage value allowed by the manufacturer, such as 0.3V.

[0110] In some embodiments of the present application, the third interface 1023 of the PMIC 102 is connected to the third power interface 1035 of the UFS device 103, and the third power interface 1035 of the UFS device 103 is connected to the storage unit 1032. Exemplarily, the PMIC 102 can provide voltage to the outside through the third interface 1023, and input voltage to the third power interface 1035 of the UFS device 103 through the third voltage path, so that the third power interface 1035 of the UFS device 103 can supply power to the storage unit 1032.

[0111] Optionally, the third power interface 1035 of the UFS device 103 can provide power to the flash memory medium (NAND array) in the storage unit 1032 .

[0112] Exemplarily, the voltage provided by the third interface 1023 of the PMIC 102 and the voltage received by the third power interface 1035 of the UFS device 103 may be referred to as a power supply voltage VCC. Optionally, VCC includes but is not limited to any voltage value less than or equal to 2.5V.

[0113] In some embodiments of the present application, the voltage provided by the second interface 1022 of the PMIC 102 and the voltage (VCCQ2) received by the second power interface 1034 of the UFS device 103 may be referred to as a first voltage. The voltage provided by the first interface 1021 of the PMIC 102 and the voltage (VCCQ) received by the first power interface 1033 of the UFS device 103, and / or the voltage provided by the third interface 1023 of the PMIC 102 and the voltage (VCC) received by the third power interface 1035 of the UFS device 103 may be referred to as a second voltage. Optionally, the first voltage is less than the second voltage.

[0114] See also Figure 4A , Figure 4A It is a schematic diagram of the hardware structure of another electronic device 100 provided in an embodiment of the present application. Figure 4A The electronic device 100 and Figure 3 The electronic device 100 shown is similar except that Figure 4A The PMIC 102 of the electronic device 100 shown further includes a register 1024 , which is connected to one or more of the first interface 1021 , the second interface 1022 , and the third interface 1023 of the PMIC 102 and is used to control the on and off of the power interface.

[0115] In some embodiments of the present application, after triggering the reading of the storage device (for example, starting an application, decompressing a large file, loading a video resource), SoC101 may generate one or more read commands, and optionally, the read command is used to indicate a read operation on the UFS device 103. Exemplarily, the host system in SoC101 obtains the above one or more read commands, and parses to obtain the memory address and memory length (length) of the UFS device carried in the read command. Optionally, the memory address includes a logical block address (logical block address, LBA), LBA is used to indicate the starting logical block address, and length is used to indicate the number of logical blocks.

[0116] Exemplarily, SoC 101 determines the data amount according to the memory address and the memory length, and then sets / selects the target voltage according to the data amount. Exemplarily, SoC 101 sets / selects the target voltage by writing data in register 1024 of PMIC 102. Optionally, UFS device 103 further includes a frequency regulator ( Figure 4AThe frequency regulator is used to adjust the frequency according to the target voltage so that the adjusted target frequency corresponds to the target voltage. Optionally, in the embodiment of the present application, the data volume may be referred to as chunksize.

[0117] In one implementation, if the data written in the register 1024 corresponds to the first interface 1021, the target voltage may be set / selected to be the voltage provided by the first interface 1021. Exemplarily, the PMIC 102 may input a voltage to the first power interface 1033 of the UFS device 103 through the first interface 1021, so that the first power interface 1033 may supply power to the UFS device 103, and perform a read operation on the UFS device 103 according to the read command at the voltage. Optionally, the electronic device 100 performs a read operation on the UFS device 103 according to the read command at the voltage and the frequency corresponding to the voltage.

[0118] In one implementation, if the data written in the register 1024 corresponds to the second interface 1022, the target voltage may be set / selected to be the voltage provided by the second interface 1022. Exemplarily, the PMIC 102 may input a voltage to the second power interface 1034 of the UFS device 103 through the second interface 1022, so that the second power interface 1034 may supply power to the UFS device 103, and perform a read operation on the UFS device 103 according to the read command at the voltage. Optionally, the electronic device 100 performs a read operation on the UFS device 103 according to the read command at the voltage and the frequency corresponding to the voltage.

[0119] In one implementation, if the data written in the register 1024 corresponds to the third interface 1023, the target voltage may be set / selected to be the voltage provided by the third interface 1023. Exemplarily, the PMIC 102 may input a voltage to the third power interface 1035 of the UFS device 103 through the third interface 1023, so that the third power interface 1035 may supply power to the UFS device 103, and perform a read operation on the UFS device 103 according to the read command at the voltage. Optionally, the electronic device 100 performs a read operation on the UFS device 103 according to the read command at the voltage and the frequency corresponding to the voltage.

[0120] See also Figure 4B , Figure 4B It is a schematic diagram of the hardware architecture of another electronic device 100 provided in an embodiment of the present application. Figure 4B The electronic device 100 and Figure 4A The electronic device 100 shown is similar except that Figure 4B The register 1024 is connected to the first interface 1021 and the second interface 1022 of the PMIC 102 , and is used to control the on / off of the first interface 1021 and the on / off of the second interface 1022 . Figure 4BThe register 1024 shown is not connected to the third interface 1023 and does not control the on / off of the third interface 1023 . Optionally, the third interface 1023 may continuously input voltage to the UFS device 103 through a third voltage path.

[0121] Exemplarily, the voltage provided to the outside by the first interface 1021 of the PMIC 102 is greater than the voltage provided to the outside by the second interface 1022 of the PMIC 102. Optionally, the voltage input from the first interface 1021 of the PMIC 102 to the first power interface 1033 of the UFS device 103 is greater than the voltage input from the second interface 1022 of the PMIC 102 to the second power interface 1034 of the UFS device 103. Optionally, the voltage provided to the control unit 1031 by the first power interface 1033 of the UFS device 103 is greater than the voltage provided to the control unit 1031 by the second power interface 1034 of the UFS device 103.

[0122] In some embodiments of the present application, after triggering the reading of the storage device (for example, starting an application, decompressing a large file, loading a video resource), SoC101 may generate one or more read commands, and optionally, the read command is used to indicate a read operation on the UFS device 103. Exemplarily, the host system in SoC101 obtains the above one or more read commands, and parses to obtain the memory address and memory length (length) of the UFS device carried in the read command. Optionally, the memory address includes a logical block address LBA, LBA is used to indicate the starting logical block address, and length is used to indicate the number of logical blocks.

[0123] In one implementation, when the amount of data corresponding to the memory address and memory length of the UFS device is less than or equal to a preset threshold, SoC101 may set / select the target voltage to be a first voltage, and the first voltage may be considered to be a low voltage. Optionally, SoC101 sets / selects the target voltage to be a voltage (i.e., a first voltage) that can be provided by the second interface 1022 by writing data corresponding to the second interface 1022 in the register 1024 of PMIC102. It is understandable that when the data written in the register 1024 corresponds to the second interface 1022, the second interface 1022 is in an on state; when no data corresponding to the first interface 1021 is written in the register 1024, the first interface 1021 is in a disconnected state. Optionally, the UFS device 103 also includes a frequency regulator ( Figure 4B (not shown), the frequency regulator is used to adjust the frequency according to the first voltage so that the adjusted target frequency corresponds to the first voltage.

[0124] Exemplarily, when the amount of data corresponding to the memory address and memory length of the UFS device is less than or equal to a preset threshold, under the voltage provided by PMIC102 to the control unit 1031 of the UFS device 103 through the second interface 1022, and under the voltage provided by PMIC102 to the storage unit 1032 of the UFS device 103 through the third interface 1023, the UFS device 103 can read the amount of data corresponding to the memory address and memory length.

[0125] In another implementation, when the amount of data corresponding to the memory address and memory length of the UFS device is greater than a preset threshold, SoC101 may determine that the target voltage is a second voltage, and the second voltage may be considered a high voltage. Optionally, SoC101 sets / selects the target voltage to be a voltage (i.e., a second voltage) that can be provided by the first interface 1021 by writing data corresponding to the first interface 1021 in the register 1024 of PMIC102. It is understandable that when the data written in the register 1024 corresponds to the first interface 1021, the first interface 1021 is in an on state; when no data corresponding to the second interface 1022 is written in the register 1024, the second interface 1022 is in a disconnected state. Optionally, the UFS device 103 also includes a frequency regulator ( Figure 4B (not shown), the frequency regulator is used to adjust the frequency according to the second voltage so that the adjusted target frequency corresponds to the second voltage.

[0126] Exemplarily, when the amount of data corresponding to the memory address and memory length of the UFS device is greater than a preset threshold, under the voltage provided by PMIC102 to the control unit 1031 of the UFS device 103 through the first interface 1021, and under the voltage provided by PMIC102 to the storage unit 1032 of the UFS device 103 through the third interface 1023, the UFS device 103 can read the amount of data corresponding to the memory address and memory length.

[0127] See also Figure 4C , Figure 4C It is a schematic diagram of the hardware architecture of another electronic device 100 provided in an embodiment of the present application. Figure 4C The electronic device 100 and Figure 4A The electronic device 100 shown is similar except that Figure 4C The register 1024 is connected to the second interface 1022 and the third interface 1023 of the PMIC 102 , and is used to control the on / off of the second interface 1022 and the on / off of the third interface 1023 . Figure 4B The register 1024 shown is not connected to the first interface 1021 and does not control the on / off of the first interface 1021 . Optionally, the first interface 1021 may continuously input voltage to the UFS device 103 through the first voltage path.

[0128] Exemplarily, the voltage provided to the outside by the third interface 1023 of the PMIC 102 is greater than the voltage provided to the outside by the second interface 1022 of the PMIC 102. Optionally, the voltage input from the third interface 1023 of the PMIC 102 to the third power interface 1035 of the UFS device 103 is greater than the voltage input from the second interface 1022 of the PMIC 102 to the second power interface 1034 of the UFS device 103. Optionally, the voltage provided to the storage unit 1032 by the third power interface 1035 of the UFS device 103 is greater than the voltage provided to the storage unit 1032 by the second power interface 1034 of the UFS device 103.

[0129] In some embodiments of the present application, after triggering a read operation for a storage device (for example, starting an application, decompressing a large file, or loading a video resource), SoC 101 may generate one or more read commands, and optionally, the read command is used to indicate a read operation on the UFS device 103. Exemplarily, the host system in SoC 101 obtains the above one or more read commands, and parses the memory address and memory length (length) of the UFS device carried in the read command. Optionally, the memory address includes a logical block address LBA, where LBA is used to indicate the starting logical block address, and length is used to indicate the number of logical blocks.

[0130] In one implementation, when the amount of data corresponding to the memory address and memory length of the UFS device is less than or equal to a preset threshold, SoC101 may set / select the target voltage to be a first voltage, and the first voltage may be considered to be a low voltage. Optionally, SoC101 sets / selects the target voltage to be a voltage (i.e., a first voltage) that can be provided by the second interface 1022 by writing data corresponding to the second interface 1022 in the register 1024 of PMIC102. It is understandable that when the data written in the register 1024 corresponds to the second interface 1022, the second interface 1022 is in an on state; when no data corresponding to the first interface 1021 is written in the register 1024, the first interface 1021 is in a disconnected state. Optionally, the UFS device 103 also includes a frequency regulator ( Figure 4B (not shown), the frequency regulator is used to adjust the frequency according to the first voltage so that the adjusted target frequency corresponds to the first voltage.

[0131] Exemplarily, when the amount of data corresponding to the memory address and memory length of the UFS device is less than or equal to a preset threshold, under the voltage provided by PMIC102 to the storage unit 1032 of the UFS device 103 through the second interface 1022, and under the voltage provided by PMIC102 to the control unit 1031 of the UFS device 103 through the first interface 1021, the UFS device 103 can read the amount of data corresponding to the memory address and memory length.

[0132] In another implementation, when the amount of data corresponding to the memory address and memory length of the UFS device is greater than a preset threshold, SoC101 may determine that the target voltage is the second voltage, and the second voltage may be considered to be a high voltage. Optionally, SoC101 sets / selects the target voltage to be the voltage (i.e., the second voltage) that can be provided by the third interface 1023 by writing data corresponding to the third interface 1023 in the register 1024 of PMIC102. It is understandable that when the data written in the register 1024 corresponds to the third interface 1023, the third interface 1023 is in an on state; when no data corresponding to the second interface 1022 is written in the register 1024, the second interface 1022 is in a disconnected state. Optionally, the UFS device 103 also includes a frequency regulator ( Figure 4B (not shown), the frequency regulator is used to adjust the frequency according to the second voltage so that the adjusted target frequency corresponds to the second voltage.

[0133] Exemplarily, when the amount of data corresponding to the memory address and memory length of the UFS device is greater than a preset threshold, under the voltage provided by PMIC102 to the storage unit 1032 of the UFS device 103 through the third interface 1023, and under the voltage provided by PMIC102 to the control unit 1031 of the UFS device 103 through the first interface 1021, the UFS device 103 can read the amount of data corresponding to the memory address and memory length.

[0134] See also Figure 4D , Figure 4D It is a schematic diagram of the hardware architecture of another electronic device 100 provided in an embodiment of the present application. Figure 4D The electronic device 100 and Figure 4A The electronic device 100 shown is similar except that Figure 4C The second power interface 1034 of the UFS device 103 shown includes a first sub-interface 1134 and a second sub-interface 1234 . The first sub-interface 1134 is connected to the control unit 1031 of the UFS device 103 , and the second sub-interface 1234 is connected to the storage unit 1032 of the UFS device 103 .

[0135] Exemplarily, the voltage output by the first sub-interface 1134 and the second sub-interface 1234 is consistent with the voltage output by the second power interface 1034 of the UFS device 103. Optionally, the voltage output by the first sub-interface 1134 and the second sub-interface 1234 is consistent with the voltage input by the second power interface 1034 of the UFS device 103 received from the second interface 1022 of the PMIC 102.

[0136] Exemplarily, the voltage provided to the outside by the first interface 1021 of PMIC102 is greater than the voltage provided to the outside by the second interface 1022 of PMIC102; the voltage provided to the outside by the third interface 1023 of PMIC102 is greater than the voltage provided to the outside by the second interface 1022 of PMIC102. Optionally, the voltage input from the first interface 1021 of PMIC102 to the first power interface 1033 of UFS device 103 is greater than the voltage input from the second interface 1022 of PMIC102 to the second power interface 1034 of UFS device 103; the voltage input from the third interface 1023 of PMIC102 to the third power interface 1035 of UFS device 103 is greater than the voltage input from the second interface 1022 of PMIC102 to the second power interface 1034 of UFS device 103. Optionally, the voltage provided by the first power interface 1033 of the UFS device 103 to the control unit 1031 is greater than the voltage provided by the first sub-interface 1134 of the UFS device 103 to the control unit 1031; the voltage provided by the third power interface 1035 of the UFS device 103 to the storage unit 1032 is greater than the voltage provided by the second sub-interface 1234 of the UFS device 103 to the storage unit 1032.

[0137] In some embodiments of the present application, after triggering a read operation for a storage device (for example, starting an application, decompressing a large file, or loading a video resource), SoC 101 may generate one or more read commands, and optionally, the read command is used to indicate a read operation on the UFS device 103. Exemplarily, the host system in SoC 101 obtains the above one or more read commands, and parses the memory address and memory length (length) of the UFS device carried in the read command. Optionally, the memory address includes a logical block address LBA, where LBA is used to indicate the starting logical block address, and length is used to indicate the number of logical blocks.

[0138] In one implementation, when the amount of data corresponding to the memory address and memory length of the UFS device is less than or equal to a preset threshold, SoC101 may set / select the target voltage to be a first voltage, and the first voltage may be considered to be a low voltage. Optionally, SoC101 sets / selects the target voltage to be a voltage (i.e., the first voltage) that can be provided by the second interface 1022 by writing data corresponding to the second interface 1022 in the register 1024 of PMIC102. It can be understood that when the data written in the register 1024 corresponds to the second interface 1022, the second interface 1022 is in an on state; when no data corresponding to the first interface 1021 is written in the register 1024 and no data corresponding to the third interface 1023 is written, the first interface 1021 and the third interface 1023 are in a disconnected state. Optionally, the UFS device 103 also includes a frequency regulator ( Figure 4B (not shown), the frequency regulator is used to adjust the frequency according to the first voltage so that the adjusted target frequency corresponds to the first voltage.

[0139] Exemplarily, when the amount of data corresponding to the memory address and memory length of the UFS device is less than or equal to a preset threshold, the PMIC 102 inputs a voltage to the second power interface 1034 of the UFS device 103 through the second interface 1022, and the second power interface 1034 of the UFS device 103 can supply power to the control unit 1031 through the first sub-interface 1134, and supply power to the storage unit 1032 through the second sub-interface 1234. Under the above voltage, the UFS device 103 can read the amount of data corresponding to the memory address and memory length.

[0140] In another implementation, when the amount of data corresponding to the memory address and memory length of the UFS device is greater than a preset threshold, SoC101 may determine that the target voltage is a second voltage, and the second voltage may be considered to be a high voltage. Optionally, SoC101 sets / selects the target voltage to include the voltage that can be provided by the third interface 1023 and the voltage provided by the first interface 1021 by writing data corresponding to the third interface 1023 and writing data corresponding to the first interface 1021 in the register 1024 of PMIC102. It can be understood that when the data written in the register 1024 corresponds to the third interface 1023 and the first interface 1021, the third interface 1023 and the first interface 1021 are in an on state; when no data corresponding to the second interface 1022 is written in the register 1024, the second interface 1022 is in a disconnected state. Optionally, the UFS device 103 also includes a frequency regulator ( Figure 4B (not shown), the frequency regulator is used to adjust the frequency according to the second voltage so that the adjusted target frequency corresponds to the second voltage.

[0141] Exemplarily, when the amount of data corresponding to the memory address and memory length of the UFS device is greater than a preset threshold, the PMIC 102 inputs a voltage to the first power interface 1033 of the UFS device 103 through the first interface 1021, and inputs a voltage to the third power interface 1035 of the UFS device 103 through the third interface 1023. The first power interface 1033 of the UFS device 103 can supply power to the control unit 1031, and the third power interface 1035 can supply power to the storage unit 1032. Under the above voltage, the UFS device 103 can read the amount of data corresponding to the memory address and memory length.

[0142] See also Figure 5A , Figure 5A It is a schematic diagram of the hardware structure of another electronic device 100 provided in an embodiment of the present application. Figure 5A The electronic device 100 and Figure 3 The electronic device 100 shown is similar except that Figure 5A The UFS device 103 of the electronic device 100 shown further includes a power regulator 1036 , which is connected to one or more of the first power interface 1033 , the second power interface 1034 and the third power interface 1035 of the UFS device 103 to control the on and off of the power interfaces.

[0143] In some embodiments of the present application, after triggering the reading of the storage device (for example, starting an application, decompressing a large file, loading a video resource), SoC101 may generate one or more read commands, and optionally, the read command is used to indicate a read operation on the UFS device 103. Exemplarily, the host system in SoC101 transmits the above one or more read commands to the UFS device 103, and optionally, the power regulator 1036 in the UFS device 103 may parse the memory address and memory length (length) of the UFS device carried in the read command. Optionally, the memory address includes a logical block address (logicalblock address, LBA), LBA is used to indicate the starting logical block address, and length is used to indicate the number of logical blocks.

[0144] Exemplarily, the power regulator 1036 determines the data amount according to the memory address and the memory length, and then sets / selects the target voltage according to the data amount. Exemplarily, the power regulator 1036 controls the on and off of the power interface to set / select the voltage provided by the on power interface as the target voltage. Optionally, the UFS device 103 further includes a frequency regulator ( Figure 5A (not shown), the frequency regulator is used to adjust the frequency according to the target voltage so that the adjusted target frequency corresponds to the target voltage.

[0145] In one implementation, the power regulator 1036 controls the first power interface 1033 to be turned on, and the target voltage can be set / selected as the voltage provided by the first power interface 1033. Exemplarily, the PMIC 102 inputs a voltage to the first power interface 1033 of the UFS device 103 through the first interface 1021, and the first power interface 1033 in the turned-on state can supply power to the control unit 1031 of the UFS device 103, and perform a read operation on the UFS device 103 according to the read command at this voltage. Optionally, the electronic device 100 performs a read operation on the UFS device according to the read command at this voltage and the frequency corresponding to the voltage.

[0146] In one implementation, the power regulator 1036 controls the second power interface 1034 to be turned on, and the target voltage can be set / selected as the voltage provided by the second power interface 1034. Exemplarily, the PMIC 102 inputs a voltage to the second power interface 1034 of the UFS device 103 through the second interface 1022, and the second power interface 1034 in the turned-on state can supply power to the control unit 1031 and / or the storage unit 1032 of the UFS device 103, and performs a read operation on the UFS device 103 according to the read command at this voltage. Optionally, the electronic device 100 performs a read operation on the UFS device according to the read command at this voltage and the frequency corresponding to the voltage.

[0147] In one implementation, the power regulator 1036 controls the third power interface 1035 to be turned on, and the target voltage can be set / selected as the voltage provided by the third power interface 1035. Exemplarily, the PMIC 102 inputs a voltage to the third power interface 1035 of the UFS device 103 through the third interface 1023, and the third power interface 1035 in the turned-on state can supply power to the storage unit 1032 of the UFS device 103, and perform a read operation on the UFS device 103 according to the read command at this voltage. Optionally, the electronic device 100 performs a read operation on the UFS device according to the read command at this voltage and the frequency corresponding to the voltage.

[0148] See also Figure 5B , Figure 5B It is a schematic diagram of the hardware architecture of another electronic device 100 provided in an embodiment of the present application. Figure 5B The electronic device 100 and Figure 5A The electronic device 100 shown is similar except that Figure 5B The second power interface 1034 in the UFS device shown is connected to the control unit 1031 . Figure 5B The power regulator 1036 shown is connected to the first power interface 1033 and the second power interface 1034 , and is used to control the on and off of the first power interface 1033 and the second power interface 1034 . Figure 5BThe power regulator shown is not connected to the third power interface 1035 and does not control the on / off of the third power interface 1035 . Optionally, the third power interface 1035 can continuously supply power to the storage unit 1032 .

[0149] Exemplarily, the voltage provided to the outside by the first interface 1021 of the PMIC 102 is greater than the voltage provided to the outside by the second interface 1022 of the PMIC 102. Optionally, the voltage input from the first interface 1021 of the PMIC 102 to the first power interface 1033 of the UFS device 103 is greater than the voltage input from the second interface 1022 of the PMIC 102 to the second power interface 1034 of the UFS device 103. Optionally, the voltage provided to the control unit 1031 by the first power interface 1033 of the UFS device 103 is greater than the voltage provided to the control unit 1031 by the second power interface 1034 of the UFS device 103.

[0150] In some embodiments of the present application, after triggering a function for reading a storage device (for example, starting an application, decompressing a large file, or loading a video resource), SoC 101 may generate one or more read commands, and optionally, the read command is used to indicate a read operation on the UFS device 103. Exemplarily, the host system in SoC 101 transmits the above one or more read commands to the UFS device 103, and optionally, the power regulator 1036 in the UFS device 103 may parse the memory address and memory length (length) of the UFS device carried in the read command. Optionally, the memory address includes a logical block address (logical block address, LBA), and LBA is used to indicate the starting logical block address, and length is used to indicate the number of logical blocks.

[0151] In one implementation, when the amount of data corresponding to the memory address and memory length of the UFS device is less than or equal to a preset threshold, the power regulator 1036 may set / select the target voltage to be the first voltage. Optionally, the power regulator 1036 sets / selects the target voltage to be the voltage that the second power interface 1034 can provide (i.e., the first voltage) by controlling the first power interface 1033 to be disconnected and controlling the second power interface 1034 to be turned on. It is understandable that the second power interface 1034 in the on state can transmit voltage to the control unit 1031; the first power interface 1033 in the off state cannot transmit voltage to the control unit 1031. Optionally, the UFS device 103 also includes a frequency regulator ( Figure 5B (not shown), the frequency regulator is used to adjust the frequency according to the first voltage so that the adjusted target frequency corresponds to the first voltage.

[0152] Exemplarily, when the amount of data corresponding to the memory address and memory length of the UFS device is less than or equal to a preset threshold, the second power interface 1034 of the UFS device 103 supplies power to the control unit 1031, and the third power interface 1035 of the UFS device 103 supplies power to the storage unit 1032. At this voltage, the UFS device 103 can read the amount of data corresponding to the memory address and memory length.

[0153] In another implementation, when the amount of data corresponding to the memory address and memory length of the UFS device is greater than a preset threshold, the power regulator 1036 may set / select the target voltage to be the second voltage. Optionally, the power regulator 1036 sets / selects the target voltage to be the voltage that the first power interface 1033 can provide (i.e., the second voltage) by controlling the first power interface 1033 to be turned on and the second power interface 1034 to be turned off. It is understandable that the first power interface 1033 in the turned-on state can transmit voltage to the control unit 1031; the second power interface 1034 in the turned-off state cannot transmit voltage to the control unit 1031. Optionally, the UFS device 103 also includes a frequency regulator ( Figure 5B (not shown), the frequency regulator is used to adjust the frequency according to the first voltage so that the adjusted target frequency corresponds to the first voltage.

[0154] Exemplarily, when the amount of data corresponding to the memory address and memory length of the UFS device is greater than a preset threshold, the first power interface 1033 of the UFS device 103 supplies power to the control unit 1031, and the third power interface 1035 of the UFS device 103 supplies power to the storage unit 1032. At this voltage, the UFS device 103 can read the amount of data corresponding to the memory address and memory length.

[0155] See also Figure 5C , Figure 5C It is a schematic diagram of the hardware architecture of another electronic device 100 provided in an embodiment of the present application. Figure 5C The electronic device 100 and Figure 5A The electronic device 100 shown is similar except that Figure 5C The second power interface 1034 in the UFS device 103 is shown to be connected to the storage unit 1032 . Figure 5C The power regulator 1036 shown is connected to the second power interface 1034 and the third power interface 1035 , and is used to control the on and off of the second power interface 1034 and the third power interface 1035 . Figure 5B The power regulator 1036 shown is not connected to the first power interface 1033 and does not control the on / off of the first power interface 1033 . Optionally, the first power interface 1033 can continuously supply power to the control unit 1031 .

[0156] Exemplarily, the voltage provided to the outside by the third interface 1023 of the PMIC 102 is greater than the voltage provided to the outside by the second interface 1022 of the PMIC 102. Optionally, the voltage input from the third interface 1023 of the PMIC 102 to the third power interface 1035 of the UFS device 103 is greater than the voltage input from the second interface 1022 of the PMIC 102 to the second power interface 1034 of the UFS device 103. Optionally, the voltage provided to the storage unit 1032 by the third power interface 1035 of the UFS device 103 is greater than the voltage provided to the storage unit 1032 by the second power interface 1034 of the UFS device 103.

[0157] In some embodiments of the present application, after triggering a function for reading a storage device (for example, starting an application, decompressing a large file, or loading a video resource), SoC 101 may generate one or more read commands, and optionally, the read command is used to indicate a read operation on the UFS device 103. Exemplarily, the host system in SoC 101 transmits the above one or more read commands to the UFS device 103, and optionally, the power regulator 1036 in the UFS device 103 may parse the memory address and memory length (length) of the UFS device carried in the read command. Optionally, the memory address includes a logical block address (logical block address, LBA), and LBA is used to indicate the starting logical block address, and length is used to indicate the number of logical blocks.

[0158] In one implementation, when the amount of data corresponding to the memory address and memory length of the UFS device is less than or equal to a preset threshold, the power regulator 1036 may set / select the target voltage to be the first voltage. Optionally, the power regulator 1036 sets / selects the target voltage to be the voltage (i.e., the first voltage) that the second power interface 1034 can provide by controlling the third power interface 1035 to be disconnected and controlling the second power interface 1034 to be turned on. It is understandable that the second power interface 1034 in the on state can transmit voltage to the storage unit 1032; the third power interface 1035 in the off state cannot transmit voltage to the storage unit 1032. Optionally, the UFS device 103 also includes a frequency regulator ( Figure 5C (not shown), the frequency regulator is used to adjust the frequency according to the first voltage so that the adjusted target frequency corresponds to the first voltage.

[0159] Exemplarily, when the amount of data corresponding to the memory address and memory length of the UFS device is less than or equal to a preset threshold, the second power interface 1034 of the UFS device 103 supplies power to the storage unit 1032, and the first power interface 1033 of the UFS device 103 supplies power to the control unit 1031. At this voltage, the UFS device 103 can read the amount of data corresponding to the memory address and memory length.

[0160] In another implementation, when the amount of data corresponding to the memory address and memory length of the UFS device is greater than a preset threshold, the power regulator 1036 may set / select the target voltage to be the second voltage. Optionally, the power regulator 1036 sets / selects the target voltage to be the voltage that the third power interface 1035 can provide (i.e., the second voltage) by controlling the second power interface 1034 to be disconnected and controlling the third power interface 1035 to be turned on. It is understandable that the third power interface 1035 in the on state can transmit voltage to the storage unit 1032; the second power interface 1034 in the off state cannot transmit voltage to the storage unit 1032. Optionally, the UFS device 103 also includes a frequency regulator ( Figure 5B (not shown), the frequency regulator is used to adjust the frequency according to the first voltage so that the adjusted target frequency corresponds to the first voltage.

[0161] Exemplarily, when the amount of data corresponding to the memory address and memory length of the UFS device is greater than a preset threshold, the first power interface 1033 of the UFS device 103 supplies power to the control unit 1031, and the third power interface 1035 of the UFS device 103 supplies power to the storage unit 1032. At this voltage, the UFS device 103 can read the amount of data corresponding to the memory address and memory length.

[0162] See also Figure 5D , Figure 5D It is a schematic diagram of the hardware architecture of another electronic device 100 provided in an embodiment of the present application. Figure 5D The electronic device 100 and Figure 5A The electronic device 100 shown is similar except that Figure 5D The second power interface 1034 in the UFS device 103 shown is connected to the control unit 1031 through the first sub-interface 1134 , and is connected to the storage unit 1032 through the second sub-interface 1234 .

[0163] Exemplarily, the voltage output by the first sub-interface 1134 and the second sub-interface 1234 is consistent with the voltage output by the second power interface 1034 of the UFS device 103. Optionally, the voltage output by the first sub-interface 1134 and the second sub-interface 1234 is consistent with the voltage input by the second power interface 1034 of the UFS device 103 received from the second interface 1022 of the PMIC 102.

[0164] Exemplarily, the voltage provided to the outside by the first interface 1021 of PMIC102 is greater than the voltage provided to the outside by the second interface 1022 of PMIC102; the voltage provided to the outside by the third interface 1023 of PMIC102 is greater than the voltage provided to the outside by the second interface 1022 of PMIC102. Optionally, the voltage input from the first interface 1021 of PMIC102 to the first power interface 1033 of UFS device 103 is greater than the voltage input from the second interface 1022 of PMIC102 to the second power interface 1034 of UFS device 103; the voltage input from the third interface 1023 of PMIC102 to the third power interface 1035 of UFS device 103 is greater than the voltage input from the second interface 1022 of PMIC102 to the second power interface 1034 of UFS device 103. Optionally, the voltage provided by the first power interface 1033 of the UFS device 103 to the control unit 1031 is greater than the voltage provided by the first sub-interface 1134 of the UFS device 103 to the control unit 1031; the voltage provided by the third power interface 1035 of the UFS device 103 to the storage unit 1032 is greater than the voltage provided by the second sub-interface 1234 of the UFS device 103 to the storage unit 1032.

[0165] In some embodiments of the present application, after triggering a function for reading a storage device (for example, starting an application, decompressing a large file, or loading a video resource), SoC 101 may generate one or more read commands, and optionally, the read command is used to indicate a read operation on the UFS device 103. Exemplarily, the host system in SoC 101 transmits the above one or more read commands to the UFS device 103, and optionally, the power regulator 1036 in the UFS device 103 may parse the memory address and memory length (length) of the UFS device carried in the read command. Optionally, the memory address includes a logical block address (logical block address, LBA), and LBA is used to indicate the starting logical block address, and length is used to indicate the number of logical blocks.

[0166] In one implementation, when the amount of data corresponding to the memory address and memory length of the UFS device is less than or equal to a preset threshold, the power regulator 1036 may set the target voltage to the first voltage. Optionally, the power regulator 1036 sets the target voltage to the voltage that the second power interface 1034 can provide (i.e., the first voltage) by controlling the first power interface 1033 and the third power interface 1035 to be disconnected, and controlling the second power interface 1034 to be turned on. It can be understood that the second power interface 1034 in the on state can transmit voltage to the control unit 1031 through the first sub-interface 1134, and can transmit voltage to the storage unit 1032 through the second sub-interface 1234; the first power interface 1033 in the disconnected state cannot transmit voltage to the control unit 1031, and the third power interface 1035 in the disconnected state cannot transmit voltage to the storage unit 1032. Optionally, the UFS device 103 also includes a frequency regulator ( Figure 5C (not shown), the frequency regulator is used to adjust the frequency according to the first voltage so that the adjusted target frequency corresponds to the first voltage.

[0167] Exemplarily, when the amount of data corresponding to the memory address and memory length of the UFS device is less than or equal to a preset threshold, the second power interface 1034 of the UFS device 103 supplies power to the control unit 1031 through the first sub-interface 1134, and the second power interface 1034 of the UFS device 103 supplies power to the storage unit 1032 through the second sub-interface 1234. At this voltage, the UFS device 103 can read the amount of data corresponding to the memory address and memory length.

[0168] In another implementation, when the amount of data corresponding to the memory address and memory length of the UFS device is greater than a preset threshold, the power regulator 1036 may set the target voltage to the second voltage. Optionally, the power regulator 1036 sets the target voltage to the voltage that can be provided by the first power interface 1033 and the voltage provided by the third power interface 1035 by controlling the first power interface 1033 and the third power interface 1035 to be turned on and controlling the second power interface 1034 to be turned off. Optionally, the UFS device 103 further includes a frequency regulator ( Figure 5C (not shown), the frequency regulator is used to adjust the frequency according to the first voltage so that the adjusted target frequency corresponds to the first voltage.

[0169] Exemplarily, when the amount of data corresponding to the memory address and memory length of the UFS device is greater than a preset threshold, the first power interface 1033 of the UFS device 103 supplies power to the control unit 1031, and the third power interface 1035 of the UFS device 103 supplies power to the storage unit 1032. At this voltage, the UFS device 103 can read the amount of data corresponding to the memory address and memory length.

[0170] See also Figure 6 , Figure 6 is a flow chart of a voltage regulation method provided in an embodiment of the present application, which can be applied to Figure 3 , FIG. 4A to FIG. 4D , FIG. 5A to FIG. 5D Any electronic device 100 in. Optionally, the method includes but is not limited to the following steps:

[0171] Step S601: Obtain a read command, where the read command is used to instruct a read operation to be performed on a UFS device.

[0172] Exemplarily, after the electronic device 100 receives an operation for triggering a read operation on a storage device (such as a UFS device) (such as starting an application, scanning a code, compressing a large file, loading a large game, etc.), in response to the operation, one or more read commands can optionally be generated by the HOST system in the SoC.

[0173] Exemplarily, the HOST system may send the one or more read commands to the UFS storage device.

[0174] Step S602: parse and obtain the memory address and memory length of the UFS device carried in the read command.

[0175] Exemplarily, the HOST system in the electronic device 100 can parse the read command to obtain the memory address and memory length of the UFS device. Optionally, the memory address includes LBA, which is an addressing mode that can locate blocks from 0, for example, the first logical block LBA=0, the second logical block LBA=1..., the Nth logical block LBA=N, and the memory length (length)=1,2,3...N, where N is the number of logical blocks in the UFS device.

[0176] Step S603: setting a target voltage according to the memory address and memory length of the UFS device.

[0177] Exemplarily, the memory address is used to indicate the starting logical block address, and the length is used to indicate the number of logical blocks. Optionally, the size of a logical block is 4KB. The amount of data required to be read by the read command can be determined based on the memory address and the memory length. For example, the amount of data = the size of the logical block multiplied by the number of logical blocks.

[0178] In one implementation, the electronic device 100 includes a PMIC, and the UFS device includes one or more of a control unit, a storage unit, a first power interface, and a third power interface. Optionally, the PMIC is used to input a voltage to the first power interface of the UFS device, so that the first power interface supplies power to the control unit. Optionally, the PMIC is used to input a voltage to the second power interface of the UFS device, so that the second power interface supplies power to the control unit and / or the storage unit. Optionally, the PMIC is used to input a voltage to the third power interface of the UFS device, so that the third power interface supplies power to the storage unit. For a detailed description, see the above Figure 3 . I will not go into details here.

[0179] In a possible implementation, when the amount of data corresponding to the memory address and memory length of the UFS device is less than or equal to a preset threshold, setting the target voltage includes a first voltage. When the amount of data corresponding to the memory address and memory length of the UFS device is greater than the preset threshold, setting the target voltage includes a second voltage. The second voltage is greater than the first voltage.

[0180] Optionally, the PMIC includes a register, and when the amount of data corresponding to the memory address and memory length of the UFS device is less than a preset threshold, the first voltage is determined as the target voltage through the register of the PMIC; when the amount of data corresponding to the memory address and memory length of the UFS device is less than a preset threshold, the second voltage is determined as the target voltage through the register of the PMIC. For detailed description, please refer to the above FIG. 4A to FIG. 4D , I will not go into details this time.

[0181] Optionally, the UFS device includes a power regulator. When the amount of data corresponding to the memory address and memory length of the UFS device is less than a preset threshold, the first voltage is determined as the target voltage by the power regulator of the UFS device; when the amount of data corresponding to the memory address and memory length of the UFS device is less than a preset threshold, the second voltage is determined as the target voltage by the power regulator of the UFS device. For detailed description, please refer to the above FIG. 5A to FIG. 5D , I will not go into details this time.

[0182] Exemplarily, when the first power interface of the UFS device and the second power interface of the UFS device supply power to the control unit, and the third power interface of the UFS device supplies power to the storage unit, the first voltage includes the voltage input through the second power interface of the UFS device, and the second voltage includes the voltage input through the first power interface of the UFS device; wherein the voltage input through the first power interface of the UFS device is greater than the voltage input through the second power interface of the UFS device. For detailed description, please refer to Figure 4B or Figure 5B , I will not go into details this time.

[0183] Exemplarily, when the first power interface of the UFS device is used to supply power to the control unit, and the second power interface of the UFS device and the third power interface of the UFS device are used to supply power to the storage unit, the first voltage includes the voltage input through the second power interface of the UFS device, and the second voltage includes the voltage input through the third power interface of the UFS device; wherein the voltage input through the third power interface of the UFS device is greater than the voltage input through the second power interface of the UFS device. For detailed description, please refer to Figure 4C or Figure 5C , I will not go into details this time.

[0184] Exemplarily, the second power interface of the UFS device includes a first sub-interface and a second sub-interface, and in the case where the first power interface and the first sub-interface are used to supply power to the control unit, and the second sub-interface and the third power interface are used to supply power to the storage unit, the first voltage includes the voltage input through the first sub-interface and the voltage input through the second sub-interface, and the second voltage includes the voltage input through the first power interface and the voltage input through the third power interface; wherein the voltage input to the first power interface is greater than the voltage input to the first sub-interface, and the voltage input to the third power interface is greater than the voltage input to the second power supply. For detailed description, please refer to Figure 4D or Figure 5D , I will not go into details this time.

[0185] Optionally, when the HOST system of the SoC recognizes that the amount of data corresponding to the memory address and memory length of the UFS device carried by the read command is less than or equal to a preset threshold, this type of read command can be grouped to form a first group, and the first voltage can be set as the target voltage subsequently using the read commands included in the first group.

[0186] Optionally, when the HOST system of the SoC recognizes that the amount of data corresponding to the memory address and memory length of the UFS device carried by the read command is greater than a preset threshold, this type of read command can be grouped into a second group, and the second voltage can be set as the target voltage subsequently using the read commands included in the second group.

[0187] In the embodiment of the present application, the preset threshold is a value obtained from historical data research, which can be used to measure whether the amount of data corresponding to the memory address and memory length of the UFS device carried in the read command is a small amount of data or a large amount of data. Optionally, the preset threshold is 128 kilobytes (KB).

[0188] Step S604: powering the UFS device using the target voltage, and performing a read operation on the UFS device according to the read command at the target voltage.

[0189] Exemplarily, when the amount of data corresponding to the memory address and memory length of the UFS device is less than or equal to a preset threshold, the electronic device 100 performs a read operation on the UFS device according to the read command at the first voltage. Optionally, at the first voltage, the electronic device can set a first frequency corresponding to the first voltage through the UFS device, and at the first voltage and the first frequency, the electronic device 100 performs a read operation on the UFS device according to the read command.

[0190] Exemplarily, when the amount of data corresponding to the memory address and memory length of the UFS device is greater than a preset threshold, the electronic device 100 performs a read operation on the UFS device according to the read command at the second voltage. Optionally, at the second voltage, the electronic device can set a second frequency corresponding to the second voltage through the UFS device, and at the second voltage and the second frequency, the electronic device 100 performs a read operation on the UFS device according to the read command.

[0191] In one implementation, the electronic device 100 pre-sets the first voltage as a default voltage and the first frequency corresponding to the first voltage as a default frequency. Optionally, after the first voltage is switched to the second voltage, and the first frequency is switched to the second frequency corresponding to the second voltage, after the corresponding read command is processed at the second voltage and the second frequency, it can be determined whether such read commands continue to be obtained. If not, the second voltage is switched to the first voltage, and the second frequency is switched to the first frequency.

[0192] It should be understood that each step in the above method embodiment provided by the present application can be completed by an integrated logic circuit of hardware in a processor or by instructions in the form of software. The method steps disclosed in the embodiments of the present application can be directly embodied as being executed by a hardware processor, or by a combination of hardware and software modules in a processor.

[0193] The present application also provides an electronic device, which may include: a memory and a processor, wherein the memory may be used to store a computer program; and the processor may be used to call the computer program in the memory so that the electronic device executes the method in any one of the above embodiments.

[0194] The present application also provides a chip system, which includes at least one processor for implementing the functions involved in the method executed by the electronic device in any of the above embodiments.

[0195] In one possible design, the chip system also includes a memory, which is used to store program instructions and data, and the memory is located inside or outside the processor.

[0196] The chip system may be composed of the chip, or may include the chip and other discrete devices.

[0197] Optionally, the processor in the chip system may be one or more. The processor may be implemented by hardware or by software. When implemented by hardware, the processor may be a logic circuit, an integrated circuit, etc. When implemented by software, the processor may be a general-purpose processor implemented by reading software code stored in a memory.

[0198] Optionally, the memory in the chip system may also be one or more. The memory may be integrated with the processor or may be separately arranged with the processor, which is not limited in the embodiments of the present application. Exemplarily, the memory may be a non-transient processor, such as a read-only memory ROM, which may be integrated with the processor on the same chip or may be arranged on different chips respectively. The embodiments of the present application do not specifically limit the type of memory and the arrangement of the memory and the processor.

[0199] Exemplarily, the chip system may be a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a system on chip (SoC), a central processor unit (CPU), a network processor (NP), a digital signal processor (DSP), a microcontroller unit (MCU), a programmable logic device (PLD), or other integrated chips.

[0200] The present application also provides a computer program product, which includes: a computer program (also referred to as code, or instruction), which enables a computer to execute the method executed by the electronic device in any of the above embodiments when the computer program is executed.

[0201] The present application also provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program (also referred to as code or instruction). When the computer program is executed, the computer executes the method executed by the electronic device in any of the above embodiments.

[0202] The various implementation modes of the present application can be combined arbitrarily to achieve different technical effects.

[0203] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented by software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in this application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website site, computer, server or data center to another website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) mode. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that includes one or more available media integrated. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state hard disk SolidState Disk), etc.

[0204] Those skilled in the art can understand that to implement all or part of the processes in the above-mentioned embodiments, the processes can be completed by computer programs to instruct related hardware, and the programs can be stored in computer-readable storage media. When the programs are executed, they can include the processes of the above-mentioned method embodiments. The aforementioned storage media include: ROM or random access memory RAM, magnetic disk or optical disk and other media that can store program codes.

[0205] In short, the above description is only an embodiment of the technical solution of the present invention, and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made according to the disclosure of the present invention shall be included in the protection scope of the present invention.

Claims

1. A voltage regulation method, characterized in that: The method is applied to an electronic device, the electronic device comprising a universal flash storage UFS device and a power management chip PMIC, the UFS device comprising a control unit, a storage unit, a first power interface, a second power interface and a third power interface, the PMIC is used to input a voltage to the first power interface so that the first power interface supplies power to the control unit; the PMIC is used to input a voltage to the second power interface so that the second power interface supplies power to the control unit and / or the storage unit; The PMIC is used to input voltage to the third power interface so that the third power interface supplies power to the storage unit; The method comprises: Get the read command; Parsing and obtaining the memory address and memory length of the UFS device carried in the read command, wherein the amount of data corresponding to the memory address and memory length of the UFS device is the amount of data indicated by the read command to be read; When the amount of data corresponding to the memory address and the memory length of the UFS device is less than or equal to a preset threshold, setting the target voltage includes a first voltage; When the amount of data corresponding to the memory address and the memory length of the UFS device is greater than the preset threshold, setting the target voltage to include a second voltage, wherein the second voltage is greater than the first voltage, the voltage received by the second power interface is the first voltage, and the voltage received by the first power interface and / or the voltage received by the third power interface is the second voltage; The UFS device is powered by the PMIC using the target voltage, and a read operation is performed on the UFS device according to the read command at the target voltage.

2. The method according to claim 1, characterized in that When the first power interface and the second power interface supply power to the control unit, and the third power interface supplies power to the storage unit, the first voltage includes the voltage input through the second power interface, and the second voltage includes the voltage input through the first power interface; wherein the voltage input to the first power interface is greater than the voltage input to the second power interface.

3. The method according to claim 1, characterized in that When the first power interface is used to supply power to the control unit, and the second power interface and the third power interface are used to supply power to the storage unit, the first voltage includes the voltage input through the second power interface, and the second voltage includes the voltage input through the third power interface; wherein the voltage input to the third power interface is greater than the voltage input to the second power interface.

4. The method according to claim 1, characterized in that The second power interface includes a first sub-interface and a second sub-interface; When the first power interface and the first sub-interface are used to supply power to the control unit, and the second sub-interface and the third power interface are used to supply power to the storage unit, the first voltage includes a voltage input through the first sub-interface and a voltage input through the second sub-interface, and the second voltage includes a voltage input through the first power interface and a voltage input through the third power interface; wherein the voltage input to the first power interface is greater than the voltage input to the first sub-interface, and the voltage input to the third power interface is greater than the voltage input to the second sub-interface.

5. The method according to any one of claims 1 to 4, characterized in that: The PMIC includes a register, and determining a target voltage according to a memory address and a memory length of the UFS device includes: When the amount of data corresponding to the memory address and the memory length of the UFS device is less than a preset threshold, determining, by the register, that the first voltage is the target voltage; When the amount of data corresponding to the memory address and the memory length of the UFS device is less than a preset threshold, the second voltage is determined as the target voltage through the register.

6. The method according to any one of claims 1 to 4, characterized in that: The UFS device includes a power regulator, and determining a target voltage according to a memory address and a memory length of the UFS device includes: When the amount of data corresponding to the memory address and the memory length of the UFS device is less than a preset threshold, determining, by the power regulator, that the first voltage is the target voltage; When the amount of data corresponding to the memory address and the memory length of the UFS device is less than a preset threshold, the second voltage is determined to be the target voltage by the power regulator.

7. An electronic device, characterized in that: The electronic device comprises: one or more processors; a memory; wherein the memory is coupled to the one or more processors, the memory is used to store computer program code, the computer program code comprises computer instructions, and the one or more processors call the computer instructions so that the electronic device executes the method as described in any one of claims 1-6.

8. A chip system, characterized in that: The chip system is applied to an electronic device, and the chip system includes one or more processors, and the processor is used to call computer instructions so that the electronic device executes the method as described in any one of claims 1-6.

9. A computer program product comprising instructions, characterized in that When the computer program product is executed on an electronic device, the electronic device is enabled to execute the method according to any one of claims 1 to 6.

10. A computer-readable storage medium comprising instructions, characterized in that: When the instructions are executed on an electronic device, the electronic device is caused to execute the method as claimed in any one of claims 1 to 6.

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