Verification method and device for page missing abnormity caused by page table modification of processor

Abstract

The invention provides a verification method and device for page missing abnormity caused by processor page table modification, and relates to the technical field of processors, the method comprises the steps that a storage instruction of a to-be-verified processor is acquired, and the storage instruction is used for modifying a page table of the to-be-verified processor; performing write tracking on the storage instruction to determine a modification result of the page table; simulating the modification result of the page table based on the data storage instruction to obtain a simulation result; and comparing the modification result with the simulation result to obtain a verification result. The bottleneck that the simulator cannot directly verify processor behaviors due to lack of processor microstructure information in simulation verification is solved, the synchronization condition of page table updating of the processor can be tracked, and synchronous verification of the processor is realized through the simulator.

Description

Technical Field

[0001] The present application relates to the field of processor technology, and in particular to a method and device for verifying a page fault exception caused by processor page table modification. Background Art

[0002] The processor introduces a page fault exception (Page Fault) because the virtual memory introduced by the operating system kernel makes it impossible for the program to directly access the physical memory. When accessing the virtual memory, the processor needs to modify the page table.

[0003] The simulator is a behavioral simulation and does not involve various queues, so the execution results of the simulator's store instruction and the modification of the page table are immediately visible. However, the modification of the page table by some results of the processor to be verified is not visible.

[0004] Therefore, if synchronization instructions are not used, the simulation of the simulator and the simulation of the processor to be verified will not be able to align the analysis of the behavior of the page fault exception caused by the processor page table modification, making it difficult to compare the results. Summary of the invention

[0005] The present application aims to solve one of the technical problems in the related art at least to some extent.

[0006] To this end, the first objective of the present application is to propose a verification method for page fault exception caused by processor page table modification, so as to realize verification of processor behavior by a simulator.

[0007] The second objective of the present application is to provide a verification device for page fault exception caused by processor page table modification.

[0008] The third objective of the present application is to provide an electronic device.

[0009] A fourth objective of the present application is to provide a computer-readable storage medium.

[0010] A fifth object of the present application is to provide a computer program product.

[0011] To achieve the above-mentioned purpose, the first embodiment of the present application proposes a method for verifying a page fault exception caused by processor page table modification, comprising:

[0012] Obtaining a storage instruction of the processor to be verified, wherein the storage instruction is used to modify a page table of the processor to be verified;

[0013] Performing write tracking on the store instruction to determine the modification result of the page table;

[0014] Based on the store instruction, simulating the modification result of the page table to obtain a simulation result;

[0015] The modification result is compared with the simulation result to obtain a verification result.

[0016] To achieve the above-mentioned purpose, the second embodiment of the present application proposes a verification device for a page fault exception caused by a processor page table modification, comprising:

[0017] An acquisition module, used for acquiring a storage instruction of a processor to be verified, wherein the storage instruction is used for modifying a page table of the processor to be verified;

[0018] A write tracking module, used for performing write tracking on the store instruction to determine the modification result of the page table;

[0019] A simulation module, used for simulating the modification result of the page table based on the store instruction to obtain a simulation result;

[0020] The verification module is used to compare the modification result with the simulation result to obtain a verification result.

[0021] To achieve the above-mentioned purpose, the third aspect of the present application provides an electronic device, including: a processor, and a memory communicatively connected to the processor;

[0022] The memory stores computer-executable instructions;

[0023] The processor executes the computer execution instructions stored in the memory to implement a verification method for a page fault exception caused by processor page table modification proposed in the first aspect of the embodiment of the present application.

[0024] To achieve the above-mentioned purpose, the fourth aspect embodiment of the present application proposes a computer-readable storage medium, in which computer execution instructions are stored. When the computer execution instructions are executed by the processor, they are used to implement a verification method for page fault exception caused by processor page table modification proposed in the first aspect embodiment of the present application.

[0025] To achieve the above-mentioned purpose, the fifth aspect embodiment of the present application proposes a computer program product, including a computer program, which, when executed by a processor, implements a verification method for a page fault exception caused by processor page table modification proposed in the first aspect embodiment of the present application.

[0026] The present application provides a verification method and device for page fault exception caused by processor page table modification, which obtains the store instruction of the processor to be verified, wherein the store instruction is used to modify the page table of the processor to be verified; writes and tracks the store instruction to determine the modification result of the page table; simulates the modification result of the page table based on the store instruction to obtain the simulation result; compares the modification result with the simulation result to obtain the verification result. The method solves the bottleneck that the simulator cannot directly verify the behavior of the processor due to the lack of processor microstructure information in simulation verification, and can track the synchronization of the processor to the page table update, and realize the synchronization verification of the processor through the simulator.

[0027] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0029] Figure 1 A flowchart of a method for verifying a page fault exception caused by processor page table modification provided in an embodiment of the present application;

[0030] Figure 2 A flowchart of another verification method for a page fault exception caused by processor page table modification provided in an embodiment of the present application;

[0031] Figure 3 A schematic diagram of a process of a storage instruction provided in an embodiment of the present application;

[0032] Figure 4 A dirty bit display schematic diagram provided in an embodiment of the present application;

[0033] Figure 5 A dirty bit setting schematic diagram provided in an embodiment of the present application;

[0034] Figure 6 A dirty bit clearing schematic diagram provided in an embodiment of the present application;

[0035] Figure 7 A flowchart of another verification method for a page fault exception caused by processor page table modification provided in an embodiment of the present application;

[0036] Figure 8 A schematic diagram of the structure of a verification device for a page fault exception caused by processor page table modification provided in an embodiment of the present application. DETAILED DESCRIPTION

[0037] Embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application.

[0038] The following describes a method and device for verifying a page fault exception caused by processor page table modification according to an embodiment of the present application with reference to the accompanying drawings.

[0039] Figure 1 A flowchart of a method for verifying a page fault exception caused by processor page table modification provided in an embodiment of the present application.

[0040] Simulation verification includes verification of running specific applications and random verification. In simulation verification, the simulator gives the correct execution result. The simulation of the processor to be verified generates instruction submission, and the simulator also executes the same instruction submission. By comparing the execution result of the simulation verification of the processor to be verified with the execution result of the reference design given by the simulator, the correctness of the execution result of the processor to be verified is determined. The checker compares the execution results. The execution results include data, status, etc.

[0041] Modern high-performance processor cores all use aggressive out-of-order execution technology, including the use of store queues and store buffer technologies to cache submitted store instructions, allowing store instructions to exit the out-of-order scheduling queue and reorder buffer (ROB) as quickly as possible, and wait in the store buffer to be written to the cache (cache for short).

[0042] Page fault exception (Page Fault, also known as page fault interrupt) is not actually a real program "abnormality", but an intentional abnormality. It can be considered as an abnormality triggered by hardware and corrected by software logic. The processor introduces page fault exception (Page Fault) because the virtual memory introduced by the operating system kernel makes it impossible for the program to directly access the physical memory. Therefore, various situations need to be handled when accessing virtual memory. This processing process requires Page Fault to complete. When accessing virtual memory, there will be the following situations: (1) The accessed address is not in the virtual address space; (2) The accessed address is in the virtual address space, but its permissions are insufficient, such as W (write) in the R (readable) + X (executable) area, or X (execute) in the R (readable) + W (writable) area; (3) The accessed address has not yet been assigned a corresponding physical memory and has no corresponding mapping; (4) The physical memory corresponding to the accessed address is no longer in the memory; (5) The mapped physical page permissions are insufficient, etc. The processing of these situations is completed by the processor modifying the page table.

[0043] The processor page table is modified through the store instruction. In order to improve the execution efficiency, the processor will submit the store instruction in the store instruction queue, and then store the submitted store instruction in the store buffer. At this time, it has not been written to the cache. When the submitted store instruction is in the store instruction queue and the store buffer, the store queue and store buffer will store a part of the submitted store data, which is invisible to the page table modification. Only by synchronizing through the synchronization instruction to ensure that the data in the store queue and store buffer is written to the cache, the modification result of the store instruction to the page table is visible. For example, RISC-V (Reduced Instruction Set Computing-Five, the fifth generation of reduced instruction set) uses the virtual memory barrier (Fence Virtual Memory) instruction sfence.vma (sfence for short) to synchronize the page table updates.

[0044] Because the simulator is a behavioral simulation, it does not involve various queues, such as the StoreQueue queue for store instructions, the Store Buffer buffer for submitting store instructions, and other processor microarchitecture-level simulations. Therefore, the execution results of the simulator's store instructions are immediately visible to the page table. However, the Store Queue and StoreBuffer of the processor to be verified store some of the results of the Store, and these results are invisible to the page table modification. In fact, without the use of synchronization instructions, whether the processor's modification of the page table affects the address mapping is correct behavior. However, it will cause the simulator's simulation and the simulation of the processor to be verified to be unable to align the analysis of the behavior of the processor page table modification causing page fault exceptions, making it difficult to compare the results.

[0045] To address this problem, the present application provides a method for verifying a page fault exception caused by a processor page table modification, so as to implement verification of the processor behavior by a simulator, such as Figure 1 As shown, the verification method of the processor page table modification causing page fault exception includes the following steps:

[0046] Step 101, obtaining a store instruction of the processor to be verified, wherein the store instruction is used to modify a page table of the processor to be verified.

[0047] Optionally, a store instruction is a basic instruction in a computer instruction system, which is used to copy data from a storage location (such as a register) in the computer to a specified address in the memory; the processor to be verified simulates running an application or a randomly generated instruction sequence.

[0048] In the embodiment of the present application, the processor to be verified simulates and runs a store instruction, and modifies the page table through the store instruction.

[0049] Step 102, write tracking is performed on the store instruction to determine the modification result of the page table.

[0050] Optionally, the page table update status of the processor to be verified is tracked and synchronized through a write tracking mechanism, so that the modification result of the page table can be determined.

[0051] For example, by means of dirty page tracking, it is determined whether the store instruction is written into the cache, thereby implementing write tracking of the store instruction.

[0052] Optionally, whether the page table of the processor to be verified has been modified or the modification status is determined by write tracking, so that the page table modification result is visible and the page table modification result is obtained.

[0053] Step 103, based on the store instruction, simulate the modification result of the page table to obtain a simulation result.

[0054] It is understandable that each processor has a corresponding simulator that generates comparison results, running the same application or randomly generated instruction sequence as the processor to be verified. The simulator generally uses high-level languages ​​such as C to perform behavioral level simulation, does not involve the specific microarchitecture of the processor, directly calculates the execution result of the instruction, and gives the correct result of the instruction execution for comparison with the emulator.

[0055] Optionally, the same instruction as the store instruction is executed through a simulator to simulate the modification result of the store instruction on the page table of the processor to be verified, and obtain a simulation result.

[0056] It should be noted that the execution result of the store instruction implemented by the simulator makes the modification of the page table visible immediately, that is, the simulation result is visible immediately.

[0057] Step 104, comparing the modified result with the simulation result to obtain a verification result.

[0058] Optionally, the modification result and the simulation result may be compared through a checker to determine whether the modification result obtained through write tracing is consistent with the simulation result of the simulator, thereby obtaining a verification result.

[0059] The verification result can be normal or abnormal.

[0060] In this embodiment, by obtaining the store instruction of the processor to be verified, wherein the store instruction is used to modify the page table of the processor to be verified; writing tracking is performed on the store instruction to determine the modification result of the page table; based on the store instruction, the modification result of the page table is simulated to obtain a simulation result; the modification result and the simulation result are compared to obtain a verification result. This solves the bottleneck that the simulator cannot directly verify the behavior of the processor due to the lack of processor microstructure information in simulation verification, and can track the synchronization of the processor to the page table update, and realize the synchronization verification of the processor through the simulator.

[0061] This embodiment provides another verification method for a page fault exception caused by a processor page table modification. Figure 2 A flowchart of another method for verifying a page fault exception caused by processor page table modification provided in an embodiment of the present application.

[0062] like Figure 2 As shown, the verification method for the processor page table modification causing page fault exception may include the following steps:

[0063] Step 201, obtaining a store instruction of the processor to be verified, wherein the store instruction is used to modify a page table of the processor to be verified.

[0064] Optionally, a store instruction is a basic instruction in a computer instruction system, used to copy data from a storage location (such as a register) in the computer to a specified address in the memory.

[0065] In the embodiments of the present application, Figure 3 As shown, in the storage pipeline, the submitted storage instructions are stored in the storage instruction queue and / or the submitted storage instruction write buffer, and are not written to the cache memory. The modifications to the page table by the data stored in the storage instruction queue and the submitted storage instruction write buffer are invisible.

[0066] Optionally, the processor to be verified modifies the page table through a store instruction.

[0067] Step 202, execute a store instruction on the page table to determine the dirty bit corresponding to the page table; track the dirty bit to determine the modification result of the page table.

[0068] Optionally, when determining whether a page fault exception is legal, it is necessary to check whether the write to the page table has been synchronized by a synchronization instruction. The dirty bit can be used in the simulator to track the state of the page table, and the dirty bit can be checked when the simulator reads the page table to determine the state of the page table.

[0069] As an example, dirty bit tracking can be implemented by setting a dirty bit in the simulator's memory space.

[0070] In the embodiment of the present application, the dirty bit corresponds to a first dirty bit value and a second dirty bit value, which are used to distinguish the status of the dirty bit.

[0071] As an example, the first dirty bit value is 1, and the second dirty bit value is 0.

[0072] As a possible implementation, during initialization, all dirty bits are set to 0. The synchronization instruction clears all dirty bit states, that is, sets all dirty bits to 0.

[0073] Furthermore, the position of the dirty bit is determined with bytes as the granularity.

[0074] Taking a memory size of 128MB as an example, if the dirty bit is set with byte as the granularity, the size of the dirty bit required is 16MB, which puts a lot of storage pressure on the simulator.

[0075] In the embodiment of the present application, the tracking granularity of the dirty bit is reduced, and a coarse-grained approach is adopted to set a dirty bit at every preset number of byte positions.

[0076] As an example, the preset number may be 8, that is, a dirty bit is set for every 8 bytes to track the state of the page table. 8 bytes is also the maximum granularity of a store instruction, and the maximum granularity of a store instruction is generally a double word (StoreDoubleword).

[0077] like Figure 4 As shown, a dirty bit is set for every 8 bytes in the simulated memory. The dirty bit value is 0, which indicates the location in the page table where the modification is made before the synchronization instruction and is determined to take effect. The dirty bit is 1, which indicates the location in the page table that has been modified but has not yet been synchronized by the synchronization instruction, that is, the dirty location.

[0078] In other embodiments, it may also be set to a precise granularity or other granularity, for example, the preset number of bytes may be 2 bytes, 4 bytes, 16 bytes, etc.

[0079] It should be noted that the check is performed before the simulator sets a page fault exception.

[0080] Optionally, the location to which the store instruction is written is set to the first dirty bit value; when the store instruction is executed synchronously, the dirty bit location is set to the second dirty bit value.

[0081] See also Figure 5 , the simulator executes the store instruction and sets the dirty bit of the location written by the store instruction to 1, that is, the dirty bit value at the write location is set from the initialized 0 to 1.

[0082] Furthermore, when the simulator executes a synchronization instruction, all dirty bits are flushed and cleared, that is, the dirty bits are set to 0. Figure 6 , set all dirty bits to 0 to clear the dirty bits.

[0083] By using the dirty bit in the simulator, the state of the page table can be tracked, and the value of the dirty bit can reflect the synchronization status of the page table. Furthermore, when the simulator reads the page table, the dirty bit is checked and the state of the page table is determined according to the value of the dirty bit.

[0084] Step 203: Based on the store instruction, simulate the modification result of the page table to obtain a simulation result.

[0085] For step 203, reference may be made to the relevant description of the aforementioned embodiment, which will not be described in detail in this embodiment.

[0086] Step 204, comparing the modification result with the simulation result to obtain a verification result.

[0087] Optionally, the modification result and the simulation result may be compared through a checker to determine whether the modification result obtained through write tracing is consistent with the simulation result of the simulator, thereby obtaining a verification result.

[0088] The verification result can be normal or abnormal.

[0089] As a possible implementation method, the process of the processor to be verified implementing the modification result may be simulated for comparative verification.

[0090] Optionally, obtain a simulation result of the simulator executing a store instruction on the processor to be verified; compare the simulation result with the simulation result through a checker to obtain a verification result.

[0091] Among them, the simulator can use simulation tools such as Verilator and VCS to simulate the processor code.

[0092] In this embodiment, by obtaining the store instruction of the processor to be verified, wherein the store instruction is used to modify the page table of the processor to be verified; executing the store instruction on the page table to determine the dirty bit corresponding to the page table; tracking the dirty bit to determine the modification result of the page table; simulating the modification result of the page table based on the store instruction to obtain the simulation result; comparing the modification result with the simulation result to obtain the verification result. This solves the bottleneck that the simulator cannot directly verify the behavior of the processor due to the lack of processor microstructure information in simulation verification, and can track the synchronization of the processor to the page table update, and realize the synchronization verification of the processor through the simulator.

[0093] This embodiment provides another verification method for a page fault exception caused by a processor page table modification. Figure 7 A flowchart of another method for verifying a page fault exception caused by processor page table modification provided in an embodiment of the present application.

[0094] like Figure 7 As shown, the verification method for the processor page table modification causing page fault exception may include the following steps:

[0095] Step 701, obtaining a store instruction of the processor to be verified, wherein the store instruction is used to modify the page table of the processor to be verified.

[0096] For step 701, reference may be made to the relevant description of the aforementioned embodiment, which will not be described in detail in this embodiment.

[0097] Step 702, receiving the micro-architecture state of the processor to be verified, where the micro-architecture state is used to instruct the simulator to adjust the state; and determining the modification result of the page table based on the micro-architecture state.

[0098] Optionally, the processor to be verified transmits execution information (ie, micro-architecture state) to the simulator when executing a store instruction to write to the cache and executing a synchronization instruction.

[0099] It should be noted that when writing a page table entry without synchronization instructions, the latest value of the page table entry may exist in the storage instruction queue or the storage instruction write buffer, which may trigger a page fault interrupt when performing address conversion.

[0100] Optionally, according to the microstructure state, the simulator state is changed at the corresponding node; when the simulator state change is legal, the store instruction is executed.

[0101] In the embodiment of the present application, the simulator state is updated and a reminder is given according to the state of the processor to be verified. The simulator forcibly changes the simulator state at the corresponding node according to the incoming micro-architecture state. Further, the simulator checks whether the forced state change is legal, and executes the store instruction if it is legal.

[0102] Co-simulation is achieved by synchronizing the microarchitectural states of the processor to be verified and the simulator.

[0103] Step 703, based on the store instruction, simulate the modification result of the page table to obtain a simulation result.

[0104] It is understandable that each processor has a corresponding simulator that generates comparison results, running the same application or randomly generated instruction sequence as the processor to be verified. The simulator generally uses high-level languages ​​such as C to perform behavioral level simulation, does not involve the specific microarchitecture of the processor, directly calculates the execution result of the instruction, and gives the correct result of the instruction execution for comparison with the emulator.

[0105] Optionally, the simulator triggers a page fault interrupt according to a micro-structure state obtained by executing a store instruction on the processor to be verified, simulates the modification result of the page table, and obtains a simulation result.

[0106] It should be noted that the simulation results achieved through the simulator are immediately visible.

[0107] Step 704, comparing the modification result with the simulation result to obtain a verification result.

[0108] Optionally, the modification result and the simulation result may be compared through a checker to determine whether the modification result obtained through write tracing is consistent with the simulation result of the simulator, thereby obtaining a verification result.

[0109] The verification result can be normal or abnormal.

[0110] As a possible implementation method, the process of the processor to be verified implementing the modification result may be simulated for comparative verification.

[0111] Optionally, obtain a simulation result of the simulator executing a store instruction on the processor to be verified; compare the simulation result with the simulation result through a checker to obtain a verification result.

[0112] Among them, the simulator can use simulation tools such as Verilator and VCS to simulate the processor code.

[0113] The embodiment of the present application can also be applied to other situations where the processor to be verified cannot be aligned with the simulator. Co-simulation is achieved by synchronizing the microstructure states of the processor to be verified and the simulator. The processor microstructure state is transmitted to the simulator to synchronize the simulator and the processor.

[0114] For example, the processor verifies the storage instructions and peripheral interrupts in the peripheral space. Since the simulator cannot simulate the behavior of all external devices, the simulator cannot know the correct result of the storage instructions mapped to the external device address space. In this case, it is also impossible to align the analysis of the behavior of the processor to be verified and the simulator.

[0115] As an example, the store instruction includes a target store instruction of an external device of the processor to be verified. When the store instruction is received, the micro-structure state of the processor to be verified is received and synchronized; and the execution result of the target store instruction is copied.

[0116] In an embodiment of the present application, the microstructure state of the processor to be verified is passed to the simulator for synchronization, the memory-mapped peripheral address space is marked by the processor, and when a store instruction to the peripheral space is submitted, the simulator copies the execution result of the store instruction from the processor.

[0117] Furthermore, when the simulator and the processor to be verified need to be synchronized with respect to the peripheral interrupt, the interrupt information of the external device sent by the processor to be verified is received; and the interrupt of the simulator is triggered according to the interrupt information.

[0118] For example, the simulator does not know when the processor will trigger a peripheral interrupt. To solve this problem, when a peripheral interrupt is triggered, the processor sends the interrupt information of the external device and synchronizes it to the simulator. When the simulator receives the interrupt information, the same interrupt is also triggered in the simulator.

[0119] By passing the processor micro-architecture state to the simulator, the simulator and the processor are synchronized. The processor passes the micro-architecture state to the simulator, and the simulator checks the state sent by the processor and adjusts its own state. The execution results of the processor and the simulator are compared to achieve co-simulation of the processor and the simulator.

[0120] In this embodiment, by obtaining the storage instruction of the processor to be verified, wherein the storage instruction is used to modify the page table of the processor to be verified; receiving the microstructure state of the processor to be verified, the microstructure state is used to instruct the simulator to adjust the state; based on the microstructure state, the modification result of the page table is determined; based on the storage instruction, the modification result of the page table is simulated to obtain the simulation result; the modification result and the simulation result are compared to obtain the verification result. This solves the bottleneck that the simulator cannot directly verify the processor behavior due to the lack of processor microstructure information in simulation verification, and can track the synchronization of the processor to the page table update, and realize the synchronization verification of the processor through the simulator.

[0121] In order to implement the above embodiment, the present application also proposes a verification device for page fault exception caused by processor page table modification.

[0122] Figure 8 A schematic diagram of the structure of a verification device for a page fault exception caused by processor page table modification provided in an embodiment of the present application.

[0123] like Figure 8 As shown, the verification device 800 for page fault exception caused by processor page table modification includes: an acquisition module 801, a write tracking module 802, a simulation module 803 and a verification module 804.

[0124] An acquisition module 801 is used to acquire a storage instruction of a processor to be verified, wherein the storage instruction is used to modify a page table of the processor to be verified;

[0125] A write tracking module 802 is used to perform write tracking on the store instruction to determine the modification result of the page table;

[0126] The simulation module 803 is used to simulate the modification result of the page table based on the store instruction to obtain a simulation result;

[0127] The verification module 804 is used to compare the modification result with the simulation result to obtain a verification result.

[0128] Furthermore, in a possible implementation of the embodiment of the present application, the write tracking module 802 is used to:

[0129] Execute the store instruction on the page table to determine the dirty bit corresponding to the page table;

[0130] Track the dirty bit to determine the modification results of the page table.

[0131] The dirty bit corresponds to a first dirty bit value and a second dirty bit value, and the location written by the store instruction is set to the first dirty bit value;

[0132] When executing the store instruction synchronously, the dirty bit position is set to the second dirty bit value.

[0133] Determine the location of the dirty bit at byte granularity.

[0134] receiving a micro-architecture state of a processor to be verified, where the micro-architecture state is used to instruct the simulator to adjust the state;

[0135] Based on the micro-architecture state, the modification result of the page table is determined.

[0136] According to the microstructure state, change the simulator state at the corresponding node;

[0137] When the simulator state changes legally, execute the store instruction.

[0138] Furthermore, in a possible implementation of the embodiment of the present application, the verification module 804 is used to:

[0139] Obtain the simulation result of the simulator executing the storage instruction on the processor to be verified;

[0140] The simulation results are compared with the simulation results through the checker to obtain the verification results.

[0141] Furthermore, in a possible implementation of the embodiment of the present application, the count instruction is stored in a store count instruction queue and / or a submit store count instruction write buffer.

[0142] It should be noted that the above explanation of the embodiment of the verification method for page fault exception caused by processor page table modification is also applicable to the verification device for page fault exception caused by processor page table modification of this embodiment, and will not be repeated here.

[0143] In this embodiment, by obtaining the store instruction of the processor to be verified, wherein the store instruction is used to modify the page table of the processor to be verified; writing tracking is performed on the store instruction to determine the modification result of the page table; based on the store instruction, the modification result of the page table is simulated to obtain a simulation result; the modification result and the simulation result are compared to obtain a verification result. This solves the bottleneck that the simulator cannot directly verify the behavior of the processor due to the lack of processor microstructure information in simulation verification, and can track the synchronization of the processor to the page table update, and realize the synchronization verification of the processor through the simulator.

[0144] In order to implement the above-mentioned embodiments, the present application also proposes an electronic device, comprising: a processor, and a memory communicatively connected to the processor; the memory stores computer execution instructions; the processor executes the computer execution instructions stored in the memory to implement the verification method for page fault exception caused by processor page table modification provided in the above-mentioned embodiments.

[0145] In order to implement the above embodiments, the present application also proposes a computer-readable storage medium, which stores computer execution instructions. When the computer execution instructions are executed by the processor, they are used to implement the verification method of the page fault exception caused by the processor page table modification provided in the above embodiments.

[0146] In order to implement the above embodiments, the present application also proposes a computer program product, including a computer program, which, when executed by a processor, implements the verification method for page fault exception caused by processor page table modification provided in the above embodiments.

[0147] The collection, storage, use, processing, transmission, provision and disclosure of user personal information involved in this application are in compliance with relevant laws and regulations and do not violate public order and good morals.

[0148] It should be noted that personal information from users should be collected for legitimate and reasonable purposes and should not be shared or sold outside of these legitimate uses. In addition, such collection / sharing should be carried out after receiving the user's informed consent, including but not limited to notifying the user to read the user agreement / user notice and sign the agreement / authorization including authorization of relevant user information before the user uses the function. In addition, any necessary steps should be taken to protect and safeguard access to such personal information data and ensure that others who have access to personal information data comply with its privacy policy and procedures.

[0149] This application is expected to provide an implementation scheme for users to selectively block the use or access of personal information data. That is, this application is expected to provide hardware and / or software to prevent or block access to such personal information data. Once the personal information data is no longer needed, risks can be minimized by limiting data collection and deleting data. In addition, when applicable, personal identifiers are removed from such personal information to protect the privacy of users.

[0150] In the description of the aforementioned embodiments, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0151] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0152] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, fragment or portion of code comprising one or more executable instructions for implementing the steps of a custom logical function or process, and the scope of the preferred embodiments of the present application includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by technicians in the technical field to which the embodiments of the present application belong.

[0153] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as an ordered list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, device or apparatus and execute instructions), or in combination with these instruction execution systems, devices or apparatuses. For the purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in combination with these instruction execution systems, devices or apparatuses. More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection with one or more wires (electronic devices), a portable computer disk box (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), a fiber optic device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or processing in other suitable ways if necessary, and then stored in a computer memory.

[0154] It should be understood that the various parts of the present application can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0155] A person skilled in the art may understand that all or part of the steps in the method for implementing the above-mentioned embodiment may be completed by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, which, when executed, includes one or a combination of the steps of the method embodiment.

[0156] In addition, each functional unit in each embodiment of the present application may be integrated into a processing module, or each unit may exist physically separately, or two or more units may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0157] The storage medium mentioned above may be a read-only memory, a magnetic disk or an optical disk, etc. Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limiting the present application. A person of ordinary skill in the art may change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A method for verifying a page fault exception caused by processor page table modification, characterized in that: The following steps are involved: Obtaining a storage instruction of the processor to be verified, wherein the storage instruction is used to modify a page table of the processor to be verified; Performing write tracking on the store instruction to determine the modification result of the page table; Based on the store instruction, simulating the modification result of the page table to obtain a simulation result; The modification result is compared with the simulation result to obtain a verification result.

2. The method according to claim 1, characterized in that The step of writing and tracking the store instruction to determine the modification result of the page table includes: Executing the store instruction on the page table to determine a dirty bit corresponding to the page table; The dirty bit is tracked to determine the modification result of the page table.

3. The method according to claim 2, characterized in that The dirty bit corresponds to a first dirty bit value and a second dirty bit value, and executing the store instruction on the page table to determine the dirty bit corresponding to the page table includes: Setting the location written by the store instruction to the first dirty bit value; When executing the store instruction synchronously, the dirty bit position is set to the second dirty bit value.

4. The method according to claim 2, characterized in that: The method further comprises: The position of the dirty bit is determined with bytes as the granularity.

5. The method according to claim 2, characterized in that: The method further comprises: A dirty bit is set at every preset number of byte positions.

6. The method according to claim 1, characterized in that The step of writing and tracking the store instruction to determine the modification result of the page table includes: Receiving a microstructure state of the processor to be verified, wherein the microstructure state is used to instruct the simulator to adjust its state; Based on the micro-architecture state, a modification result of the page table is determined.

7. The method according to claim 6, characterized in that The method further comprises: According to the microstructure state, changing the simulator state at the corresponding node; When the simulator state change is legal, the store instruction is executed.

8. The method according to claim 1, characterized in that The storage instruction includes a target storage instruction of an external device of the processor to be verified, and the method further includes: Receiving and synchronizing the micro-architecture state of the processor to be verified; Copy the execution result of the target storage instruction.

9. The method according to claim 8, characterized in that The method further comprises: Receiving interrupt information of the external device sent by the processor to be verified; According to the interrupt information, an interrupt of the simulator is triggered.

10. The method according to claim 1, characterized in that The step of comparing the modification result with the simulation result to obtain a verification result includes: Obtaining a simulation result of the simulator executing the store instruction on the processor to be verified; The simulation result and the emulation result are compared by a checker to obtain the verification result.

11. The method according to claim 1, characterized in that: The store instruction is stored in a store instruction queue and / or a store instruction write buffer.

12. A verification device for page fault exception caused by processor page table modification, characterized in that: include: An acquisition module, used for acquiring a storage instruction of a processor to be verified, wherein the storage instruction is used for modifying a page table of the processor to be verified; A write tracking module, used for performing write tracking on the store instruction to determine the modification result of the page table; A simulation module, used for simulating the modification result of the page table based on the store instruction to obtain a simulation result; The verification module is used to compare the modification result with the simulation result to obtain a verification result.

13. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, which are used to implement the method according to any one of claims 1 to 11 when executed by a processor.

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