A PLL clock abnormality processing method and circuit structure

Abstract

The present application discloses a PLL clock abnormality processing method and circuit structure, wherein the PLL clock abnormality processing method includes: when the PLL clock is abnormal, determining whether the switching control circuit for switching the output clock is invalid; if not, switching the output clock to the Free‑running clock through the switching control circuit; if yes, determining whether the PLL clock is lost through a preset clock loss judgment circuit, and if the PLL clock is lost, generating a forced control signal, and controlling the PLL clock to be forced off according to the forced control signal, and controlling the Free‑running clock to be forced on according to the forced control signal, so as to switch the output clock to the Free‑running clock. When the PLL clock is abnormal, the present application can make different controls for different states of the switching control circuit, so as to realize normal switching of the output clock from the PLL clock to the Free‑running clock.

Description

Technical Field

[0001] The present application relates to the technical field of clock circuit design, and in particular to a PLL clock abnormality processing method and circuit structure. Background Art

[0002] PLL (Phase Locked Loop) is a commonly used module in chips, and its function is to provide high-speed clock for high-speed circuits.

[0003] During the operation of PLL, some abnormal conditions may occur, causing its function to fail. The abnormal conditions include incorrect configuration, reference clock loss, voltage abnormality, etc., and when PLL is abnormal, it usually outputs an unlock signal. The chip can sense the abnormality of PLL through the unlock signal and handle it. In the prior art in the related field, the unlock signal is usually used as the switching signal of CLKMUX to switch the PLL clock to a non-PLL clock when PLL loses lock.

[0004] However, the above solution requires that the PLL can still output the clock when it is abnormal, so it is impossible to implement output clock switching when the PLL clock is lost. Summary of the invention

[0005] In order to solve the above technical problems, an embodiment of the present application provides a PLL clock abnormality processing method and circuit structure.

[0006] According to one aspect of an embodiment of the present application, a PLL clock abnormality processing method is provided, comprising: when the PLL clock is abnormal, controlling whether a switching control circuit for switching the output clock fails to switch the output clock to a free-running clock, and judging whether the switching is successful; if yes, after the output clock is switched to a free-running clock by the switching control circuit, program control is terminated; if no, judging whether the PLL clock is lost by a preset clock loss judgment circuit, if the PLL clock is lost, generating a forced control signal, and controlling the PLL clock to be forced off according to the forced control signal, and controlling the free-running clock to be forced on according to the forced control signal, so as to switch the output clock to a free-running clock, and then terminating program control.

[0007] In some embodiments of the present application, based on the above technical solution, the switching control circuit for controlling the output clock switches the output clock to a free-running clock, and determines whether the switching is successful, including: obtaining the output value of the PLL clock; if the output value of the PLL clock is 0 or 1, it is determined that the switching of the switching control circuit has failed.

[0008] In some embodiments of the present application, based on the above technical solution, the output clock is switched to the Free-running clock through the switching control circuit, including: generating an unlocked flag signal when an abnormality occurs in the PLL clock, and inputting the unlocked flag signal, the PLL clock and the Free-running clock into the switching control circuit respectively; controlling the switching control circuit to generate a Free-running clock gating enable signal and a PLL clock gating enable signal respectively according to the unlocked flag signal, so as to switch the output clock to the Free-running clock according to the Free-running clock gating enable signal and the PLL clock gating enable signal.

[0009] In some embodiments of the present application, based on the above technical solution, the switching control circuit is controlled according to the lock-out flag signal to generate a free-running clock gating enable signal and a PLL clock gating enable signal respectively, including: controlling the switching control circuit to obtain a preset clock selection signal according to the lock-out flag signal, and encoding the clock selection signal into a one-hot code; inputting the one-hot code into a preset feedback logic circuit and a synchronization logic circuit in the switching control circuit to generate a free-running clock gating enable signal and a PLL clock gating enable signal.

[0010] In some embodiments of the present application, based on the above technical solution, before the unlocking flag signal, the PLL clock and the Free-running clock are respectively input into the switching control circuit, it also includes: controlling the PLL clock to perform delay processing according to a preset first time length, and the first time length is greater than the preset control time of the switching control circuit to execute the switching control.

[0011] In some embodiments of the present application, based on the above technical solution, the forced control signal includes a Free-running clock forced on signal and a PLL clock forced off signal; controlling the PLL clock to be forced off according to the forced control signal, and controlling the Free-running clock to be forced on according to the forced control signal, including: obtaining the Free-running clock gating enable signal and the PLL clock gating enable signal output by the switching control circuit; inputting the Free-running clock gating enable signal and the Free-running clock forced on signal into a preset gating enable OR gate, and inputting the output signal of the gating enable OR gate and the output of the Free-running clock into a preset Free-running clock gating to output a first control signal; inputting the PLL clock gating enable signal and the PLL clock into a preset PLL clock gating, and inputting the output signal of the PLL clock gating and the PLL clock forced off signal into a preset AND gate gating to output a second control signal; inputting the first control signal and the second control signal into a preset clock OR gate to output the Free-running clock as the output clock.

[0012] In some embodiments of the present application, based on the above technical solution, after determining that the PLL clock is lost, it also includes: controlling the clock loss judgment circuit to generate a clock loss flag signal according to the determination result of the PLL clock loss, and changing the clock loss judgment circuit from a pending state to a determination state; controlling the clock loss judgment circuit to send the clock loss flag signal to a preset update system, and receiving a clock loss flag clear signal fed back by the update system, so that the clock loss judgment circuit is restored to the pending state according to the clock loss flag clear signal.

[0013] In some embodiments of the present application, based on the above technical solution, the forced closure of the PLL clock according to the forced control signal and the forced opening of the Free-running clock according to the forced control signal also include: after the PLL clock is forced closure controlled by the forced control signal, the PLL clock is controlled to perform delay processing according to a preset second time length, and then the Free-running clock is forced to be opened according to the forced control signal.

[0014] According to another aspect of the embodiment of the present application, a PLL clock exception processing circuit is also provided, including: a switching control circuit, the input end of the switching control circuit is electrically connected to the output end of a preset PLL, and is used to switch the output clock to a free-running clock when the PLL clock is abnormal; a clock loss judgment circuit, the input end of the clock loss judgment circuit is electrically connected to the output end of the PLL and the output end of the switching control circuit, respectively, and is used to generate a forced control signal of the output clock when the switching control circuit fails, so as to control the PLL clock to be forced off according to the forced control signal, and to control the free-running clock to be forced on according to the forced control signal.

[0015] In some embodiments of the present application, based on the above technical solution, it also includes: PLL clock gating, the input end of the PLL clock gating is electrically connected to the output end of the PLL and the output end of the switching control circuit respectively; a gated enable OR gate, the input end of the gated enable OR gate is electrically connected to the output end of the switching control circuit and the output end of the clock loss judgment circuit respectively; Free-running clock gating, the input end of the Free-running clock gating is electrically connected to the output end of the gated enable OR gate and the output end of the switching control circuit respectively; AND gate gating, the input end of the AND gate gating is electrically connected to the output end of the PLL clock gating and the output end of the clock loss judgment circuit respectively; clock OR gate, the input end of the clock OR gate is electrically connected to the output end of the AND gate gating and the output end of the Free-running clock gating respectively.

[0016] In the technical solution of the embodiment of the present application, the above invention content can at least bring the following beneficial effects:

[0017] When the PLL clock is abnormal, it is determined whether the switching control circuit used to switch the output clock fails. If the switching control circuit does not fail, the output clock can be directly switched from the PLL clock to the Free-running clock through the switching control circuit. If the switching control circuit fails, it is further determined whether the PLL clock is lost. If the PLL clock is lost, a forced control signal is generated to control the PLL clock to be forced off according to the forced control signal, and to control the Free-running clock to be forced on according to the forced control signal, so as to realize the switching of the output clock from the PLL clock to the Free-running clock. Therefore, when processing the PLL clock abnormality, the PLL clock abnormality processing method of the present application can be compatible with the switching of the output clock from the PLL clock to the Free-running clock when the switching control circuit does not fail, and the switching of the output clock from the PLL clock to the Free-running clock when the PLL clock is lost. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present application, and together with the specification, are used to explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application, and for those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0019] Figure 1 The present invention is a schematic diagram of a circuit structure of a PLL clock abnormality processing circuit exemplified in the present application.

[0020] Figure 2 The following is a logic diagram of a method for handling PLL clock abnormality as exemplified in the present application.

[0021] Figure 3 The present invention is a flowchart of judging failure of a switching control circuit in a method for handling abnormal PLL clock.

[0022] Figure 4 The present invention is a flowchart of a method for handling a PLL clock abnormality, which is exemplified in the present application.

[0023] Figure 5 The present invention exemplifies an internal control flow chart of a switching control circuit in a PLL clock abnormality processing method.

[0024] Figure 6 The following is a flowchart of a method for handling a PLL clock abnormality, which is another exemplary embodiment of the present application.

[0025] Figure 7The present invention is a flowchart of controlling the state change of a clock loss judgment circuit in a PLL clock abnormality processing method exemplified in the present application. DETAILED DESCRIPTION

[0026] In order to make the purpose and implementation method of the present application clearer, the exemplary implementation method of the present application will be clearly and completely described below in conjunction with the drawings in the exemplary embodiments of the present application. Obviously, the described exemplary embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0027] It should be noted that the brief description of terms in this application is only for the convenience of understanding the embodiments described below, and is not intended to limit the embodiments of this application. Unless otherwise specified, these terms should be understood according to their common and usual meanings.

[0028] The terms "first", "second", "third", etc. in the specification and claims of this application and the above drawings are used to distinguish similar or similar objects or entities, and do not necessarily mean to limit a specific order or sequence, unless otherwise noted. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances.

[0029] The terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover but not exclude inclusion, for example, a product or device comprising a list of components is not necessarily limited to all the components expressly listed but may include other components not expressly listed or inherent to such product or device.

[0030] It should be noted that the "multiple" mentioned in this article refers to two or more. "And / or" describes the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the associated objects before and after are in an "or" relationship.

[0031] The present application provides a PLL clock abnormality processing method and circuit structure. Figure 1 FIG. 1 is a schematic diagram of a circuit structure of a PLL clock abnormality processing circuit exemplarily shown in the present application, such as Figure 1 As shown, the PLL clock abnormality processing circuit at least includes a switching control circuit and a clock loss judgment circuit.

[0032] An encoder, a feedback logic circuit and a synchronization logic circuit are arranged inside the switching control circuit.

[0033] Among them, the encoder is used to compile and convert signals (such as bit streams) or data into a signal form that can be used for communication, transmission and storage, and can convert analog signals into digital signals, or convert digital signals into analog signals, and convert one digital signal format into another digital signal format. For example, the encoder in this application is used to encode the clock selection signal of the input switching control circuit into a single hot code. Of course, other forms of format conversion can also be used, such as conventional binary code, decimal code, hexadecimal code, etc.

[0034] By way of example, a feedback logic circuit controls and adjusts circuit performance by directing part or all of the circuit output signal back to the circuit input and performing some form of comparison or combination with the original input signal.

[0035] A synchronous logic circuit refers to a circuit in which there is only one global clock signal in the entire design, and all memory elements (such as triggers, registers, etc.) are uniformly controlled by the clock signal. Only when the clock pulse arrives can the state of the memory element change, thereby changing the output of the circuit. Therefore, the design of the synchronous logic circuit in this application is based on the existence of the clock signal. The clock signal is a periodic signal, and a rising edge or a falling edge occurs in each cycle. The synchronous logic circuit can operate according to the edge of the clock signal, and the operation of each element in the circuit is triggered by the arrival of the clock edge. In this way, the signal transmission and processing between different elements can be synchronized, avoiding signal confusion and misalignment.

[0036] This application does not impose any specific restrictions on the specific circuit structures of the feedback logic circuit and the synchronization logic circuit, and any execution logic that can complete the above description is sufficient. In this application, through the cooperation of the feedback logic circuit and the synchronization logic circuit, a Free-running clock gating enable signal and a PLL clock gating enable signal are generated to control the preset Free-running clock gating and the preset PLL clock gating.

[0037] The switching control circuit of the present application is further disclosed. The switching control circuit may include at least four input terminals and four output terminals. In other embodiments of the present application, an exemplary description is given by a first switching control input terminal, a second switching control input terminal, a third switching control input terminal, a fourth switching control input terminal, a first switching control output terminal, a second switching control output terminal, a third switching control output terminal and a fourth switching control output terminal.

[0038] It should be noted that in order to more clearly understand and correspond to the wiring ports in the figure, the footer values ​​of the wiring terminals in the figure are used as a schematic of the output terminal or the preamble of the output terminal. For example, the footer of the wiring terminal in the figure is 1, and the corresponding output terminal or the preamble of the output terminal is "first"; for another example, the footer of the wiring terminal in the figure is 2, and the corresponding output terminal or the preamble of the output terminal is "second", and so on, and will not be repeated in other embodiments.

[0039] The first switch control input terminal is used to receive a clock selection signal sent by the system where the PLL is located.

[0040] The second switch control input terminal is connected to the PLL and is used to receive a clock signal generated by the PLL, that is, the PLL clock shown in the figure.

[0041] The third switch control input terminal is also connected to the PLL and is used to receive an unlock flag signal generated by the PLL.

[0042] The fourth switch control input terminal is used to receive a free-running clock sent by the system where the PLL is located, that is, a clock signal used for clock switching when the PLL clock is abnormal, that is, switching the PLL clock to a free-running clock.

[0043] In the PLL clock abnormality processing circuit of the present application, the output end of the switching control circuit is also provided with a PLL clock gating, which can be understood as a switching element of the clock signal. The PLL clock gating includes two input ends and one output end, and in other embodiments of the present application, an exemplary description is respectively made through a first PLL clock gating input end, a second PLL clock gating input end and a PLL clock gating output end.

[0044] Among them, the first PLL clock gating input terminal is connected to the PLL and is used to receive the PLL clock generated by the PLL; the second PLL clock gating input terminal is connected to the first switching control output terminal and is used to receive the PLL clock gating enable signal generated by the switching control circuit.

[0045] Specifically, the clock gating of the present application mainly turns off the clock signal on the logic gates that do not need to perform operations to reduce unnecessary power consumption and heat generation. At the same time, the clock signal is turned on on the logic gates that need to perform operations to ensure the normal operation of the system. The clock tree structure is used to control the switch state of the gating unit to achieve the stop and recovery of the local clock.

[0046] It should be noted that clock gating technology can significantly reduce the power consumption of the circuit, mainly including dynamic power consumption and leakage power consumption. Dynamic power consumption is generated by the flipping of the gated clock signal and is related to the clock activity factor and load capacitance. Leakage power consumption is mainly caused by transistor subthreshold leakage and gate oxide tunnel leakage. Through clock gating technology, it is possible to avoid switching the clock when the clock pulse is not needed, thereby reducing the power consumption of clock distribution and triggers, and even reducing the dynamic power consumption of logic gates.

[0047] In the PLL clock abnormality processing circuit of the present application, the clock loss judgment circuit is also arranged at the output end of the switching control circuit, and the clock loss judgment circuit includes at least four input ends and three output ends. In other embodiments of the present application, exemplary descriptions are respectively made through the first judgment circuit input end, the second judgment circuit input end, the third judgment circuit input end, the fourth judgment circuit input end, the first judgment circuit output end, the second judgment circuit output end and the third judgment circuit output end.

[0048] The first judgment circuit input terminal is connected to the second switching control output terminal of the switching control circuit, and is used to receive the free-running clock gating enable signal generated by the switching control circuit.

[0049] The second judgment circuit input terminal is connected to the third switch control output terminal of the switch control circuit, and is used to receive the PLL clock gating enable signal generated by the switch control circuit.

[0050] The input terminal of the third judgment circuit is connected to the PLL and is used to receive the unlock flag signal generated by the PLL.

[0051] The fourth judgment circuit input terminal is used to receive a clock loss flag clearing signal sent by the system where the PLL is located.

[0052] In addition, the first judgment circuit output terminal of the clock loss judgment circuit is used to send the clock loss flag signal to the system where the PLL is located, so that the system where the PLL is located feeds back a clock loss flag clear signal.

[0053] In the PLL clock abnormality processing circuit of the present application, a gated enable OR gate is provided at the output end of the clock loss judgment circuit, and two input ends of the gated enable OR gate are respectively connected to the fourth switching control output end and the second judgment circuit output end, for respectively obtaining the Free-running clock gating enable signal generated by the switching control circuit and the Free-running clock forced-on signal generated by the clock loss judgment circuit.

[0054] Further, a free-running clock gating is provided at the output of the gated enable or gate, which can be understood as a switching element of the clock signal in the same way as the PLL clock gating. The free-running clock gating includes two input terminals and one output terminal, and in other embodiments of the present application, an exemplary description is respectively given by a first free-running clock gating input terminal, a second free-running clock gating input terminal and a free-running clock gating output terminal.

[0055] Among them, the first Free-running clock gating input end is used to receive the Free-running clock sent by the system where the current PLL is located; the second Free-running clock gating input end is connected to the output end of the gated enable OR gate, and is used to receive the output signal of the gated enable OR gate.

[0056] In the PLL clock abnormality processing circuit of the present application, the output end of the clock loss judgment circuit is also provided with an AND gate, and the two input ends of the AND gate are respectively connected to the PLL clock gating output end and the third judgment circuit output end, for respectively obtaining the output signal of the PLL clock gating and the PLL clock forced off signal generated by the clock loss judgment circuit.

[0057] A clock OR gate is arranged at the output end of the AND gate control, and two input ends of the clock OR gate are respectively connected to the Free-running clock gate control output end and the AND gate control output end.

[0058] For illustrative purposes, the gated enable OR gate and the clock OR gate in the present application may be an OR gate in a digital circuit logic gate, or a combinational circuit capable of implementing an OR operation.

[0059] Similarly, the AND gate control in the present application can be an AND gate in a digital circuit logic gate, or a combinational circuit that can implement an AND operation.

[0060] The PLL clock gating and free-running clock gating in the above embodiment can be latch-type or reg-type clock gating, and the switch switching also depends on the input clock. Only one of the two gatings will be open and the other closed at the same time, and the clock switching is realized in conjunction with the clock OR gate. The gated enable OR gate is used to enable the switching control circuit and the clock loss judgment circuit to open the free-running clock gating, so as to realize the flexible adjustment of the PLL clock abnormal and non-abnormal situations.

[0061] Figure 2 The following is a logic diagram of a PLL clock abnormality processing method exemplified in the present application, such as Figure 2As shown, based on the above-mentioned PLL clock abnormality processing circuit, the PLL clock abnormality processing method provided by the present application may at least include the following steps:

[0062] When the PLL clock is abnormal, controlling the switching control circuit for switching the output clock to switch the output clock to the free-running clock, and determining whether the switching is successful;

[0063] If yes, the output clock is switched to the free-running clock by the switching control circuit, and the program control is terminated;

[0064] If not, the preset clock loss judgment circuit is used to determine whether the PLL clock is lost. If the PLL clock is lost, a forced control signal is generated, and the PLL clock is forced to be turned off according to the forced control signal, and the Free-running clock is forced to be turned on according to the forced control signal, so as to switch the output clock to the Free-running clock and end the program control.

[0065] For example, when the PLL clock is abnormal, first try to switch the output clock to the free-running clock;

[0066] If the switching is successful, that is, the switching control circuit is able to perform switching control in the case of clock abnormality to switch the output clock, and after successfully completing the switching of the output clock, the corresponding program control ends;

[0067] If the switching is unsuccessful, the clock signal loss judgment is performed through the clock loss judgment circuit, and when it is determined that the clock signal is lost, a forced control signal is generated to execute the corresponding clock gating switch control according to the forced control signal, thereby forcibly switching the output clock to the free-running clock, and after successfully completing the forced switching of the output clock, the corresponding program control is ended.

[0068] Specifically, PLL clock abnormalities may be caused by a variety of factors, such as incorrect PLL parameter settings, input clock source problems, unstable power supply voltage, external environment interference, hardware design problems, software configuration errors, etc. At the same time, the abnormal results caused by different factors are also different, for example, missing or incorrect timing constraints, PLL cannot be locked or the output frequency is incorrect, PLL output frequency does not meet expectations, hardware damage, etc.

[0069] Based on this, when the PLL clock is abnormal, the present application determines whether the switching control circuit fails, and makes further abnormal adjustment and control according to the determination result.

[0070] For example, if the judgment result is that the switching control circuit is not invalid, the output clock is directly switched through the switching control circuit, that is, the PLL (phase-locked loop) clock under normal circumstances is switched to a free-running clock, so that its output no longer maintains a phase-locked relationship with the reference clock, but runs freely, thereby solving the problem of abnormal output clock.

[0071] For another example, when the judgment result is that the switching control circuit fails, it indicates that the switching control circuit cannot perform the switching control of the output clock. The present application proposes a solution to this problem, and determines whether the PLL clock is lost by the clock loss judgment circuit in the above embodiment. For example, the clock loss judgment circuit detects the failure flag signal output by the PLL, and then determines whether the PLL clock is lost according to the detection result.

[0072] In other embodiments, whether the PLL clock is lost can also be judged by the output signal of the switching control circuit. In one case, the switching control circuit is partially abnormal, that is, it cannot perform control, but can input and output signals normally. In this case, whether the PLL clock is lost can be judged by the output signal of the switching control circuit. In another case, the switching control circuit is completely abnormal. To judge whether the PLL clock is lost, it can be judged by whether the clock loss judgment circuit receives the output signal of the switching control circuit. Of course, the above-mentioned judgment methods are only exemplary, and there is no specific limitation on which method is used in this application to judge whether the PLL clock is lost.

[0073] It should be noted that the method for determining whether the switching control circuit is invalid may also be to determine by a clock loss determination circuit, or may be based on other units or modules of the system where the PLL is located.

[0074] Further, if the PLL clock is lost, a forced control signal is generated, and the PLL clock is forced to be turned off according to the forced control signal, and the Free-running clock is forced to be turned on according to the forced control signal, so as to switch the output clock to the Free-running clock. Specifically, the PLL clock is lost, and the PLL clock cannot be switched by the switching control circuit. The clock loss judgment circuit generates a forced control signal for forcibly turning off the PLL clock and forcibly turning on the Free-running clock according to the above judgment result, thereby realizing the switching of the output clock.

[0075] Through the above implementation, when the PLL clock is abnormal, it is determined whether the switching control circuit for switching the output clock fails. If the switching control circuit does not fail, it indicates that the PLL clock is not lost, and the output clock can be directly switched from the PLL clock to the Free-running clock through the switching control circuit. In the case of failure of the switching control circuit, it is further determined whether the PLL clock is lost, and in the case of the PLL clock being lost, a forced control signal is generated to control the PLL clock to be forced off according to the forced control signal, and to control the Free-running clock to be forced on according to the forced control signal, so as to realize the switching of the output clock from the PLL clock to the Free-running clock. Therefore, when processing the PLL clock abnormality, the PLL clock abnormality processing method of the present application can be compatible with the switching of the output clock from the PLL clock to the Free-running clock when the PLL clock is not lost, and the switching of the output clock from the PLL clock to the Free-running clock when the PLL clock is lost.

[0076] In some embodiments of the present application, based on the above other embodiments, Figure 3 FIG. 1 is a flow chart of a method for judging failure of a switching control circuit in a method for handling abnormal PLL clock in the present application. Figure 3 As shown, when controlling the switching control circuit for switching the output clock to switch the output clock to the free-running clock and determining whether the switching is successful, at least the following execution steps may be included:

[0077] S300, obtaining the output value of the PLL clock;

[0078] S301: If the output value of the PLL clock is 0 or 1, it is determined that the switching control circuit fails to switch.

[0079] Specifically, in combination with the other implementations above, in one of the methods for determining whether the switching control circuit has failed, the judgment is made by obtaining the output value of the PLL clock, that is, determining whether the output clock of the PLL is fixed to output 0 or 1. If the output clock is fixed to 0 or 1, it is determined that the switching control circuit has failed. Otherwise, it is determined that the switching control circuit has not failed, that is, it is determined that the switching of the switching control circuit has failed.

[0080] Of course, the present application may also have other judgment methods for judging the failure of the switching control circuit, for example, judging based on the slow deviation of the frequency. In one case, the judgment may be made directly based on the deviation value; in another case, the judgment may be made based on the deviation speed in a specified time period.

[0081] At the same time, the setting order of multiple logic gates in the above embodiment is further exemplified. AND gate gating is mainly used to force the PLL clock to turn off when the PLL clock is fixed at 1. Since the PLL clock gating fails when the PLL clock is fixed at 1, the AND gate gating must be set after the PLL clock gating.

[0082] In some embodiments of the present application, based on the above other embodiments, Figure 4 This is a flowchart of a PLL clock abnormality processing method exemplified in the present application, such as Figure 4 As shown, when the output clock is switched to the free-running clock by switching the control circuit, at least the following execution steps may be included:

[0083] S400, generating an unlocked flag signal when an abnormality occurs in the PLL clock, and inputting the unlocked flag signal, the PLL clock and the Free-running clock into a switching control circuit respectively;

[0084] S401, controlling the switching control circuit to generate a free-running clock gating enable signal and a PLL clock gating enable signal respectively according to the unlock flag signal, so as to switch the output clock to a free-running clock according to the free-running clock gating enable signal and the PLL clock gating enable signal.

[0085] Specifically, when an abnormality occurs in the PLL clock, the PLL generates an unlocked flag signal. Under the premise that the switching control circuit is not invalid, the PLL clock can be switched to the free-running clock according to the input unlocked flag signal, the PLL clock and the free-running clock. At the same time, the clock loss judgment circuit can also make corresponding judgments according to the free-running clock gating enable signal and the PLL clock gating enable signal output by the switching control circuit, so as to cooperate with the switching control circuit to perform the switching of the output clock.

[0086] In some embodiments of the present application, based on the above other embodiments, Figure 5 FIG. 1 is an internal control flow chart of a switching control circuit in a PLL clock abnormality processing method exemplarily shown in the present application, such as Figure 5 As shown, when the switching control circuit is controlled to generate the free-running clock gating enable signal and the PLL clock gating enable signal respectively according to the unlock flag signal, at least the following execution steps may be included:

[0087] S500, controlling the switching control circuit to obtain a preset clock selection signal according to the unlock flag signal, and encoding the clock selection signal into a one-hot code;

[0088] S501 , inputting the one-hot code into a preset feedback logic circuit and a synchronization logic circuit in a switching control circuit to generate a free-running clock gating enable signal and a PLL clock gating enable signal.

[0089] To illustrate, a one-hot code is intuitively a code system in which there are as many bits as there are states, and only one bit is 1, while the others are all 0. For example, if there are three states A, B, and C, they can be encoded as [1,0,0], [0,1,0], and [0,0,1], respectively. This encoding method makes each state correspond to a unique vector, and only one element in the vector is 1, while the rest are 0.

[0090] Moreover, the present application can, based on the coding advantage of one-hot coding, only need to compare one bit when comparing the states of the switching control circuit, thereby simplifying the decoding logic. When the same number of states needs to be represented, although one-hot coding occupies more bits (i.e. consumes more triggers), the area occupied by these additional triggers can offset the area saved by the decoding circuit.

[0091] At the same time, if one-hot codes are used to represent states, no decoder is needed, because if the nth bit is 1, it means that the machine is currently in the nth state. And because the structure of one-hot codes is simple, the state switching speed of one-hot codes can be faster, because only one trigger value needs to be changed each time.

[0092] Therefore, inputting the encoded one-hot code into the preset feedback logic circuit and synchronization logic circuit in the switching control circuit can improve the response speed of generating the free-running clock gating enable signal and the PLL clock gating enable signal, thereby improving the control effect of the switching control circuit.

[0093] In some embodiments of the present application, based on the other embodiments mentioned above, before the unlocked flag signal, PLL clock and Free-running clock are respectively input into the switching control circuit, it also includes: controlling the PLL clock to perform delay processing according to a preset first time length, and the first time length is greater than the preset control time of the switching control circuit to execute the switching control.

[0094] Specifically, after delay processing based on the first time length, clock loss judgment can be performed based on the two enable signals. It should be noted that there are at least two reasons why the first time length is greater than the preset control time for the switching control circuit to perform switching control. The first is that it is necessary to ensure that the switching control circuit has enough time to generate a free-running clock enable signal and a PLL clock enable signal. The second is that it is necessary to ensure that the switching control circuit can complete the switching control of the output clock so as to reduce the probability of misjudgment when judging the effectiveness of the switching control circuit and when judging the PLL clock loss.

[0095] In some embodiments of the present application, based on the above other embodiments, Figure 6 FIG. 1 is another flowchart of a method for handling a PLL clock abnormality as shown in the present application. Figure 6 As shown, the forced control signal includes a free-running clock forced on signal and a PLL clock forced off signal; and when the PLL clock is forced off according to the forced control signal, and the free-running clock is forced on according to the forced control signal, at least the following execution steps may be included:

[0096] S600, obtaining a free-running clock gating enable signal and a PLL clock gating enable signal output by a switching control circuit;

[0097] S601, inputting a Free-running clock gating enable signal and a Free-running clock forced-on signal into a preset gated enable OR gate, and inputting an output signal of the gated enable OR gate and an output of the Free-running clock into a preset Free-running clock gating to output a first control signal;

[0098] S602, inputting the PLL clock gating enable signal and the PLL clock into a preset PLL clock gating, and inputting the output signal of the PLL clock gating and the PLL clock forced off signal into a preset AND gate gating to output a second control signal;

[0099] S603: Input the first control signal and the second control signal into a preset clock OR gate to output a free-running clock as an output clock.

[0100] Specifically, in the case where the switching control circuit fails, the clock loss judgment circuit obtains the Free-running clock gating enable signal and the PLL clock gating enable signal output by the switching control circuit. It should be noted that it can be detected whether the Free-running clock gating enable signal and the PLL clock gating enable signal are output by the switching control circuit, or it can be directly obtained by the Free-running clock gating enable signal and the PLL clock gating enable signal generated by the internal circuit of the switching control circuit according to the input signal. For example, when the switching control circuit is not failed, the Free-running clock gating enable signal and the PLL clock gating enable signal are 1; when the switching control circuit fails, the Free-running clock gating enable signal and the PLL clock gating enable signal are 0.

[0101] After obtaining the Free-running clock gating enable signal and the PLL clock gating enable signal output by the switching control circuit, the clock loss judgment circuit generates a Free-running clock forced on signal and a PLL clock forced off signal.

[0102] The free-running clock forced-on signal and the free-running clock gating enable signal are input into the gated enable OR gate for logic calculation, so as to input the obtained output signal into the free-running clock gating, and the free-running clock gating is combined with the input free-running clock to output the control signal of the free-running clock, that is, the first control signal, and the obtained first control signal is input into the clock OR gate.

[0103] The PLL clock gating generates a PLL clock shutdown signal based on the input PLL clock and the PLL clock gating enable signal output by the switching control circuit, and then inputs the PLL clock control signal and the PLL clock forced shutdown signal into the gate gating for logical calculation, so as to input the obtained output signal, that is, the second control signal, into the clock OR gate.

[0104] The OR operation is performed based on the clock OR gate to obtain the final output signal. Since the PLL clock corresponds to the shutdown signal and the free-running clock corresponds to the start signal, after the OR operation, the output clock is the free-running clock.

[0105] In some embodiments of the present application, based on the above other embodiments, Figure 7 FIG. 1 is a flow chart showing, by way of example, a method for handling a PLL clock abnormality in the present application for controlling a clock loss judgment circuit state change. Figure 7As shown, after determining that the PLL clock is lost, at least the following execution steps may be included:

[0106] S700, controlling the clock loss determination circuit to generate a clock loss flag signal according to the determination result of the PLL clock loss, and changing the clock loss determination circuit from a waiting state to a determination state;

[0107] S701, control the clock loss judgment circuit to send a clock loss flag signal to a preset update system, and receive a clock loss flag clear signal fed back by the update system, so that the clock loss judgment circuit is restored to a waiting state according to the clock loss flag clear signal.

[0108] Based on the above scheme, when the switching control circuit fails, the clock loss judgment circuit is changed from the waiting state to the judgment state; the clock loss judgment circuit controls the clock loss judgment circuit to generate the Free-running clock forced on signal and the PLL clock forced off signal according to the input loss-of-lock flag signal, the Free-running clock gating enable signal and the PLL clock gating enable signal.

[0109] The clock loss judgment circuit of the present application generates a clock loss flag signal after generating a free-running clock forced-on signal and a PLL clock forced-off signal, and sends the clock loss flag signal to the system where the PLL is located. Through the feedback mechanism preset by the system, after receiving the clock loss flag signal, the clock loss flag clear signal is sent to the clock loss judgment circuit, so that the clock loss judgment circuit is restored to the waiting state according to the clock loss flag clear signal, so as to perform the next judgment.

[0110] In some embodiments of the present application, based on the other embodiments mentioned above, the PLL clock is forced to be turned off according to a forced control signal, and the Free-running clock is forced to be turned on according to the forced control signal, and also includes: after the PLL clock is forced to be turned off according to the forced control signal, the PLL clock is controlled to perform delay processing according to a preset second time length, and then the Free-running clock is forced to be turned on according to the forced control signal.

[0111] Specifically, based on the Free-running clock forced-on signal and the PLL clock forced-off signal generated by the clock loss judgment circuit, the PLL clock needs to be forced-off first, and then the Free-running clock needs to be forced-on to achieve the switching of the output clock. At the same time, in order to avoid the burrs in the switching process, after the PLL clock is forced-off and before the Free-running clock is forced-on, a delay control of the second time length is performed to ensure that the Free-running clock is forced-on only after the PLL clock is completely turned off.

[0112] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

[0113] For the convenience of explanation, the above description has been made in conjunction with specific embodiments. However, the above exemplary discussion is not intended to be exhaustive or limit the embodiments to the specific forms disclosed above. Based on the above teachings, various modifications and variations can be obtained. The selection and description of the above embodiments are to better explain the principles and practical applications, so that those skilled in the art can better use the embodiments and various different variations of the embodiments suitable for specific use considerations.

Claims

1. A method for processing a PLL clock abnormality, characterized in that: include: When the PLL clock is abnormal, controlling the switching control circuit for switching the output clock to switch the output clock to the free-running clock, and determining whether the switching is successful; If yes, it is considered that the PLL clock is not lost, and after the output clock is switched to the free-running clock by the switching control circuit, the program control is terminated; If not, determine whether the PLL clock is lost through a preset clock loss judgment circuit. If the PLL clock is lost, generate a forced control signal based on the clock loss judgment circuit, and control the PLL clock to be forced off according to the forced control signal, and control the Free-running clock to be forced on according to the forced control signal, so as to switch the output clock to the Free-running clock, and then end the program control; The forced control signal includes a free-running clock forced on signal and a PLL clock forced off signal; controlling the PLL clock to be forced off according to the forced control signal, and controlling the free-running clock to be forced on according to the forced control signal, including: Obtaining a free-running clock gating enable signal and a PLL clock gating enable signal output by the switching control circuit; Input the Free-running clock gating enable signal and the Free-running clock forced-on signal into a preset gated enable OR gate, and input the output signal of the gated enable OR gate and the output of the Free-running clock into a preset Free-running clock gating to output a first control signal; Input the PLL clock gating enable signal and the PLL clock into a preset PLL clock gating, and input the output signal of the PLL clock gating and the PLL clock forced off signal into a preset AND gate gating to output a second control signal; The first control signal and the second control signal are input into a preset clock or gate to output a free-running clock as the output clock.

2. The PLL clock abnormality processing method according to claim 1, characterized in that: The control circuit for switching the output clock switches the output clock to a free-running clock, and determines whether the switching is successful, including: Obtaining an output value of the PLL clock; If the output value of the PLL clock is 0 or 1, it is determined that the switching control circuit fails to switch.

3. The PLL clock abnormality processing method according to claim 1, characterized in that: After the output clock is switched to the free-running clock by the switching control circuit, the program control is ended, including: When an abnormality occurs in the PLL clock, an unlock flag signal is generated, and the unlock flag signal, the PLL clock and the free-running clock are respectively input into the switching control circuit; The switching control circuit is controlled to generate a Free-running clock gating enable signal and a PLL clock gating enable signal respectively according to the unlock flag signal, so as to switch the output clock to a Free-running clock according to the Free-running clock gating enable signal and the PLL clock gating enable signal.

4. The PLL clock abnormality processing method according to claim 3, characterized in that: The step of controlling the switching control circuit to generate a free-running clock gating enable signal and a PLL clock gating enable signal respectively according to the unlock flag signal comprises: Controlling the switching control circuit to obtain a preset clock selection signal according to the unlock flag signal, and encoding the clock selection signal into a one-hot code; The one-hot code is input into a preset feedback logic circuit and a synchronization logic circuit in the switching control circuit to generate a free-running clock gating enable signal and a PLL clock gating enable signal.

5. The PLL clock abnormality processing method according to claim 3, characterized in that: Before the unlock flag signal, the PLL clock and the Free-running clock are input into the switching control circuit respectively, the method further comprises: The PLL clock is controlled to perform delay processing according to a preset first time length, and the first time length is greater than a preset control time for the switching control circuit to perform switching control.

6. The PLL clock abnormality processing method according to claim 1, characterized in that: After determining that the PLL clock is lost, the method further includes: Controlling the clock loss determination circuit to generate a clock loss flag signal according to the determination result of the PLL clock loss, and changing the clock loss determination circuit from a waiting state to a determination state; The clock loss judgment circuit is controlled to send the clock loss flag signal to a preset update system, and receive a clock loss flag clear signal fed back by the update system, so that the clock loss judgment circuit is restored to a waiting state according to the clock loss flag clear signal.

7. The PLL clock abnormality processing method according to any one of claims 1 to 6, characterized in that: The method of controlling the PLL clock to be forcibly turned off according to the forced control signal, and controlling the Free-running clock to be forcibly turned on according to the forced control signal, further includes: After the PLL clock is controlled to be forcibly turned off according to the forced control signal, the PLL clock is controlled to be delayed according to a preset second time length, and then the Free-running clock is controlled to be forcibly turned on according to the forced control signal.

8. A circuit structure, used to implement the PLL clock abnormality processing method according to any one of claims 1 to 7, characterized in that: include: A switching control circuit, wherein an input end of the switching control circuit is electrically connected to an output end of a preset PLL, and is used to switch the output clock to a free-running clock when the PLL clock is abnormal; A clock loss judgment circuit, wherein the input end of the clock loss judgment circuit is electrically connected to the output end of the PLL and the output end of the switching control circuit respectively, and is used for outputting a forced control signal of the output clock when the switching control circuit fails, so as to control the PLL clock to be forced off according to the forced control signal, and control the free-running clock to be forced on according to the forced control signal.

9. The circuit structure according to claim 8, characterized in that: Also includes: PLL clock gating, wherein the input end of the PLL clock gating is electrically connected to the output end of the PLL and the output end of the switching control circuit respectively; A gated enable OR gate, wherein the input end of the gated enable OR gate is electrically connected to the output end of the switching control circuit and the output end of the clock loss determination circuit respectively; Free-running clock gating, wherein the input end of the free-running clock gating is electrically connected to the output end of the gated enable OR gate and the output end of the switching control circuit respectively; AND gate gating, wherein the input end of the AND gate gating is electrically connected to the output end of the PLL clock gating and the output end of the clock loss judgment circuit respectively; A clock OR gate, wherein the input end of the clock OR gate is electrically connected to the output end of the AND gate control and the output end of the Free-running clock gate control respectively.

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