Method and system suitable for improving self-checking coverage rate of MCU (Microprogrammed Control Unit)

Abstract

The invention relates to the technical field of MCU self-checking, in particular to a method and system suitable for improving the MCU self-checking coverage rate, and the method comprises the following steps: evaluating the characteristics and functions of an MCU module, setting input and output vectors, and selecting a self-checking combination module; power-on reset is carried out, the BootROM jumps to a Flash self-checking program, and the self-checking combination module is tested; configuring an X-BAY, starting an input / output and combination test, configuring a loopback mode, and starting a loopback test; configuring an analog channel selection switch circuit, and starting a combined test of the ADC, the DAC and other analog channels; and obtaining a test result through the serial port. The module is flexible and reliable in self-inspection and high in coverage rate, does not need extra hardware support, can realize single-chip self-inspection, does not influence a peripheral circuit, integrates software and hardware, provides reliability and safety, and reduces the development difficulty of a user.

Description

Technical Field

[0001] The present invention relates to the technical field of MCU self-test, and in particular to a method and system suitable for improving the self-test coverage of an MCU. Background Art

[0002] With the rapid development of the intelligent era, MCU chips are increasingly used in consumer, industrial control, new energy vehicles and other fields. In view of the specific requirements for MCU chips in different application fields, chip safety self-test has become an indispensable and important indicator in industrial control and automotive applications. In view of the high requirements for product life cycle and complex application environment in these fields, chips may face the risk of overstress damage during use. Therefore, improving the chip's safety self-test capability is crucial to enhancing its risk controllability, thus establishing the chip safety self-test capability as one of the core indicators for evaluating the reliability and safety of MCU chips.

[0003] Analysis of existing technologies and problems faced. Currently, manufacturers mainly focus on functional self-test of key parts such as CPU, RAM, ROM, Flash, OTP, and digital and analog peripherals. This strategy stems from the characteristics of MCU products as general-purpose programmable devices, and their user application scenarios are highly diverse. In the process of implementing self-test, manufacturers need to weigh the possible impact of self-test signals on peripheral circuits and consider the way to generate self-test stimuli. For example, for common modules such as PWM and ADC, due to technical limitations, it is often difficult to achieve comprehensive on-chip loopback self-test, or only partial functional self-test can be performed.

[0004] Currently, most users in the MCU application field are more concerned about the implementation and effect of their own solutions. When considering chip safety self-test, they often face additional hardware configuration requirements, which undoubtedly increases the cost and design complexity of user solutions. In the program development stage, users usually focus more on the implementation of system-level applications, and the addition of MCU safety self-test programs may increase the difficulty of project development, and the coverage of self-test is difficult to be fully guaranteed. Summary of the invention

[0005] In view of the shortcomings of the prior art, the present invention discloses a method and system for improving the self-test coverage of MCU, which integrates digital and analog signal matrix switch controllers and uses CPU configuration registers to realize on-chip module signal interconnection self-test without affecting peripheral circuits. It aims to improve the self-test test coverage and accuracy, reduce board-level hardware configuration, and simplify software development.

[0006] The present invention is achieved through the following technical solutions: In a first aspect, the present invention provides a method for improving the self-test coverage of an MCU, comprising the following steps: Evaluate the features and functions of the MCU module, set the input and output vectors based on the self-test requirements, and select the self-test combination module; Enter the self-test phase, power-on reset is completed, BootROM jumps to the Flash self-test program, and tests each self-test combination module; Configure X-BAY, start input and output test and combination test of each group module, configure loopback mode, and start loopback test; Configure the external analog channel selection switch circuit to start the combined test between ADC and DAC and other analog channels; After the self-test is completed, the test results including PASS and FAIL are obtained through the serial port.

[0007] Furthermore, in the method, test and failure data are recorded, and then the test results are determined, including two results: PASS and FAIL.

[0008] Furthermore, in the method, the specific contents of testing each inspection combination module cover the following aspects: first, a detailed test of the CPU and CLA instructions is performed to ensure the correctness and stability of their functions; second, a strict test is performed on storage modules such as RAM, ROM and Flash to verify their read and write performance and data integrity; finally, tests of key modules such as TIMER, WATCHDOG and DMA are also required to ensure the accuracy of system time, the effectiveness of system monitoring and the efficiency of data transmission.

[0009] Furthermore, in the method, configuring X-BAY is specifically as follows: configuring the X-BAY environment: configuring the X-BAY system according to the standard to ensure that the components and interfaces are initialized correctly. GPI 0 test: starting the GPI 0 group input and output test to verify the data input and output functions, including signal integrity, transmission delay and error rate. GPI 0 and CLB, XINT test: jointly testing GPI 0, CLB and XINT to simulate application scenarios to verify the ability to work together. PWM and CAP, QEP, SDFM test: combining PWM with CAP, QEP, SDFM to verify the performance and collaborative working ability of PWM in complex control scenarios. SCIA / B and SPIA / B test: completing the SCIA / B and SPIA / B combined test to evaluate the system communication capability and verify compatibility, stability and data transmission efficiency.

[0010] Furthermore, in the method, a loopback mode is configured, and the communication interface is set to loopback mode during the system configuration phase to verify the interface function. Start multiple interface loopback tests FSI loopback test: Verify the data transmission and response capabilities of the FSI interface in a security scenario. CAN loopback test: Evaluate the communication performance and reliability of the CAN network. LIN loopback test: Verify the data transmission efficiency and stability of the LIN bus in low-cost, low-speed communication scenarios. I2C loopback test: Verify the communication quality of the I2C bus. PMBus loopback test: Evaluate the data transmission capability, command response speed and system monitoring function of PMBus in the power management system.

[0011] Furthermore, in the method, the combination test between the ADC (analog-to-digital converter) and the DAC (digital-to-analog converter) and other analog channels is started, and the specific steps include: accurately setting the IO configuration external analog channel selection switch circuit to ensure that the test path is accurate and reliable. Start the ADC and DAC combination test to verify the collaborative working ability and performance. Perform the ADC and LDO, REF combination test to evaluate the stability and accuracy. Perform the DAC and COMP, PGA combination test to verify the output signal performance and ensure that the analog signal link is complete and accurate.

[0012] In a second aspect, the present invention provides a system suitable for improving the self-check coverage of an MCU, wherein the system is used to implement the method suitable for improving the self-check coverage of an MCU as described in the first aspect, comprising: Core CPU, used to implement chip self-test system control and test data processing and judgment; Memory, including RAM and OTP, where RAM provides data cache space for CPU operation, and OTP area is the self-test program running area; Digital signal matrix switch controller, used to realize programmable matrix switch for interconnecting digital ports and port signals and internal digital signals; Analog signal matrix switch controller, used to realize programmable matrix switch for interconnecting analog ports and port signals and internal analog signals; Analog peripherals, including ADC, DAC, COMP, PGA, and LDO; Digital peripherals including PWM, CAP, QEP, GPIO, SCI, SPI, CAN, LIN, and I2C.

[0013] Furthermore, during the interconnection process of analog peripheral configuration, it is necessary to ensure that the following connections are accurate: the output of the DAC (digital-to-analog converter) should be directly connected to the input of the ADC (analog-to-digital converter); at the same time, the output of the DAC must also be connected to the input of the COMP (comparator); in addition, the output of the LDO (low-dropout linear regulator) should be accurately connected to the input of the ADC; finally, the output of the REF (reference voltage source) should also be connected to the input of the ADC to ensure stable system operation and accurate data conversion.

[0014] Furthermore, during the interconnection process of digital peripheral configuration, the following connections should be ensured to be correct: PWM output ports should be accurately connected to CAP input ports. PWM output ports should also be accurately connected to QEP input ports. Group A GPIO ports should be accurately connected to Group B GPIO ports. SCIA should be interconnected with SCIB. SPIA and SPIB should also be accurately interconnected.

[0015] Furthermore, the core CPU peripheral bus configuration register is used to enter the self-test mode, and then an operation is performed to disconnect the port from the peripheral board-level circuit. Next, the digital signal matrix switch register and the analog signal matrix switch controller are configured to achieve effective interconnection between the on-chip peripherals.

[0016] The beneficial effects of the present invention are: The module of the present invention has high self-checking flexibility, reliability and wide coverage. Its uniqueness lies in that it can realize the self-checking function of a single chip without relying on the support of additional peripheral hardware circuits, and this self-checking process does not affect the normal operation of the peripheral circuits at all. The present invention significantly enhances the reliability and security of the chip by realizing the high integration of on-chip software and hardware, and effectively reduces the development difficulty of users.

[0017] The present invention integrates a digital signal matrix switch controller and an analog signal matrix switch controller in a chip, and allows the signal interconnection self-check between the modules in the chip to be realized through the CPU configuration register. This process not only realizes the comprehensive detection of the modules in the chip, improves the coverage and detection accuracy of the self-test, but also greatly reduces the user's configuration requirements for board-level hardware, thereby further simplifying the complexity of software development. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0019] Figure 1 It is a method principle and step diagram suitable for improving the self-test coverage of MCU; Figure 2 It is a flowchart of a specific implementation process of the present invention; Figure 3 This is a principle block diagram of the AVP32F0049 series self-test system according to an embodiment of the present invention; Figure 4 It is a self-checking flow chart of an embodiment of the present invention; Figure 5 The invention is a system principle block diagram suitable for improving the self-check coverage of MCU. DETAILED DESCRIPTION

[0020] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0021] In one embodiment, if Figure 1 As shown, a method for improving the self-test coverage of an MCU is provided, comprising the following steps: Evaluate the features and functions of the MCU module, set the input and output vectors based on the self-test requirements, and select the self-test combination module; Enter the self-test phase, power-on reset is completed, BootROM jumps to the Flash self-test program, and tests each self-test combination module; Configure X-BAY, start input and output test and combination test of each group module, configure loopback mode, and start loopback test; Configure the external analog channel selection switch circuit to start the combined test between ADC and DAC and other analog channels; After the self-test is completed, the test results including PASS and FAIL are obtained through the serial port.

[0022] In one embodiment, the specific steps of configuring X-BAY are: Configure the X-BAY environment: First, the X-BAY system must be accurately configured according to established standards and specifications to ensure that all components and interfaces are in the correct initialization state.

[0023] Start GPI 0 packet input and output test: Then, start the packet input and output test for GPI 0. This step is to verify whether the data input and output functions of the GPI 0 module in packet mode are normal, including but not limited to the detection of key indicators such as signal integrity, transmission delay and error rate.

[0024] Perform combined testing of GPI 0, CLB and XINT: Further, perform joint testing of GPI 0, CLB (configurable logic block) and XINT (external interrupt). By simulating actual application scenarios, the collaborative working ability of the three is tested to ensure the accuracy and timeliness of data transmission and event response.

[0025] Implementation of combined testing of PWM with CAP, QEP, and SDFM: Next, the PWM (pulse width modulation) module is tested in combination with CAP (capture unit), QEP (quadrature coded pulse) and SDFM (specific functional module, the specific name may vary depending on the system). This link aims to verify the performance of the PWM module in complex control scenarios, especially when working with the above functional modules, whether it can accurately control the signal waveform, measure the speed or position, and achieve specific functional requirements.

[0026] Perform a combined test of SCIA / B and SPIA / B: Finally, complete the combined test of SCIA / B (Serial Communication Interface A / B) and SPIA / B (Serial Peripheral Interface A / B). This step is crucial to evaluating the communication capabilities of the system. By simulating data transmission under different communication protocols and rates, the compatibility, stability and data transmission efficiency between SCIA / B and SPIA / B modules are verified.

[0027] In one embodiment, during the system configuration phase, the relevant communication interface needs to be set to loopback mode. Loopback mode is a self-detection mechanism that allows data sent by an interface to be directly returned to the same interface, thereby verifying whether the sending and receiving functions of the interface are normal without relying on external devices.

[0028] As a preferred embodiment of this invention, the FSI, CAN, LIN, I2C and PMBus loopback tests are started as follows: FSI (Functional Safety Interface) loopback test: Start the loopback test of the FSI interface to verify its data transmission and response capabilities in safety function scenarios.

[0029] CAN (Controller Area Network) loopback test: Perform a loopback test on the CAN bus to ensure that the nodes in the CAN network can correctly send and receive data frames, thereby evaluating the communication performance and reliability of the CAN network.

[0030] LIN (Local Interconnect Network) loopback test: Perform LIN loopback test to verify the data transmission efficiency and stability of the LIN bus in low-cost, low-speed communication scenarios.

[0031] I2C (Inter-Integrated Circuit) loopback test: Start the loopback test of the I2C interface to ensure that the master device and the slave device can exchange data accurately and verify the communication quality of the I2C bus.

[0032] PMBus (Power Management Bus) loopback test: Perform a loopback test on the PMBus to evaluate its data transmission capability, command response speed, and accuracy of system monitoring functions in the power management system.

[0033] The above test steps are designed to comprehensively cover the key communication interfaces in the system. Through rigorous loopback testing, it is ensured that each interface can demonstrate good performance and stability when running independently, providing a solid guarantee for the overall operation of the system.

[0034] In one embodiment, referring to Figure 2 As shown, a specific implementation framework is provided, as follows: Evaluate MCU module features and functions, evaluate MCU module self-test, input and output vector requirements, select inter-module self-test combination objects, draw module self-test interconnection diagrams, write self-test programs (serial and parallel), debug and verify, and perform functional tests to ensure correct data interaction between modules.

[0035] In one embodiment, referring to Figure 4 As shown, when the system of this embodiment performs self-check, the details are as follows: 1. Record test and failure data, and then determine the test results, including PASS and FAIL.

[0036] 2. After the power-on reset is completed, BootROM completes the jump to the Flash self-test program.

[0037] 3. Perform CPU, CLA instruction tests, as well as RAM, ROM, and Flash tests.

[0038] 4. Perform TIMER, WATCHDOG and DMA tests.

[0039] 5. Configure X-BAY, start GPI 0 group input and output test, GPI 0 and CLB, XINT combination test, PWM and CAP, QEP, SDFM combination test, SCIA / B, SPIA / B combination test.

[0040] 6. Configure the loopback mode and start the FSI, CAN, LIN, I2C, and PMBus loopback tests.

[0041] 7. Configure the external analog channel selection switch circuit through IO to start the ADC and DAC combination test, the ADC and LDO, REF combination test, and the DAC and COMP, PGA combination test.

[0042] 8. After the self-test is completed, the test results are printed through the serial port.

[0043] 9. Finally, record the test results, including PASS and FAIL.

[0044] The overall introduction of the present invention is as follows: Hardware Function Test: The document first records multiple hardware function tests, including tests on key hardware components such as CPU, CLA instructions, RAM, ROM, Flash, etc. After each test, "FAIL" or "PASS" is marked to indicate the test result.

[0045] Self-test program execution: After the hardware function test, the self-test program starts to execute, including power-on reset, BootROM jump to Flash self-test program, TIMER, WATCHDOG, DMA test and other steps, ensuring the stability and reliability of the system.

[0046] Peripheral interface testing: The document records in detail the testing of various peripheral interfaces, such as configuring X-BAY, starting GPIO group input and output testing, PWM and CAP, QEP, SDFM combination testing, and SCIA / B, SPIA / B combination testing, etc., to verify that the peripheral interfaces function normally.

[0047] Loopback mode test: After configuring the loopback mode, the loopback test of FSI, CAN, LIN, I2C, PMBus and other interfaces is started to ensure the accuracy and stability of data transmission.

[0048] Analog channel and converter test: By configuring the external analog channel selection switch circuit through IO, combination tests such as ADC and DAC, ADC and LDO, REF, DAC and COMP, PGA, etc. were carried out to verify the analog signal processing capability.

[0049] Test result summary: The document summarizes the results of all tests at the end. Most tests passed and are marked as "PASS", but some tests failed and are marked as "FAIL". There are detailed records of the results of each test and records of failure data.

[0050] In one embodiment, referring to Figure 5 As shown, a system suitable for improving the self-check coverage of MCU is provided, including Core CPU, used to implement chip self-test system control and test data processing and judgment; Memory, including RAM and OTP, where RAM provides data cache space for CPU operation, and OTP area is the self-test program running area; Digital signal matrix switch controller, used to realize programmable matrix switch for interconnecting digital ports and port signals and internal digital signals; Analog signal matrix switch controller, used to realize programmable matrix switch for interconnecting analog ports and port signals and internal analog signals; Analog peripherals, including ADC, DAC, COMP, PGA, and LDO; Digital peripherals including PWM, CAP, QEP, GPIO, SCI, SPI, CAN, LIN, and I2C.

[0051] Reference Figure 3 As shown, in this embodiment, the self-test program of the AVP32F0049 series is applied. This program can make full use of the X-BAR function inside the chip to realize self-detection and testing of the digital module. It should be noted that for analog modules, this series of chips does not integrate a matrix switch controller, so other methods or means must be adopted in related tests or applications.

[0052] In one embodiment, a combined test between an ADC (analog-to-digital converter) and a DAC (digital-to-analog converter) and other analog channels is started, and the specific steps include: 1. Through IO (input and output) configuration, accurately set the selection switch circuit of the external analog channel to ensure the accuracy and reliability of the test path.

[0053] 2. Then, the combined test of ADC and DAC is started to verify their ability to work together and their performance during the data conversion process.

[0054] 3. At the same time, the combination test of ADC with LDO (low dropout linear regulator) and REF (reference voltage source) is carried out to evaluate the stability and accuracy of ADC under different power supply and reference voltage conditions.

[0055] 4. In addition, a combined test of DAC with COMP (comparator) and PGA (programmable gain amplifier) ​​is required to verify the performance changes of the DAC output signal after passing through these analog signal processing components to ensure the integrity and accuracy of the entire analog signal chain.

[0056] In one embodiment, during the interconnection process of the digital peripheral configuration, the following connections should be ensured to be correct: 1. The output port of PWM (Pulse Width Modulation) should be precisely connected to the input port of CAP (Capture).

[0057] 2. Similarly, the PWM output port must be accurately connected to the QEP (Quadrature Encoder Pulse) input port.

[0058] 3. For the connection of GPIO (general purpose input and output) ports, the GPIO input and output ports of group A must be accurately connected to the GPIO input and output ports of group B.

[0059] 4. In terms of serial communication, SCIA (serial communication interface A) should be interconnected with SCIB (serial communication interface B).

[0060] 5. In addition, SPIA (Serial Peripheral Interface A) and SPIB (Serial Peripheral Interface B) should also be interconnected accurately.

[0061] In this embodiment, in the configuration of the digital communication peripheral module, if only a single module is integrated, or specific digital peripherals such as CAN, LIN, etc., need to be configured by the driver networking to achieve the self-test purpose, we can take a built-in loop test mode as a solution to achieve the self-test function. This mode is designed to ensure that the module can independently complete the function verification and status check without relying on external components.

[0062] In this embodiment, when performing self-test, the number of channels of the matrix switch should be carefully considered for the selection of serial and parallel modes. By cleverly combining the advantages of serial and parallel modes, we can achieve the best balance between self-test efficiency and hardware resource utilization, thereby ensuring that the self-test process is both efficient and economical.

[0063] In summary, the module of the present invention has high self-test flexibility, reliability and wide coverage. Its uniqueness lies in that it can realize the single-chip self-test function without relying on additional peripheral hardware circuit support, and this self-test process does not affect the normal operation of the peripheral circuit at all. By realizing the high integration of on-chip software and hardware, the present invention significantly enhances the reliability and security of the chip and effectively reduces the development difficulty of users.

[0064] The present invention integrates a digital signal matrix switch controller and an analog signal matrix switch controller in a chip, and allows the signal interconnection self-check between the modules in the chip to be realized through the CPU configuration register. This process not only realizes the comprehensive detection of the modules in the chip, improves the coverage and detection accuracy of the self-test, but also greatly reduces the user's configuration requirements for board-level hardware, thereby further simplifying the complexity of software development.

[0065] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for improving MCU self-test coverage, It is characterized in that The following steps are involved: Evaluate the features and functions of the MCU module, set the input and output vectors based on the self-test requirements, and select the self-test combination module; Enter the self-test phase, power-on reset is completed, BootROM jumps to the Flash self-test program, and tests each self-test combination module; Configure X-BAY, start input and output test and combination test of each group module, configure loopback mode, and start loopback test; Configure the external analog channel selection switch circuit to start the combined test between ADC and DAC and other analog channels; After the self-test is completed, the test results including PASS and FAIL are obtained through the serial port.

2. A method for improving MCU self-test coverage according to claim 1, It is characterized in that In the method, test and failure data are recorded, and then the test results are determined.

3. A method for improving MCU self-test coverage according to claim 1, It is characterized in that In the method, the testing of each inspection combination module specifically includes performing CPU and CLA instruction testing, performing RAM, ROM and Flash testing, and performing TIMER, WATCHDOG and DMA testing.

4. A method for improving MCU self-test coverage according to claim 1, It is characterized in that In the method, X-BAY is configured, GPI 0 group input and output test is started, GPI 0 is tested in combination with CLB and XINT, PWM is tested in combination with CAP, QEP and SDFM, and SCIA / B is tested in combination with SPIA / B.

5. A method for improving MCU self-test coverage according to claim 1, It is characterized in that In the method, the loopback mode is configured and the FSI, CAN, LIN, I2C and PMBus loopback tests are started.

6. A method for improving MCU self-test coverage according to claim 1, It is characterized in that In the method, starting the combined test between ADC and DAC and with other analog channels specifically includes configuring the external analog channel selection switch circuit through IO, starting the combined test of ADC and DAC, the combined test of ADC, LDO and REF, and the combined test of DAC, COMP and PGA.

7. A system for improving MCU self-test coverage, the system being used to implement the method for improving MCU self-test coverage as claimed in any one of claims 1 to 6, It is characterized in that include Core CPU, used to implement chip self-test system control and test data processing and judgment; Memory, including RAM and OTP, where RAM provides data cache space for CPU operation, and OTP area is the self-test program running area; Digital signal matrix switch controller, used to realize programmable matrix switch for interconnecting digital ports and port signals and internal digital signals; Analog signal matrix switch controller, used to realize programmable matrix switch for interconnecting analog ports and port signals and internal analog signals; Analog peripherals, including ADC, DAC, COMP, PGA, and LDO; Digital peripherals including PWM, CAP, QEP, GPIO, SCI, SPI, CAN, LIN, and I2C.

8. A system for improving MCU self-test coverage according to claim 7, It is characterized in that When configuring the analog peripheral interconnection, the DAC output is connected to the ADC input, the DAC output is connected to the COMP input, the LDO output is connected to the ADC input, and the REF output is connected to the ADC input.

9. A system for improving MCU self-test coverage according to claim 7, It is characterized in that When interconnecting digital peripheral configurations, PWM outputs are connected to CAP inputs, PWM outputs are connected to QEP inputs, group A GPIO inputs and outputs are connected to group B GPIO inputs and outputs, SCIA is interconnected with SCIB, and SPIA is interconnected with SPIB.

10. A system for improving MCU self-test coverage according to claim 7, It is characterized in that Entering the self-test mode through the core CPU peripheral bus configuration register disconnects the port from the peripheral board-level circuit, configures the digital signal matrix switch register and the analog signal matrix switch controller, and realizes the interconnection of on-chip peripherals.

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