A monitoring filter

Abstract

The present invention provides a monitoring filter, which divides the cache address used to represent cache line retrieval information into multiple segments, and sets segment connection indications between adjacent segments. Therefore, when performing cache query, the address is segmented. When the segmented addresses are connected, it is considered that the cache line may have been cached by the current processor. In order to maintain cache consistency, it is necessary to access the cache of the processor. In the prior art, most of the retrieval is carried out by fully expanding the address after segmentation, which occupies a large space. The present invention groups the segments on the basis of segmentation, so the method of the present invention can quickly hit the cache address, reduce storage space, reduce the error rate, and improve retrieval efficiency.

Description

Technical Field

[0001] The invention belongs to the field of processors, and in particular relates to a monitoring filter. Background Art

[0002] In order to ensure that the data in the local cache of all processors or bus masters in the shared memory area is consistent, modern heterogeneous multi-core systems implement cache consistency by sending snoop requests to all processors to check the existence of data in the cache. After receiving the snoop request, the processor retrieves its own cache tag and takes appropriate actions. Since cache retrieval caused by snoop requests usually misses, in order to reduce the power consumption caused by unnecessary cache retrieval, a snoop filter is introduced for the processor. By maintaining the shared cache address information of the processor, it provides the current hit / miss information for the address. If it hits, it will enter the processor for search, and if it misses, it will immediately return to the miss state, filtering out unnecessary snoop requests at a low cost. However, considering the hardware overhead, the snoop filter cannot accurately indicate the existence status of all caches in the processor. If the request from the hit signal eventually leads to a cache miss in the retrieval, the hit signal is called a false positive signal, and the proportion of false positive signals in all hit signals is called the false positive rate. Therefore, designing an efficient snoop filter requires a trade-off between the false positive rate and the hardware overhead. Summary of the invention

[0003] The main problem solved by the present invention is how to reduce the misjudgment rate of a monitoring filter without increasing hardware overhead, and provides a monitoring filter.

[0004] In order to solve the above technical problems, the technical solution adopted is:

[0005] A monitoring filter divides a cache address into two parts according to the length of a cache line in a multi-core system. The address value within the cache line is used to represent the offset information within the cache line, and the address value outside the cache line is used to represent the cache line retrieval information. The cache address used to represent the cache line retrieval information is divided into multiple segments, and each of the divided segment cache addresses is respectively corresponded to a corresponding segment register. A segment connection indicator is provided between adjacent segment registers, and the segment connection indicator is used to indicate the connection status of a previous segment cache address connected to the segment connection indicator and a subsequent segment cache address.

[0006] Furthermore, the segment connection indicator is a multi-bit register, and the number of bits of the multi-bit register depends on the number of specific address values ​​that may be represented by the cache address in the subsequent segment register connected to the segment connection indicator. Each specific value of the cache address corresponds to one bit in the multi-bit register. When a bit in the multi-bit register is 1, it indicates that the subsequent cache address corresponding to the bit is connected to the previous cache address connected to the segment connection indicator.

[0007] Furthermore, the segment register is also configured with a counter, which is used to increment the counter when each segment cache address corresponds to a corresponding segment register, and decrement the counter when the cache is evicted.

[0008] Furthermore, each segment of cache addresses is divided into multiple groups, and each group of cache addresses is equipped with a group connection indicator, which is used to indicate the connection status between the current group of cache addresses and the next group of cache addresses.

[0009] Further, the group connection indicator refers to using a plurality of multi-bit registers, a plurality of which correspond to the number of possible multiple specific address values ​​of the current group cache address, listing all possible cache address values ​​of the current group, and assigning serial numbers to all possible cache address values ​​of the current group, then the nth multi-bit register of the current group corresponds to the cache address value corresponding to the nth serial number, and using the plurality of multi-bit registers to respectively represent the connection relationship of the subsequent group of cache addresses that are connected to the group connection indicator respectively after the multiple values ​​of the group are respectively taken;

[0010] The number of bits of the multi-bit register depends on the number of possible various group cache address values ​​of the subsequent group cache address connected to the current group. All possible cache address values ​​of the subsequent group cache address that are connected to the current group are listed, and a cache address value is corresponded to each bit of the multi-bit register in advance. When the current group has a connection relationship with a cache address of the subsequent group, the corresponding bit corresponding to the cache address in the multi-bit register with the serial number corresponding to the specific address value of the current group in the group connection indicator of the current group is 1. If multiple bits in the multi-bit register are 1, it means that the current group cache address has a connection relationship with the subsequent group cache addresses corresponding to multiple corresponding bits 1 in the multi-bit register.

[0011] Furthermore, each group of cache addresses is classified, and a numerical value is assigned to each class, and the numerical value is used to represent several cache addresses of the corresponding class.

[0012] Furthermore, each group of cache addresses is divided into two categories according to the preset binary specific value of the group cache address, and a group of cache addresses is assigned a value of 0 or 1 according to the divided class. A group of cache addresses is represented by a value of 0 or 1, and a segment of cache addresses is represented by the value of the class corresponding to each group and the group connection indicator equipped with each group.

[0013] Furthermore, a segment of cache addresses is evenly divided into three groups, each group of cache addresses is divided into two categories according to a preset group cache address binary specific value, and a group of cache addresses is assigned a value of 0 or 1 according to the category divided by each group of cache address binary specific value. The values ​​0 or 1 represent several possible cache address values ​​of a group of cache addresses, and each group is equipped with a group connection indicator.

[0014] Furthermore, the group connection indicator is 4 4-bit registers, 4 of the 4 4-bit registers represent the number of cache address values ​​that may be represented by the class into which the group of cache addresses is divided, and the various possible cache address values ​​corresponding to the numerical values ​​0 or 1 assigned to the current classification are listed and a serial number is given. The nth 4-bit register represents the nth cache address value corresponding to the numerical value of the current group classification, and each bit in the 4-bit register corresponds to the connection relationship between the group cache address of the next group connected to the current group, and the corresponding bit with a connection relationship is 1.

[0015] By adopting the above technical solution, the present invention has the following beneficial effects:

[0016] The present invention provides a monitoring filter, which divides the cache address used to represent cache line retrieval information into multiple segments, and sets segment connection indicators between adjacent segments. Therefore, when performing a cache query, the address is segmented. When the segmented addresses are all connected, it is considered that the cache line may have been cached by the current processor. In order to maintain cache consistency, it is necessary to access the cache of the processor. In the prior art, most of the retrieval methods after segmentation are fully expanded, which occupies a large space. The present invention groups the segments on the basis of segmentation, so the method of the present invention can quickly hit the cache address, reduce storage space, reduce the error rate, and improve retrieval efficiency.

[0017] The present invention groups cache addresses within a segment, classifies each group, replaces the expanded address with a value of 0 or 1, and implements address specific value retrieval by group connection indication. Compared with fully expanding the address within the segment, the address storage space is reduced by about 30%. At the same time, the use of segment connection indication and group connection indication can minimize the occurrence of multiple segments or multiple groups hitting at the same time, and the misjudgment rate caused by permutations and combinations. In the prior art, segmentation and then refinement of connection indication will occupy a large storage space. The present invention uses group connection indication to retrieve specific address values. For a scenario where there are 3 segments with a total of 27 bits of address, if only segment connection indication is used, there will be a maximum of 8 (2 3 ) hit situations, that is, the worst case has a 75% misjudgment rate; after adding the group connection indication, even if there are 8 hit situations between segments, they will be corrected by the group connection indication. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 A system architecture for a coherent bus with snoop filters;

[0019] Figure 2 FIG. 4 is a block diagram of a monitoring filter according to the present invention. DETAILED DESCRIPTION

[0020] The technical solution of the present invention will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0021] Figure 1 and Figure 2 The specific embodiment of a snoop filter of the present invention is shown. The snoop filter in this embodiment relies on a consistency bus system, and on the basis of the original snoop filter (on the basis of the JETTY type and Stream Register type snoop filter), improves the retrieval method of the cache address directory, reduces hardware overhead, and reduces the false positive hit ratio. Figure 1 As shown, in the snoop filter of this embodiment, when processor 0 initiates snooping from the snoop request channel, the snoop request is forwarded to processor 1 and processor 2 at the same time through the consistency bus. The snoop enters the snoop filter from the snooped request channel, and after the search, if it is confirmed to be a hit, it is sent to the cache controller of the processor for cache search, and a response and data are returned, and a miss signal is returned if it is a miss.

[0022] The monitoring filter in this embodiment divides the cache address into two parts according to the length of the cache line in the multi-core system. The address value within the cache line is used to represent the offset information within the cache line, and the address value outside the cache line is used to represent the cache line retrieval information. The cache address used to represent the cache line retrieval information is divided into multiple segments, and each segment of the divided cache address corresponds to a corresponding segment register. A segment connection indicator is set between adjacent segment registers, and the segment connection indicator is used to indicate the connection status of the previous segment cache address connected to the segment connection indicator and the next segment cache address. When performing a cache query, when the multiple segments corresponding to the query address are all connected, it can be regarded that the cache line may have been cached by the current processor. In order to maintain cache consistency, it is necessary to go to the cache of the processor for access. This embodiment divides the cache address used to represent cache line retrieval information into multiple segments, and sets segment connection indications between adjacent segments, so that the specific value of the next segment can be quickly found out according to the segment connection indication. Therefore, when performing address retrieval, the address is divided, and only the address of the first segment needs to be retrieved. Through the segment connection indication, the addresses of the following segments can be quickly and accurately found out. Compared with the prior art, most of the retrieval is carried out by fully expanding the address after segmentation, which occupies a large space. The method of the present invention can quickly hit the cache address, reduce storage space, reduce the error rate, and improve retrieval efficiency.

[0023] In this embodiment, the segment connection indicator is a multi-bit register. The number of bits of the multi-bit register depends on the number of specific address values ​​that may be represented by the cache address in the next segment register connected to the segment connection indicator. Each cache address specific value corresponds to one bit in the multi-bit register. When a bit in the multi-bit register is 1, it means that the next cache address corresponding to the bit is connected to the previous cache address connected to the segment connection indicator. When each segment has m bits, the number of specific cache address values ​​when the address is fully expanded is 2. m , then the number of bits of the multi-bit register is 2 m , if a bit in the multi-bit register is 1, it means that the specific cache address value corresponding to the bit in the next cache address is connected to the cache address of the previous segment. If multiple bits are 1, it means that the cache address values ​​corresponding to multiple corresponding bits in the next cache address are respectively connected to the cache address of the previous segment. Therefore, by using the segment connection indication, the specific value of the next segment that may be connected can be quickly found. When the specific address values ​​of all segments are found, it is considered that the cache line may have been cached. In order to maintain cache consistency, it is necessary to go to the cache of the processor for access. Therefore, using this method can quickly hit the cache address and reduce storage space.

[0024] In this embodiment, for a 32-bit cache address and a 32-byte cache line length, if the cache address is divided into two parts, address [4:0] is the cache line offset information, and address [31:5] is the cache line retrieval information. The cache line retrieval information is divided into three segments according to [31:23], [22:14] and [13:5], each with 9 bits of address information. The cache address consists of three segments of registers (each segment represents a 9-bit address value), and segment connection indicators are set between segments. The segment connection indicator consists of 2 9 Therefore, when an address is retrieved after receiving a snoop request on the consistency bus, the address is segmented. When multiple segments corresponding to the retrieved address are connected, it can be considered that the cache line may have been cached by the current processor.

[0025] In this embodiment, Figure 2 As shown, the segment register is also configured with a counter for incrementing the counter when the cache addresses correspond to the corresponding segment registers, and decrementing the counter when the cache is evicted. In the traditional filter, if the cache address is divided into 3 segments, each with 9 bits, the filter records the binary addresses 111111111_1111111111_111111111, 111111111_0000000000_111111111, 111111111_111111111_0000000000, 111111111_0000000000 _000000000 are all present in the cache, that is, the segment connection indication indicates that the first segment 111111111 is connected to the second segment 111111111, 000000000, and the second segment 111111111, 000000000 is connected to the third segment 111111111, 000000000, indicating four connection situations, that is, there are four cache line hit situations. When any two cache lines are evicted, if the segment connection indication is not processed, the deterioration of the permutation and combination mentioned at the beginning will occur. There are four possible situations. In fact, since two cache lines are evicted, there are only two cache lines, so there are only two correct hits. The misjudgment rate has deteriorated from 0% at the beginning to 50%. With continuous use, it will continue to accumulate. When the cache line is evicted, that is, this line is no longer hit, the segment tag cannot be cleared, and the misjudgment rate will even increase. Therefore, using a counter can effectively prevent the filter from deteriorating. A counter is provided for each segment register, and when it is detected that the counter is 0, the segment connection indicator pointing to the segment is automatically cleared.

[0026] Although the segment connection indicator is set in this embodiment, the hit rate is improved to a certain extent and the misjudgment rate is reduced. However, since the multi-bit register used by the segment connection indicator has a large number of bits, taking three segments, each with 9 bits, as an example, the number of multi-bit registers used by the segment connection indicator is 2. 9= 512 bits. Even if only 1 bit is used to indicate whether the connection is established, 512*2 = 1024 bits of registers are required. Therefore, further simplification is required.

[0027] In this embodiment, each cache address segment is divided into multiple groups, and each cache address segment is equipped with a group connection indicator, which is used to indicate the connection status between the current cache address segment and the next cache address segment. Although segmented, each segment is still relatively long, so each segment continues to be grouped. When searching, only the cache address of the first group needs to be retrieved, and then the addresses of other groups can be quickly found through the group connection indicator.

[0028] In this embodiment, the group connection indicator refers to using a plurality of multi-bit registers, a plurality of which correspond to the number of possible specific address values ​​of the current group cache address, listing all possible cache address values ​​of the current group, and assigning serial numbers to all possible cache address values ​​of the current group, then the multi-bit register of the current group corresponds to the cache address value of the serial number;

[0029] The number of bits of the multi-bit register depends on the number of possible various group cache address values ​​of the next group of cache addresses connected to the current group. All possible cache address values ​​of the next group of cache addresses connected to the current group are listed, and a cache address value is corresponded to each bit of the multi-bit register in advance. When the current group has a connection relationship with a cache address of the next group, the corresponding bit corresponding to the cache address in the multi-bit register with the serial number corresponding to the specific address value of the current group in the group connection indicator of the current group is 1. If multiple bits in the multi-bit register are 1, it means that the current group cache address has a connection relationship with the next group of cache addresses corresponding to multiple corresponding bits in the multi-bit register being 1.

[0030] In this embodiment, each group of cache addresses is classified, and a numerical value is assigned to each class, and the numerical value is used to represent several cache address values ​​of the corresponding class. In this embodiment, each group of cache addresses is divided into two categories according to the preset group cache address binary specific value, and a group of cache addresses is assigned a numerical value of 0 or 1 according to the divided class, and a group of cache addresses is represented by a numerical value of the class corresponding to each group and a group connection indicator between groups. Since each group has several cache addresses after grouping, by classifying and assigning a representative numerical value to each class, a numerical value represents several cache addresses of a certain length, which is equivalent to shortening the length of a cache address, thereby reducing the storage space.

[0031] In this embodiment, specifically, a segment of cache addresses is evenly divided into three groups, each group of cache addresses is divided into two categories, and a group of cache addresses is assigned 0 or 1 according to the category divided by each group of cache address values, and a group of cache addresses is represented by a value of 0 or 1, and a group connection indicator is set between groups. For example, if a segment of 9-bit addresses is divided into three groups, the 3-bit binary address information of each group is divided into one category (represented by 0) according to 000, 001, 010, and 100, and another category (represented by 1) according to 111, 110, 101, and 011. In this embodiment, it is pre-set which specific address values ​​are represented by 0 and which are represented by 1. It can also be divided into two categories according to whether there are more 0s or more 1s in each group of cache binary address values. If there are more 0s in the cache binary address values, the value 0 is used to represent it, and if there are more 1s in the cache binary address values, the value 1 is used to represent it. It can be pre-defined. For example, for a 32-bit cache address and a 32-byte cache line length, except for address [4:0] which is the cache line offset information, address [31:5] is the cache line retrieval information. The cache line retrieval information address [31:5] is divided into three segments of cache addresses, which correspond to three segment registers respectively. Each segment cache address represents a 9-bit address value, where each segment register contains three groups (each group represents a 3-bit address value, and each group of address values ​​is classified). After classification, each group takes a value of 0 or 1. The value 0 represents 4 specific address values ​​(000, 001, 010, 100), and the value 1 represents 4 specific address values ​​(111, 110, 101, 011). The combination of three groups of registers, and using two values ​​to represent a segment register, can retrieve a 9-bit address value: 0-0-0, 0-0-1, 0-1-0, 0-1-1, 1-0-0, 1-0-1, 1-1-0, 1-1-1, that is, by grouping, the length of address retrieval is shortened, and by grouping and using classification values ​​to represent, the state of each segment has only 2 3 =8 types, such as Figure 2 As shown, the number of bits of the multi-bit register of the segment connection indicator is 8, compared with 2 when the segment connection indicator is fully expanded. 9 =512 bits, saving storage space.

[0032] In this embodiment, the group connection indicator is four 4-bit registers, and four of the four 4-bit registers represent the number of cache address values ​​that may be represented by the class into which the current group cache address is divided. The various possible cache address values ​​corresponding to the numerical values ​​0 or 1 assigned to the current classification are listed and a serial number is given. The nth 4-bit register represents the nth cache address value corresponding to the numerical value of the current group classification. Each bit in the 4-bit register corresponds to the connection relationship of the group cache address of the next group connected to the current group, and the corresponding bit with a connection relationship is 1.

[0033] Since the current group classification value is 0 or 1, the address contained is 3 bits, 23 = 8, so after equal distribution, the number of cache addresses that the current group can represent is 2 2 =4, then 4 registers are set, and the number of bits of the register is 4 bits, which indicates the number of cache addresses of the next group connected to the current group. Since the next group is also represented by the classified value 0 or 1, it is also 4. Therefore, the group connection indicator uses 4 4-bit registers to set. For example, in the 4 4-bit registers corresponding to the current group's classified value of 0, the order of the 4 binary cache address values ​​of the current group is pre-set as follows: the first register (counting from left to right) corresponds to the address specific value 000 of the current group's classified value 0, the second register corresponds to the address specific value 001, the third register corresponds to the address specific value 010, and the fourth register corresponds to the address specific value 100. In the 4 4-bit registers corresponding to the current group's classified value of 1, the order of the 4 binary cache address values ​​is pre-set as follows: the first register corresponds to the address specific value 111, the second register corresponds to the address specific value 110, the third register corresponds to the address specific value 101, and the fourth register corresponds to the address specific value 011. The values ​​of each bit of the 4-bit register correspond to the connection relationship of the group cache address of the next group connected to the current group, and the corresponding bits with a connection relationship are 1. According to the above sequence, if the value of the latter group after classification is 0, the corresponding relationship between the value of each bit in the 4-bit register (counting from right to left) and the specific address value is preset as follows: the first bit corresponds to the specific address value 000 of the latter group, the second bit represents the specific address value 001 of the latter group, the third bit corresponds to the specific address value 010 of the latter group, and the fourth bit corresponds to the specific address value 100 of the latter group. If the value of the latter group after classification is 1, the corresponding relationship between the value of each bit in the 4-bit register (counting from right to left) and the specific address value is preset as follows: the first bit corresponds to the specific address value 111 of the latter group, the second bit corresponds to the specific address value 110 of the latter group, the third bit corresponds to the specific address value 101 of the latter group, and the fourth bit corresponds to the specific address value 011 of the latter group. The corresponding bits with a connection relationship are set to 1. The specific values ​​of the group corresponding to the register serial number and the corresponding relationship of the specific values ​​in the 4-bit register are shown in Table 1.

[0034] Table 1 Meaning of group connection bits

[0035]

[0036] For example, in segment 0-1-0, the second group value is 1, and the corresponding second register value is 0011. From Table 1, it can be seen that when the current group value is 1, the specific address value of the corresponding second register is 110, and the register value is 0011 (that is, 0001 and 0010), indicating that the first and second bits of the value in the register are 1 respectively, and are connected to the first and second cache address values ​​corresponding to the current group classification of the third group. Since the group classification of the third group is 0, the corresponding first cache address value is 000, and the second cache address is 001. That is, through the group connection indicator, it can be known that the specific address value 110 of the second group is connected to the specific address values ​​000 and 001 of the third group.

[0037] For example, the binary address after the cache line search address is divided into three segments is: 111111110_1011111111_111111111, 111111110_0000000000_000000000, all of which are in the cache. Since a cache address segment is represented by the value of the class corresponding to each group and the group connection indicator equipped for each group, the above two binary addresses: the first cache line address segment is represented as 1-1-1 for the first segment, 1-1-1 for the second segment, and 1-1-1 for the third segment; the second cache line address segment is represented as 1-1-1 for the first segment, 0-0-0 for the second segment, and 0-0-0 for the third segment. Therefore, the segment connection indicator will record that the first segment is 1-1-1 and has a connection relationship with the second segment 0-0-0 and 1-1-1, and the second segment 0-0-0 has a connection relationship with the third segment 0-0-0 and 1-1-1.

[0038] When a processor in a multi-core system queries whether 111111110_000000000_010000000 exists in the cache, it enters the monitoring filter for query. According to the previously agreed classification information, the cache line address is segmented as 1-1-1 for the first segment, 0-0-0 for the second segment, and 0-0-0 for the third segment. The query segment connection indication shows that there is a connection relationship between the first segment 1-1-1, the second segment 0-0-0, and the third segment 0-0-0, so it is necessary to further query the group connection indication.

[0039] Since the cache line binary retrieval address 111111110_0000000000_000000000 exists in the cache, according to the segmentation and grouping principles of the present invention, taking the second segment as an example, the address is 000000000, therefore according to the previously agreed classification information, it corresponds to 0-0-0, that is, the group classifications of the first group, the second group, and the third group of the second segment are all 0. Since the order of the 4 binary cache address values ​​in the 4 4-bit registers corresponding to the value 0 is pre-set as follows: the first register corresponds to the address specific value 000 of the current group classification value. Therefore, the first 4-bit register value of the first, second, and third groups of the second segment should be queried, which is currently: 0001 (indicating the first group of the second segment, the specific address value is 000, connected to the first cache address value corresponding to the current group classification of the second group of the second segment. Since the group classification of the second group of the second segment is 0, the corresponding first cache address value is 000), 0001 (indicating the second group of the second segment, the specific address value is 000, connected to the third group of the second segment, the specific address value is 000), 0001 (indicating the third group of the second segment, the specific address value is 000, connected to the first cache address value corresponding to the current group classification of the first group of the third segment. It can be seen from the segment connection indicator that the segment currently connected to the second segment 0-0-0 is the third segment 0-0-0. Therefore, the group classification of the first group of the third segment is 0, and the corresponding first cache address value is 000). From the above content, we can know that the third group of the second segment is only connected to the first group of the third segment. The corresponding specific cache address is that 000 of the third group of the second segment is only connected to 000 of the first group of the third segment. The queried address is 111111110_0000000000_010000000, that is, 000 of the third group of the second segment needs to be connected to 010 of the first group of the third segment. Therefore, the query group connection indicator result is not connected.

[0040] like Figure 2 As shown, when a 9-bit address is divided into 3 groups and the specific address values ​​of each group are classified, and the segment address is represented by the numerical value assigned after classification, then a 9-bit address is represented as a 3-bit numerical value. For example, the segment address 111111110 is represented as a 3-bit numerical value 1-1-1 by dividing the segment address into 3 groups and assigning values ​​to each group after classification. Then the number of bits of the multi-bit register used by the segment connection indicator depends on the state of the next segment address 000000000 after grouping. The next segment address 000000000 is represented as 0-0-0 after grouping and the possible address representation state is 2. 3 =8 bits, so the number of bits of the multi-bit register used by the segment connection indicator is 8 bits.

[0041] Therefore, when a snoop request is received on the consistency bus, the address is split to find out whether the segment connection indication and the group connection indication corresponding to the specific value of the address are both enabled. If all are hit, a search is initiated to the cache controller.

[0042] Since the present embodiment uses grouping and group connection indication to replace the expansion mode of the segment address in the prior art, if the address is fully expanded, the three segments will each have a 9-bit address, that is, the three segments need to be expanded to 0-511. Even if only a 1-bit register is used to indicate whether it is connected, a 512*512*2-bit register is required, which is a very large number. Therefore, when fully expanded, a common solution is to discard the segment connection indication and use the segment's own 0 / 1 to indicate whether it is a hit, that is, 512*3 = 1536. This embodiment uses segment connection indication, then there are 3 segments, each segment is expanded into 8 rows, each row has 3 groups, each group carries 4 4-bit registers (the last group of the last segment does not carry it, because there is no need to indicate it further), then a total of 4*4*3*8+4*4*3*8+4*4*2*8 = 16*24+16*24+16*16 = 1024 bits of registers, the segment connection indication occupies 8 bits, a total of 8*8*2 = 128 bits, that is, this embodiment saves 384 bits compared to full expansion, so the space occupied by the filter is much smaller.

[0043] The monitoring filter in this embodiment sets an 8-bit connection indication between each segment, and each bit indicates the connection status with the next segment register. Each segment is divided into three groups, and each group is equipped with 4 group connection registers to indicate the connection status of the 4 address values ​​of this group with the 4 address values ​​of the next group. It is queried whether there is a segment connection relationship between multiple segments. If there is, it is queried whether there is a connection relationship between specific address values ​​according to the group connection register, and the segment connection relationship is corrected with the group connection relationship, so that accurate hits can be achieved and the misjudgment rate can be reduced.

[0044] In this embodiment, since all addresses are connected and recorded through connection indications, the JETTY type full expansion result can be achieved with a smaller bit width. At the same time, it is more accurate than the Stream Register type, and the misjudgment rate does not increase exponentially with the storage of non-continuous addresses. Therefore, while maintaining a small hardware overhead, the misjudgment rate is reduced, thereby reducing system power consumption and improving the efficiency of monitoring filtering.

[0045] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A monitoring filter, characterized in that: The cache address is divided into two parts according to the length of the cache line in the multi-core system, the address value belonging to the cache line is used to represent the offset information within the cache line, and the address value belonging to the outside of the cache line is used to represent the cache line retrieval information, the cache address used to represent the cache line retrieval information is divided into multiple segments, and each of the divided segment cache addresses is respectively corresponded to a corresponding segment register, and a segment connection indicator is provided between adjacent segment registers, and the segment connection indicator is used to indicate the connection state of the previous segment cache address connected to the segment connection indicator and the next segment cache address; The segment connection indicator is a multi-bit register, and the number of bits of the multi-bit register depends on the number of specific address values ​​that may be represented by the cache address in the subsequent segment register connected to the segment connection indicator. Each specific value of the cache address corresponds to one bit in the multi-bit register. When a bit in the multi-bit register is 1, it means that the subsequent cache address corresponding to the bit is connected to the previous cache address connected to the segment connection indicator.

2. A monitoring filter according to claim 1, characterized in that: The segment register is also configured with a counter, which is used to increment the counter when each segment cache address corresponds to a corresponding segment register, and decrement the counter when the cache is evicted.

3. A monitoring filter according to claim 2, characterized in that: Each segment of cache addresses is divided into multiple groups, and each group of cache addresses is equipped with a group connection indicator, which is used to indicate the connection status between the current group of cache addresses and the next group of cache addresses.

4. A monitoring filter according to claim 3, characterized in that: The group connection indicator refers to using a plurality of multi-bit registers, wherein a plurality of the multi-bit registers correspond to the number of possible specific address values ​​of the current group cache address, listing all possible cache address values ​​of the current group, and assigning serial numbers to all possible cache address values ​​of the current group, then the cache address value of which serial number corresponds to the multi-bit register of the current group; The number of bits of the multi-bit register depends on the number of possible various group cache address values ​​of the next group of cache addresses connected to the current group. All possible cache address values ​​of the next group of cache addresses connected to the current group are listed, and a cache address value is corresponded to each bit of the multi-bit register in advance. When the current group has a connection relationship with a cache address of the next group, the corresponding bit corresponding to the cache address in the multi-bit register with the serial number corresponding to the specific address value of the current group in the group connection indicator of the current group is 1. If multiple bits in the multi-bit register are 1, it means that the current group cache address has a connection relationship with the next group of cache addresses corresponding to multiple corresponding bits in the multi-bit register being 1.

5. A monitoring filter according to claim 4, characterized in that: Each group of cache addresses is classified, and a numerical value is assigned to each class, which is used to represent several cache addresses of the corresponding class.

6. A monitoring filter according to claim 5, characterized in that: According to the preset group cache address binary specific value, each group of cache addresses is divided into two categories, and a group of cache addresses is assigned a value of 0 or 1 according to the divided class. A group of cache addresses is represented by a value of 0 or 1, and a segment of cache addresses is represented by the value of the class corresponding to each group and the group connection indicator equipped with each group.

7. A monitoring filter according to claim 6, characterized in that: A segment of cache addresses is evenly divided into three groups. Each group of cache addresses is divided into two categories according to a preset group cache address binary specific value. A group of cache addresses is assigned a value of 0 or 1 according to the category divided by each group of cache address binary specific value. The value 0 or 1 represents several possible cache address values ​​in a group of cache addresses, and each group is equipped with a group connection indicator.

8. A monitoring filter according to claim 7, characterized in that: The group connection indicator is 4 4-bit registers, 4 of the 4 4-bit registers represent the number of cache address values ​​that may be represented by the class into which the group of cache addresses is divided, and lists the various possible cache address values ​​corresponding to the numerical values ​​0 or 1 assigned to the current classification and gives a serial number. The nth 4-bit register represents the nth cache address value corresponding to the numerical value of the current group classification. Each bit in the 4-bit register corresponds to the connection relationship of the group cache address of the next group connected to the current group, and the corresponding bit with a connection relationship is 1.

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