Quantum circuit construction method, ciphertext decryption method and related devices

Abstract

The invention discloses a quantum circuit construction method, a ciphertext decryption method and related devices, and the quantum circuit construction method comprises the steps: carrying out the LUP matrix decomposition of a preset matrix corresponding to a fixed polynomial, obtaining an L-type matrix, a U-type matrix and a P-type matrix, and constructing a quantum circuit based on the L-type matrix, the U-type matrix and the P-type matrix obtained through decomposition and a preset modulus arithmetic unit. The quantum circuit can calculate multiplication of an arbitrary polynomial and a fixed polynomial in a finite field GF (p, k), efficient generation of multiplication data in the GF (p, k) can be achieved through the quantum circuit, and cracking of ciphertext in a classic encryption algorithm can be accelerated through the generated multiplication data.

Description

Technical Field

[0001] The present invention belongs to the field of quantum computing technology, and in particular to a quantum circuit construction method, a ciphertext decryption method and related devices. Background Art

[0002] Quantum computers are physical devices that follow the laws of quantum mechanics to perform high-speed mathematical and logical operations, store and process quantum information. When a device processes and calculates quantum information and runs quantum algorithms, it is a quantum computer. Quantum computers have become a key technology under research because they can process mathematical problems more efficiently than ordinary computers. For example, they can speed up the time it takes to crack a key from hundreds of years to just a few hours.

[0003] Finite field, also known as Galois Field (GF), is a very important concept in many disciplines such as abstract algebra and cryptography. Taking cryptography as an example, the discrete logarithm problem over finite fields is one of the two core difficult problems in the classical public key cryptography system. Therefore, how to efficiently generate multiplication operation data in GF(p, k) and thus accelerate the cracking of classical encryption algorithms. Summary of the invention

[0004] The purpose of the present invention is to provide a quantum circuit construction method and a ciphertext decryption method and related devices, which can efficiently generate multiplication operation data in GF(p, k) through the constructed quantum circuit, thereby accelerating the cracking of classical encryption algorithms.

[0005] An embodiment of the present invention provides a method for constructing a quantum circuit, the method comprising:

[0006] Perform LUP matrix decomposition on the matrix corresponding to a preset fixed polynomial to obtain L-type, U-type and P-type matrices;

[0007] Based on the L-type, U-type and P-type matrices and a preset modulus operator, a quantum circuit for calculating the multiplication of an arbitrary polynomial and a fixed polynomial is constructed, and both the fixed polynomial and the arbitrary polynomial belong to a finite field GF(p, k).

[0008] Optionally, the quantum circuit for calculating the multiplication of an arbitrary polynomial and the fixed polynomial based on the L-type, U-type and P-type matrices and a preset modulus operator comprises:

[0009] Constructing a quantum circuit corresponding to the L-type matrix based on the L-type matrix and a preset modulus operator, constructing a quantum circuit corresponding to the U-type matrix based on the U-type matrix and a preset modulus operator, and constructing a quantum circuit corresponding to the P-type matrix based on the P-type matrix and a SWAP gate;

[0010] The quantum circuits corresponding to the L-type matrix, the U-type matrix and the P-type matrix are sequentially cascaded to obtain a quantum circuit for calculating the multiplication operation of an arbitrary polynomial and the fixed polynomial.

[0011] Optionally, the modulus operator includes a modulus addition operator and a modulus multiplication operator, and the step of constructing a quantum circuit corresponding to the L-type matrix based on the L-type matrix and a preset modulus operator includes:

[0012] Determine the non-zero elements of each row in the L-type matrix;

[0013] A quantum circuit corresponding to the L-type matrix is ​​constructed based on the non-zero elements of each row and the modular addition operator and the modular multiplication operator.

[0014] Optionally, constructing a quantum circuit corresponding to the P-type matrix based on the P-type matrix and the SWAP gate includes:

[0015] Determine the non-zero elements a in the P-type matrix except the diagonal mn ;

[0016] If m is less than n, the SWAP gate is applied to the mth and nth qubits;

[0017] If m is greater than n, determine the non-zero element a m′n′ , and apply the SWAP gate to the mth and n′th qubits, m′ is less than m, and n′ is greater than m;

[0018] If m is equal to n or n′, no operation is performed;

[0019] The quantum circuit corresponding to the P-type matrix is ​​determined.

[0020] Another embodiment of the present invention provides a ciphertext decryption method, which is applied to a ciphertext encrypted based on discrete logarithm encryption, and the method comprises:

[0021] Obtaining a public key and a plaintext parameter corresponding to the ciphertext, wherein the public key and the plaintext parameter are both elements in a finite field GF(p, k);

[0022] Determine the square matrix corresponding to the public key and the plaintext parameters;

[0023] Constructing a target quantum circuit based on the square matrix and the quantum circuit in any one of claims 1 to 4;

[0024] Determining a private key corresponding to the ciphertext based on the operation result of the target quantum circuit;

[0025] The ciphertext is decrypted based on the private key.

[0026] Optionally, the step of constructing a target quantum circuit based on the square matrix and the quantum circuit in any one of the above method embodiments includes:

[0027] Performing a square operation on the square matrix corresponding to the public key a preset number of times to obtain a plurality of first square matrices; and performing a square operation on the square matrix corresponding to the plaintext parameter a preset number of times to obtain a plurality of second square matrices;

[0028] Based on the quantum circuits in any of the above method embodiments, determine the square matrix corresponding to the public key and the first modulus polynomial exponential operation quantum circuits corresponding to the first square matrix, and the square matrix corresponding to the plaintext parameter and the second modulus polynomial exponential operation quantum circuits corresponding to the second square matrix;

[0029] The quantum Fourier transform circuit, the first modulus polynomial exponential operation quantum circuit, the second modulus polynomial exponential operation quantum circuit and the quantum inverse Fourier transform circuit are sequentially cascaded to obtain a target quantum circuit.

[0030] Optionally, the determining, based on the quantum circuit in any of the above method embodiments, the square matrix corresponding to the public key and the first modulus polynomial exponential operation quantum circuits corresponding to the first square matrixes includes:

[0031] The square matrix corresponding to the public key and the plurality of the first square matrices are respectively used as the fixed polynomials in any one of the above method embodiments, and a first modular polynomial exponential operation quantum circuit is determined based on the fixed polynomials.

[0032] Another embodiment of the present invention provides a quantum circuit construction device, the device comprising:

[0033] A matrix decomposition unit, used for performing LUP matrix decomposition on a matrix corresponding to a preset fixed polynomial to obtain L-type, U-type and P-type matrices;

[0034] A circuit construction unit is used to construct a quantum circuit for calculating the multiplication operation of an arbitrary polynomial and a fixed polynomial based on the L-type, U-type and P-type matrices and a preset modulus operator, wherein both the fixed polynomial and the arbitrary polynomial belong to a finite field GF(p, k).

[0035] Another embodiment of the present invention provides a ciphertext decryption device, which is applied to ciphertext based on discrete logarithm encryption, and the device includes:

[0036] An acquisition unit is used to acquire a public key and a plaintext parameter corresponding to the ciphertext, wherein the public key and the plaintext parameter both belong to an element in a finite field GF(p, k;

[0037] A determination unit, used to determine the square matrix corresponding to the public key and the plaintext parameter;

[0038] A construction unit, configured to construct a target quantum circuit based on the square matrix and the quantum circuit in any one of the above method embodiments;

[0039] The determining unit is further used to determine the private key corresponding to the ciphertext based on the operation result of the target quantum circuit;

[0040] A decryption unit is used to decrypt the ciphertext based on the private key.

[0041] Yet another embodiment of the present invention provides a storage medium, wherein the storage medium stores a computer program, wherein the computer program is configured to execute any of the above methods when running.

[0042] Yet another embodiment of the present invention provides an electronic device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute any of the above methods.

[0043] It can be seen that the present invention performs LUP matrix decomposition on a matrix corresponding to a preset fixed polynomial to obtain L-type, U-type and P-type matrices, and then constructs a quantum circuit based on the decomposed L-type, U-type and P-type matrices and a preset modulus operator. The quantum circuit can calculate the multiplication operation of an arbitrary polynomial and a fixed polynomial in a finite field GF(p, k. The quantum circuit can be used to achieve efficient generation of multiplication operation data in GF(p, k. The generated multiplication operation data can be used to accelerate the cracking of ciphertext in a classical encryption algorithm. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 A network block diagram of a quantum circuit construction system and a ciphertext decryption system provided by an embodiment of the present invention;

[0045] Figure 2 A schematic diagram of a process for constructing a quantum circuit provided by an embodiment of the present invention;

[0046] Figure 3 A schematic diagram of the structure of a quantum circuit corresponding to an L-type matrix provided in an embodiment of the present invention;

[0047] Figure 4 A schematic diagram of the structure of a quantum circuit corresponding to a P-type matrix provided in an embodiment of the present invention;

[0048] Figure 5 A schematic diagram of the structure of a quantum circuit corresponding to another P-type matrix provided in an embodiment of the present invention;

[0049] Figure 6 A flowchart of a ciphertext decryption method provided by an embodiment of the present invention;

[0050] Figure 7 A schematic diagram of the structure of a target quantum circuit provided by an embodiment of the present invention;

[0051] Figure 8 A schematic diagram of the structure of a quantum circuit construction device provided by an embodiment of the present invention;

[0052] Fig. 9 A schematic diagram of the structure of a ciphertext decryption device provided by an embodiment of the present invention;

[0053] Fig.10 A schematic diagram of the structure of a computer device provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0054] The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, but should not be construed as limiting the present invention.

[0055] Figure 1 1 is a network block diagram of a quantum circuit construction system and a ciphertext decryption system provided by an embodiment of the present invention. The quantum circuit construction system or the ciphertext decryption system may include a network 110, a server 120, a wireless device 130, a client 140, a storage 150, a classical computing unit 160, a quantum computing unit 170, and may also include additional memories, classical processors, quantum processors, and other devices not shown.

[0056] The network 110 is a medium for providing communication links between various devices and computers connected together in a quantum circuit construction system or a ciphertext decryption system, including but not limited to the Internet, corporate intranets, local area networks, mobile communication networks and combinations thereof. The connection method may be wired, wireless communication links or optical fiber cables, etc.

[0057] The server 120, the wireless device 130 and the client 140 are conventional data processing systems, which may contain data and applications or software tools for performing conventional computing processes. The client 140 may be a personal computer or a network computer, so the data may also be provided by the server 120. The wireless device 130 may be a smart phone, a tablet, a laptop, a smart wearable device, etc. The storage unit 150 may include a database 151, which may be configured to store data such as quantum bit parameters, quantum logic gate parameters, quantum circuits, quantum programs, etc.

[0058] The classical computing unit 160 (quantum computing unit 170) may include a classical processor 161 (quantum processor 171) for processing classical data (quantum data) and a memory 162 (memory 172) for storing classical data (quantum data). The classical data (quantum data) may be a boot file, an operating system image, and an application 163 (application 173). The application 163 (application 173) may be used to implement a quantum algorithm compiled by a quantum circuit construction method or a ciphertext decryption method provided in an embodiment of the present invention.

[0059] Any data or information stored or generated in the classical computing unit 160 (quantum computing unit 170) can also be configured to be stored or generated in another classical (quantum) processing system in a similar manner, and any application program executed by it can also be configured to be executed in another classical (quantum) processing system in a similar manner.

[0060] It should be noted that a true quantum computer is a hybrid structure, which includes at least Figure 1 There are two major parts in it: the classical computing unit 160, which is responsible for performing classical computing and control; the quantum computing unit 170, which is responsible for running quantum programs and thus realizing quantum computing.

[0061] The classical computing unit 160 and the quantum computing unit 170 may be integrated into one device or distributed in two different devices. For example, the first device including the classical computing unit 160 runs a classical computer operating system, on which quantum application development tools and services are provided, as well as storage and network services required for quantum applications. Users develop quantum programs through the quantum application development tools and services thereon, and send quantum programs to the second device including the quantum computing unit 170 through the network services thereon. The second device runs a quantum computer operating system, and the code of the quantum program is parsed and compiled into instructions that can be recognized and executed by the quantum processor 170 through the quantum computer operating system. The quantum processor 170 implements the quantum algorithm corresponding to the quantum program according to the instructions.

[0062] The computing unit of the classic processor 161 in the classic computing unit 160 is a CMOS tube based on a silicon chip. This computing unit is not limited by time and coherence, that is, this computing unit is not limited by the length of use and can be used at any time. In addition, in the silicon chip, the number of such computing units is also sufficient. At present, the number of computing units in a classic processor 161 is tens of thousands. The number of computing units is sufficient and the computing logic that can be selected by the CMOS tube is fixed, such as: AND logic. When calculating with the help of CMOS tubes, a large number of CMOS tubes are combined with limited logic functions to achieve the calculation effect.

[0063] The basic computing unit of the quantum processor 171 in the quantum computing unit 170 is a quantum bit, and the input of the quantum bit is limited by coherence and coherence time, that is, the quantum bit is limited by the use time and is not available at any time. Making full use of the quantum bit within the available use time of the quantum bit is a key problem in quantum computing. In addition, the number of quantum bits in a quantum computer is one of the representative indicators of the performance of a quantum computer. Each quantum bit realizes the computing function through the logical function configured on demand. In view of the limited number of quantum bits, the logical functions in the field of quantum computing are diverse, such as: Hadamard gate (Hadamard gate, H gate), Pauli-X gate (X gate), Pauli-Y gate (Y gate) Pauli-Z gate (Z gate), X gate, RY gate, RZ gate, CNOT gate, CR gate, iSWAP gate, Toffoli gate, etc. During quantum computing, it is necessary to use limited quantum bits combined with a variety of logical functions to achieve the computing effect.

[0064] Based on these differences, the design of CMOS tubes by classical logic functions and the design of quantum bits by quantum logic functions are significantly and essentially different. The design of CMOS tubes by classical logic functions does not need to consider the individuality of CMOS tubes. For example, the representation of CMOS tubes in silicon chips is the individual identification, position, and usable life of each CMOS tube. Therefore, the classical algorithm composed of classical logic functions only expresses the operational relationship of the algorithm, but does not express the algorithm's dependence on individual CMOS tubes.

[0065] When quantum logic functions act on qubits, the individuality of qubits needs to be considered, such as the individual identification of the qubit in the quantum chip, its position, its relationship with surrounding qubits, and the usable time of each qubit. Therefore, the quantum algorithm composed of quantum logic functions not only expresses the computational relationship of the algorithm, but also expresses the algorithm's dependence on individual qubits.

[0066] Exemplary:

[0067] Quantum algorithm 1: H1, H2, CNOT(1,3), H3, CNOT(2,3);

[0068] Quantum Algorithm 2: H1, H2, CNOT(1,2), H3, CNOT(2,3);

[0069] Among them, 1 / 2 / 3 represent three sequentially connected quantum bits Q1, Q2, Q3 or mutually connected quantum bits Q1, Q2, Q3 respectively;

[0070] An exemplary explanation of how quantum algorithms are affected by the coherence time of qubits is as follows:

[0071] Define the execution time of a single-qubit logic gate as t, and the execution time of a two-qubit logic gate acting on adjacent bits as 2t; then:

[0072] When Q1, Q2, and Q3 are interconnected, the calculation of quantum algorithm 1 takes 6t, which is divided into 4 time periods. The duration of each time period is t, 2t, t, and 2t respectively. The operations performed in each time period are: H1, H2; CNOT(1,3); H3; CNOT(2,3);

[0073] The calculation of quantum algorithm 1 takes 5t, which is divided into 3 time periods. The duration of each time period is t, 2t, and 2t respectively. The operations performed in each time period are: H1, H2, H3; CNOT(1,2); CNOT(2,3);

[0074] When Q1, Q2, and Q3 are connected in sequence, the quantum algorithm 1 needs to be equivalent to: H 1, H2; swap(1,2), CNOT(2,3), swap(1,2); H3; CNOT(2,3); the calculation of the equivalent quantum algorithm 1 requires 10t, which is divided into 4 time periods, and the duration of each time period is t, 6t, t, and 2t respectively. The operations performed in each time period are: H1, H2; swap(1,2), CNOT(2,3), swap(1,2); H3; CNOT(2,3).

[0075] Therefore, the design of the quantum logic function acting on the quantum bit (including the design of whether the quantum bit is used or not and the design of the efficiency of the use of each quantum bit) is the key to improving the computing performance of the quantum computer, and requires special design. This is also the uniqueness of the quantum algorithm based on the quantum logic function, which is essentially and significantly different from the classical algorithm based on the classical logic function. The above-mentioned design for quantum bits is a technical problem that ordinary computing devices do not need to consider or face. The present invention proposes a quantum circuit construction method and a ciphertext decryption method and related devices, which efficiently generate multiplication operation data in GF(p, k through the constructed quantum circuit, thereby accelerating the cracking of the classical encryption algorithm.

[0076] See also Figure 2 , Figure 2 A schematic diagram of a process for constructing a quantum circuit provided by an embodiment of the present invention, the method comprising:

[0077] Step 201: performing LUP matrix decomposition on a matrix corresponding to a preset fixed polynomial to obtain L-type, U-type and P-type matrices;

[0078] Among them, GF(2 k) are polynomials with coefficients of 0 and 1, or more precisely, the remainder class of polynomials, where the equivalence relation is characterized by modulo division (modulo division means dividing a polynomial and taking the remainder) an irreducible polynomial of degree k. An irreducible polynomial is one that has no other polynomials as factors except 1 and the polynomial itself in the current number field.

[0079] Finite field GF(p, k and GF(2 k ), GF(p, k can also be described by polynomials. The difference is that the polynomial coefficients of GF(p, k) are taken from the set {0, 1, 2, ···, p-1}, where p is generally a prime number. k ), GF(p, k also requires a k-order irreducible polynomial to be given first. For example, for GF(3, 2 with p=3, k=2, assume that the irreducible polynomial is:

[0080] x 2 ++2=0

[0081] This irreducible polynomial can be equivalently written as:

[0082] x 2 =-(x+2)=2x+1

[0083] Assuming that λ is the root of the above polynomial, all elements in GF(3,2=GF(9) can be expressed as:

[0084] 0,λ,λ 2 =2λ+1,λ 3 =2λ+2,λ 4 =2,λ 5 =2λ,λ 6 =λ+2,λ 7 =λ+1,λ 8 =1 or you can change the sign:

[0085] {0,1,2,x,x+1,x+2,2,2+1,2+2}

[0086] The above elements are closed by multiplication, and all non-zero elements have inverses, forming a finite field, denoted as GF(3,2, where the number of non-zero elements is p k -1=3 2 -1=8.

[0087] Wherein, the fixed polynomial belongs to GF(p, k).

[0088] Among them, decomposing a square matrix A into the product of the lower triangular matrix L and the upper triangular matrix U is called LU decomposition. LUP decomposition is to add a permutation matrix P on the basis of LU decomposition. The square matrix A is first subjected to the permutation matrix to obtain AP, and then the new matrix is ​​decomposed by LU, that is, AP = LU.

[0089] Furthermore, before performing LUP matrix decomposition on a matrix corresponding to a preset fixed polynomial, the method includes:

[0090] Determining the degree corresponding to the highest term in a preset irreducible polynomial, wherein the preset irreducible polynomial is a modulus;

[0091] Determine a modular multiplication result of a preset fixed polynomial and each term of a lower degree than the highest term;

[0092] A matrix corresponding to the fixed polynomial is determined based on the modular multiplication result.

[0093] For example, the preset irreducible polynomial is:

[0094] f(x)=x 3 +3x 2 ++2

[0095] Right now

[0096] x 3 =-(3x 2 ++2)=2x 2 +4x+3

[0097] The result of modular multiplication of the fixed polynomial 2+3 with each term of a lower degree than the highest term is:

[0098] (2+3)×1 ()=2+3

[0099] (2+3)×x ()=2 2 +3x

[0100] (2+3)×x 2 ()=(2 3 +3x 2 ) (2 2 +4x+3)=2 2 +3x

[0101] Translating the above expression into the language of linear algebra:

[0102] (3,2,0)×(1,0,0)=(3,2,0)

[0103] (3,2,0)×(0,1,0)=(0,3,2)

[0104] (3,2,0)×(0,0,1)=(1,3,2)

[0105] Putting the above four equations together we get:

[0106]

[0107] Therefore, the matrix corresponding to the fixed polynomial can be determined as:

[0108]

[0109] Here, you can verify:

[0110] (2 2 ++4)×(2x+3)=x 2 +2x+4mod5

[0111] It can also be calculated using matrices:

[0112]

[0113] Step 202: constructing a quantum circuit for calculating the multiplication of an arbitrary polynomial and a fixed polynomial based on the L-type, U-type and P-type matrices and a preset modulus operator, wherein both the fixed polynomial and the arbitrary polynomial belong to a finite field GF(p, k.

[0114] The mathematical representation of quantum logic gates is a matrix, so the matrix can be processed, for example, by decomposing it, and then using the preset modulus operator to construct the quantum logic gate corresponding to the decomposed matrix, and then applying the quantum logic gate to the corresponding quantum bit to obtain a quantum circuit.

[0115] Here, an arbitrary polynomial is the input of the quantum circuit.

[0116] It can be seen that the present invention performs LUP matrix decomposition on a matrix corresponding to a preset fixed polynomial to obtain L-type, U-type and P-type matrices, and then constructs a quantum circuit based on the decomposed L-type, U-type and P-type matrices and a preset modulus operator. The quantum circuit can calculate the multiplication operation of an arbitrary polynomial and a fixed polynomial in a finite field GF(p, k. The quantum circuit can be used to achieve efficient generation of multiplication operation data in GF(p, k. The generated multiplication operation data can be used to accelerate the cracking of ciphertext in a classical encryption algorithm.

[0117] Optionally, the quantum circuit for calculating the multiplication of an arbitrary polynomial and the fixed polynomial based on the L-type, U-type and P-type matrices and a preset modulus operator comprises:

[0118] Constructing a quantum circuit corresponding to the L-type matrix based on the L-type matrix and a preset modulus operator, constructing a quantum circuit corresponding to the U-type matrix based on the U-type matrix and a preset modulus operator, and constructing a quantum circuit corresponding to the P-type matrix based on the P-type matrix and a SWAP gate;

[0119] The quantum circuits corresponding to the L-type matrix, the U-type matrix and the P-type matrix are sequentially cascaded to obtain a quantum circuit for calculating the multiplication operation of an arbitrary polynomial and the fixed polynomial.

[0120] Specifically, the modulus operator includes a modulus addition operator and a modulus multiplication operator, and the quantum circuit corresponding to the L-type matrix is ​​constructed based on the L-type matrix and the preset modulus operator, including:

[0121] Determine the non-zero elements of each row in the L-type matrix;

[0122] A quantum circuit corresponding to the L-type matrix is ​​constructed based on the non-zero elements of each row and the modular addition operator and the modular multiplication operator.

[0123] Specifically, the quantum circuit corresponding to the L-type matrix is ​​constructed based on the non-zero elements of each row and the modular addition operator and the modular multiplication operator, including:

[0124] Determine the diagonal non-zero elements and off-diagonal non-zero elements in each row of non-zero elements;

[0125] Determining a modular addition and modular multiplication operation circuit based on the diagonal non-zero elements and the off-diagonal non-zero elements and the modular addition operator and the modular multiplication operator, the multiplier of the modular addition and modular multiplication operation circuit is the diagonal non-zero element, the addend of the modular addition and modular multiplication operation circuit is the product of the coefficients of the off-diagonal non-zero elements and the corresponding terms of the off-diagonal non-zero elements in an arbitrary polynomial, and the modulus of the modular addition and modular multiplication operation circuit is the p;

[0126] A quantum circuit corresponding to the L-type matrix is ​​constructed based on the modular addition and modular multiplication operation circuit corresponding to each row.

[0127] More specifically, for each non-zero element in a row, if the non-zero element is an element on the diagonal, multiply the element; if the non-zero element is an element off the diagonal, add the product of the element and the coefficient of the corresponding term in an arbitrary polynomial. After completing the addition and multiplication operations on all non-zero elements in the row, take the modulus of the result, and the modulus is p.

[0128] The number of data bits required is The number of auxiliary bits required depends on the modular addition operator and modular multiplication operator used. In a specific embodiment, the auxiliary bits are

[0129] For example, the L-type matrix on GF(5,3) is:

[0130]

[0131] p=5, the non-zero element in row 0 is a 00 =3, a 02 =1, then the modular addition and modular multiplication operation is determined to be (×3+C) mod 5, and the logic gate corresponding to the modular addition and modular multiplication operation acts on the data bit and auxiliary bit corresponding to the first term of an arbitrary polynomial; the non-zero element in the first row is a 11 =3, a 12 =41, then the modular addition and modular multiplication operation is determined to be (×3+4C) mod 5, and the logic gate corresponding to the modular addition and modular multiplication operation acts on the second term of an arbitrary polynomial corresponding to data bits and Auxiliary bits; where an arbitrary polynomial is Cx 2 +Bx+A.

[0132] like Figure 3 As shown, Figure 3 A schematic diagram of a quantum circuit corresponding to an L-type matrix provided in an embodiment of the present invention. The quantum circuit includes 12 quantum bits, 9 of which are data bits used to encode an arbitrary polynomial Cx 2 +Bx+A corresponds to the quantum state, for example, the quantum state corresponding to A is |a2>|a1>|a0>, the quantum state corresponding to B is |b2>|b1>|b0>, and the quantum state corresponding to C is |c2>|c1>|c0>. The other 4 are auxiliary bits, and the corresponding quantum states are |aux3>|aux2>|aux1>|aux0>, which are used to assist modular addition and modular multiplication operations. The initial quantum states of the 4 quantum bits are |0>|0>|0>|0>, and they will be reset to 0 after completing one operation for the next operation.

[0133] The quantum logic gate corresponding to (×3+C)mod 5 acts on the quantum bits corresponding to |a2>|a1>|a0> and |aux3>|aux2>|aux1>|aux0>, and the quantum logic gate corresponding to (×3+4C)mod 5 acts on the quantum bits corresponding to |b2>|b1>|b0> and |aux3>|aux2>|aux1>|aux0>.

[0134] The specific implementation process of the quantum circuit corresponding to the U-type matrix is ​​similar to the specific implementation process of the quantum circuit corresponding to the L-type matrix, except that one is an upper triangular matrix and the other is a lower triangular matrix. Please refer to the specific implementation process of the quantum circuit corresponding to the above L-type matrix, which will not be repeated here.

[0135] In one of the embodiments provided by the present invention, the quantum circuit corresponding to the P-type matrix is ​​constructed based on the SWAP gate, and the dimension of the P-type matrix is ​​k×k, including:

[0136] The quantum state of the k qubits corresponding to the number of rows is transferred to the quantum state of the k qubits corresponding to the number of columns, and the non-zero elements a except the diagonal in the P-type matrix are determined. mn , m and n are the number of rows and columns of the P-type matrix respectively;

[0137] The SWAP gate is applied to the mth qubit among the k qubits corresponding to the number of rows and the nth qubit among the k qubits corresponding to the number of columns to obtain a quantum circuit corresponding to the P-type matrix.

[0138] Further, the step of transferring the quantum state of the k qubits corresponding to the number of rows to the quantum state of the k qubits corresponding to the number of columns includes:

[0139] The SWAP gate is applied to the qubits corresponding to the row number and the qubits corresponding to the column number with the same serial number, that is, k qubits corresponding to both the row number and the column number.

[0140] For example, Figure 4 As shown, Figure 4 A schematic diagram of a quantum circuit structure corresponding to a P-type matrix provided in an embodiment of the present invention. If t=4, the quantum circuit includes four quantum bits corresponding to the number of rows: q Line0 ,q Line1 ,q Line2 ,q Line3 , the number of columns corresponds to the four quantum bits: q Row0 ,q Row1 ,q Row2 ,q Row3 . You can first use SWAP(q Line0 ,q Row0 )、SWAP(q Line1 ,q Row1 )、SWAP(q Line2 ,q Row2 )、SWAP(q Line3 ,q Row3 ) transfers the quantum state of the qubit corresponding to the row number to the quantum state of the qubit corresponding to the column number. Here, the four SWAP gates act on different qubits, so their action sequence is not affected. Figure 4 Just one example.

[0141] If the P-type matrix is:

[0142]

[0143] Then the non-zero elements have a 01 、a 12 、a 23 、a 30 , so there exists SWAP(q Line0 ,q Row1 )、SWAP(q Line1 ,q Row2 )、SWAP(q Line2 ,q Row3 )、SWAP(q Line3 ,q Row0 ). Similarly, the four SWAP gates act on different quantum bits, so it does not affect their timing. Figure 4 Just one example.

[0144] In another embodiment provided by the present invention, the step of determining the quantum circuit corresponding to the P-type matrix based on the SWAP gate includes:

[0145] Determine the non-zero elements a in the P-type matrix except the diagonal mn ;

[0146] If m is less than n, the SWAP gate is applied to the mth and nth qubits;

[0147] If m is greater than n, determine the non-zero element a m′n′ , and apply the SWAP gate to the mth and nth ′ On qubits, m ′ is less than m, and n ′ greater than m;

[0148] If m is equal to n or n ′ , no action is performed;

[0149] The quantum circuit corresponding to the P-type matrix is ​​determined.

[0150] For example, Figure 5 As shown, Figure 5 A schematic diagram of the structure of a quantum circuit corresponding to another P-type matrix provided in an embodiment of the present invention.

[0151] If the P-type matrix is:

[0152]

[0153] The non-zero elements are a 03 、a 10 、a 21 、a 32 , for non-zero elements a 03 , 0<3, then the SWAP gate acts on the 0th and 3rd quantum bits (q0 and q3); for non-zero elements a10 , 1>0, then search upward to get a 03 , m=1>m ′ =0 and n ′ =3>m=1, the SWAP gate is applied to the first and third qubits (q1 and q3); similarly, for the non-zero element a 21 , apply the SWAP gate to the second and third qubits (q2 and q3); for non-zero elements a 32 , no operation is performed; after all non-zero elements are traversed, the quantum circuit corresponding to the P-type matrix is ​​determined.

[0154] It can be seen that in the embodiment of the present invention, the number of qubits required is k, which is less than the number of qubits required in the previous embodiment, 2k. The previous embodiment involves less computational complexity in classical calculations, and the logic is more direct, but the number of qubits called is larger. The advantages and disadvantages of the embodiment of the present invention are opposite to those of the previous embodiment.

[0155] It should be noted that the maximum value of the elements in the L-type and U-type matrices is p-1, so each element needs data bits represent that for k×k L-type and U-type matrices, the corresponding quantum circuits need data bits; since all elements in the P-type matrix are 1, each element requires 1 data bit to represent. For a k×k P-type matrix, its corresponding quantum circuit requires k or 2k data bits; when cascading, the P-type matrix can be expanded to A quantum circuit with 100 data bits, that is, data bits represent one element.

[0156] Discrete logarithms are regarded as one of the three foundations of contemporary cryptography. They rely on the difficulty of calculating discrete exponents over finite fields to ensure their security. The discrete logarithm problem is: given a prime number p and a positive integer b, knowing that b = a x (mod p) value, solve for x. In the encryption method based on discrete logarithms, x is the private key, a is the public key, and the plaintext parameter is b. It is difficult to solve x if a and b are known. Even if the most efficient number field sieve method is used to decompose the binary number represented by 795 bits, it will take more than 3,000 years. The ELGamal encryption algorithm, DSA digital signature scheme, ECDSA signature algorithm, SM3 signature algorithm, identity-based cryptographic algorithm (IBE, IBS), SM9 identification cryptographic algorithm, etc. are all based on the assumption of the difficulty of discrete logarithm problems. Therefore, how to realize the rapid cracking of ciphertext based on discrete logarithm encryption in the field of traditional cryptography based on the quantum circuit in the above embodiment is a difficult problem.

[0157] The present invention proposes a ciphertext decryption method, see Figure 6 , Figure 6 A flowchart of a ciphertext decryption method provided by an embodiment of the present invention, the method comprising:

[0158] Step 601: Obtain the public key and plaintext parameters corresponding to the ciphertext, wherein the public key and plaintext parameters both belong to the elements in the finite field GF(p, k);

[0159] Step 602: Determine the square matrix corresponding to the public key and the plaintext parameter;

[0160] Specifically, the public key and the plaintext parameter are both in the form of polynomials, the polynomials corresponding to the public key and the plaintext parameter are respectively used as fixed polynomials, and then the square matrices corresponding to the public key and the plaintext parameter are determined by referring to the matrix determination method of the fixed polynomial.

[0161] Step 603: constructing a target quantum circuit based on the square matrix and the quantum circuit in any of the above embodiments;

[0162] Optionally, constructing a target quantum circuit based on the square matrix and the quantum circuit in any one of the above embodiments includes:

[0163] Performing a square operation on the square matrix corresponding to the public key a preset number of times to obtain a plurality of first square matrices; and performing a square operation on the square matrix corresponding to the plaintext parameter a preset number of times to obtain a plurality of second square matrices;

[0164] Based on the quantum circuits in any of the above embodiments, determine the square matrix corresponding to the public key and the first modulus polynomial exponential operation quantum circuits corresponding to the first square matrix, and the square matrix corresponding to the plaintext parameter and the second modulus polynomial exponential operation quantum circuits corresponding to the second square matrix;

[0165] The quantum Fourier transform circuit, the first modulus polynomial exponential operation quantum circuit, the second modulus polynomial exponential operation quantum circuit and the quantum inverse Fourier transform circuit are sequentially cascaded to obtain a target quantum circuit.

[0166] Specifically, the determining of the square matrix corresponding to the public key and the first modulus polynomial exponential operation quantum circuits corresponding to the plurality of first square matrices based on the quantum circuit in any of the above embodiments includes:

[0167] The square matrix corresponding to the public key and the plurality of the first square matrices are respectively used as the fixed polynomials in any of the above embodiments, and a first modular polynomial exponential operation quantum circuit is determined based on the fixed polynomials.

[0168] The preset number is k-1, so k-1 first matrices and k-1 second matrices can be obtained. Figure 2The method embodiment can determine the quantum circuit corresponding to each square matrix. The square matrix corresponding to the public key and the k quantum circuits constructed by the k-1 first square matrices are cascaded to obtain the first modulus polynomial exponential operation quantum circuit; similarly, the square matrix corresponding to the plaintext parameter and the k quantum circuits constructed by the k-1 second square matrices are cascaded to obtain the second modulus polynomial exponential operation quantum circuit.

[0169] Step 604: Determine the private key corresponding to the ciphertext based on the operation result of the target quantum circuit;

[0170] The target quantum circuit runs on a quantum computing unit, which can be on a quantum computer or a quantum virtual machine. The classical computing unit sends the target quantum circuit to the quantum computing unit, which excites the quantum bits in the target quantum circuit to an initial state, and then applies corresponding analog signals to the quantum bits based on the quantum logic gates in the target quantum circuit, so that the initial state of the quantum bits evolves, and finally applies analog signals to measure the quantum bits, determines the operation result of the target quantum circuit, and feeds the result back to the classical computing unit.

[0171] The quantum computing unit executes the target quantum circuit for a specified number of times. The measured operation result may be in the form of an array. For example, for two quantum bits and 1024 execution times, the measurement results may be "00": 251, "01": 213, "10": 260, "11": 300, where "00", "01", "10", "11" are the measured quantum states, and "251, 213, 260, 300" are the times corresponding to the measured quantum states.

[0172] Step 605: Decrypt the ciphertext based on the private key.

[0173] To determine the private key corresponding to the ciphertext based on the running result, and to decrypt the ciphertext based on the private key, you can refer to the patent document with application number "202111365914.4" and invention name "Ciphertext decryption method and related equipment"; or refer to the patent document with application number "202111365902.1" and invention name "Ciphertext decryption method and related equipment".

[0174] It can be seen that the present invention converts the public key and plaintext parameters corresponding to the obtained ciphertext into a square matrix, the ciphertext is a ciphertext based on discrete logarithm encryption, and the public key and plaintext parameters both belong to elements in the finite field GF(p, k; then, based on the square matrix and the quantum circuit in the above method embodiment, a target quantum circuit is constructed and operated, the private key is determined by the operation result of the target quantum circuit, and the ciphertext is decrypted by the private key; the prior art requires more than 3000 years to decompose a binary number represented by 795 bits using the most efficient number field sieve method. Compared with the prior art, the present invention greatly realizes the ciphertext cracking speed based on discrete logarithm encryption through the superposition and entanglement characteristics of quantum computing.

[0175] Optionally, the quantum Fourier transform circuit includes an H gate acting on a first auxiliary bit and a second auxiliary bit, the first modulus polynomial exponential operation quantum circuit is controlled by the second auxiliary bit, the second modulus polynomial exponential operation quantum circuit is controlled by the first auxiliary bit, and the quantum inverse Fourier transform circuit includes quantum inverse Fourier transform modules each acting on the first auxiliary bit and the second auxiliary bit.

[0176] Among them, the quantum circuits corresponding to the L-type, U-type, and P-type matrices require at least qubits, so the first-mode polynomial exponential operation quantum circuit and the second-mode polynomial exponential operation quantum circuit also require at least A quantum bit.

[0177] The first modulus polynomial exponential operation quantum circuit is controlled by the second auxiliary bit, and the first polynomial exponential operation quantum circuit includes k items, each of which is controlled by A second auxiliary bit is controlled, so it is necessary The second auxiliary bit is controlled. Similarly, the second modulus polynomial exponential operation quantum circuit requires The first auxiliary bit is controlled.

[0178] Among them, the H gate is a single gate, and the H gate acts on the first auxiliary bit and the second auxiliary bit, so it is necessary An H gate.

[0179] Specifically, the quantum inverse Fourier transform circuit includes quantum inverse Fourier transform modules each acting on the first auxiliary bit and the second auxiliary bit, including: the quantum inverse Fourier transform circuit includes two quantum inverse Fourier transform modules, one of which acts on The first auxiliary bit and the other one acts on A second auxiliary bit.

[0180] like Figure 7 As shown, Figure 7A schematic diagram of a target quantum circuit provided by an embodiment of the present invention. The target quantum circuit includes The first auxiliary bit, The second auxiliary bit, data bits. The first auxiliary bit and The initial quantum states of the second auxiliary bits are all |0>, Except for the lowest bit of data whose initial quantum state is |1>, the other bits The initial quantum state of the quantum bits is |0>.

[0181] Among them, the square matrix corresponding to the public key a is A, and the first square matrix is ​​A2, A3...A k-1 , A k , the quantum circuit corresponding to matrix A is Mat A, and the quantum circuits corresponding to the first matrix are Mat2, MatA3,...,MatA k-1 、MatA k , each square matrix or the quantum circuit corresponding to the first square matrix is ​​controlled by the corresponding second auxiliary bit, and together constitutes the first modular polynomial exponential operation quantum circuit.

[0182] Among them, the square matrix corresponding to the plaintext parameter b is B, and the second square matrix is ​​B2, B3...B k-1 , B k , the quantum circuit corresponding to matrix B is Mat B, and the quantum circuits corresponding to the second matrix are Mat2, MatB3,...MatB k-1 MatB k , the quantum circuit corresponding to each square matrix or the second square matrix is ​​controlled by the corresponding second auxiliary bit, and together constitutes the second modular polynomial exponential operation quantum circuit.

[0183] The quantum Fourier transform operation is performed by an H gate acting on each first auxiliary bit and each second auxiliary bit, wherein a quantum inverse Fourier transform operation Acts on The first auxiliary bit, another quantum inverse Fourier transform operation Acts on A second auxiliary bit.

[0184] Optionally, the determining of the private key corresponding to the ciphertext based on the operation result of the target quantum circuit, wherein the operation result of the target quantum circuit includes a good number pair, includes:

[0185] Determine a first good number vector based on one of the good number pairs, and determine a second good number vector based on the other of the good number pairs;

[0186] Determine the inverse element of each element in the second good number vector to obtain a third good number vector;

[0187] determining a tensor product of the first good number vector and the third good number vector;

[0188] A private key corresponding to the ciphertext is determined from the tensor product.

[0189] Among them, the good number is the classical data obtained after good-state decoding of the quantum data, the good state is the quantum state obtained by measuring the first auxiliary bit or the second auxiliary bit, and the good number pair includes two good numbers, which are two good numbers corresponding to the two good states obtained by measuring the first auxiliary bit and the second auxiliary bit.

[0190] run Figure 7 The quantum circuit shown in the figure has The first auxiliary bit and By measuring the second auxiliary bit, we can get the good number pair s and t of the binary string and convert it into decimal. Then the discrete logarithm problem can be transformed into solving the congruence equation:

[0191] t×x=smod2 k

[0192] The solution to the above equation is not necessarily unique, and considering the measurement error (errors in s and t), it is necessary to expand the calculation range of the polynomial size.

[0193] Without considering the error, and assuming that the t measured above is not an even number, then 2 k and t are relatively prime, so there exists an integer t -1 ,satisfy:

[0194] t×t -1 =1mod2 k

[0195] Thus:

[0196] x=t×x×t -1 =s×t -1 mod2 k

[0197] The computational simulation can use the extended Euclidean algorithm, whose time complexity is log = 2 k = t, even if polynomial modular inverses are calculated, the above complexity can ensure that the total time complexity is at the polynomial level. Compared with traditional algorithms, its time complexity is greatly reduced.

[0198] Taking into account the measurement error (errors exist in s and t), it is necessary to expand the calculation range of the polynomial size. Specifically, determining the first good number vector based on one of the good number pairs includes: extending one of the good number pairs to both sides to obtain the first good number vector, for example, s and t may be extended to both sides to obtain the good number vector, for example, the first good number vectors long s and long t are respectively as follows:

[0199] longs=[s-ks-k+1···s-1ss+1···s+k-1s+k]

[0200] longt=[t-kt-k+1···t-1tt+1···t+k-1t+k]

[0201] Specifically, the inverse element of each element in the second good number vector long t is determined to obtain a third good number vector long t -1 :

[0202] longt -1 =[(tk) -1 ···t -1 ···(t+k) -1 ]

[0203] longs and longt -1 The tensor product of is:

[0204]

[0205] Finally, from the above tensor product of 4k 2 Determine the appropriate element from the elements as the private key x corresponding to the ciphertext.

[0206] See also Figure 8 , Figure 8 A schematic diagram of the structure of a quantum circuit construction device provided in an embodiment of the present invention, the device comprising:

[0207] The matrix decomposition unit 801 is used to perform LUP matrix decomposition on a matrix corresponding to a preset fixed polynomial to obtain L-type, U-type and P-type matrices;

[0208] The circuit construction unit 802 is used to construct a quantum circuit for calculating the multiplication operation of an arbitrary polynomial and a fixed polynomial based on the L-type, U-type and P-type matrices and a preset modulus operator, wherein the fixed polynomial and the arbitrary polynomial both belong to a finite field GF(p, k).

[0209] See also Fig. 9 , Fig. 9A ciphertext decryption device provided in an embodiment of the present invention is applied to ciphertext based on discrete logarithm encryption, and the device includes:

[0210] The acquisition unit 901 is used to acquire the public key and plain text parameters corresponding to the ciphertext, wherein the public key and plain text parameters both belong to the elements in the finite field GF(p, k);

[0211] A determination unit 902, configured to determine a square matrix corresponding to the public key and the plaintext parameter;

[0212] A construction unit 903, configured to construct a target quantum circuit based on the square matrix and the quantum circuit in any one of claims 1 to 4;

[0213] The determining unit 902 is further configured to determine a private key corresponding to the ciphertext based on the operation result of the target quantum circuit;

[0214] The decryption unit 904 is configured to decrypt the ciphertext based on the private key.

[0215] Regarding the specific functions and effects achieved by the quantum circuit construction device and the ciphertext decryption device, you can refer to the other embodiments of this specification for comparison and explanation, and will not repeat them here. The various modules in the quantum circuit construction device and the ciphertext decryption device can be implemented in whole or in part by software, hardware, and a combination thereof. The modules can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory of the computer device in the form of software, so that the processor can call and execute the operations corresponding to the above modules.

[0216] See also Fig.10 The present specification also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor implements the quantum circuit construction method or ciphertext decryption method in any of the above embodiments when executing the computer program. Fig.10 , the computer device may be a classical computer. The computer device may also be a quantum computer.

[0217] The embodiments of this specification also provide a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a computer, the computer executes the quantum circuit construction method or ciphertext decryption method in any of the above embodiments.

[0218] The embodiments of this specification also provide a computer program product including instructions, which, when executed by a computer, enables the computer to execute the quantum circuit construction method or ciphertext decryption method in any of the above embodiments.

[0219] It should be understood that the specific examples in this specification are only intended to help those skilled in the art to better understand the implementation methods of this specification, rather than to limit the scope of the present invention.

[0220] It can be understood that in the various implementations of this specification, the size of the sequence number of each process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the implementation methods of this specification.

[0221] It can be understood that the various embodiments described in this specification can be implemented individually or in combination, and the embodiments of this specification are not limited to this.

[0222] Unless otherwise specified, all technical and scientific terms used in the embodiments of this specification have the same meaning as those generally understood by those skilled in the art of the technical field of this specification. The terms used in this specification are only for the purpose of describing specific embodiments and are not intended to limit the scope of this specification. The term "and / or" used in this specification includes any and all combinations of one or more related listed items. The singular forms of "a", "above", and "the" used in the embodiments of this specification and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0223] It can be understood that the processor of the embodiment of this specification can be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method implementation can be completed by the hardware integrated logic circuit or software instructions in the processor. The above processor can be a general processor, a digital signal processor (Digital Signal Processor, DSP), an application specific integrated circuit (Application Specific Integrated Circuit, ASIC), a field programmable gate array (Field Programmable Gate Array, FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The disclosed methods, steps and logic block diagrams in the embodiment of this specification can be implemented or executed. The general processor can be a microprocessor or the processor can also be any conventional processor, etc. The steps of the method disclosed in the embodiment of this specification can be directly embodied as a hardware decoding processor to perform, or the hardware and software modules in the decoding processor are combined and executed. The software module can be located in a mature storage medium in the field such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc. The storage medium is located in the memory, and the processor reads the information in the memory and completes the steps of the above method in combination with its hardware.

[0224] It is understood that the memory in the embodiments of this specification may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memory. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (programmable ROM, PROM), an erasable programmable read-only memory (erasablePROM, EPROM), an electrically erasable programmable read-only memory (EEPROM) or a flash memory. The volatile memory may be a random access memory (RAM). It should be noted that the memory of the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0225] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this specification.

[0226] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method implementation methods and will not be repeated here.

[0227] In the several embodiments provided in this specification, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device implementation described above is only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0228] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0229] In addition, each functional unit in each embodiment of the present specification may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0230] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this specification, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the method described in each embodiment of this specification. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, etc., various media that can store program codes.

[0231] The above is only a specific implementation of this specification, but the protection scope of the present invention is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in this specification, which should be included in the protection scope of this specification. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A method for constructing a quantum circuit, characterized in that: The method comprises: Perform LUP matrix decomposition on the matrix corresponding to a preset fixed polynomial to obtain L-type, U-type and P-type matrices; A quantum circuit for calculating the multiplication of an arbitrary polynomial and a fixed polynomial is constructed based on the L-type, U-type and P-type matrices and a preset modulus operator, wherein both the fixed polynomial and the arbitrary polynomial belong to a finite field GF(p, k).

2. The method according to claim 1, characterized in that The quantum circuit for calculating the multiplication operation of an arbitrary polynomial and a fixed polynomial based on the L-type, U-type and P-type matrices and a preset modulus operator comprises: Constructing a quantum circuit corresponding to the L-type matrix based on the L-type matrix and a preset modulus operator, constructing a quantum circuit corresponding to the U-type matrix based on the U-type matrix and a preset modulus operator, and constructing a quantum circuit corresponding to the P-type matrix based on the P-type matrix and a SWAP gate; The quantum circuits corresponding to the L-type matrix, the U-type matrix and the P-type matrix are sequentially cascaded to obtain a quantum circuit for calculating the multiplication operation of an arbitrary polynomial and the fixed polynomial.

3. The method according to claim 2, characterized in that The modulus operator includes a modulus addition operator and a modulus multiplication operator, and the quantum circuit corresponding to the L-type matrix is ​​constructed based on the L-type matrix and the preset modulus operator, including: Determine the non-zero elements of each row in the L-type matrix; A quantum circuit corresponding to the L-type matrix is ​​constructed based on the non-zero elements of each row and the modular addition operator and the modular multiplication operator.

4. The method according to claim 2, characterized in that The step of constructing a quantum circuit corresponding to the P-type matrix based on the P-type matrix and the SWAP gate includes: Determine the non-zero elements a in the P-type matrix except the diagonal mn ; If m is less than n, the SWAP gate is applied to the mth and nth qubits; If m is greater than n, determine the non-zero element a m′n′ , and apply the SWAP gate to the mth and n′th qubits, m′ is less than m, and n′ is greater than m; If m is equal to n or n′, no operation is performed; The quantum circuit corresponding to the P-type matrix is ​​determined.

5. A ciphertext decryption method, characterized in that: Applied to ciphertext based on discrete logarithm encryption, the method comprises: Obtain a public key and a plaintext parameter corresponding to the ciphertext, wherein the public key and the plaintext parameter both belong to an element in a finite field GF(p, k); Determine the square matrix corresponding to the public key and the plaintext parameters; Constructing a target quantum circuit based on the square matrix and the quantum circuit in any one of claims 1 to 4; Determining a private key corresponding to the ciphertext based on the operation result of the target quantum circuit; The ciphertext is decrypted based on the private key.

6. The method according to claim 5, characterized in that The method of constructing a target quantum circuit based on the square matrix and the quantum circuit in any one of claims 1 to 4 comprises: Performing a square operation on the square matrix corresponding to the public key a preset number of times to obtain a plurality of first square matrices; and performing a square operation on the square matrix corresponding to the plaintext parameter a preset number of times to obtain a plurality of second square matrices; Based on the quantum circuit in any one of claims 1 to 4, determine the square matrix corresponding to the public key and the first modulus polynomial exponential operation quantum circuits corresponding to the first square matrix, and the square matrix corresponding to the plaintext parameter and the second modulus polynomial exponential operation quantum circuits corresponding to the second square matrix; The quantum Fourier transform circuit, the first modulus polynomial exponential operation quantum circuit, the second modulus polynomial exponential operation quantum circuit and the quantum inverse Fourier transform circuit are sequentially cascaded to obtain a target quantum circuit.

7. The method according to claim 6, characterized in that The method of determining the square matrix corresponding to the public key and the first modulus polynomial exponential operation quantum circuits corresponding to the plurality of the first square matrices based on the quantum circuit in any one of claims 1 to 4 comprises: The square matrix corresponding to the public key and the plurality of the first square matrices are respectively used as the fixed polynomials in any one of claims 1 to 4, and a first modular polynomial exponential operation quantum circuit is determined based on the fixed polynomials.

8. A quantum circuit construction device, characterized in that: The device comprises: A matrix decomposition unit, used for performing LUP matrix decomposition on a matrix corresponding to a preset fixed polynomial to obtain L-type, U-type and P-type matrices; A circuit construction unit is used to construct a quantum circuit for calculating the multiplication operation of an arbitrary polynomial and a fixed polynomial based on the L-type, U-type and P-type matrices and a preset modulus operator, wherein both the fixed polynomial and the arbitrary polynomial belong to a finite field GF(p, k).

9. A ciphertext decryption device, characterized in that: Applied to ciphertext based on discrete logarithm encryption, the device comprises: An acquisition unit is used to acquire a public key and a plaintext parameter corresponding to the ciphertext, wherein the public key and the plaintext parameter both belong to an element in a finite field GF(p, k; A determination unit, used to determine the square matrix corresponding to the public key and the plaintext parameter; A construction unit, used to construct a target quantum circuit based on the square matrix and the quantum circuit in any one of claims 1 to 4; The determining unit is further used to determine the private key corresponding to the ciphertext based on the operation result of the target quantum circuit; A decryption unit is used to decrypt the ciphertext based on the private key.

10. A storage medium, characterized in that: The storage medium stores a computer program, wherein the computer program is configured to execute the method described in any one of claims 1 to 4 or 5 to 7 when executed.

11. An electronic device comprising a memory and a processor, characterized in that: A computer program is stored in the memory, and the processor is configured to run the computer program to perform the method described in any one of claims 1 to 4 or 5 to 7.

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