Voltage control method and device and storage medium

Abstract

The embodiment of the invention provides a voltage control method and device and a storage medium, and is applied to the technical field of terminals. The method is applied to the electronic equipment with a pixel circuit, the pixel circuit comprises a driving module, the control end of the driving module is connected with a first node, and the source end of the driving module is connected with a second node; the method comprises the steps of controlling the voltage of a first node to be a first voltage and controlling the voltage of a second node to be a second voltage when a first region of a first frame image is driven and displayed; controlling the voltage of the first node to be a third voltage and controlling the voltage of the second node to be a fourth voltage when a second region of the first frame image is driven and displayed; wherein the voltage difference value between the first voltage and the second voltage is greater than the voltage difference value between the third voltage and the fourth voltage; the refresh rate of the first region is a first refresh rate, the refresh rate of the second region is a second refresh rate, and the first refresh rate is lower than the second refresh rate. Therefore, the occurrence probability of flicker of the display panel of the electronic equipment can be reduced.

Description

Technical Field

[0001] The present application relates to the field of terminal technology, and in particular to a voltage control method, device and storage medium. Background Art

[0002] With the development of terminal technology, electronic devices provide the function of displaying dynamic images in one area of ​​the display panel and static images in other areas of the display panel. In order to reduce the power consumption of electronic devices, the refresh rate of the static image display area is lower than the refresh rate of the dynamic image display area.

[0003] However, when the static image display area switches to display a dynamic image, or the dynamic image display area switches to display a static image, the display panel of the electronic device may flicker. Summary of the invention

[0004] The embodiments of the present application provide a voltage control method, device and storage medium, which are applied to the field of terminal technology. Since the image may be refreshed at a high refresh rate when a dynamic image is displayed, and the image may be refreshed at a low refresh rate when a static image is displayed, by controlling the gate voltage of the driving thin film transistor in the pixel circuit, the gate voltage of the driving thin film transistor in the light-emitting stage when the image is refreshed at a low refresh rate is reduced, and the difference between the gate voltage of the driving thin film transistor in the light-emitting stage when the image is refreshed at a high refresh rate is reduced, which can reduce the brightness difference between the static image display area and the dynamic image display area within the surface of the display panel, thereby reducing the probability of flickering of the display panel when the refresh rate of the display area is switched.

[0005] In a first aspect, an embodiment of the present application provides a voltage control method, which is applied to an electronic device having a pixel circuit, wherein the pixel circuit includes a driving module, a control end of the driving module is connected to a first node, and a source end of the driving module is connected to a second node; the method includes:

[0006] When driving the first area to display the first frame image, controlling the voltage of the first node to be the first voltage, and controlling the voltage of the second node to be the second voltage;

[0007] When driving the second area to display the first frame image, controlling the voltage of the first node to be the third voltage, and controlling the voltage of the second node to be the fourth voltage;

[0008] Among them, the voltage difference between the first voltage and the second voltage is greater than the voltage difference between the third voltage and the fourth voltage; the refresh rate of the first area is the first refresh rate, the refresh rate of the second area is the second refresh rate, and the first refresh rate is lower than the second refresh rate.

[0009] In this way, when the electronic device drives to display an image, the voltage difference between the first node and the second node of the driving module corresponding to the first area and the voltage difference between the first node and the second node of the driving module corresponding to the second area can be reduced.

[0010] In a possible implementation manner, the first voltage is greater than the third voltage, and / or the second voltage is less than the fourth voltage.

[0011] In this way, when the electronic device drives to display an image, the voltage difference between the first node and the second node of the driving module corresponding to the first area and the voltage difference between the first node and the second node of the driving module corresponding to the second area can be reduced.

[0012] In a possible implementation, the pixel circuit further includes a data writing unit, the data writing unit is connected to the second node; when the first area and the second area of ​​the first frame image are displayed, the data writing unit is enabled; and the method further includes:

[0013] When driving the first area to display the second frame image, controlling the voltage of the first node to be the first voltage, and controlling the voltage of the second node to be the second voltage; when displaying the first area of ​​the second frame image, the data writing unit is not enabled;

[0014] When driving the second area to display the second frame image, the voltage of the first node is controlled to be the third voltage, and the voltage of the second node is controlled to be the fourth voltage; when displaying the second area of ​​the second frame image, the data writing unit is enabled.

[0015] In this way, when the electronic device drives to display an image, the voltage difference between the first node and the second node of the driving module corresponding to the first area and the voltage difference between the first node and the second node of the driving module corresponding to the second area can be reduced.

[0016] In a possible implementation, the method further includes:

[0017] When driving the first area to display the third frame image, controlling the voltage of the first node to be the first voltage, and controlling the voltage of the second node to be the second voltage; when displaying the first area of ​​the third frame image, the data writing unit is not enabled;

[0018] When driving the second area to display the third frame image, the voltage of the first node is controlled to be the third voltage, and the voltage of the second node is controlled to be the fourth voltage; when displaying the second area of ​​the third frame image, the data writing unit is enabled.

[0019] In this way, when the electronic device drives to display an image, the voltage difference between the first node and the second node of the driving module corresponding to the first area and the voltage difference between the first node and the second node of the driving module corresponding to the second area can be reduced.

[0020] In a possible implementation, the method further includes:

[0021] When driving the first area to display the fourth frame image, controlling the voltage of the first node to be the third voltage, and controlling the voltage of the second node to be the fourth voltage; when displaying the first area of ​​the fourth frame image, the data writing unit is not enabled;

[0022] When driving the second area to display the fourth frame image, the voltage of the first node is controlled to be the third voltage, and the voltage of the second node is controlled to be the fourth voltage; when displaying the second area of ​​the fourth frame image, the data writing unit is enabled.

[0023] In this way, when the electronic device drives to display an image, the power consumption of the electronic device can be reduced.

[0024] In a possible implementation, the pixel circuit further includes a data writing unit, the data writing unit is connected to the second node; when the first area and the second area of ​​the first frame image are displayed, the data writing unit is enabled; and the method further includes:

[0025] When driving the first area to display the second frame image, controlling the voltage of the first node to be the third voltage, and controlling the voltage of the second node to be the fourth voltage; when displaying the first area of ​​the second frame image, the data writing unit is not enabled;

[0026] When driving the second area to display the second frame image, the voltage of the first node is controlled to be the third voltage, and the voltage of the second node is controlled to be the fourth voltage; when displaying the second area of ​​the second frame image, the data writing unit is enabled.

[0027] In this way, when the electronic device drives to display an image, the power consumption of the electronic device can be reduced.

[0028] In a possible implementation, the method further includes:

[0029] Determine a starting position and an ending position of the first region based on an identifier of a pixel circuit corresponding to the first region;

[0030] Based on the identifier of the pixel circuit corresponding to the second area, the starting position and the ending position of the second area are determined.

[0031] In this way, when the electronic device is driven to display an image, the accuracy and integrity of the image display can be improved.

[0032] In a possible implementation, the method further includes:

[0033] When driving the third area to display the first frame image, the voltage of the first node is controlled to be the first voltage, and the voltage of the second node is controlled to be the second voltage; the refresh rate of the third area is the third refresh rate, and the third refresh rate is lower than the second refresh rate.

[0034] In this way, images can be displayed in multiple display areas, improving the user experience of the electronic device.

[0035] In a possible implementation, the driving module includes a driving thin film transistor DTFT, a drain terminal of the DTFT is connected to the third node, and the DTFT is used to output current to the third node under the control of the first node;

[0036] The pixel circuit also includes:

[0037] A first reset unit, connected to the first node, for responding to a first reset signal to load a first initialization voltage to the first node;

[0038] A storage capacitor, one end of which is connected to the first node, and the other end of which is connected to the positive electrode of the power supply;

[0039] A first light-emitting control unit, connected to the positive electrode of the power supply and the second node, for loading a first power supply voltage of the positive electrode of the power supply to the second node in response to a light-emitting control signal;

[0040] a threshold compensation unit connected to the first node and the third node, and configured to make the third node conductive with the first node in response to the first scanning signal;

[0041] a second light emitting control unit connected to the third node and the fourth node, and configured to conduct the third node and the fourth node in response to a light emitting control signal;

[0042] A light emitting element, one end of which is connected to the fourth node, and the other end of which is connected to the negative electrode of the power supply to load the second power supply voltage of the negative electrode of the power supply;

[0043] A second reset unit, connected to the fourth node, for loading a second initialization voltage to the fourth node in response to a second reset signal;

[0044] A data writing unit connected to the second node and used for loading a data voltage to the second node in response to a second scanning signal;

[0045] The third reset unit is connected to the second node and is used for loading a third initialization voltage to the second node in response to the second reset signal.

[0046] In this way, when the electronic device drives to display an image, the voltage difference between the first node and the second node of the driving module corresponding to the first area and the voltage difference between the first node and the second node of the driving module corresponding to the second area can be reduced, thereby reducing the probability of flickering of the display panel of the electronic device.

[0047] In one possible implementation, the first reset unit includes a first reset transistor, the first light-emitting control unit includes a first light-emitting control transistor, the threshold compensation unit includes a threshold compensation transistor, the second light-emitting control unit includes a second light-emitting control transistor, the light-emitting element includes an organic light-emitting diode OLED, the second reset unit includes a second reset transistor, the data writing unit includes a data writing transistor, and the third reset unit includes a third reset transistor.

[0048] In this way, when the electronic device drives to display an image, the voltage difference between the first node and the second node of the driving module corresponding to the first area and the voltage difference between the first node and the second node of the driving module corresponding to the second area can be reduced, thereby reducing the probability of flickering of the display panel of the electronic device.

[0049] In a second aspect, an embodiment of the present application provides an electronic device, including: a processor, a display driver chip DDIC, a pixel circuit and a memory;

[0050] Memory stores computer-executable instructions;

[0051] The processor instructs the display driver chip to drive the pixel circuit;

[0052] The display driving chip executes the computer execution instructions stored in the memory, so that the electronic device executes the method of the first aspect and drives the pixel circuit.

[0053] In a third aspect, an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a display driver chip DDIC, the method of the first aspect is implemented.

[0054] In a fourth aspect, an embodiment of the present application provides a computer program product, which includes a computer program. When the computer program is executed, the computer executes the method of the first aspect.

[0055] In a fifth aspect, an embodiment of the present application provides a chip, the chip including a processor, the processor being used to call a computer program in a memory to execute the method of the first aspect.

[0056] It should be understood that the second to fifth aspects of the present application correspond to the technical solutions of the first aspect of the present application, and the beneficial effects achieved by each aspect and the corresponding feasible implementation methods are similar and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] Figure 1 A schematic diagram of the structure of a display panel provided in an embodiment of the present application;

[0058] Figure 2Schematic diagram of a pixel circuit provided in an embodiment of the present application Figure 1 ;

[0059] Figure 3 The level timing diagram of each signal provided in the embodiment of the present application is as follows Figure 1 ;

[0060] Figure 4 A comparison diagram of the number of times the transistor T4 is enabled in the high-frequency display area and the low-frequency display area when the electronic device provided in the embodiment of the present application refreshes an image;

[0061] Figure 5 The level timing diagram of each signal corresponding to the low-frequency display area provided in the embodiment of the present application and the schematic diagram of each initialization voltage Figure 1 ;

[0062] Figure 6 A level timing diagram of each signal corresponding to the high-frequency display area and a schematic diagram of each initialization voltage provided in an embodiment of the present application;

[0063] Figure 7 The timing sequence of the bias voltage when refreshing the image of the electronic device provided in the embodiment of the present application Figure 1 ;

[0064] Figure 8 The timing sequence of the bias voltage when refreshing the image of the electronic device provided in the embodiment of the present application Figure 2 ;

[0065] Fig. 9 The level timing diagram of each signal corresponding to the low-frequency display area provided in the embodiment of the present application and the schematic diagram of each initialization voltage Figure 2 ;

[0066] Fig.10 The timing sequence of the bias voltage when refreshing the image of the electronic device provided in the embodiment of the present application Figure 3 ;

[0067] Fig.11 The timing sequence of the bias voltage when refreshing the image of the electronic device provided in the embodiment of the present application Figure 4 ;

[0068] Fig.12 The level timing diagram of each signal corresponding to the low-frequency display area provided in the embodiment of the present application and the schematic diagram of each initialization voltage Figure 3 ;

[0069] Fig.13 The timing sequence of the bias voltage when refreshing the image of the electronic device provided in the embodiment of the present application Figure 5 ;

[0070] Fig.14 The timing sequence of the bias voltage when refreshing the image of the electronic device provided in the embodiment of the present application Figure 6 ;

[0071] Fig.15 Schematic diagram of a pixel circuit provided in an embodiment of the present application Figure 2 ;

[0072] Fig.16 A schematic diagram of the structure of an electronic device 100 provided in an embodiment of the present application;

[0073] Fig.17 A software structure block diagram of the electronic device 100 provided in an embodiment of the present application. DETAILED DESCRIPTION

[0074] In order to clearly describe the technical solutions of the embodiments of the present application, some terms and technologies involved in the embodiments of the present application are briefly introduced below:

[0075] 1. Some terms

[0076] In the embodiments of the present application, words such as "first" and "second" are used to distinguish the same or similar items with substantially the same functions and effects. For example, the first chip and the second chip are only used to distinguish different chips, and their order is not limited. Those skilled in the art can understand that words such as "first" and "second" do not limit the quantity and execution order, and words such as "first" and "second" do not necessarily limit them to be different.

[0077] It should be noted that in the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0078] In the embodiments of the present application, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, ab, a--c, bc, or abc, where a, b, c can be single or multiple.

[0079] It should be noted that the "at..." in the embodiment of the present application can be the instant when a certain situation occurs, or a period of time after a certain situation occurs, and the embodiment of the present application does not specifically limit this. In addition, the display interface provided in the embodiment of the present application is only an example, and the display interface can also include more or less content.

[0080] 2. Electronic equipment

[0081] The electronic device of the embodiment of the present application may include a handheld device, a vehicle-mounted device, etc. with an image processing function. For example, some electronic devices are: mobile phones, tablet computers, PDAs, laptop computers, mobile internet devices (MIDs), wearable devices, virtual reality (VR) devices, augmented reality (AR) devices, wireless terminals in industrial control, wireless terminals in self driving, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, wireless terminals in smart homes, cellular phones, cordless phones, session initiation protocol (SIP) phones, wireless local loop (WLL) stations, personal digital assistants (PDAs), handheld devices with wireless communication capabilities, computing devices or other processing devices connected to wireless modems, vehicle-mounted devices, wearable devices, terminal devices in 5G networks or future evolved public land mobile communication networks (PLANs), and wireless terminals in smart cities. The embodiments of the present application do not limit this.

[0082] As an example but not limitation, in the embodiments of the present application, the electronic device may also be a wearable device. Wearable devices may also be referred to as wearable smart devices, which are a general term for wearable devices that are intelligently designed and developed using wearable technology for daily wear, such as hearing aids, glasses, gloves, watches, clothing, and shoes. A wearable device is a portable device that is worn directly on the body or integrated into the user's clothes or accessories. Wearable devices are not only hardware devices, but also powerful functions achieved through software support, data interaction, and cloud interaction. Broadly speaking, wearable smart devices include full-featured, large-sized, and fully or partially independent of smartphones, such as smart watches or smart glasses, as well as devices that only focus on a certain type of application function and need to be used in conjunction with other devices such as smartphones, such as various types of smart bracelets and smart jewelry for vital sign monitoring.

[0083] In addition, in the embodiments of the present application, the electronic device can also be a terminal device in the Internet of Things (IoT) system. IoT is an important part of the future development of information technology. Its main technical feature is to connect objects to the network through communication technology, thereby realizing an intelligent network that interconnects people and machines and things.

[0084] The electronic devices in the embodiments of the present application may also be referred to as: user equipment (UE), mobile station (MS), mobile terminal (MT), access terminal, user unit, user station, mobile station, mobile station, remote station, remote terminal, mobile device, user terminal, terminal, wireless communication equipment, user agent or user device, etc.

[0085] In an embodiment of the present application, the electronic device or each network device includes a hardware layer, an operating system layer running on the hardware layer, and an application layer running on the operating system layer. The hardware layer includes hardware such as a central processing unit (CPU), a memory management unit (MMU), and a memory (also called main memory). The operating system can be any one or more computer operating systems that implement business processing through processes, such as Linux operating system, Unix operating system, Android operating system, iOS operating system, or Windows operating system. The application layer includes applications such as browsers, address books, word processing software, and instant messaging software.

[0086] In a possible implementation, an electronic device includes a display panel. Figure 1 Schematic diagram of the structure of the display panel is shown. Figure 1As shown, the display panel includes a light control signal generating unit, a first reset signal generating unit, a second scan signal generating unit, a display area for displaying an image, a second scan signal generating unit, a first scan signal generating unit, a second reset signal generating unit and a display driver chip (display driver integrated circuit, DDIC). The display area includes a plurality of pixel circuits of an array. The light control signal generating unit, the first reset signal generating unit, the second scan signal generating unit, the display area for displaying an image, the second scan signal generating unit, the first scan signal generating unit, the second reset signal generating unit and the display driver chip can transmit their respective corresponding signals to each pixel circuit through a lead. The display driver chip can control the transmission of the corresponding signals of the light control signal generating unit, the first reset signal generating unit, the second scan signal generating unit, the display area for displaying an image, the second scan signal generating unit, the first scan signal generating unit and the second reset signal generating unit. The pixel circuit includes a driving thin film transistor and a light emitting element. The driving thin film transistor is used to drive the light emitting element to emit light. The light emitting element can be used as a sub-pixel of the display panel. The electronic device realizes the function of displaying dynamic images and static images on the display panel by driving and controlling the corresponding pixel circuits of the display area.

[0087] The display area may include a high-frequency display area and a low-frequency display area. The high-frequency display area refreshes the image at a high-frequency refresh rate. The low-frequency display area refreshes the image at a low-frequency refresh rate. When a dynamic image is displayed, the image may be refreshed at a high refresh rate. When a static image is displayed, the image may be refreshed at a low refresh rate. In a possible implementation, under the same data voltage, there is a difference between the brightness of the display area at a low-frequency refresh rate and the brightness of the display area at a high-frequency refresh rate. When the refresh rate of the display area is switched from a low refresh rate to a high refresh rate, or the refresh rate of the display area is switched from a high refresh rate to a low refresh rate, the display area where the refresh rate is switched will flicker, and the display panel of the electronic device will also flicker.

[0088] In view of this, an embodiment of the present application provides a voltage control method, which controls the gate voltage of the driving thin film transistor to reduce the difference between the gate voltage of the driving thin film transistor during low-frequency display and the gate voltage of the driving thin film transistor during high-frequency display, thereby reducing the brightness difference between the high-frequency and low-frequency display areas within the surface of the display panel, thereby reducing the probability of the display panel flickering when the refresh rate of the display area is switched.

[0089] The voltage control method provided in the embodiments of the present application is described below in conjunction with some embodiments.

[0090] Figure 2 Schematic diagram of a pixel circuit provided in an embodiment of the present application Figure 1 .like Figure 2 As shown, the pixel circuit includes a plurality of thin film transistors (TFT), a capacitor C1, and a light emitting element. The light emitting element may include an organic light-emitting diode (OLED).

[0091] In the embodiments of the present application, a thin film transistor may be referred to as a transistor or a TFT transistor for short.

[0092] Multiple thin film transistors, e.g. Figure 2 Shown are transistor T1, transistor T2, transistor T3, transistor T4, transistor T5, transistor T6, transistor T7 and transistor T8.

[0093] Among them, transistor T3 is a driving TFT (DTFT) for driving the light emitting element to emit light. Transistor T2 is a compensation transistor for controlling the charging of capacitor C1 and the conduction of transistor T3. Transistors T1 and T2 may include oxide transistors. Other transistors may include transistors of low temperature polysilicon (LTPS) technology.

[0094] like Figure 2 As shown, the transistor T1 is connected to the first node N1 and is used to load the first initialization voltage to the first node N1 in response to the first reset signal. The first reset signal can be called ResetN. The first initialization voltage can be called Vinit1.

[0095] The capacitor C1 has one end connected to the first node N1 and the other end connected to the positive power supply VDD. The first node N1 may be referred to as an N1 node or an N1 point.

[0096] The transistor T5 is connected to the positive power source VDD and the second node N2, and is used to load the first power supply voltage of the positive power source VDD to the second node N2 in response to the light emitting control signal. The light emitting control signal can be called EM. The second node N2 can be called N2 node or N2 point.

[0097] The transistor T3 is connected to the first node N1, the second node N2 and the third node N3, and is used to output current to the third node N3 under the control of the first node N1. The third node N3 may be referred to as an N3 node or an N3 point.

[0098] The transistor T2 is connected to the first node N1 and the third node N3, and is used to conduct the third node N3 and the first node N1 in response to the first scan signal. The first scan signal may be referred to as GateN.

[0099] The transistor T6 is connected to the third node N3 and the fourth node N4, and is used for conducting the third node N3 and the fourth node N4 in response to the light emitting control signal.

[0100] The light emitting element has one end connected to the fourth node N4 and the other end connected to the negative power electrode VSS to load the second power voltage of the negative power electrode VSS.

[0101] The transistor T7 is connected to the fourth node N4 and is used to load the second initialization voltage to the fourth node N4 in response to the second reset signal. The second reset signal may be referred to as ResetP. The second initialization voltage may be referred to as Vinit2.

[0102] The transistor T4 is connected to the second node N2 and is used to load a data voltage to the second node N2 in response to a second scan signal. The second scan signal may be referred to as GateP. The data voltage may be referred to as Vdata.

[0103] The transistor T8 is connected to the second node N2 and is used to load a third initialization voltage to the second node N2 in response to the second reset signal. The third initialization voltage may be referred to as Vinit3.

[0104] In the embodiment of the present application, the "on" state of the transistor refers to the state in which the source and drain of the transistor are electrically connected. The "off" state of the transistor refers to the state in which the source and drain of the transistor are electrically disconnected. It can be understood that when the transistor is turned off, it can still have leakage current. The on condition of transistors T1 and T2 is: Vgs>Vth. The on condition of the remaining transistors is: Vgs<Vth. The high level in the embodiment of the present application can meet the on condition of transistors T1 and T2, and the low level in the embodiment of the present application can meet the on condition of the remaining transistors. Transistor T4 is turned on and loads the data voltage to the second node N2, which can be called transistor T4 enabled. Transistor T4 is not turned on or transistor T4 is in the off state, and no data voltage is loaded to the second node N2, which can be called transistor T4 disabled. Transistor T2 is turned on, which can be called transistor T2 enabled. Transistor T2 is not turned on or transistor T2 is in the off state, which can be called transistor T2 disabled. When the transistor T1 is turned on, it can be called that the transistor T1 is enabled. When the transistor T1 is not turned on or the transistor T1 is in the cut-off state, it can be called that the transistor T1 is disabled.

[0105] When an electronic device refreshes a frame of image to display on a display panel, it can drive and control the pixel circuit in a row driving mode or in a column driving mode. The principles of the two are similar. The following takes the example of the electronic device driving and controlling the pixel circuit in a row driving mode as an example.

[0106] Every time the electronic device refreshes a frame of image, the operation of the pixel circuit may include a reset phase, a write phase, a light-emitting waiting phase and a light-emitting phase.

[0107] Figure 3 The level timing diagram of each signal provided in the embodiment of the present application is as follows Figure 1 The following combination Figure 2 and Figure 3 , the various stages of operation of the pixel circuit when an electronic device refreshes a frame of image are explained.

[0108] When an electronic device refreshes a frame of image, if transistors T1, T4 and T2 are enabled, the display area of ​​this frame of image corresponds to the various stages of operation of the pixel circuit as shown in (1.1)-(1.4) below.

[0109] (1.1) Reset phase:

[0110] The light emission control signal (EM) is at a high level, and the transistors T5 and T6 are in a cut-off state.

[0111] The first reset signal (ResetN) changes from a low level to a high level. The high level of the first reset signal turns on the transistor T1.

[0112] The second reset signal (ResetP) changes from high level to low level, and then changes from low level to high level. The low level start time of the second reset signal (ResetP) is earlier than the high level start time of the first reset signal (ResetN). The low level of the second reset signal turns on transistors T8 and T7.

[0113] The first scanning signal (GateN) changes from high level to low level, and then changes from low level to high level. The low level start time and end time are both within the high level time period of the first reset signal. The high level of the first scanning signal turns on the transistor T2, and then turns on the N1 node and the N3 node.

[0114] The second scanning signal (GateP) is at a high level, and the transistor T4 is in a cut-off state.

[0115] The turned-on transistor T1 loads the first initialization voltage Vinit1 to the point N1, resets the point N1, and clears the potential written in the previous frame. Thus, the first initialization voltage Vinit1 is also written to the capacitor C1. The turned-on transistor T2 also loads the first initialization voltage Vinit1 to the point N3, resets the point N3, and clears the residual signal that may exist in the previous stage.

[0116] The turned-on transistor T8 loads the third initialization voltage Vinit3 to the point N2, and writes the initial state voltage Vinit3 to the point N2. At this time, the gate-source voltage difference Vgs of the transistor T3 is the voltage difference between the points N1 and N2, that is, Vgs is the voltage difference between Vinit1 and Vinit3. At this time, Vgs is greater than the threshold voltage Vth of the transistor T3, so that the transistor T3 is not turned on.

[0117] The turned-on transistor T7 loads the second initialization voltage Vinit2 to the point N4, and writes the initial state voltage Vinit2 into the point N4.

[0118] (1.2) Writing phase:

[0119] The light emission control signal (EM) maintains a high level, and the transistors T5 and T6 are in a cut-off state.

[0120] The first reset signal (ResetN) changes from a high level to a low level, so that the transistor T1 is in a cut-off state.

[0121] The second reset signal (ResetP) maintains a high level. The transistor T8 and the transistor T7 are both in the cut-off state.

[0122] The first scanning signal (GateN) maintains a high level. The high level of the first scanning signal (GateN) turns on the transistor T2, and then turns on N1 and N3.

[0123] The second scanning signal (GateP) changes from a high level to a low level, and then from a low level to a high level. The low level of the second scanning signal (GateP) turns on transistor T4. The turned-on transistor T4 loads the data voltage Vdata to the N2 node. Since the capacitor C1 can discharge to the transistor T3, the transistor T3 is turned on. Therefore, the turned-on transistor T4 can feed back the data voltage Vdata to N1 through the transistors T3 and T2, and charge the capacitor C1. The voltage at point N1 is Vdata+Vth. Vth is the threshold voltage of transistor T3. When transistor T4 is turned on, the voltage at point N2 is Vdata.

[0124] (1.3) Waiting stage for luminescence:

[0125] The light emission control signal (EM) maintains a high level, and the transistors T5 and T6 are in a cut-off state.

[0126] The first reset signal (ResetN) maintains a low level, and the transistor T1 is in a cut-off state.

[0127] The second reset signal (ResetP) changes from high level to low level, and then changes from low level to high level. The low level of the second reset signal turns on transistors T8 and T7. The high level of the second reset signal turns on transistors T8 and T7. Both transistors T8 and transistor T7 are in the cut-off state.

[0128] The first scanning signal (GateN) is at a low level, so that the transistor T2 is in a cut-off state.

[0129] The second scanning signal (GateP) maintains a high level, and the transistor T4 is in a cut-off state.

[0130] The turned-on transistor T8 loads the third initialization voltage Vinit3 to the point N2, and writes the initial state voltage Vinit3 into the point N2.

[0131] The turned-on transistor T7 loads the second initialization voltage Vinit2 to the N4 point, and writes the initial state voltage Vinit2 to the N4 point. In this way, the light emitting element is reset before the light emitting element emits light, thereby reducing the influence of the residual signal in the previous stage on the light emitting element.

[0132] The capacitor C1 can discharge the transistor T3 , and the gate-source voltage difference of the transistor T3 is greater than the threshold voltage Vth of the transistor T3 , so the transistor T3 is not turned on.

[0133] (1.4) Lighting stage:

[0134] Capacitor C1 can maintain the N1 voltage of transistor T3.

[0135] The light emitting control signal (EM) changes from high level to low level. The low level of the light emitting control signal turns on transistors T5 and T6. The first power supply voltage of the positive power supply (VDD) is written to the N2 node, Vgs of transistor T3 is less than Vth, and transistor T3 is turned on.

[0136] The first reset signal (ResetN) maintains a low level, and the transistor T1 is in a cut-off state.

[0137] The second reset signal (ResetP) maintains a high level, and transistors T7 and T8 are in a cut-off state.

[0138] The first scanning signal (GateN) maintains a low level, and the transistor T2 is in a cut-off state.

[0139] The second scanning signal (GateP) maintains a high level, and the transistor T4 is in a cut-off state.

[0140] The turned-on transistor T5 loads the first power supply voltage at the positive pole of the power supply to the N2 point. The turned-on transistor T3 turns on. The turned-on transistor T6 turns on the N3 and N4 points. One end of the light-emitting element is loaded with the second power supply voltage at the negative pole of the power supply. The light-emitting element starts to emit light.

[0141] When the light-emitting element emits light, the transistor T3 divides the voltage, so that the brightness of the light-emitting element is controlled by the transistor T3. The voltage division of the transistor T3 is affected by the gate voltage of the transistor T3, that is, the voltage of N1. For example, the larger the gate-source voltage difference of the transistor T3, the smaller the current flowing through the transistor T3, the light-emitting element is connected in series with the transistor T3, the smaller the current flowing through the light-emitting element, and the lower the brightness of the light-emitting element.

[0142] When an electronic device refreshes a frame of image, if transistors T1, T4 and T2 are not enabled, the display area of ​​this frame of image corresponds to the various stages of operation of the pixel circuit as shown in (2.1)-(2.4) below.

[0143] (2.1) Reset phase:

[0144] The light emission control signal (EM) is at a high level, and the transistors T5 and T6 are in a cut-off state.

[0145] The first reset signal (ResetN) maintains a low level, and the transistor T1 remains in the off state.

[0146] The second reset signal (ResetP) changes from a high level to a low level, and then changes from a low level to a high level. Similar to the reset phase shown in (1.1), the low level of the second reset signal turns on transistors T8 and T7. The turned-on transistor T8 loads the third initialization voltage Vinit3 to point N2, and writes the third initialization voltage Vinit3 to point N2. The turned-on transistor T7 loads the second initialization voltage Vinit2 to point N4, and writes the initial state voltage Vinit2 to point N4.

[0147] The first scanning signal (GateN) maintains a low level, and the transistor T2 is in a cut-off state.

[0148] The second scanning signal (GateP) is at a high level, and the transistor T4 remains in the off state.

[0149] The capacitor C1 can discharge to the transistor T3, and the transistor T3 is in the cut-off state. The gate voltage of the transistor T3 is the voltage at the point N1.

[0150] (2.2) Writing phase:

[0151] The light emission control signal (EM) maintains a high level, and the transistors T5 and T6 are in a cut-off state.

[0152] The first reset signal (ResetN) maintains a low level, and the transistor T1 is in a cut-off state.

[0153] The second reset signal (ResetP) maintains a high level, and transistors T7 and T8 are in a cut-off state.

[0154] The first scanning signal (GateN) maintains a low level, and the transistor T2 is in a cut-off state.

[0155] The second scanning signal (GateP) maintains a high level, and the transistor T4 is in a cut-off state.

[0156] The capacitor C1 can discharge to the transistor T3, and the transistor T3 is in the cut-off state. The gate voltage of the transistor T3 is the voltage at the point N1.

[0157] (2.3) Waiting stage for luminescence:

[0158] The light emission control signal (EM) maintains a high level, and the transistors T5 and T6 are in a cut-off state.

[0159] The first reset signal (ResetN) maintains a low level, and the transistor T1 is in a cut-off state.

[0160] The second reset signal (ResetP) changes from high level to low level, and then changes from low level to high level. The low level of the second reset signal turns on transistors T8 and T7. The high level of the second reset signal turns on transistors T8 and T7. Both transistors T8 and transistor T7 are in the cut-off state.

[0161] The first scanning signal (GateN) maintains a low level, and the transistor T2 is in a cut-off state.

[0162] The second scanning signal (GateP) maintains a high level, and the transistor T4 is in a cut-off state.

[0163] The turned-on transistor T8 loads the third initialization voltage Vinit3 to the point N2, and writes the initial state voltage Vinit3 into the point N2.

[0164] The turned-on transistor T7 loads the second initialization voltage Vinit2 to the N4 point, and writes the initial state voltage Vinit2 to the N4 point. In this way, the light emitting element is reset before the light emitting element emits light, thereby reducing the influence of the residual signal in the previous stage on the light emitting element.

[0165] The capacitor C1 can discharge the transistor T3, and the transistor T3 is in the cut-off state. The gate voltage of the transistor T3 is the voltage at the point N1.

[0166] (2.4) Lighting stage:

[0167] Capacitor C1 can maintain the N1 voltage of transistor T3.

[0168] The light emitting control signal (EM) changes from high level to low level. The low level of the light emitting control signal turns on transistors T5 and T6. The first power supply voltage of the positive power supply (VDD) is written to the N2 node, Vgs of transistor T3 is less than Vth, and transistor T3 is turned on.

[0169] The first reset signal (ResetN) maintains a low level, and the transistor T1 remains in the off state.

[0170] The second reset signal (ResetP) maintains a high level, and transistors T7 and T8 are in a cut-off state.

[0171] The first scanning signal (GateN) maintains a low level, and the transistor T2 is in a cut-off state.

[0172] The second scanning signal (GateP) maintains a high level, and the transistor T4 is in a cut-off state.

[0173] The turned-on transistor T5 loads the first power supply voltage at the positive pole of the power supply to the N2 point. The turned-on transistor T3 turns on. The turned-on transistor T6 turns on the N3 and N4 points. One end of the light-emitting element is loaded with the second power supply voltage at the negative pole of the power supply. The light-emitting element starts to emit light.

[0174] When the light-emitting element emits light, transistor T3 divides the voltage so that the brightness of the light-emitting element is controlled by transistor T3. The voltage division of transistor T3 is affected by the voltage at point N1 maintained by capacitor C1. The voltage at point N1 is affected by the potential of capacitor C1. The potential of capacitor C1 is the potential remaining after capacitor C1 is discharged at the end of the previous stage. For example, the smaller the voltage at point N1, the smaller the gate-source voltage difference of transistor T3, the larger the current flowing through transistor T3, the light-emitting element is connected in series with transistor T3, the larger the current flowing through the light-emitting element, and the higher the brightness of the light-emitting element.

[0175] It can be seen from the above that when the electronic device refreshes a frame of image, if the transistors T1, T4 and T2 corresponding to the display area are enabled, the capacitor C1 corresponding to the display area is charged in the reset phase.

[0176] When the electronic device refreshes a frame of image, if the transistors T1, T4 and T2 corresponding to the display area are not enabled, the potential of the capacitor C1 corresponding to the display area is always maintained at the gate voltage of the transistor T3 during the reset stage, the write stage and the light-emitting stage, or the potential of the capacitor C1 corresponding to the display area is always in a discharge state during the reset stage, the write stage and the light-emitting stage, and is not charged. The initial voltage of the capacitor C1 corresponding to the display area is the voltage remaining after the discharge of the previous frame.

[0177] Generally, when an electronic device refreshes an image, the refresh rate of a high-frequency display area is higher than the refresh rate of a low-frequency display area.

[0178] For ease of understanding, the embodiment of the present application is described by taking the refresh rate of the low-frequency display area as 10 Hz and the refresh rate of the high-frequency display area as 120 Hz as an example.

[0179] The refresh rate may be equal to the number of times the transistors T1, T4, and T2 are enabled per unit time when the electronic device refreshes the image. The higher the refresh rate, the more times the transistors T1, T4, and T2 are enabled. Therefore, in the same time period, the number of times the transistors T1, T4, and T2 corresponding to the high-frequency display area are enabled is greater than the number of times the transistors T1, T4, and T2 corresponding to the low-frequency display area are enabled.

[0180] Figure 4 The figure shows the comparison of the number of times transistors T4 and T2 are enabled in the high-frequency display area and the low-frequency display area when the electronic device refreshes the image within 1 second. Figure 4 The first area shown. The high frequency display area is as Figure 4 The refresh rate of the low-frequency display area or the first area is 120 Hz. The refresh rate of the high-frequency display area or the second area is 10 Hz.

[0181] from Figure 2 and Figure 3 It can be seen that when the electronic device refreshes a frame of image, transistors T1, T4 and T2 are enabled once or zero times. Figure 4 As shown, when the electronic device refreshes 120 frames of images within 1 second, the refresh rate of the high-frequency display area is 120Hz, and the refresh rate of the low-frequency display area is 10Hz. The high-frequency display area corresponds to transistors T1, T4 and T2 are enabled 120 times. The low-frequency display area corresponds to transistors T1, T4 and T2 are enabled 10 times, and there are 11 frames of images between two enables. The image sequence of the 120 frames of images refreshed by the electronic device within 1 second is as follows Figure 4 F1, F2,…, F120.

[0182] from Figure 2 and Figure 3 It can be seen that when the electronic device refreshes a frame of image, if the display area of ​​this frame of image corresponding to transistors T1, T2 and T4 are enabled, the display area of ​​this frame of image corresponding to capacitor C1 can be charged during the writing stage. Figure 2 and Figure 3In the embodiment shown, when the electronic device refreshes 120 frames of images within 1 second and the refresh rate of the high-frequency display area is 120Hz, within 1 second, the capacitor C1 corresponding to the high-frequency display area is charged 120 times, or the frequency of writing Vdata in the high-frequency display area to the N1 point is 120Hz. When the electronic device refreshes 120 frames of images within 1 second and the refresh rate of the low-frequency display area is 10Hz, within 1 second, the capacitor C1 corresponding to the low-frequency display area is charged 10 times, or the frequency of writing Vdata in the low-frequency display area to the N1 point is 10Hz.

[0183] In a possible implementation, the voltage values ​​of the first initialization voltage, the second initialization voltage, and the third initialization voltage in the high-frequency display area are the same as the voltage values ​​of the first initialization voltage, the second initialization voltage, and the third initialization voltage in the low-frequency display area. Figure 2 , Figure 3 and Figure 4 It can be seen that there are the following differences between the brightness of the high-frequency display area and the brightness of the low-frequency display area:

[0184] In the process of refreshing 120 frames of images in 1 second by the electronic device, the refresh rate of the low-frequency display area is low, and the number of times the capacitor C1 corresponding to the low-frequency display area is charged is small. The charging amount of capacitor C1 when transistors T1, T4 and T2 are enabled is required to provide gate voltage for the display of this frame of image enabled by transistors T1, T4 and T2, and for transistor T3 when subsequent transistors T1, T4 and T2 are not enabled for displaying 11 consecutive frames of images. In the process of capacitor C1 providing gate voltage for transistor T3 for displaying 11 consecutive frames of images when transistors T1, T4 and T2 are not enabled, capacitor C1 is always in a state of discharge and not being charged, and the potential of point N1 decreases as capacitor C1 discharges. When the light-emitting element emits light, the gate voltage of transistor T3 will become lower and lower, and the gate-source voltage difference of transistor T3 will become smaller and smaller. When the light-emitting element emits light, the current flowing through transistor T3 becomes larger and larger. The light-emitting element is connected in series with transistor T3, and the current flowing through the light-emitting element becomes larger and larger, making the brightness of the light-emitting element higher and higher, thereby making the brightness of the low-frequency display area higher and higher.

[0185] Correspondingly, in the process of refreshing 120 frames of images in 1 second by the electronic device, the refresh rate of the high-frequency display area is high, and the capacitor C1 corresponding to the high-frequency display area is charged more times. In addition, the amount of electricity obtained by capacitor C1 when transistors T1, T4 and T2 are enabled only needs to provide gate voltage for transistor T3 when the frame of image enabled by transistors T1, T4 and T2 is displayed. When the light-emitting element emits light, the current flowing through transistor T3 is small, the light-emitting element is connected in series with transistor T3, and the current flowing through the light-emitting element is small, which makes the brightness of the light-emitting element low, thereby making the brightness of the high-frequency display area low and constant.

[0186] It can be seen that when the voltage values ​​of the first initialization voltage, the second initialization voltage and the third initialization voltage of the high-frequency display area are the same as the voltage values ​​of the first initialization voltage, the second initialization voltage and the third initialization voltage of the low-frequency display area, when the light-emitting element emits light or in the light-emitting stage, the greater the difference between the gate voltage of the transistor T3 corresponding to the low-frequency display area and the gate voltage of the transistor T3 corresponding to the high-frequency display area, the greater the difference in brightness between the low-frequency display area and the high-frequency display area. When the refresh rate of the display area is switched, the display panel of the electronic device will flicker.

[0187] Therefore, when the electronic device refreshes the image, the amount of electricity charged in the capacitor C1 corresponding to the low-frequency display area when the transistors T1, T4 and T2 are enabled can be increased, and the difference between the gate voltage of the transistor T3 corresponding to the low-frequency display area and the gate voltage of the transistor T3 corresponding to the high-frequency display area when the light-emitting element emits light can be reduced, or the difference between the gate voltage of the transistor T3 corresponding to the low-frequency display area and the gate voltage of the transistor T3 corresponding to the high-frequency display area during the light-emitting stage can be reduced. This can reduce the difference in brightness between the low-frequency display area and the high-frequency display area, thereby reducing the probability of flickering on the display panel of the electronic device.

[0188] In this regard, Figure 5 The schematic diagram shows the level timing of each signal provided in the embodiment of the present application. Figure 2 , Figure 6 The schematic diagram shows the level timing of each signal provided in the embodiment of the present application. Figure 3 .

[0189] Figure 5 The diagram shows the level timing diagram of each signal corresponding to the low-frequency display area and the schematic diagram of each initialization voltage when the electronic device refreshes the image. Figure 1 .like Figure 5 As shown, when the electronic device refreshes an image, if the transistors T1 , T4 , and T2 are enabled, the DDIC of the electronic device can control the first initialization voltage Vinit1 to be V1 , and control the third initialization voltage Vinit3 to be V2 .

[0190] Figure 6 The figure shows the level timing diagram of each signal corresponding to the high-frequency display area and the schematic diagram of each initialization voltage when the electronic device refreshes the image. Figure 6 As shown, when the electronic device refreshes an image, if the transistors T1, T4 and T2 are enabled, the DDIC of the electronic device can control the first initialization voltage Vinit1 to be V3, and control the third initialization voltage Vinit3 to be V4.

[0191] Among them, V1>V3 and V2<V4.

[0192] Alternatively, V1 may be equal to V3.

[0193] Alternatively, V2 may be equal to V4.

[0194] If V1>V3 and V2≤V4, and the transistors T1, T4 and T2 in the low-frequency display area are enabled, when the electronic device refreshes a frame of image, in the reset phase, the voltage V1 is written to the capacitor C1, so that the potential of C1 is reset and initialized, the voltage at point N1 is V1, the voltage at point N2 is V2, and the gate-source voltage difference of the transistor T3 is the voltage difference between V1 and V2.

[0195] In the write phase, when transistor T4 is turned on, Vdata is loaded to point N2, and capacitor C1 is charged. The duration of the second scanning signal keeping the low level in the write phase is fixed, and the duration of transistor T4 keeping the on state is fixed. The amount of electricity charged to capacitor C1 in the write phase is related to the transient characteristics of transistor T3, or the value of Vdata written to capacitor C1 in the write phase is related to the transient characteristics of transistor T3. The transient characteristics of transistor T3 are determined by the gate-source voltage difference Vgs-1 of transistor T3 in the reset phase, that is, the voltage difference between V1 and V2. Exemplarily, the Vth of transistor T3 is affected by the gate-source voltage difference of transistor T3. The more positive the gate-source voltage difference of transistor T3 is, the more positive the Vth of transistor T3 is, and the more negative the gate-source voltage difference of transistor T3 is, the more negative the Vth of transistor T3 is.

[0196] If V1>V3 and V2≤V4, and the transistors T1, T4 and T2 in the high-frequency display area are enabled, when the electronic device refreshes a frame of image, in the reset phase, the voltage V3 is written to the capacitor C1, so that the potential of C1 is reset and initialized, the voltage at point N1 is V3, the voltage at point N2 is V4, and the gate-source voltage difference of the transistor T3 is the voltage difference between V3 and V4.

[0197] In the write phase, when transistor T4 is turned on, Vdata is loaded to point N2 and capacitor C1 is charged. Similarly, when the duration of transistor T4 remaining in the on state is fixed, the amount of electricity charged to capacitor C1 in the write phase is related to the transient characteristics of transistor T3, or the value of Vdata written to capacitor C1 in the write phase is related to the transient characteristics of transistor T3. The transient characteristics of transistor T3 are determined by the gate-source voltage difference Vgs-h of transistor T3 in the reset phase, that is, the voltage difference between V3 and V4.

[0198] When the capacitor C1 is charged in the write phase, the larger the gate-source voltage difference of the transistor T3, the more positively shifted the Vth of the transistor T3, the larger the current flowing through the transistor T3, the more electricity charged into the capacitor C1 or the more sufficient the Vdata written into C1. Correspondingly, when the capacitor C1 is charged in the write phase, the smaller the gate-source voltage difference of the transistor T3, the more negatively shifted the Vth of the transistor T3, the smaller the current flowing through the transistor T3, the less electricity charged into the capacitor C1 or the less sufficient the Vdata written into C1.

[0199] Since Vgs-l>Vgs-h, the amount of electricity charged for the capacitor C1 when the transistors T1, T4 and T2 in the low-frequency display area are enabled is greater than the amount of electricity charged for the capacitor C1 when the transistors T1, T4 and T2 in the high-frequency display area are enabled, or the Vdata written into the capacitor C1 when the transistors T1, T4 and T2 in the low-frequency display area are enabled is more sufficient than the Vdata written into the capacitor C1 when the transistors T1, T4 and T2 in the high-frequency display area are enabled.

[0200] In this way, when the electronic device refreshes the image, the amount of charge each time of the capacitor C1 corresponding to the low-frequency display area is increased, which can reduce the difference between the gate voltage of the transistor T3 corresponding to the low-frequency display area and the gate voltage of the transistor T3 corresponding to the high-frequency display area when the light-emitting element emits light.

[0201] In addition, for the low-frequency display area, since the transient characteristics of the transistor T3 are affected by the gate-source voltage difference of the transistor T3, the electronic device refreshes 120 frames of images within 1 second (such as Figure 4 In the process of F1-F120 shown in FIG. 1 , when transistors T1, T4 and T2 are enabled, the display brightness of the corresponding image changes as compared to when transistors T1, T4 and T2 are disabled as follows:

[0202] When F1 is displayed, the corresponding transistors T1, T4 and T2 are enabled, and when F2-F12 are displayed, the corresponding transistors T1, T4 and T2 are disabled. The display brightness of F1-F12 will become brighter and brighter.

[0203] Compared with F12, when F13 is displayed, the transistors T1, T4 and T2 corresponding to F13 are enabled, and the display brightness of F13 is equivalent to that of F1, both lower than the display brightness of F12. When F14-F24 are displayed, the corresponding transistors T1, T4 and T2 are not enabled, and the display brightness of F13-F24 will become brighter and brighter.

[0204] Similarly, the display brightness of F25-F36 will become brighter and brighter; ...; the display brightness of F109-F120 will become brighter and brighter.

[0205] Due to the gate-source voltage difference of transistor T3 and the change of the transient characteristics of transistor T3, there is a large difference in brightness between two adjacent frames of images during the display process of F1-F120, resulting in flickering. For example, the display brightness of F1 is too different from the display brightness of F2, resulting in flickering, or the display brightness of F3 is too different from the display brightness of F4, resulting in flickering, or the display brightness of F12 is too different from the display brightness of F13, resulting in flickering.

[0206] When the low-frequency display area displays an image, flickering may occur in the low-frequency display area due to the large difference in brightness between two adjacent frames of the image.

[0207] Therefore, when the electronic device refreshes an image, the amount of charge each time of the capacitor C1 corresponding to the low-frequency display area is increased, and the brightness difference between two adjacent frames of images displayed in the low-frequency display area can also be reduced.

[0208] Similarly, if V1≥V3 and V2<V4, transistors T1, T4 and T2 are enabled, when the electronic device refreshes a frame of image, since V2<V4, the charge amount of capacitor C1 corresponding to the low-frequency display area in the reset phase is greater than the charge amount of capacitor C1 corresponding to the high-frequency display area in the reset phase, or, the Vdata written into capacitor C1 when transistors T1, T4 and T2 in the low-frequency display area are enabled is more sufficient than the Vdata written into capacitor C1 when transistors T1, T4 and T2 in the high-frequency display area are enabled.

[0209] In this way, when the electronic device refreshes the image, the amount of charge per time of the capacitor C1 corresponding to the low-frequency display area is also increased, which can reduce the difference between the gate voltage of the transistor T3 corresponding to the low-frequency display area and the gate voltage of the transistor T3 corresponding to the high-frequency display area when the light-emitting element emits light. In addition, by increasing the amount of charge per time of the capacitor C1 corresponding to the low-frequency display area, the brightness difference between two adjacent frames of images displayed in the low-frequency display area can also be reduced.

[0210] Reducing the brightness difference between the high-frequency display area and the low-frequency display area, as well as reducing the brightness difference between two adjacent frames of images displayed in the low-frequency display area, can make the display within the surface of the electronic device display panel more uniform, and can improve the user experience of using the display surface electronic device.

[0211] Alternatively, if Figure 5 and Figure 6 As shown, when the electronic device is in one frame of image, if the transistors T1, T4 and T2 are not enabled and the capacitor C1 is not charged, the DDIC of the electronic device can control the first initialization voltage Vinit1 to be V3 and the third initialization voltage Vinit3 to be V4. In this way, the power consumption of the electronic device can be reduced.

[0212] When the electronic device refreshes each frame of the image, the voltage difference between the point N1 and the point N2 in the reset phase is also called the bias voltage of the transistor T3. As can be seen from the above, the bias voltage will affect the charge amount of the capacitor C1 in the write phase.

[0213] Figure 7 The timing of the bias voltage when the electronic device refreshes the image is shown. Figure 1 . Figure 8 The timing of the bias voltage when the electronic device refreshes the image is shown. Figure 2 .like Figure 7 Shown and Figure 8 As shown, the first area may be a low-frequency display area, and the refresh rate of the first area is, for example, 10 Hz; the second area may be a high-frequency display area, and the refresh rate of the second area is, for example, 120 Hz.

[0214] The time for the electronic device to refresh a frame of image line by line is from 0 to t3. Figure 7 As shown, during the time period 0-t1, the electronic device drives to display the first area of ​​this frame image. During the time period t1-t2, the electronic device drives to display the second area of ​​this frame image. During the time period t2-t3, the electronic device drives to display the first area of ​​this frame image. Figure 8 As shown, during the time period 0-t1, the electronic device drives to display the first area of ​​this frame image. During the time period t1-t3, the electronic device drives to display the second area of ​​this frame image.

[0215] like Figure 5 , Figure 6 , Figure 7 and Figure 8 As shown, when the electronic device refreshes the first frame image such as F1, the transistors T1, T4 and T2 corresponding to the first area and the second area of ​​F1 are all enabled. DDIC can control the first initialization voltage Vinit1 and the third initialization voltage Vinit3 so that the bias voltage when driving the first area of ​​F1 is higher than the bias voltage when driving the second area of ​​F1.

[0216] The implementation principle of DDIC is that the bias voltage when driving the first area of ​​display F1 is higher than the bias voltage when driving the second area of ​​display F1 by controlling the first initialization voltage Vinit1 and the third initialization voltage Vinit3. Figure 5 and Figure 6 The implementation principles of the illustrated embodiments are similar and will not be described in detail.

[0217] When the electronic device refreshes the second frame image such as F2, the transistors T1, T4 and T2 corresponding to the first area of ​​F2 are not enabled, and the transistors T1, T4 and T2 corresponding to the second area of ​​F2 are enabled. DDIC can control the first initialization voltage Vinit1 and the third initialization voltage Vinit3 so that the bias voltage when driving the first area of ​​F2 to be displayed is equal to the bias voltage when driving the second area of ​​F2 to be displayed.

[0218] Similarly, when the electronic device refreshes the third frame image such as F3, the transistors T1, T4 and T2 corresponding to the first area of ​​F3 are not enabled, and the transistors T1, T4 and T2 corresponding to the second area of ​​F3 are enabled. DDIC can control the first initialization voltage Vinit1 and the third initialization voltage Vinit3 so that the bias voltage when driving the first area of ​​F3 to be displayed is equal to the bias voltage when driving the second area of ​​F3 to be displayed.

[0219] Similarly, when the electronic device refreshes the thirteenth frame image such as F13, the transistors T1, T4 and T2 corresponding to the first area and the second area of ​​F13 are all enabled. DDIC can control the first initialization voltage Vinit1 and the third initialization voltage Vinit3 so that the bias voltage when driving the first area to display F13 is higher than the bias voltage when driving the second area to display F13.

[0220] Similarly, when the electronic device refreshes the fourteenth frame image such as F14, the transistors T1, T4 and T2 corresponding to the first area of ​​F14 are not enabled, and the transistors T1, T4 and T2 corresponding to the second area of ​​F14 are enabled. DDIC can control the first initialization voltage Vinit1 and the third initialization voltage Vinit3 so that the bias voltage when driving the first area of ​​F14 to be displayed is equal to the bias voltage when driving the second area of ​​F14 to be displayed.

[0221] In this way, when the light-emitting element emits light, the difference between the gate voltage of the transistor T3 corresponding to the low-frequency display area and the gate voltage of the transistor T3 corresponding to the high-frequency display area can be reduced, thereby reducing the difference in brightness between the first area and the second area, thereby reducing the probability of flickering in the first area when the refresh rate of the first area is switched, and / or reducing the probability of flickering in the second area when the refresh rate of the second area is switched, thereby reducing the probability of flickering in the display panel of the electronic device. In addition, the brightness uniformity of the first area can be improved, reducing the probability of flickering in the first area due to the brightness difference between two adjacent frames of images, and further reducing the probability of flickering in the display panel of the electronic device.

[0222] The refresh rate of the first region is switched, for example, the refresh rate of the first region is switched to the refresh rate of the second region.

[0223] The refresh rate of the second region is switched, for example, the refresh rate of the second region is switched to the refresh rate of the first region.

[0224] In one possible implementation, Fig. 9 The diagram shows the level timing diagram of each signal corresponding to the low-frequency display area and the schematic diagram of each initialization voltage when the electronic device refreshes the image. Figure 2 . Fig.10 The timing of the bias voltage when the electronic device refreshes the image is shown. Figure 3 . Fig.11 The timing of the bias voltage when the electronic device refreshes the image is shown. Figure 4 .like Fig.10 Shown and Fig.11 As shown, the first area may be a low-frequency display area. The refresh rate of the first area is, for example, 10 Hz. The second area may be a high-frequency display area. The refresh rate of the second area is, for example, 120 Hz. When the electronic device refreshes the image, the level timing diagram of each signal corresponding to the high-frequency display area (or the second area) and the schematic diagram of each initialization voltage are as shown in Figure 6 shown.

[0225] The time for the electronic device to refresh a frame of image line by line is from 0 to t3. Fig.10 As shown, during the time period 0-t1, the electronic device drives to display the first area of ​​this frame image. During the time period t1-t2, the electronic device drives to display the second area of ​​this frame image. During the time period t2-t3, the electronic device drives to display the first area of ​​this frame image. Fig.11 As shown, during the time period 0-t1, the electronic device drives to display the first area of ​​this frame image. During the time period t1-t3, the electronic device drives to display the second area of ​​this frame image.

[0226] like Figure 6 , Fig. 9 , Fig.10 and Fig.11 As shown, when the electronic device refreshes the first frame image such as F1, the transistors T1, T4 and T2 corresponding to the first area and the second area of ​​F1 are all enabled. DDIC can control the first initialization voltage Vinit1 and the third initialization voltage Vinit3 so that the bias voltage when driving the first area of ​​F1 is higher than the bias voltage when driving the second area of ​​F1.

[0227] The implementation principle of DDIC is that the bias voltage when driving the first area of ​​display F1 is higher than the bias voltage when driving the second area of ​​display F1 by controlling the first initialization voltage Vinit1 and the third initialization voltage Vinit3. Figure 5 and Figure 6 The implementation principles of the illustrated embodiments are similar and will not be described in detail.

[0228] When the electronic device refreshes the second frame image such as F2, the transistors T1, T4 and T2 corresponding to the first area of ​​F2 are not enabled, and the transistors T1, T4 and T2 corresponding to the second area of ​​F2 are enabled. DDIC can control the first initialization voltage Vinit1 and the third initialization voltage Vinit3 so that the bias voltage when driving the first area of ​​F2 to be displayed is higher than the bias voltage when driving the second area of ​​F2 to be displayed.

[0229] Similarly, when the electronic device refreshes the third frame image such as F3, the transistors T1, T4 and T2 corresponding to the first area of ​​F3 are not enabled, and the transistors T1, T4 and T2 corresponding to the second area of ​​F3 are enabled. DDIC can control the first initialization voltage Vinit1 and the third initialization voltage Vinit3 so that the bias voltage when driving the first area of ​​F3 to be displayed is equal to the bias voltage when driving the second area of ​​F3 to be displayed.

[0230] Similarly, when the electronic device refreshes the fourth frame image such as F4, the transistors T1, T4 and T2 corresponding to the first area of ​​F4 are not enabled, and the transistors T1, T4 and T2 corresponding to the second area of ​​F4 are enabled. DDIC can control the first initialization voltage Vinit1 and the third initialization voltage Vinit3 so that the bias voltage when driving the first area of ​​F4 to be displayed is equal to the bias voltage when driving the second area of ​​F4 to be displayed.

[0231] Similar to when the electronic device refreshes the first frame image such as F1, when the electronic device refreshes the thirteenth frame image such as F13, the transistors T1, T4 and T2 corresponding to the first area and the second area of ​​F13 are all enabled. DDIC can control the first initialization voltage Vinit1 and the third initialization voltage Vinit3 so that the bias voltage when driving the first area of ​​F13 to display is higher than the bias voltage when driving the second area of ​​F13 to display.

[0232] Similar to when the electronic device refreshes the second frame image such as F2, when the electronic device refreshes the fourteenth frame image such as F14, the transistors T1, T4 and T2 corresponding to the first area of ​​F14 are not enabled, and the transistors T1, T4 and T2 corresponding to the second area of ​​F14 are enabled. DDIC can control the first initialization voltage Vinit1 and the third initialization voltage Vinit3 so that the bias voltage when driving the first area of ​​F14 to be displayed is higher than the bias voltage when driving the second area of ​​F14 to be displayed.

[0233] Similar to when the electronic device refreshes the third frame image such as F3, when the electronic device refreshes the fifteenth frame image such as F15, the transistors T1, T4 and T2 corresponding to the first area of ​​F15 are not enabled, and the transistors T1, T4 and T2 corresponding to the second area of ​​F15 are enabled. DDIC can control the first initialization voltage Vinit1 and the third initialization voltage Vinit3 so that the bias voltage when driving the first area of ​​F15 to be displayed is equal to the bias voltage when driving the second area of ​​F15 to be displayed.

[0234] In this way, when the light-emitting element emits light, the difference between the gate voltage of the transistor T3 corresponding to the low-frequency display area and the gate voltage of the transistor T3 corresponding to the high-frequency display area can be reduced, thereby reducing the difference in brightness between the first area and the second area, and improving the brightness uniformity of the first area. It has been verified through experiments that the voltage control method provided in this embodiment can reduce the probability of flickering of the display panel of an electronic device.

[0235] In one possible implementation, Fig.12 The diagram shows the level timing diagram of each signal corresponding to the low-frequency display area and the schematic diagram of each initialization voltage when the electronic device refreshes the image. Figure 3 . Fig.13 The timing of the bias voltage when the electronic device refreshes the image is shown. Figure 5 . Fig.14 The timing of the bias voltage when the electronic device refreshes the image is shown. Figure 6 .like Fig.13 Shown and Fig.14 As shown, the first area may be a low-frequency display area. The refresh rate of the first area is, for example, 10 Hz. The second area may be a high-frequency display area. The refresh rate of the second area is, for example, 120 Hz. When the electronic device refreshes the image, the level timing diagram of each signal corresponding to the high-frequency display area (or the second area) and the schematic diagram of each initialization voltage are as shown in Figure 6 shown.

[0236] The time for the electronic device to refresh a frame of image line by line is from 0 to t3. Fig.13 As shown, during the time period 0-t1, the electronic device drives to display the first area of ​​this frame image. During the time period t1-t2, the electronic device drives to display the second area of ​​this frame image. During the time period t2-t3, the electronic device drives to display the first area of ​​this frame image. Fig.14 As shown, during the time period 0-t1, the electronic device drives to display the first area of ​​this frame image. During the time period t1-t3, the electronic device drives to display the second area of ​​this frame image.

[0237] like Figure 6 , Fig.12 , Fig.13 and Fig.14 As shown, when the electronic device refreshes the first frame image such as F1, the transistors T1, T4 and T2 corresponding to the first area and the second area of ​​F1 are all enabled. DDIC can control the first initialization voltage Vinit1 and the third initialization voltage Vinit3 so that the bias voltage when driving the first area of ​​F1 is higher than the bias voltage when driving the second area of ​​F1.

[0238] The implementation principle of DDIC is that the bias voltage when driving the first area of ​​display F1 is higher than the bias voltage when driving the second area of ​​display F1 by controlling the first initialization voltage Vinit1 and the third initialization voltage Vinit3. Figure 5 and Figure 6 The implementation principles of the illustrated embodiments are similar and will not be described in detail.

[0239] When the electronic device refreshes the second frame image such as F2, the transistors T1, T4 and T2 corresponding to the first area of ​​F2 are not enabled, and the transistors T1, T4 and T2 corresponding to the second area of ​​F2 are enabled. DDIC can control the first initialization voltage Vinit1 and the third initialization voltage Vinit3 so that the bias voltage when driving the first area of ​​F2 to be displayed is higher than the bias voltage when driving the second area of ​​F2 to be displayed.

[0240] When the electronic device refreshes the third frame image such as F3, the transistors T1, T4 and T2 corresponding to the first area of ​​F3 are not enabled, and the transistors T1, T4 and T2 corresponding to the second area of ​​F2 are enabled. DDIC can control the first initialization voltage Vinit1 and the third initialization voltage Vinit3 so that the bias voltage when driving the first area of ​​F3 to be displayed is higher than the bias voltage when driving the second area of ​​F3 to be displayed.

[0241] When the electronic device refreshes the fourth frame image such as F4, the transistors T1, T4 and T2 corresponding to the first area of ​​F4 are not enabled, and the transistors T1, T4 and T2 corresponding to the second area of ​​F4 are enabled. DDIC can control the first initialization voltage Vinit1 and the third initialization voltage Vinit3 so that the bias voltage when driving the first area of ​​F4 to be displayed is equal to the bias voltage when driving the second area of ​​F4 to be displayed.

[0242] When the electronic device refreshes the fifth frame image such as F5, the transistors T1, T4 and T2 corresponding to the first area of ​​F5 are not enabled, and the transistors T1, T4 and T2 corresponding to the second area of ​​F5 are enabled. DDIC can control the first initialization voltage Vinit1 and the third initialization voltage Vinit3 so that the bias voltage when driving the first area of ​​F5 to be displayed is equal to the bias voltage when driving the second area of ​​F5 to be displayed.

[0243] The bias voltage of the first area when the electronic device refreshes the thirteenth frame image such as F13 is similar to the control method and effect of the bias voltage of the first area when the electronic device refreshes the first frame image such as F1. The bias voltage of the first area when the electronic device refreshes the fourteenth frame image such as F14 is similar to the control method and effect of the bias voltage of the first area when the electronic device refreshes the second frame image such as F2. The bias voltage of the first area when the electronic device refreshes the fifteenth frame image such as F15 is similar to the control method and effect of the bias voltage of the first area when the electronic device refreshes the third frame image such as F3. The bias voltage of the first area when the electronic device refreshes the sixteenth frame image such as F16 is similar to the control method and effect of the bias voltage of the first area when the electronic device refreshes the fourth frame image such as F4. No further details will be given.

[0244] In this way, the difference between the gate voltage of the transistor T3 corresponding to the static image display area and the gate voltage of the transistor T3 corresponding to the dynamic image display area when the light-emitting element emits light can be reduced, thereby reducing the difference in brightness between the first area and the second area, and improving the brightness uniformity of the first area. It has been verified by experiments that the voltage control method provided in this embodiment can reduce the probability of flickering of the display panel of an electronic device.

[0245] Next, combine Fig.15 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13 and Fig.14 , the voltage control method provided in the embodiment of the present application is described.

[0246] Fig.15 Schematic diagram of a pixel circuit provided in an embodiment of the present application Figure 2 .like Fig.15 As shown, the pixel circuit includes:

[0247] The driving module 13 includes a control terminal of the driving module 13 connected to a first node N1, and a source terminal of the driving module 13 connected to a second node N2. The driving module 13 may include a driving thin film transistor (DTFT). The drain terminal of the DTFT is connected to a third node N3, and the DTFT is used to output current to the third node N3 under the control of the first node N1. The DTFT may include Figure 2 Transistor T3 is shown.

[0248] The first reset unit 10 is connected to the first node N1 and is used to load a first initialization voltage to the first node N1 in response to a first reset signal. The first reset unit 10 may include a first reset transistor. Figure 2 The transistor T1 is shown.

[0249] The storage capacitor 11 has one end connected to the first node N1 and the other end connected to the positive power supply (VDD). The storage capacitor 11 may include Figure 2 Capacitor C1 is shown.

[0250] The first light emitting control unit 12 is connected to the positive electrode of the power supply and the second node N2, and is used to load the first power supply voltage of the positive electrode of the power supply to the second node N2 in response to the light emitting control signal. The first light emitting control unit 12 may include a first light emitting control transistor. The first light emitting control transistor is as shown in FIG. Figure 2 Transistor T5 is shown.

[0251] The threshold compensation unit 14 is connected to the first node N1 and the third node N3, and is used to connect the third node N3 and the first node N1 in response to the first scan signal. The threshold compensation unit 14 may include a threshold compensation transistor. The threshold compensation transistor is as follows: Figure 2 The transistor T2 is shown.

[0252] The second light emitting control unit 15 is connected to the third node N3 and the fourth node N4, and is used to connect the third node N3 and the fourth node N4 in response to the light emitting control signal. The second light emitting control unit 15 may include a second light emitting control transistor. Figure 2 Transistor T6 is shown.

[0253] The light emitting element 16 has one end connected to the fourth node and the other end connected to the negative electrode of the power supply to load the second power supply voltage of the negative electrode of the power supply. The light emitting element 16 may include an organic light emitting diode (OLED).

[0254] The second reset unit 17 is connected to the fourth node N4 and is used to load the second initialization voltage to the fourth node N4 in response to the second reset signal. The second reset unit 17 may include a second reset transistor. Figure 2 Transistor T7 is shown.

[0255] The data writing unit 18 is connected to the second node N2 and is used to load the data voltage to the second node N2 in response to the second scan signal. The data writing unit 18 may include a data writing transistor. The data writing transistor may be Figure 2 Transistor T4 is shown.

[0256] The first reset unit 10 is turned on, which can be referred to as the first reset unit 10 is enabled. The first reset unit 10 is not turned on, which can be referred to as the first reset unit 10 is disabled. The data writing unit 18 loads the data voltage to the second node N2 in response to the second scan signal, which can be referred to as the data writing unit 18 is enabled. The data writing unit 18 does not load the data voltage to the second node N2, which can be referred to as the data writing unit 18 is disabled. The threshold compensation unit 14 makes the third node N3 and the first node N1 conductive in response to the first scan signal, which can be referred to as the threshold compensation unit 14 is enabled. The threshold compensation unit 14 makes the third node N3 and the first node N1 not conductive, which can be referred to as the threshold compensation unit 14 is disabled.

[0257] The third reset unit 19 is connected to the second node N2 and is used to load a third initialization voltage to the second node N2 in response to the second reset signal. The third reset unit 19 may include a third reset transistor. Figure 2 Transistor T8 is shown.

[0258] like Figure 4 , Figure 5 , Figure 6 , Figure 7 and Figure 8 As shown, when the electronic device drives the first area to display the first frame image, the voltage of the first node is controlled to be the first voltage, and the voltage of the second node is controlled to be the second voltage. The first voltage may include V1. The second voltage may include V2.

[0259] When the electronic device drives the second area to display the first frame image, the voltage of the first node is controlled to be a third voltage, and the voltage of the second node is controlled to be a fourth voltage. The third voltage may include V3. The fourth voltage may include V4.

[0260] The voltage difference between the first voltage and the second voltage is greater than the voltage difference between the third voltage and the fourth voltage; the refresh rate of the first area is the first refresh rate, the refresh rate of the second area is the second refresh rate, and the first refresh rate is lower than the second refresh rate. The first refresh rate is, for example, 10 Hz. The second refresh rate is, for example, 120 Hz.

[0261] Optionally, the first voltage is greater than the third voltage, and / or the second voltage is less than the fourth voltage.

[0262] Furthermore, if Fig.15 As shown, the pixel circuit further includes a data writing unit 18, and the data writing unit 18 is connected to the second node N2. Figure 3 and Figure 4 As shown, when the electronic device displays the first region and the second region of the first frame image, the data writing unit 18 is enabled. The voltage control method provided in this embodiment also includes:

[0263] like Figure 5 As shown, when the electronic device drives the first area to display the second frame image, the voltage of the first node is controlled to be the third voltage, and the voltage of the second node is controlled to be the fourth voltage. When the electronic device displays the first area of ​​the second frame image, the data writing unit 18 is not enabled.

[0264] like Figure 6 As shown, when the electronic device drives the second area to display the second frame image, the voltage of the first node is controlled to be the third voltage, and the voltage of the second node is controlled to be the fourth voltage. When the electronic device displays the second area of ​​the second frame image, the data writing unit 18 is enabled.

[0265] Alternatively, if Fig.15 As shown, the pixel circuit further includes a data writing unit 18 and a threshold compensation unit 14. Figure 3 and Figure 4 As shown, when the electronic device displays the first area and the second area of ​​the first frame image, the first reset unit 10 is enabled, the data writing unit 18 is enabled, and the threshold compensation unit 14 is enabled. The voltage control method provided in this embodiment also includes:

[0266] like Figure 5 As shown, when the electronic device drives the first area to display the second frame image, the voltage of the first node is controlled to be the third voltage, and the voltage of the second node is controlled to be the fourth voltage. When the electronic device displays the first area of ​​the second frame image, the first reset unit 10, the data writing unit 18 and the threshold compensation unit 14 are not enabled.

[0267] like Figure 6 As shown, when the electronic device drives the second area to display the second frame image, the voltage of the first node is controlled to be the third voltage, and the voltage of the second node is controlled to be the fourth voltage. When the electronic device displays the second area of ​​the second frame image, the first reset unit 10, the data writing unit 18 and the threshold compensation unit 14 are enabled.

[0268] Optionally, the display area on the display panel of the electronic device may further include a third area. When the electronic device drives the third area to display the first frame image, the voltage of the first node is controlled to be the first voltage, and the voltage of the second node is controlled to be the second voltage. The refresh rate of the third area is a third refresh rate. The third refresh rate is lower than the second refresh rate.

[0269] Optionally, the third refresh rate may be the same as the first refresh rate, or may be different from the first refresh rate. When the third refresh rate is the same as the first refresh rate, the third area, for example Figure 7 , Fig.10 and Fig.13 The time period t2-t3 shown corresponds to the first area.

[0270] It is understood that the first refresh rate and the third refresh rate in the embodiment of the present application may include but are not limited to 10 Hz. The second refresh rate in the embodiment of the present application may include but are not limited to 120 Hz. For example, the third refresh rate may also be 30 Hz or 60 Hz.

[0271] Optionally, when refreshing a frame of image, the electronic device may determine the starting position and ending position of the first region based on the identifier of the pixel circuit corresponding to the first region, and may determine the starting position and ending position of the second region based on the identifier of the pixel circuit corresponding to the second region.

[0272] Exemplarily, the DDIC can determine the starting position and the ending position of the second area through the position information of the second area indicated by the application processor (AP) of the electronic device, and then determine the starting position and the ending position of the first area. The position information of the second area indicated by the AP can be the relative position information of the second area indicated by the AP, or it can be the real position information of the second area indicated by the AP. The real position information of the second area indicated by the AP can include the identifier of the pixel circuit corresponding to the starting position of the second area and the identifier of the pixel circuit corresponding to the ending position.

[0273] The position information of the second area indicated by the AP is determined by the AP based on the application type to which the image data generated by the AP belongs or based on the application scenario to which the image data generated by the AP belongs. The image data generated by the AP refers to the data corresponding to Vdata when transistors T4 and T2 are enabled. If the image data generated by the AP belongs to the dynamic image data of application A, the position information of the second area indicated by the AP can be determined based on the position information of the area displaying the dynamic image in the display interface of application A.

[0274] The specific implementation principle and technical effects of this embodiment are Figure 2 , Figure 5 , Figure 6 , Figure 7 and Figure 8 The specific implementation principles and technical effects of the illustrated embodiments are similar and will not be described in detail.

[0275] like Fig.15 , Figure 4 , Figure 6 , Fig. 9 , Fig.10 and Fig.11 As shown, when the electronic device displays the first area and the second area of ​​the first frame image, the data writing unit 18 is enabled, and the voltage control method provided in this embodiment also includes:

[0276] When the electronic device drives the first area to display the second frame image, the voltage of the first node is controlled to be the first voltage, and the voltage of the second node is controlled to be the second voltage. When the electronic device displays the first area of ​​the second frame image, the data writing unit 18 is disabled.

[0277] When the electronic device drives the second area to display the second frame image, the voltage of the first node is controlled to be the third voltage, and the voltage of the second node is controlled to be the fourth voltage. When the electronic device displays the first area of ​​the second frame image, the data writing unit 18 is enabled.

[0278] The specific implementation principle and technical effects of this embodiment are Figure 6 , Fig. 9 , Fig.10 and Fig.11 The specific implementation principles and technical effects of the illustrated embodiments are similar and will not be described in detail.

[0279] For example, Fig.15 , Figure 4 , Figure 6 , Fig. 9 , Fig.10 and Fig.11 As shown, when the electronic device displays the first area and the second area of ​​the first frame image, the first reset unit 10 is enabled, the data writing unit 18 is enabled, and the threshold compensation unit 14 is enabled. The voltage control method provided in this embodiment also includes:

[0280] When the electronic device drives the first area to display the second frame image, the voltage of the first node is controlled to be the first voltage, and the voltage of the second node is controlled to be the second voltage. When the electronic device displays the first area of ​​the second frame image, the first reset unit 10, the data writing unit 18 and the threshold compensation unit 14 are not enabled.

[0281] When the electronic device drives the second area to display the second frame image, the voltage of the first node is controlled to be the third voltage, and the voltage of the second node is controlled to be the fourth voltage. When the electronic device displays the first area of ​​the second frame image, the first reset unit 10, the data writing unit 18 and the threshold compensation unit 14 are enabled.

[0282] The specific implementation principle and technical effects of this embodiment are Figure 6 , Fig. 9 , Fig.10 and Fig.11 The specific implementation principles and technical effects of the illustrated embodiments are similar and will not be described in detail.

[0283] like Fig.15 , Figure 4 , Figure 6 , Fig.12 , Fig.13 and Fig.14As shown, the voltage control method provided in this embodiment also includes:

[0284] When the electronic device drives the first area to display the third frame image, the voltage of the first node is controlled to be the first voltage, and the voltage of the second node is controlled to be the second voltage. When the electronic device displays the first area of ​​the third frame image, the data writing unit 18 is disabled.

[0285] When the electronic device drives the second area to display the third frame image, the voltage of the first node is controlled to be the third voltage, and the voltage of the second node is controlled to be the fourth voltage. When the electronic device displays the second area of ​​the third frame image, the data writing unit 18 is enabled.

[0286] When the electronic device drives the first area to display the fourth frame image, the voltage of the first node is controlled to be the third voltage, and the voltage of the second node is controlled to be the fourth voltage. When the electronic device displays the first area of ​​the fourth frame image, the data writing unit 18 is not enabled;

[0287] When the electronic device drives the second area to display the fourth frame image, the voltage of the first node is controlled to be the third voltage, and the voltage of the second node is controlled to be the fourth voltage. When the electronic device displays the second area of ​​the fourth frame image, the data writing unit 18 is enabled.

[0288] The specific implementation principle and technical effects of this embodiment are Figure 6 , Fig.12 , Fig.13 and Fig.14 The specific implementation principles and technical effects of the illustrated embodiments are similar and will not be described in detail.

[0289] For example, Fig.15 , Figure 4 , Figure 6 , Fig.12 , Fig.13 and Fig.14 As shown, the voltage control method provided in this embodiment also includes:

[0290] When the electronic device drives the first area to display the third frame image, the voltage of the first node is controlled to be the first voltage, and the voltage of the second node is controlled to be the second voltage. When the electronic device displays the first area of ​​the third frame image, the first reset unit 10, the data writing unit 18 and the threshold compensation unit 14 are not enabled.

[0291] When the electronic device drives the second area to display the third frame image, the voltage of the first node is controlled to be the third voltage, and the voltage of the second node is controlled to be the fourth voltage. When the electronic device displays the second area of ​​the third frame image, the first reset unit 10, the data writing unit 18 and the threshold compensation unit 14 are enabled.

[0292] When the electronic device drives the first area to display the fourth frame image, the voltage of the first node is controlled to be the third voltage, and the voltage of the second node is controlled to be the fourth voltage. When the electronic device displays the first area of ​​the fourth frame image, the first reset unit 10, the data writing unit 18 and the threshold compensation unit 14 are disabled;

[0293] When the electronic device drives the second area to display the fourth frame image, the voltage of the first node is controlled to be the third voltage, and the voltage of the second node is controlled to be the fourth voltage. When the electronic device displays the second area of ​​the fourth frame image, the first reset unit 10, the data writing unit 18 and the threshold compensation unit 14 are enabled.

[0294] The specific implementation principle and technical effects of this embodiment are Figure 6 , Fig.12 , Fig.13 and Fig.14 The specific implementation principles and technical effects of the illustrated embodiments are similar and will not be described in detail.

[0295] In order to better understand the embodiments of the present application, Fig.16 and Fig.17 , the structure of the electronic device in the embodiment of the present application is described.

[0296] Fig.16 A schematic structural diagram of an electronic device 100 is shown.

[0297] The electronic device 100 may include a processor 110, an external memory interface 120, an internal memory 121, a universal serial bus (USB) interface 130, a charging management module 140, a power management module 141, a battery 142, an antenna 1, an antenna 2, a mobile communication module 150, a wireless communication module 160, an audio module 170, a speaker 170A, a receiver 170B, a microphone 170C, an earphone interface 170D, a sensor module 180, a button 190, a motor 191, an indicator 192, a camera 193, a display screen 194, and a subscriber identification module (SIM) card interface 195, etc. The sensor module 180 may include a pressure sensor 180A, a gyroscope sensor 180B, an air pressure sensor 180C, a magnetic sensor 180D, an acceleration sensor 180E, a distance sensor 180F, a proximity light sensor 180G, a fingerprint sensor 180H, a temperature sensor 180J, a touch sensor 180K, an ambient light sensor 180L, a bone conduction sensor 180M, etc.

[0298] It is to be understood that the structure illustrated in the embodiment of the present invention does not constitute a specific limitation on the electronic device 100. In other embodiments of the present application, the electronic device 100 may include more or fewer components than shown in the figure, or combine some components, or separate some components, or arrange the components differently. The components shown in the figure may be implemented in hardware, software, or a combination of software and hardware.

[0299] The processor 110 may include one or more processing units, for example, the processor 110 may include an application processor (AP), a modem processor, a graphics processor (GPU), an image signal processor (ISP), a controller, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural-network processing unit (NPU), etc. Different processing units may be independent devices or integrated into one or more processors.

[0300] The controller can generate operation control signals according to the instruction operation code and timing signal to complete the control of instruction fetching and execution.

[0301] The processor 110 may also be provided with a memory for storing instructions and data. In some embodiments, the memory in the processor 110 is a cache memory. The memory may store instructions or data that the processor 110 has just used or cyclically used. If the processor 110 needs to use the instruction or data again, it may be directly called from the memory. This avoids repeated access, reduces the waiting time of the processor 110, and thus improves the efficiency of the system.

[0302] In some embodiments, the processor 110 may include one or more interfaces. The interface may include an inter-integrated circuit (I2C) interface, an inter-integrated circuit sound (I2S) interface, a pulse code modulation (PCM) interface, a universal asynchronous receiver / transmitter (UART) interface, a mobile industry processor interface (MIPI), a general-purpose input / output (GPIO) interface, a subscriber identity module (SIM) interface, and / or a universal serial bus (USB) interface, etc.

[0303] It is understandable that the interface connection relationship between the modules illustrated in the embodiment of the present invention is only a schematic illustration and does not constitute a structural limitation on the electronic device 100. In other embodiments of the present application, the electronic device 100 may also adopt different interface connection methods in the above embodiments, or a combination of multiple interface connection methods.

[0304] The charging management module 140 is used to receive charging input from a charger. The charger may be a wireless charger or a wired charger. In some wired charging embodiments, the charging management module 140 may receive charging input from a wired charger through the USB interface 130. In some wireless charging embodiments, the charging management module 140 may receive wireless charging input through a wireless charging coil of the electronic device 100. While the charging management module 140 is charging the battery 142, it may also power the electronic device through the power management module 141.

[0305] The power management module 141 is used to connect the battery 142, the charging management module 140 and the processor 110. The power management module 141 receives input from the battery 142 and / or the charging management module 140, and supplies power to the processor 110, the internal memory 121, the display screen 194, the camera 193, and the wireless communication module 160. The power management module 141 can also be used to monitor parameters such as battery capacity, battery cycle number, battery health status (leakage, impedance), etc. In some other embodiments, the power management module 141 can also be set in the processor 110. In other embodiments, the power management module 141 and the charging management module 140 can also be set in the same device.

[0306] The wireless communication function of the electronic device 100 can be Fig.16 The antenna 1, antenna 2, mobile communication module 150, wireless communication module 160, modem processor and baseband processor are shown.

[0307] Fig.16 The antenna 1 and antenna 2 shown are used to transmit and receive electromagnetic wave signals. Each antenna in the electronic device 100 can be used to cover a single or multiple communication frequency bands. Different antennas can also be reused to improve the utilization of the antennas. For example, antenna 1 can be reused as a diversity antenna for a wireless local area network. In some other embodiments, the antenna can be used in combination with a tuning switch.

[0308] The mobile communication module 150 can provide solutions for wireless communications including 2G / 3G / 4G / 5G, etc., applied to the electronic device 100. The mobile communication module 150 may include at least one filter, a switch, a power amplifier, a low noise amplifier (LNA), etc. The mobile communication module 150 can receive electromagnetic waves from the antenna 1, and filter, amplify, and process the received electromagnetic waves, and transmit them to the modulation and demodulation processor for demodulation. The mobile communication module 150 can also amplify the signal modulated by the modulation and demodulation processor, and convert it into electromagnetic waves for radiation through the antenna 1. In some embodiments, at least some of the functional modules of the mobile communication module 150 can be set in the processor 110. In some embodiments, at least some of the functional modules of the mobile communication module 150 can be set in the same device as at least some of the modules of the processor 110.

[0309] The modem processor may include a modulator and a demodulator. Among them, the modulator is used to modulate the low-frequency baseband signal to be sent into a medium-high frequency signal. The demodulator is used to demodulate the received electromagnetic wave signal into a low-frequency baseband signal. The demodulator then transmits the demodulated low-frequency baseband signal to the baseband processor for processing. After the low-frequency baseband signal is processed by the baseband processor, it is passed to the application processor. The application processor outputs a sound signal through an audio device (not limited to a speaker 170A, a receiver 170B, etc.), or displays an image or video through a display screen 194. In some embodiments, the modem processor may be an independent device. In other embodiments, the modem processor may be independent of the processor 110 and be set in the same device as the mobile communication module 150 or other functional modules.

[0310] The wireless communication module 160 can provide wireless communication solutions including wireless local area networks (WLAN) (such as wireless fidelity (Wi-Fi) networks), bluetooth (BT), global navigation satellite system (GNSS), frequency modulation (FM), near field communication (NFC), infrared (IR), etc., which are applied to the electronic device 100. The wireless communication module 160 can be one or more devices integrating at least one communication processing module. The wireless communication module 160 receives electromagnetic waves via the antenna 2, modulates the frequency of the electromagnetic wave signal and performs filtering, and sends the processed signal to the processor 110. The wireless communication module 160 can also receive the signal to be sent from the processor 110, modulate the frequency of it, amplify it, and convert it into electromagnetic waves for radiation through the antenna 2.

[0311] In some embodiments, the antenna 1 of the electronic device 100 is coupled to the mobile communication module 150, and the antenna 2 is coupled to the wireless communication module 160, so that the electronic device 100 can communicate with the network and other devices through wireless communication technology. The wireless communication technology may include global system for mobile communications (GSM), general packet radio service (GPRS), code division multiple access (CDMA), wideband code division multiple access (WCDMA), time-division code division multiple access (TD-SCDMA), long term evolution (LTE), BT, GNSS, WLAN, NFC, FM, and / or IR technology, etc. GNSS may include the global positioning system (GPS), the global navigation satellite system (GLONASS), the Beidou navigation satellite system (BDS), the quasi-zenith satellite system (QZSS) and / or the satellite based augmentation system (SBAS).

[0312] The electronic device 100 implements the display function through a GPU, a display screen 194, and an application processor. The GPU is a microprocessor for image processing, which connects the display screen 194 and the application processor. The GPU is used to perform mathematical and geometric calculations for graphics rendering. The processor 110 may include one or more GPUs that execute program instructions to generate or change display information.

[0313] The display screen 194 is used to display images, videos, etc. The display screen 194 includes a display panel. The display panel can be a liquid crystal display (LCD), an organic light-emitting diode (OLED), an active-matrix organic light-emitting diode or an active-matrix organic light-emitting diode (AMOLED), a flexible light-emitting diode (FLED), Miniled, MicroLed, Micro-oLed, a quantum dot light-emitting diode (QLED), etc. In some embodiments, the electronic device 100 may include 1 or N display screens 194, where N is a positive integer greater than 1.

[0314] The electronic device 100 can realize the shooting function through ISP, camera 193, video codec, GPU, display screen 194 and application processor.

[0315] ISP is used to process the data fed back by camera 193. For example, when taking a photo, the shutter is opened, and the light is transmitted to the camera photosensitive element through the lens. The light signal is converted into an electrical signal, and the camera photosensitive element transmits the electrical signal to ISP for processing and converts it into an image visible to the naked eye. ISP can also perform algorithm optimization on the noise, brightness, and skin color of the image. ISP can also optimize the exposure, color temperature and other parameters of the shooting scene. In some embodiments, ISP can be set in camera 193.

[0316] The camera 193 is used to capture still images or videos. The object generates an optical image through the lens and projects it onto the photosensitive element. The photosensitive element can be a charge coupled device (CCD) or a complementary metal-oxide-semiconductor (CMOS) phototransistor. The photosensitive element converts the optical signal into an electrical signal, and then passes the electrical signal to the ISP to be converted into a digital image signal. The ISP outputs the digital image signal to the DSP for processing. The DSP converts the digital image signal into an image signal in a standard RGB, YUV or other format. In some embodiments, the electronic device 100 may include 1 or N cameras 193, where N is a positive integer greater than 1.

[0317] The digital signal processor is used to process digital signals, and can process not only digital image signals but also other digital signals. For example, when the electronic device 100 is selecting a frequency point, the digital signal processor is used to perform Fourier transform on the frequency point energy.

[0318] Video codecs are used to compress or decompress digital videos. The electronic device 100 may support one or more video codecs. Thus, the electronic device 100 may play or record videos in a variety of coding formats, such as Moving Picture Experts Group (MPEG) 1, MPEG2, MPEG3, MPEG4, etc.

[0319] NPU is a neural network (NN) computing processor. By drawing on the structure of biological neural networks, such as the transmission mode between neurons in the human brain, it can quickly process input information and can also continuously self-learn. Through NPU, applications such as intelligent cognition of electronic device 100 can be realized, such as image recognition, face recognition, voice recognition, text understanding, etc.

[0320] The external memory interface 120 can be used to connect an external memory card, such as a Micro SD card, to expand the storage capacity of the electronic device 100. The external memory card communicates with the processor 110 through the external memory interface 120 to implement a data storage function, such as storing music, video and other files in the external memory card.

[0321] The internal memory 121 can be used to store computer executable program codes, and the executable program codes include instructions. The internal memory 121 may include a program storage area and a data storage area. Among them, the program storage area may store an operating system, an application required for at least one function (such as a sound playback function, an image playback function, etc.), etc. The data storage area may store data created during the use of the electronic device 100 (such as audio data, a phone book, etc.), etc. In addition, the internal memory 121 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, a universal flash storage (UFS), etc. The processor 110 executes various functional applications and data processing of the electronic device 100 by running instructions stored in the internal memory 121, and / or instructions stored in a memory provided in the processor.

[0322] The electronic device 100 can implement audio functions such as music playing and recording through the audio module 170, the speaker 170A, the receiver 170B, the microphone 170C, the headphone jack 170D, and the application processor.

[0323] The audio module 170 is used to convert digital audio information into analog audio signal output, and is also used to convert analog audio input into digital audio signals. The audio module 170 can also be used to encode and decode audio signals. In some embodiments, the audio module 170 can be arranged in the processor 110, or some functional modules of the audio module 170 can be arranged in the processor 110.

[0324] The speaker 170A, also called a "speaker", is used to convert an audio electrical signal into a sound signal. The electronic device 100 can listen to music or listen to a hands-free call through the speaker 170A.

[0325] The receiver 170B, also called a "earpiece", is used to convert audio electrical signals into sound signals. When the electronic device 100 receives a call or voice message, the voice can be received by placing the receiver 170B close to the human ear.

[0326] Microphone 170C, also called "microphone" or "microphone", is used to convert sound signals into electrical signals. When making a call or sending a voice message, the user can speak by putting their mouth close to microphone 170C to input the sound signal into microphone 170C. The electronic device 100 can be provided with at least one microphone 170C. In other embodiments, the electronic device 100 can be provided with two microphones 170C, which can not only collect sound signals but also realize noise reduction function. In other embodiments, the electronic device 100 can also be provided with three, four or more microphones 170C to collect sound signals, reduce noise, identify the sound source, realize directional recording function, etc.

[0327] The earphone interface 170D is used to connect a wired earphone and can be a USB interface 130 or a 3.5 mm open mobile terminal platform (OMTP) standard interface or a cellular telecommunications industry association of the USA (CTIA) standard interface.

[0328] The key 190 includes a power key, a volume key, etc. The key 190 may be a mechanical key or a touch key. The electronic device 100 may receive key input and generate key signal input related to user settings and function control of the electronic device 100.

[0329] Motor 191 can generate vibration prompts. Motor 191 can be used for incoming call vibration prompts, and can also be used for touch vibration feedback. For example, touch operations acting on different applications (such as taking pictures, audio playback, etc.) can correspond to different vibration feedback effects. For touch operations acting on different areas of the display screen 194, motor 191 can also correspond to different vibration feedback effects. Different application scenarios (for example: time reminders, receiving messages, alarm clocks, games, etc.) can also correspond to different vibration feedback effects. The touch vibration feedback effect can also support customization.

[0330] Indicator 192 may be an indicator light, which may be used to indicate charging status, power changes, messages, missed calls, notifications, etc.

[0331] The SIM card interface 195 is used to connect a SIM card. The SIM card can be connected to and separated from the electronic device 100 by inserting it into the SIM card interface 195 or pulling it out from the SIM card interface 195. The electronic device 100 can support 1 or N SIM card interfaces, where N is a positive integer greater than 1. The SIM card interface 195 can support Nano SIM cards, Micro SIM cards, SIM cards, and the like. Multiple cards can be inserted into the same SIM card interface 195 at the same time. The types of the multiple cards can be the same or different. The SIM card interface 195 can also be compatible with different types of SIM cards. The SIM card interface 195 can also be compatible with external memory cards. The electronic device 100 interacts with the network through the SIM card to implement functions such as calls and data communications. In some embodiments, the electronic device 100 uses an eSIM, i.e., an embedded SIM card. The eSIM card can be embedded in the electronic device 100 and cannot be separated from the electronic device 100.

[0332] The software system of the electronic device 100 may adopt a layered architecture, an event-driven architecture, a micro-core architecture, a micro-service architecture, or a cloud architecture. In the embodiment of the present invention, the Android system of the layered architecture is taken as an example to exemplify the software structure of the electronic device 100.

[0333] Fig.17 1 is a software structure block diagram of the electronic device 100 according to an embodiment of the present invention.

[0334] The layered architecture divides the software into several layers, each with clear roles and division of labor. The layers communicate with each other through software interfaces. In some embodiments, the Android system is divided into four layers, from top to bottom: the application layer, the application framework layer, the Android runtime and system library, and the kernel layer.

[0335] The application layer can include a series of application packages.

[0336] like Fig.17 As shown, the application package may include applications such as camera, gallery, game, call, map, navigation, WLAN, Bluetooth, music, video, short message, etc.

[0337] The application framework layer provides an application programming interface (API) and a programming framework for the applications in the application layer. The application framework layer includes some predefined functions.

[0338] like Fig.17 As shown, the application framework layer may include a window manager, a content provider, a view system, a phone manager, a resource manager, a notification manager, and the like.

[0339] The window manager is used to manage window programs. The window manager can obtain the display screen size, determine whether there is a status bar, lock the screen, capture the screen, etc.

[0340] Content providers are used to store and retrieve data and make it accessible to applications. The data can include videos, images, audio, calls made and received, browsing history and bookmarks, phone books, etc.

[0341] The view system includes visual controls, such as controls for displaying text, controls for displaying images, etc. The view system can be used to build applications. A display panel can be composed of one or more views. For example, a display panel including a text notification icon can include a view for displaying text and a view for displaying images.

[0342] The phone manager is used to provide communication functions of the electronic device 100, such as management of call status (including connecting, hanging up, etc.).

[0343] The resource manager provides various resources for applications, such as localized strings, icons, images, layout files, video files, and so on.

[0344] The notification manager enables applications to display notification information in the status bar. It can be used to convey notification-type messages and can disappear automatically after a short stay without user interaction. For example, the notification manager is used to notify download completion, message reminders, etc. The notification manager can also be a notification that appears in the system top status bar in the form of a chart or scroll bar text, such as notifications of applications running in the background, or a notification that appears on the screen in the form of a dialog window. For example, a text message is displayed in the status bar, a prompt sound is emitted, an electronic device vibrates, an indicator light flashes, etc.

[0345] Android Runtime includes core libraries and virtual machines. Android runtime is responsible for scheduling and management of the Android system.

[0346] The core library consists of two parts: one part is the function that needs to be called by the Java language, and the other part is the Android core library.

[0347] The application layer and the application framework layer run in a virtual machine. The virtual machine executes the Java files of the application layer and the application framework layer as binary files. The virtual machine is used to perform functions such as object life cycle management, stack management, thread management, security and exception management, and garbage collection.

[0348] The system library may include multiple functional modules, such as surface manager, media library, 3D graphics processing library (such as OpenGL ES), 2D graphics engine (such as SGL), etc.

[0349] The surface manager is used to manage the display subsystem and provide the fusion of 2D and 3D layers for multiple applications.

[0350] The media library supports playback and recording of a variety of commonly used audio and video formats, as well as static image files, etc. The media library can support a variety of audio and video encoding formats, such as: MPEG4, H.264, MP3, AAC, AMR, JPG, PNG, etc.

[0351] The 3D graphics processing library is used to implement 3D graphics drawing, image rendering, compositing, and layer processing.

[0352] A 2D graphics engine is a drawing engine for 2D drawings.

[0353] The kernel layer is the layer between hardware and software. The kernel layer contains at least display driver, camera driver, audio driver, and sensor driver.

[0354] The following is an illustrative description of the workflow of the software and hardware of the electronic device 100 in conjunction with capturing a photo scene.

[0355] When the touch sensor 180K receives a touch operation, the corresponding hardware interrupt is sent to the kernel layer. The kernel layer processes the touch operation into a raw input event (including touch coordinates, timestamp of the touch operation, and other information). The raw input event is stored in the kernel layer. The application framework layer obtains the raw input event from the kernel layer and identifies the control corresponding to the input event. For example, if the touch operation is a touch single-click operation and the control corresponding to the single-click operation is the control of the camera application icon, the camera application calls the interface of the application framework layer to start the camera application, and then starts the camera driver by calling the kernel layer to capture static images or videos through the camera 193.

[0356] The voltage control method provided in the embodiment of the present application can be applied to electronic devices with communication functions. The electronic devices include terminal devices, and the specific device form of the terminal devices can refer to the above related descriptions, which will not be repeated here.

[0357] An embodiment of the present application provides an electronic device, which includes: a processor, a display driver chip (DDIC), a pixel circuit and a memory. The memory stores computer-executable instructions. The processor instructs the display driver chip to drive the pixel circuit. The display driver chip executes the computer-executable instructions stored in the memory, so that the electronic device executes the above method and drives the pixel circuit.

[0358] The embodiment of the present application provides a chip. The chip includes a processor, and the processor is used to call a computer program in a memory to execute the technical solution in the above embodiment. Its implementation principle and technical effect are similar to those of the above related embodiments, and will not be repeated here.

[0359] The embodiment of the present application also provides a computer-readable storage medium. The computer-readable storage medium stores a computer program. The above method is implemented when the computer program is executed by a display driver chip (DDIC). The method described in the above embodiment can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. If implemented in software, the function can be stored as one or more instructions or codes on a computer-readable medium or transmitted on a computer-readable medium. Computer-readable media may include computer storage media and communication media, and may also include any medium that can transfer a computer program from one place to another. The storage medium may be any target medium that can be accessed by a computer.

[0360] In one possible implementation, a computer-readable medium may include RAM, ROM, compact disc read-only memory (CD-ROM) or other optical disk storage, disk storage or other magnetic storage devices, or any other medium that is intended to carry or store the required program code in the form of instructions or data structures and can be accessed by a computer. Moreover, any connection is appropriately referred to as a computer-readable medium. For example, if a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technology (such as infrared, radio and microwave) is used to transmit software from a website, server or other remote source, the coaxial cable, fiber optic cable, twisted pair, DSL or wireless technology such as infrared, radio and microwave are included in the definition of medium. Disks and optical disks as used herein include optical disks, laser disks, optical disks, digital versatile disks (DVD), floppy disks and Blu-ray disks, where disks usually reproduce data magnetically, while optical disks reproduce data optically using lasers. Combinations of the above should also be included in the scope of computer-readable media.

[0361] An embodiment of the present application provides a computer program product, which includes a computer program. When the computer program is executed, the computer executes the above method.

[0362] The embodiments of the present application are described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processing unit of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable device to generate a machine, so that the instructions executed by the processing unit of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0363] The above specific implementation methods further illustrate the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above are only specific implementation methods of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made on the basis of the technical solutions of the present invention should be included in the scope of protection of the present invention.

Claims

1. A voltage control method, characterized in that: Applicable to an electronic device having a pixel circuit, the pixel circuit comprising a driving module, a control end of the driving module being connected to a first node, and a source end of the driving module being connected to a second node; the method comprising: When driving the first area to display the first frame image, controlling the voltage of the first node to be the first voltage, and controlling the voltage of the second node to be the second voltage; When driving the second area to display the first frame image, controlling the voltage of the first node to be a third voltage, and controlling the voltage of the second node to be a fourth voltage; Among them, the voltage difference between the first voltage and the second voltage is greater than the voltage difference between the third voltage and the fourth voltage; the refresh rate of the first area is the first refresh rate, the refresh rate of the second area is the second refresh rate, and the first refresh rate is lower than the second refresh rate.

2. The method according to claim 1, characterized in that The first voltage is greater than the third voltage, and / or the second voltage is less than the fourth voltage.

3. The method according to claim 1 or 2, characterized in that: The pixel circuit further includes a data writing unit, wherein the data writing unit is connected to the second node; When the first area and the second area of ​​the first frame image are displayed, the data writing unit is enabled; The method further comprises: When driving the first area to display a second frame of image, controlling the voltage of the first node to be the first voltage, and controlling the voltage of the second node to be the second voltage; when displaying the first area of ​​the second frame of image, the data writing unit is not enabled; When driving the second area to display the second frame image, the voltage of the first node is controlled to be the third voltage, and the voltage of the second node is controlled to be the fourth voltage; when displaying the second area of ​​the second frame image, the data writing unit is enabled.

4. The method according to claim 3, characterized in that The method further comprises: When driving the first area to display the third frame image, controlling the voltage of the first node to be the first voltage, and controlling the voltage of the second node to be the second voltage; when displaying the first area of ​​the third frame image, the data writing unit is not enabled; When driving the second area to display the third frame image, the voltage of the first node is controlled to be the third voltage, and the voltage of the second node is controlled to be the fourth voltage; when displaying the second area of ​​the third frame image, the data writing unit is enabled.

5. The method according to claim 4, characterized in that The method further comprises: When driving the first area to display a fourth frame of image, controlling the voltage of the first node to be the third voltage, and controlling the voltage of the second node to be the fourth voltage; when displaying the first area of ​​the fourth frame of image, the data writing unit is not enabled; When driving the second area to display the fourth frame image, the voltage of the first node is controlled to be the third voltage, and the voltage of the second node is controlled to be the fourth voltage; when displaying the second area of ​​the fourth frame image, the data writing unit is enabled.

6. The method according to claim 1 or 2, characterized in that: The pixel circuit further includes a data writing unit, wherein the data writing unit is connected to the second node; When the first area and the second area of ​​the first frame image are displayed, the data writing unit is enabled; The method further comprises: When driving the first area to display the second frame image, controlling the voltage of the first node to be the third voltage, and controlling the voltage of the second node to be the fourth voltage; when displaying the first area of ​​the second frame image, the data writing unit is not enabled; When driving the second area to display the second frame image, the voltage of the first node is controlled to be the third voltage, and the voltage of the second node is controlled to be the fourth voltage; when displaying the second area of ​​the second frame image, the data writing unit is enabled.

7. The method according to any one of claims 1 to 6, characterized in that The method further comprises: Determining a starting position and an ending position of the first area based on an identifier of the pixel circuit corresponding to the first area; Based on the identifier of the pixel circuit corresponding to the second area, a starting position and an ending position of the second area are determined.

8. The method according to any one of claims 1 to 7, characterized in that The method further comprises: When driving the third area to display the first frame image, the voltage of the first node is controlled to be the first voltage, and the voltage of the second node is controlled to be the second voltage; the refresh rate of the third area is the third refresh rate, and the third refresh rate is lower than the second refresh rate.

9. The method according to any one of claims 1 to 8, characterized in that The driving module comprises a driving thin film transistor DTFT, a drain terminal of the DTFT is connected to a third node, and the DTFT is used to output current to the third node under the control of the first node; The pixel circuit further includes: A first reset unit, connected to the first node, for responding to a first reset signal to load a first initialization voltage to the first node; A storage capacitor, one end of which is connected to the first node, and the other end of which is connected to the positive electrode of the power supply; A first light-emitting control unit, connected to the positive electrode of the power supply and the second node, for loading a first power supply voltage of the positive electrode of the power supply to the second node in response to a light-emitting control signal; a threshold compensation unit, connected to the first node and the third node, and configured to make the third node conductive with the first node in response to a first scanning signal; a second light emitting control unit, connected to the third node and the fourth node, and configured to conduct the third node and the fourth node in response to a light emitting control signal; a light emitting element, one end of which is connected to the fourth node, and the other end of which is connected to the negative electrode of the power supply so as to load the second power supply voltage of the negative electrode of the power supply; A second reset unit, connected to the fourth node, and configured to load a second initialization voltage to the fourth node in response to a second reset signal; a data writing unit connected to the second node and configured to load a data voltage to the second node in response to a second scanning signal; The third reset unit is connected to the second node and is used for loading a third initialization voltage to the second node in response to a second reset signal.

10. The method according to claim 9, characterized in that The first reset unit includes a first reset transistor, the first light emitting control unit includes a first light emitting control transistor, the threshold compensation unit includes a threshold compensation transistor, the second light emitting control unit includes a second light emitting control transistor, the light emitting element includes an organic light emitting diode OLED, the second reset unit includes a second reset transistor, the data writing unit includes a data writing transistor, and the third reset unit includes a third reset transistor.

11. An electronic device, characterized in that: include: Processor, display driver chip DDIC, pixel circuit and memory; The memory stores computer-executable instructions; The processor instructs the display driver chip to drive the pixel circuit; The display driver chip executes the computer-executable instructions stored in the memory, so that the electronic device executes the method according to any one of claims 1 to 10 and drives the pixel circuit.

12. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by the display driver chip DDIC, the method according to any one of claims 1 to 10 is implemented.

13. A computer program product, characterized in that The invention comprises a computer program, which, when being executed, enables a computer to execute the method according to any one of claims 1 to 10.

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