Sense amplifier for non-volatile memory

Abstract

The invention relates to a sense amplifier applied to a nonvolatile memory. A first memory cell in the nonvolatile memory is coupled to a data line. The sense amplifier includes a first switching element, a first voltage boost circuit and a comparator. The first end of the first switch element is connected to the data line, the second end of the first switch element is connected to the grounding end, and the control end of the first switch element receives a reset signal. The input end of the first voltage boosting circuit is connected to a data line, and the output end of the first voltage boosting circuit is connected to a sensing node. A first input end of the comparator receives the comparison voltage, a second input end of the comparator is connected to the sensing node, and an output end of the comparator generates output data.

Description

Technical Field

[0001] The present invention relates to a sense amplifier, and more particularly to a sense amplifier used in a non-volatile memory. Background Art

[0002] As is known to all, a memory cell array in a non-volatile memory includes a plurality of memory cells. A memory cell includes at least a selecting device and a storage device. For example, the storage device may be a floating gate transistor, an antifuse type transistor, or a resistive element. The following is a brief description.

[0003] The floating gate in the floating gate transistor can store hot carriers, such as electrons. The storage state of the memory cell can be determined according to the amount of hot carrier storage. For example, in the programming cycle of the non-volatile memory, the threshold voltage of the floating gate transistor can be changed by controlling the amount of hot carriers injected into the floating gate, and thus the storage state of the memory cell can be changed. During the read action, a read voltage is provided to the floating gate transistor, and a memory cell current, or read current, can be generated. According to the size of the memory cell current, it can be determined whether the storage state of the memory cell is the first storage state or the second storage state. Taking a p-type floating gate transistor as an example, during the read action, if the floating gate does not store hot carriers, the memory cell current generated by the memory cell is very small (almost zero), which can be regarded as the first storage state. On the contrary, if the floating gate stores hot carriers, the memory cell current generated by the memory cell is larger, which can be regarded as the second storage state.

[0004] The storage state of the anti-fuse transistor can be determined according to whether the gate dielectric layer is broken or not. During the programming action of the non-volatile memory, a programming voltage is provided to the anti-fuse transistor, so that the gate dielectric layer of the anti-fuse transistor is broken, and the storage state of the memory cell is changed. During the reading action, a read voltage is provided to the anti-fuse transistor, and a memory cell current, or read current, can be generated. According to the size of the memory cell current, it can be determined whether the storage state of the memory cell is the first storage state or the second storage state. For example, during the reading action, if the gate dielectric layer of the anti-fuse transistor is not broken, the memory cell current generated by the memory cell is very small (almost zero), which can be regarded as the first storage state. On the contrary, if the gate dielectric layer of the anti-fuse transistor is broken, the memory cell current generated by the memory cell is larger, which can be regarded as the second storage state.

[0005] Furthermore, providing different bias voltages to the resistive element can control the resistive element to switch between a high resistance value and a low resistance value, and the storage state of the memory cell can be determined according to the resistance value. For example, during the programming cycle of the non-volatile memory, different bias voltages are provided to control the resistance value of the resistive element. During the read action, a read voltage is provided to the resistive element, and a memory cell current, or read current, can be generated. According to the size of the memory cell current, it can be determined whether the storage state of the memory cell is the first storage state or the second storage state.

[0006] From the above description, it can be seen that a sense amplifier is further required in the non-volatile memory to receive the memory cell current generated by the memory cell and determine the storage state of the memory cell. Summary of the invention

[0007] The present invention relates to a sensing amplifier used in a non-volatile memory. A first memory cell in the non-volatile memory is coupled to a data line. The sensing amplifier comprises: a first switch element, a first end of the first switch element is connected to the data line, a second end of the first switch element is connected to a ground end, a control end of the first switch element receives a first control signal, and the first control signal is a reset signal; a first voltage boosting circuit, an input end of the first voltage boosting circuit is connected to the data line, an output end of the first voltage boosting circuit is connected to a sensing node; and a comparator, a first input end of the comparator receives a comparison voltage, a second input end of the comparator is connected to the sensing node, and a comparator of the comparator receives a comparison voltage. An output terminal generates an output data; wherein, during a reset phase of a read action, a data line voltage on the data line is reset to a ground voltage, and a sensing voltage of the sensing node is reset to the ground voltage; wherein, during a charging phase after the reset phase in the read action, a first memory cell current generated by the first memory cell charges the data line, and the first voltage boost circuit adjusts the sensing voltage to the data line voltage; wherein, during a boost phase after the charging phase in the read action, the first voltage boost circuit adjusts the sensing voltage to the data line voltage plus a first voltage increment; wherein the comparator generates the output data based on the comparison voltage and the sensing voltage to determine a storage state of the first memory cell.

[0008] In order to better understand the above and other aspects of the present invention, preferred embodiments are specifically described below with reference to the accompanying drawings for detailed description as follows: BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1A A memory cell that is a non-volatile memory;

[0010] Figure 1B , Figure 1C and Figure 1D A schematic diagram of bias voltage for programming a memory cell;

[0011] Figure 1E and Figure 1F A schematic diagram of bias voltage for a memory cell to perform a read operation;

[0012] Figure 2 is a schematic diagram of a non-volatile memory;

[0013] Figure 3A A sense amplifier according to a first embodiment of the present invention;

[0014] Figure 3B A schematic diagram of the operation of the sense amplifier when performing a reading operation;

[0015] Figure 3C A schematic diagram of related signals when the sense amplifier performs a reading operation;

[0016] Figure 3D A schematic diagram of the operation of the sense amplifier when performing a reading operation;

[0017] Figure 3E A schematic diagram of related signals when the sense amplifier performs a reading operation;

[0018] Figure 3F Selecting a relationship between a drain-source voltage of a transistor in a memory cell and a memory cell current;

[0019] Figure 4 A sense amplifier according to a second embodiment of the present invention;

[0020] Figure 5A is a detailed circuit diagram of a sense amplifier according to a second embodiment of the present invention;

[0021] FIG. 5B to FIG. 5D is a schematic diagram of the operation of the sense amplifier according to the second embodiment;

[0022] Figure 5E A schematic diagram of signals associated with a sense amplifier sensing a selected memory cell with a low resistance value;

[0023] Fig. 5F A schematic diagram of signals associated with a selected memory cell for sensing a high resistance value by a sense amplifier;

[0024] Figure 6 A second embodiment sense amplifier including a plurality of push-up elements;

[0025] 7A to 7D is a schematic diagram of the operation of a second embodiment of a sense amplifier including two boost elements;

[0026] Figure 8 is a schematic diagram of a sense amplifier according to a third embodiment of the present invention;

[0027] Fig. 9 A sense amplifier according to a fourth embodiment of the present invention; and

[0028] Fig.10 A detailed structural example of a push-up element.

[0029]

Explanation of symbols

[0030] 110: memory cell array

[0031] 120: Select circuit

[0032] 130: Sensing circuit

[0033] 131~13p: Sense amplifier

[0034] 201, 410, 950: Comparator

[0035] 400, 800, 900: Sense amplifier

[0036] 420, 820, 920, 925: Voltage boost circuit

[0037] 421, 601~60N: Pushing element

[0038] 801: Select memory cell

[0039] 802: Reference memory cell

[0040] 901: First storage cell

[0041] 902: Second storage cell

[0042] 910: Differential memory cell DETAILED DESCRIPTION

[0043] Please refer to Figure 1A , which is illustrated as a memory cell of a non-volatile memory. Figure 1B , Figure 1C and Figure 1D Schematic diagram of bias voltage for programming memory cells. Figure 1E and Figure 1F Schematic diagram of the bias voltage for reading a memory cell.

[0044] The non-volatile memory cell includes a selection device and a storage device. For example, the storage device may be an anti-fuse transistor M. AF , the selection element may be a selection transistor M SEL . Select transistor M SEL The first drain / source terminal of the transistor M is connected to the bit line BL, and the transistor M is selected. SEL The gate terminal of the anti-fuse transistor M is connected to the word line WL. AF The first drain / source terminal is connected to the selection transistor M SEL The second drain / source terminal of the anti-fuse transistor M AF The gate terminal of the anti-fuse transistor M is connected to the control line CL. AF The second drain / source terminal is floating.

[0045] Basically, during programming, the memory cell can be controlled to present two different storage states. Figure 1BAs shown, during the programming action, the control line CL receives the programming voltage Vpp, the bit line BL receives the ground voltage 0V, and the word line WL receives the turn-on voltage Von. At this time, the transistor M is selected. SEL Turn on, the anti-fuse transistor M AF The voltage stress on the gate dielectric layer is the programming voltage Vpp, causing the anti-fuse transistor M AF The gate dielectric layer of the memory cell is ruptured, and the memory cell presents a low resistance storage state. For example, the programming voltage Vpp is 5V and the turn-on voltage Von is 1.2V.

[0046] like Figure 1C As shown, during the programming action, the control line CL receives the programming voltage Vpp, the bit line BL receives the ground voltage 0V, and the word line WL receives the off voltage Voff. SEL Turn off, the anti-fuse transistor M AF The gate dielectric layer of the anti-fuse transistor M will not be subjected to voltage stress, so AF The gate dielectric layer will not rupture, and the memory cell will present a high resistance storage state. Figure 1D As shown, during programming, the bit line BL is allowed to float, and the word line WL receives the on voltage Von, which can also make the memory cell present a high resistance storage state. For example, the off voltage Voff is 0V.

[0047] Furthermore, the storage state of the memory cell can be determined during the reading operation. Figure 1E and Figure 1F As shown, during the reading operation, the control line CL receives the reading voltage Vr, the bit line BL receives the ground voltage 0V, and the word line WL receives the turn-on voltage Von. Figure 1E As shown, the selection transistor M SEL Turn on. Since the anti-fuse transistor M AF The gate dielectric layer of the memory cell is ruptured, so the memory cell will output a larger memory cell current I on the bit line BL. R .like Figure 1F As shown, the selection transistor M SEL Turn on. Since the anti-fuse transistor M AF The gate dielectric layer of the memory cell is not broken, so the memory cell outputs a small almost zero memory cell current (I R =0). Therefore, during the reading operation, the two storage states of the memory cell can be determined according to the magnitude of the memory cell current on the bit line BL. For example, the reading voltage Vr is 2.5V.

[0048] Of course, other types of non-volatile memory cells, such as memory elements that are floating gate transistors or resistive elements, can also determine the storage state of the memory cell according to the magnitude of the memory cell current during the reading operation, which will not be described in detail here.

[0049] Please refer to Figure 2 , which is a schematic diagram of a non-volatile memory. The volatile memory includes a memory cell array 110, a selecting circuit 120 and a sensing circuit 130. The memory cell array 110 includes m×n memory cells C 11 ~C mn , where m and n are positive integers. 11 ~C mn The storage element may be an anti-fuse transistor, a floating gate transistor, or a resistive element.

[0050] like Figure 2 As shown, all memory cells C of the memory cell array 110 11 ~C mn All are connected to the control line CL. Furthermore, in the memory cell array 110, the n memory cells C in the first row 11 ~C 1n Connected to word line WL1, the first row of n memory cells C 11 ~C 1n Connected to the corresponding n bit lines BL1~BL n The n memory cells C in the second column 21 ~C 2n Connected to word line WL2, the n memory cells C in the second row 21 ~C 2n Connected to the corresponding n bit lines BL1~BL n . And so on, the n memory cells C in the mth column m1 ~C mn Connected to word line WL m , n memory cells C in the mth column m1 ~C mn Connected to the corresponding n bit lines BL1~BL n .

[0051] The selection circuit 120 is connected to n bit lines BL1-BL n And p data lines DL1~DL p , where p is a positive integer and p is less than or equal to n. When the non-volatile memory performs a read operation, the selection circuit 120 is composed of n bit lines BL1 to BL n p bit lines are determined and connected to p data lines DL1 to DLp .

[0052] The sensing circuit 130 includes p sensing amplifiers 131-13p connected to corresponding p data lines DL1-DL p The p sensing amplifiers 131-13p have the same circuit structure. During the reading operation, the p sensing amplifiers 131-13p of the sensing circuit 130 receive the corresponding data lines DL1-DL p The memory cell current on the memory cell generates p bits of output data D O1 ~D OP , is used to indicate the storage states of the corresponding p selected memory cells. That is, the sensing circuit 130 can determine the storage states of the p memory cells on the selected column each time.

[0053] For example, n is equal to 32, and p is equal to 8. In the read operation, the word line WL1 is activated, that is, the first column is the selected column. Furthermore, in the first sensing cycle, the selection circuit 120 connects the bit lines BL1-BL8 to the data lines DL1-DL8, so that the 8 memory cells C of the selected column 11 ~C 18 To select a memory cell, select memory cell C 11 ~C 18 The generated memory cell current flows to the sensing circuit 130. According to the memory cell current on the data lines DL1-DL8, the sensing circuit 130 generates a byte of output data D O1 ~D O8 Used to indicate the selected memory cell C 11 ~C 18 storage status.

[0054] Similarly, during the second sensing cycle of the read operation, the selection circuit 120 switches the bit lines BL9 to BL 16 connected to the data lines DL1-DL8, and the sensing circuit 130 generates output data D O1 ~D O8 In the third sensing cycle of the read operation, the selection circuit 120 will select the bit line BL 17 ~BL 24 connected to the data lines DL1-DL8, and the sensing circuit 130 generates output data D O1 ~D O8 In the fourth sensing cycle of the read operation, the selection circuit 120 will select the bit line BL 25 ~BL 32 connected to the data lines DL1-DL8, and the sensing circuit 130 generates output data D O1 ~D O8Therefore, according to the four output data D generated by the sensing circuit 130 in four sensing cycles, O1 ~D O8 , you can get the first column (selected column) of 32 (n = 32) memory cells C 11 ~C 1n Since the p sense amplifiers 131-13p have the same circuit structure, only the sense amplifier 131 and its operating principle are described below.

[0055] Please refer to Figure 3A , which illustrates a sensing amplifier according to a first embodiment of the present invention.

[0056] The detection amplifier 131 includes a switching device SW1 and a comparator 201. A first terminal of the switching device SW1 is connected to the data line DL1, a second terminal of the switching device SW1 is connected to the ground terminal GND, and a control terminal of the switching device SW1 receives a reset signal R ST The first input terminal of the comparator 201 receives a comparison voltage (V CMP ), the second input terminal of the comparator 201 is connected to the data line DL1, and the output terminal of the comparator 201 generates the output data D O1 In addition, the enable terminal of the comparator 201 receives an enable signal EN.

[0057] For example, the switch element is a switching transistor M SW1 . Switching transistor M SW1 The first drain / source terminal of the switch transistor M is connected to the data line DL1. SW1 The second drain / source terminal of the switch transistor M is connected to the ground terminal GND. SW1 The gate terminal receives the reset signal R ST Furthermore, the comparator 201 can be implemented by an operation amplifier.

[0058] During a read operation, the selection circuit 120 couples a selected memory cell in the memory cell array 110 to the sense amplifier 131. The sense amplifier 131 then senses the memory cell current I R The operation of the sense amplifier 131 can be determined by FIG. 3B to FIG. 3E ’s illustration to understand.

[0059] Please refer to Figure 3B and Figure 3D, which is a schematic diagram of the operation of the sense amplifier when performing a reading operation. Figure 3C and Figure 3E , which is a schematic diagram of related signals when the sense amplifier performs a reading operation.

[0060] like Figure 3B and Figure 3C As shown, during the read operation, the word line WL in the memory cell array Y and bit line BL Z Action, select memory cell C YZ Through the bit line BL Z is coupled to the data line DL1. Between time point t1 and time point t2, the reset signal R ST is high level, the switch transistor M SW1 Turn on means that the switch element SW1 is in a closed state, and the data line DL1 is pulled down to the ground voltage, that is, the data line voltage V DL1 is 0V.

[0061] Between time point t2 and time point t4, the reset signal R ST is low level, the switch transistor M SW1 Turnoff means that the switch element SW1 is in the open state, and the memory cell current I RYZ Charge the data line DL1, so the data line voltage V DL1 It starts to rise from 0V. Since the anti-fuse transistor M AF The gate dielectric layer of the selected memory cell C is not broken. YZ Produces a small almost zero memory cell current I RYZ The data line DL1 is charged, so the data line voltage V DL1 At time point t4, the enable signal EN is activated and the comparator 210 starts to operate. DL1 Less than the comparison voltage V CMP , the comparator 210 generates a low level output data D O1 The sense amplifier 131 generates a low level output data D O1 Represents the selected memory cell C YZ It is a storage state of high resistance value (first storage state).

[0062] like Figure 3D and Figure 3E As shown, during the read operation, the word line WL in the memory cell array W and bit line BL X Action, select memory cell CWX Through the bit line BL X is coupled to the data line DL1. Between time point t1 and time point t2, the reset signal R ST is high level, the switch transistor M SW1 Turn on means that the switch element SW1 is in a closed state, and the data line DL1 is pulled down to the ground voltage, that is, the data line voltage V DL1 is 0V.

[0063] Between time point t2 and time point t4, the reset signal R ST is low level, the switch transistor M SW1 Turnoff means that the switch element SW1 is in the open state, and the memory cell current I RWX Charge the data line DL1, so the data line voltage V DL1 It starts to rise from 0V. Since the anti-fuse transistor M AF The gate dielectric layer of the selected memory cell C is broken. WX Generates a larger memory cell current I RWX After time t3, the data line voltage V DL1 Exceeds the comparison voltage V CMP At time point t4, the enable signal EN is activated and the comparator 210 starts to operate. DL1 Greater than the comparison voltage V CMP , the comparator 210 generates a high level output data D O1 The sense amplifier 131 generates a high level output data D O1 Represents the selected memory cell C WX It is a storage state with a low resistance value (second storage state).

[0064] exist FIG. 3B to FIG. 3E , the output data D of the sense amplifier 131 O1 A low level indicates that the selected memory cell is in the first storage state and outputs data D O1 A high level indicates that the selected memory cell is in the second storage state. Of course, the present invention is not limited to this. In fact, the connection relationship of the comparator 201 can also be changed so that the output data D O1 A high level indicates that the selected memory cell is in the first storage state and outputs data D O1 A low level indicates that the selected memory cell is in the second storage state.

[0065] Please refer to Figure 3F, which shows the relationship between the drain-source voltage of the selection transistor in the memory cell and the memory cell current.

[0066] by Figure 3D The selected memory cell C WX Take the following as an example. During the read operation, the word line WL W Receiving the on-state voltage Von of 1.2V, the read voltage Vr is 2.5V. Furthermore, the memory cell current I RWX Charge the data line DL1, so that the data line voltage V DL1 It starts to rise from 0V. The data line voltage V DL1 The rise will cause the selection transistor M SEL The drain-source voltage V DS decreases, causing the memory cell current I RWX Become smaller.

[0067] like Figure 3F As shown, when the transistor M is selected SEL The drain-source voltage V DS When the voltage is 2.2V, the memory cell current I RWX About 6μA. When transistor M is selected SEL The drain-source voltage V DS When the voltage is 1.8V, the memory cell current I RWX is about 2μA. That is, the selection transistor M SEL The drain-source voltage V DS When the memory cell current I changes from 2.2V to 1.8V, RWX The size difference is about three times.

[0068] During the read operation, the memory cell current I RWX Charge the data line DL1, so that the data line voltage V DL1 The data line voltage V DL1 The rise will cause the selection transistor M SEL The drain-source voltage V DS decreases, causing the memory cell current I RWX Rapidly decreases, resulting in a long sensing time. Or, due to the memory cell current I RWX Decay too quickly, causing the data line voltage V DL1 Cannot exceed comparison voltage V CMP , which is more likely to cause the sense amplifier 131 to misjudge.

[0069] Please refer to Figure 4, which illustrates a sensing amplifier according to a second embodiment of the present invention. In the sensing amplifier 400 according to the second embodiment of the present invention, a voltage boosting circuit 420 is added and connected between the data line DL and the comparator 410. Figure 3D In the second embodiment of the sense amplifier 400, the transistor M is selected. SEL The drain-source voltage V DS There will be a larger voltage value, so that the selected memory cell can generate a larger memory cell current I R , and the voltage boost circuit 420 can be based on the larger memory cell current I R And quickly boost the data line voltage V DL Therefore, the sense amplifier 400 can correctly determine the storage state of the selected memory cell.

[0070] The sense amplifier 400 includes a switching device SW1, a voltage boost circuit 420, and a comparator 410. The first end of the switching device SW1 is connected to the data line DL, the second end of the switching device SW1 is connected to the ground terminal GND, and the control end of the switching device SW1 receives a reset signal R ST .

[0071] The input terminal of the voltage boost circuit 420 is connected to the data line DL. Furthermore, the first input terminal of the comparator 410 receives the comparison voltage V CMP The second input terminal of the comparator 410 is connected to the output terminal of the voltage boost circuit 420, the enable terminal of the comparator 410 receives the enable signal EN, and the output terminal of the comparator 410 generates the output data D O .

[0072] The voltage boosting circuit 420 includes at least one boosting device. The operation principle of the boosting device and the sense amplifier 400 are described below.

[0073] Please refer to Figure 5A , which is a detailed circuit diagram of a sense amplifier 400 according to a second embodiment of the present invention, wherein the voltage boost circuit 420 only includes one boost element 421 .

[0074] The push-up element 421 includes a switch element SW A1 , SW B1 , SW C1and a capacitor C1. Node a1 is the input end of the push-up element 421, and node a2 is the output end of the push-up element 421. The input end of the push-up element 421 is connected to the data line DL, and the output end of the push-up element 421 is connected to the comparator 410. In the push-up element 421, the switch element SW A1 The first end of the switch element SW is connected to the node a1. A1 The second end of the switch element SW is connected to the node a2. A1 The control end receives the control signal S A1 . Switching element SW B1 The first end of the switch element SW is connected to the node a1. B1 The second end of the switch element SW is connected to the node a3. B1 The control end receives the control signal S B1 . Switching element SW C1 The first end of the switch element SW is connected to the node a3. C1 The second end of the switch element SW is connected to the ground terminal GND. C1 The control end receives the control signal S C1 The capacitor C1 is connected between the node a2 and the node a3.

[0075] The first input terminal of the comparator 410 receives the comparison voltage V CMP The second input terminal of the comparator 410 is connected to the node a2, the enable terminal of the comparator 410 receives the enable signal EN, and the output terminal of the comparator 410 generates the output data D O Basically, the node a2 is the output terminal of the push-up element 421, and the node a2 can be used as a sensing node. That is, the second input terminal of the comparator 410 is connected to the sensing node a2, and the comparator 410 generates a voltage V a2 And the comparison voltage V CMP The storage state of the selected memory cell is determined based on the relationship between the storage state of the selected memory cell.

[0076] Please refer to FIG. 5B to FIG. 5D , which is a schematic diagram of the operation of the sensing amplifier of the second embodiment. Figure 5E A schematic diagram of signals associated with a sense amplifier sensing a low resistance selected memory cell (second storage state). Fig. 5F A schematic diagram of signals associated with a sense amplifier sensing a high resistance selected memory cell (first storage state).

[0077] Please refer to Figure 5B and Figure 5E, time point t1 to time point t2 is the reset phase (RST) of the read operation. ST is high level, the control signal S A1 , S B1 , S C1 is high level, the switch elements SW1 and SW A1 , SW B1 , SW C1 is in the closed state. At this time, the data line voltage V DL , the sensing voltage V at the sensing node a2 a2 , the voltage V at node a3 a3 are both ground voltage (0V). That is, the sensing voltage V a2 is reset to ground voltage (0V). Basically, the reset signal R ST RST is active only during the reset phase, and the reset signal R ST That is, the switch element SW1 is in a closed state only in the reset phase RST and is in an open state in other phases.

[0078] Please refer to Figure 5C and Figure 5E The time point t2 to the time point t3 is the charging phase (CHG) of the read operation. A1 , S C1 is high level, the control signal S B1 is low level, the switch element SW A1 , SW C1 In the closed state, the switch element SW B1 is in the disconnected state. At this time, the memory cell current I R Charge the data line DL, the data line voltage V DL The voltage boost circuit 420 controls the data line voltage V DL Equal to the sensing voltage V of the sensing node a2 a2 That is, the sensing voltage V of the sensing node a2 a2 is charged to a voltage equal to the data line voltage V DL Furthermore, the voltage V at node a3 is a3 is the ground voltage (0V).

[0079] Please refer to Figure 5D and Figure 5E , time point t3 to time point t4 is the boost phase (BST) of the read operation. A1 , S C1 is low level, the control signal S B1 is high level, the switch element SW A1 , SWC1 In the off state, the switch element SW B1 At this time, since the voltage boost circuit 420 controls the node a2 to be floating, the voltage V a3 From 0V to the data line voltage V DL , capacitor C1 boosts the sensing voltage of sensing node a2 to the data line voltage V DL Add an incremental voltage ΔV. That is, the voltage boost circuit 420 controls the sensing voltage V of the sensing node a2. a2 The data line voltage V DL Push up a voltage increment ΔV, that is (V a2 =V DL The incremental voltage ΔV can be determined by the coupling ratio of the capacitor C1.

[0080] Furthermore, at the end time point t4 of the boost phase BST, the enable signal EN is activated and the comparator 410 starts to operate. At this time, the sensing voltage V a2 Greater than the comparison voltage V CMP , the comparator 410 generates a high level output data D O , representing that the selected memory cell is in a storage state of low resistance value (second storage state).

[0081] Similarly, when the selected memory cell is a high resistance value (first storage state), the sense amplifier 400 also goes through a reset phase RST, a charge phase CHG, and a boost phase BST. Fig. 5F As shown, during the charging phase CHG, due to the memory cell current I R Very small, almost equal to zero, the data line voltage V DL The sensing voltage V a2 Then, in the boost phase BST, due to the memory cell current I R is too small to raise the voltage V a3 So the sensing voltage V at the sensing node a2 is a2 There is almost no coupling voltage V at node a3 a3 The sense voltage V a2 That is, during the push-up phase BST, the sensing voltage V a2 Still far below the comparison voltage V CMP Therefore, at the end time point t4 of the boost phase BST, the enable signal EN is activated, and the sensing voltage V a2 Less than the comparison voltage V CMP, the comparator 410 generates a low level output data D O , representing that the selected memory cell is in a storage state of high resistance value (first storage state).

[0082] Compared to Figure 3E The data line voltage V DL , the sensing amplifier 400 of the present invention is in the charging stage, and the data line voltage V DL Charged to a relatively low voltage, so that the drain-source voltage V DS Large, maintained memory cell current I R In the boosting stage BST, the boosting element 421 can further increase the sensing voltage V a2 The data line voltage V DL Push up to (V DL +ΔV). Therefore, the sense amplifier 400 can correctly determine the storage state of the selected memory cell.

[0083] In the second embodiment, before the enable signal EN is activated, the comparator 410 is not operated to reduce the power consumption of the comparator 410. When the enable signal EN is activated, the comparator 410 operates and generates the output data D O Of course, those skilled in the art can also allow the comparator 410 to continue operating during the reading process, and the sense amplifier 400 can also generate the correct output data D O That is, the comparator 410 in the sense amplifier 400 may not be designed with an enable terminal, and the reading process of the comparator 410 continues to operate, and the correct output data D can also be generated. O .

[0084] Please refer to Figure 6 , which illustrates a second embodiment of a sense amplifier including a plurality of boost elements.

[0085] Compared to Figure 5A , Figure 6 The voltage boost circuit 420 in the sense amplifier 400 includes N boost elements 601-60N, where N is a positive integer. The N boost elements 601-60N are connected between the data line DL and the comparator 410. Each boost element 601-60N has the same structure. The following only introduces the connection relationship of the boost elements 601-60N, and the rest will not be repeated.

[0086] The input terminal a1 of the first boosting element 601 is connected to the data line DL. The output terminal n2 of the last (Nth) boosting element 60N is connected to the comparator 410, so the node n2 is the sensing node. The input terminals of other boosting elements are connected to the output terminals of the previous boosting element, and the output terminals of other boosting elements are connected to the input terminals of the next boosting element. In addition, the capacitors C1 to C2 in the N boosting elements 601 to 60N are connected to the comparator 410. N The capacitance values ​​may be the same or different. For example, the capacitor C1 of the first boosting element 601 has the largest capacitance value. The capacitance values ​​of the capacitors in the other boosting elements are smaller than the capacitance values ​​of the capacitors in the previous boosting element. Similarly, the capacitor C1 of the last boosting element 60N has the largest capacitance value. N Has the smallest capacitance value.

[0087] basically, Figure 6 The operation mode of the plurality of lifting elements 601-60N is similar to Figure 5A The operation of a single boosting element 421 is similar. The operation of the sense amplifier with two boosting elements is described below. The operation of the sense amplifier with other numbers of boosting elements can be deduced by oneself and will not be described in detail.

[0088] Please refer to 7A to 7D , which is a schematic diagram of the operation of the sensing amplifier of the second embodiment including two boost elements.

[0089] like Fig. 7A As shown, during the reset phase, all switch elements SW1, SW A1 , SW B1 , SW C1 , SW AN , SW BN , SW CN is in the closed state. At this time, the data line voltage V DL The voltages of the nodes a2, a3, n2, and n3 are all ground voltage (0V). That is, in the reset phase, the sensing voltage of the sensing node n2 is reset to the ground voltage (0V). After the reset phase RST, the switch element SW1 is in the off state.

[0090] like Figure 7B As shown, during the charging phase, the switching element SW B1 , SW BN In the off state, the switch element SW A1 , SW C1 , SW AN , SW CN is in the closed state. At this time, the memory cell current I R Charge the data line DL, the data line voltage V DL rises, and the data line voltage VDL is equal to the voltage of node a2 and node n2. That is, during the charging phase, the sensing voltage of the sensing node n2 is charged to be equal to the data line voltage V DL Furthermore, the voltages of the node a3 and the node n3 are the ground voltage (0V).

[0091] like Figure 7C As shown, in the first push-up phase, the switch element SW B1 , SW AN , SW CN In the off state, the switch element SW A1 , SW C1 , SW BN is in the closed state. At this time, the data line voltage V DL = equal to the voltage of node a2 and node n3, the sensing voltage of sensing node n2 is pushed up to (V DL +ΔV1). That is, in the first boosting stage, the sensing voltage of the sensing node n2 is boosted to (V DL +ΔV1). Furthermore, the voltage of the node a3 is the ground voltage (0V).

[0092] like Fig.7D As shown, in the second push-up phase, the switch element SW A1 , SW C1 , SW AN , SW CN In the off state, the switch element SW B1 , SW BN is in the closed state. At this time, the data line voltage V DL The voltage of node a3 is equal to that of node a2, and the voltage of node n3 is pushed up to (V DL +ΔV2), the sensing voltage of the sensing node n2 is further increased to (V DL +ΔV1+ΔV2). That is, in the second boosting stage, the sensing voltage of the sensing node n2 is boosted to (V DL +ΔV1+ΔV2). Therefore, the comparator 410 can determine the storage state of the selected memory cell according to the voltage of the node n2.

[0093] In addition, in the second embodiment of the present invention, the comparison voltage V CMP is a fixed voltage that can be provided by a power supplier. The present invention can also use a similar concept to design a voltage generator. The voltage generator includes a reference memory cell, which can generate a memory cell current and is combined with a voltage boost circuit to generate a comparison voltage V CMP .

[0094] Please refer to Figure 8 , which is a schematic diagram of a sensing amplifier according to a third embodiment of the present invention. Figure 4 The sense amplifier 400 of the third embodiment further includes a voltage generator 810. The detailed circuit of the voltage generator 810 is introduced below, and the rest is not repeated here.

[0095] In the memory cell array, the memory cell in the first storage state (high resistance storage state) and the memory cell in the second storage state (low resistance storage state) will generate different memory cell currents. For example, the memory cell in the second storage state can generate a memory cell current of 3μA, and the memory cell in the first storage state can generate a memory cell current of 0μA. In the third embodiment of the present invention, the reference memory cell 802 is appropriately designed so that the reference memory cell 802 can generate a memory cell current I of 1.5μA. REF That is, in the voltage generator 810, the memory cell current I generated by the reference memory cell 802 is REF The size is between the memory cell current of the first storage state memory cell and the memory cell current of the second storage state memory cell. Therefore, during the reading operation, the selected memory cell 801 is coupled to the data line DL, and the reference memory cell 802 is coupled to the reference data line DL REF The comparator 410 determines the storage state of the selected memory cell 801 according to the voltages of the two voltage boosting circuits 420 and 820 .

[0096] The voltage generator 810 includes a reference memory cell 802, a switch element SW2, and a voltage boost circuit 820. The first terminal of the switch element SW2 is connected to the reference data line DL REF The second end of the switch element SW2 is connected to the ground terminal GND, and the control end of the switch element SW2 receives the reset signal R ST The input terminal of the voltage boost circuit 820 is connected to the reference data line DL REF The output terminal of the voltage boost circuit 820 generates a comparison voltage V CMP To comparator 410.

[0097] According to the third embodiment of the present invention, in the sense amplifier 800, the two switch elements SW1 and SW2 receive the same reset signal R ST Furthermore, the circuit structures of the two voltage boosting circuits 420 and 820 are completely the same, and the control signals received by the two voltage boosting circuits 420 and 820 are also completely the same. For example, when the two voltage boosting circuits 420 and 820 both include a boosting element, the three control signals S A1 , S B1 , S C1The corresponding three switch elements in the two voltage boosting circuits 420 and 820 can be controlled simultaneously.

[0098] During the reset phase of the read operation, the data line DL and the reference data line DL REF , both input terminals of the comparator 410 are reset to the ground voltage (0V). That is, during the reset phase, the voltage at the output terminal of the voltage boost circuit 420 is reset to the ground voltage (0V), and the comparison voltage V CMP is reset to ground voltage (0V).

[0099] During the charging phase of the read operation, the memory cell current I R Charging data line DL, reference memory cell current I of reference memory cell 802 REF Charging reference data line DL REF That is, during the charging phase, the voltage at the output end of the voltage boost circuit 420 is charged to a voltage equal to the data line voltage V DL , the comparison voltage V at the output end of the voltage boost circuit 820 CMP is charged to a voltage equal to the reference data line voltage V DLREF .

[0100] During the boost phase of the read operation, the voltage output by the voltage boost circuit 420 is the data line voltage V DL Add a first voltage increment ΔV1 (ie, V DL +ΔV1). The voltage boost circuit 820 outputs a comparison voltage V CMP is the reference data line voltage V DLREF plus a second voltage increment ΔV2 (ie, V DLREF +ΔV2). That is, in the boosting stage, the voltage at the output end of the voltage boosting circuit 420 is boosted to (V DL +ΔV1), the comparison voltage V at the output end of the voltage boost circuit 820 CMP is pushed up to (V DLREF +ΔV2). Therefore, the comparator 410 determines the storage state of the selected memory cell according to the voltages output by the two voltage boosting circuits 420 and 820.

[0101] With a similar operating principle, the sensing amplifier 800 of the third embodiment can be further applied to a non-volatile memory of a differential cell. As is well known, a single differential memory cell includes two memory cells. After the programming operation, the two memory cells are in complementary storage states. For example, when the first memory cell is in a high resistance storage state and the second memory cell is in a low resistance storage state, the differential memory cell is in a first storage state. Alternatively, when the first memory cell is in a low resistance storage state and the second memory cell is in a high resistance storage state, the differential memory cell is in a second storage state. In other words, a differential memory cell is a memory cell that stores 1 bit of data using two memory cells.

[0102] Please refer to Fig. 9 , which is a sensing amplifier of the fourth embodiment of the present invention. During the reading operation, the first memory cell 901 in the selected differential memory cell 910 is coupled to the data line DL, and the second memory cell 902 in the selected differential memory cell 910 is coupled to the inverted data line DL B Furthermore, the sense amplifier 900 includes two switch elements SW1 and SW2 , two voltage boost circuits 920 and 925 , and a comparator 950 .

[0103] The first end of the switch element SW1 is connected to the data line DL, the second end of the switch element SW1 is connected to the ground terminal GND, and the control end of the switch element SW1 receives the reset signal R ST The first end of the switch element SW2 is connected to the inverting data line DL B The second end of the switch element SW2 is connected to the ground terminal GND, and the control end of the switch element SW2 receives the reset signal R ST .

[0104] The input end of the voltage boost circuit 920 is connected to the data line DL, and the output end of the voltage boost circuit 920 is connected to the first input end of the comparator 950. The input end of the voltage boost circuit 925 is connected to the inverted data line DL B The output terminal of the voltage boost circuit 925 is connected to the second input terminal of the comparator 950. The enable terminal of the comparator 950 receives the enable signal EN, and the output terminal of the comparator 905 generates the output data D O .

[0105] Similarly, the two switch elements SW1 and SW2 receive the same reset signal R ST Furthermore, the circuit structures of the two voltage boosting circuits 920 and 925 are completely the same, and the control signals received by the two voltage boosting circuits 920 and 925 are also completely the same.

[0106] Similar to the sense amplifier 800 of the third embodiment, the sense amplifier 900 may go through a reset phase, a charging phase and a boost phase during a read operation. Afterwards, the comparator 950 determines the storage state of the selected differential memory cell according to the voltages at the output terminals of the two voltage boost circuits 920 and 925 .

[0107] Please refer to Fig.10 , which shows a detailed structural example of the push-up element. The switch element SW in the push-up element A1 , SW B1 , SW C1 This can be achieved using n-type transistors.

[0108] like Fig.10 As shown, the push-up element 980 includes a switch element SW A1 , SW B1 , SW C1 The n-type transistors M NSWA1 、M NSWB1 、M NSWC1 Transistor M NSWA1 The first drain / source terminal of transistor M is connected to node a1. NSWA1 The second drain / source terminal of transistor M is connected to node a2. NSWA1 The gate terminal receives the control signal S A1 . Transistor M NSWB1 The first drain / source terminal of transistor M is connected to node a1, NSWB1 The second drain / source terminal of transistor M is connected to node a3. NSWB1 The gate terminal receives the control signal S B1 . Transistor M NSWC1 The first drain / source terminal of transistor M is connected to node a3, NSWC1 The second drain / source terminal of the transistor M is connected to the ground terminal GND. NSWC1 The gate terminal receives the control signal S C1 Among them, the control signal S A1 , S B1 , S C1 When the switch element SW is high, A1 , SW B1 , SW C1 It is in the closed state. Control signal S A1 , S B1 , S C1 When the switching element SW is low, A1 , SW B1 , SW C1 In addition, the capacitor C1 can be connected by an n-type transistor M NC1 To achieve this, transistor MNC1 The gate terminal of transistor M is connected to node a2. NC1 The first drain / source terminal and the second drain / source terminal are connected to the node a3.

[0109] certainly, Fig.10 The connection relationship of capacitor C1 in can also be modified. For example, transistor M NC1 The first drain / source terminal and the second drain / source terminal of the transistor M are connected to the node a2. NC1 The gate terminal of transistor M is connected to node a3. NC1 It may also be a depletion n-type transistor.

[0110] From the above description, it can be seen that the present invention proposes a sensing amplifier for non-volatile memory. The sensing amplifier includes a voltage boost circuit connected between the data line and the comparator. Therefore, the sensing amplifier of the present invention can charge the data line voltage V DL to a relatively small voltage, so that the selected memory cell can generate a large memory cell current I R , the sensing time of the sense amplifier 400 can be shortened and the sense amplifier 400 can correctly determine the storage state of the selected memory cell.

[0111] In summary, although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Those skilled in the art may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the attached claims.

Claims

1. A sense amplifier for a non-volatile memory, wherein a first memory cell in the non-volatile memory is coupled to a data line, the sense amplifier comprising: A first switch element, wherein a first end of the first switch element is connected to the data line, a second end of the first switch element is connected to a ground end, and a control end of the first switch element receives a first control signal, and the first control signal is a reset signal; A first voltage boosting circuit, wherein an input end of the first voltage boosting circuit is connected to the data line, and an output end of the first voltage boosting circuit is connected to the sensing node; as well as A comparator, wherein a first input terminal of the comparator receives a comparison voltage, a second input terminal of the comparator is connected to the sensing node, and an output terminal of the comparator generates output data; Wherein, during the reset phase of the read action, the data line voltage on the data line is reset to a ground voltage, and the sensing voltage of the sensing node is reset to the ground voltage; Wherein, during the charging phase after the reset phase in the reading operation, the first memory cell current generated by the first memory cell charges the data line, and the first voltage boost circuit adjusts the sensing voltage to the data line voltage; Wherein, during the boosting phase after the charging phase in the reading operation, the first voltage boosting circuit adjusts the sensing voltage to the data line voltage plus a first voltage increment; The comparator generates the output data according to the comparison voltage and the sensing voltage to determine the storage state of the first memory cell.

2. The sensing amplifier as claimed in claim 1, wherein the first switching element is a first transistor, a first drain / source terminal of the first transistor is connected to the data line, a second drain / source terminal of the first transistor is connected to the ground terminal, and a gate terminal of the first transistor receives the first control signal.

3. The sensing amplifier as claimed in claim 1, wherein the comparator comprises an enable terminal for receiving an enable signal; and when the boost phase of the read operation ends, the enable signal is activated, and the comparator generates the output data according to the comparison voltage and the sensing voltage.

4. The sense amplifier as claimed in claim 1, wherein the first voltage boost circuit comprises a boost element, an input end of the boost element is connected to a first node, and the first node is connected to the data line, and an output end of the boost element is connected to the sensing node, and the boost element comprises: a second switch element, a first terminal of the second switch element being connected to the first node, a second terminal of the second switch element being connected to the sensing node, and a control terminal of the second switch element receiving a second control signal; a third switch element, a first terminal of the third switch element being connected to the first node, a second terminal of the third switch element being connected to the second node, and a control terminal of the third switch element receiving a third control signal; a fourth switch element, wherein a first terminal of the fourth switch element is connected to the second node, a second terminal of the fourth switch element is connected to the ground terminal, and a control terminal of the fourth switch element receives a fourth control signal; as well as A first capacitor has a first terminal connected to the sensing node and a second terminal connected to the second node.

5. The sense amplifier of claim 4, wherein: During the reset phase of the read action, the first switch element, the second switch element, the third switch element and the fourth switch element are in the closed state, and the data line voltage and the sensing voltage are reset to the ground voltage; during the charging phase of the read action, the second switch element and the fourth switch element are in the closed state, the first switch element and the third switch element are in the open state, and the data line voltage is equal to the sensing voltage; and, during the push-up phase of the read action, the third switch element is in the closed state, the first switch element, the second switch element and the fourth switch element are in the open state, and the sensing voltage is equal to the data line voltage plus the first voltage increment.

6. The sense amplifier as claimed in claim 1, wherein the first voltage boost circuit comprises a boost element, an input end of the boost element is connected to a first node, and the first node is connected to the data line, an output end of the boost element is connected to the sensing node, and the boost element comprises: a second transistor, a first drain / source terminal of the second transistor being connected to the first node, a second drain / source terminal of the second transistor being connected to the sensing node, and a gate terminal of the second transistor receiving a second control signal; a third transistor, a first drain / source terminal of the third transistor being connected to the first node, a second drain / source terminal of the third transistor being connected to the second node, and a gate terminal of the third transistor receiving a third control signal; a fourth transistor, wherein a first drain / source terminal of the fourth transistor is connected to the second node, a second drain / source terminal of the fourth transistor is connected to the ground terminal, and a gate terminal of the fourth transistor receives a fourth control signal; as well as A first capacitor has a first terminal connected to the sensing node and a second terminal connected to the second node. 7 . The sense amplifier of claim 6 , wherein the first capacitor comprises a fifth transistor, a first drain / source terminal and a second drain / source terminal of the fifth transistor are connected to the second node, and a gate terminal of the fifth transistor is connected to the sense node. 8 . The sense amplifier as claimed in claim 7 , wherein the fifth transistor is a depletion-mode transistor.

9. The sensing amplifier as described in claim 1, wherein the first voltage boost circuit includes N boost elements, N is a positive integer greater than 1; among the N boost elements, the input end of the first boost element is connected to the first node, the output end of the Nth boost element is connected to the sensing node, the input ends of the other boost elements are connected to the output ends of the previous boost element, and the output ends of the other boost elements are connected to the input ends of the next boost element; and the first point is connected to the data line.

10. The sense amplifier of claim 9, wherein the first boost element comprises: A second switch element, wherein a first end of the second switch element is connected to the first node, a second end of the second switch element is connected to a second node, and the second node is the output end of the first push-up element, and a control end of the second switch element receives a second control signal; a third switch element, a first terminal of the third switch element being connected to the first node, a second terminal of the third switch element being connected to the third node, and a control terminal of the third switch element receiving a third control signal; a fourth switch element, wherein a first terminal of the fourth switch element is connected to the third node, a second terminal of the third switch element is connected to the ground terminal, and a control terminal of the fourth switch element receives a fourth control signal; as well as A first capacitor has a first terminal connected to the second node and a second terminal connected to the third node.

11. The sense amplifier of claim 9, wherein the first boost element comprises: A second transistor, wherein a first drain / source terminal of the second transistor is connected to the first node, a second drain / source terminal of the second transistor is connected to a second node, and the second node is the output terminal of the first push-up element, and a gate terminal of the second transistor receives a second control signal; a third transistor, a first drain / source terminal of the third transistor being connected to the first node, a second drain / source terminal of the third transistor being connected to a third node, and a gate terminal of the third transistor receiving a third control signal; a fourth transistor, wherein a first drain / source terminal of the fourth transistor is connected to the third node, a second drain / source terminal of the fourth transistor is connected to the ground terminal, and a gate terminal of the fourth transistor receives a fourth control signal; as well as A first capacitor has a first terminal connected to the second node and a second terminal connected to the third node. 12 . The sense amplifier of claim 11 , wherein the first capacitor comprises a fifth transistor, a first drain / source terminal and a second drain / source terminal of the fifth transistor are connected to the third node, and a gate terminal of the fifth transistor is connected to the second node. 13 . The sense amplifier as claimed in claim 12 , wherein the fifth transistor is a depletion-mode transistor.

14. The sense amplifier of claim 1 , further comprising: a reference memory cell coupled to the reference data line; a second switch element, wherein a first end of the second switch element is connected to the reference data line, a second end of the second switch element is connected to the ground end, and a control end of the second switch element receives the reset signal; as well as a second voltage boosting circuit, wherein the input end of the second voltage boosting circuit is connected to the reference data line, the output end of the second voltage boosting circuit is connected to the first input end of the comparator, and the output end of the second voltage boosting circuit generates the comparison signal; Wherein, when the first memory cell is in the first storage state, the first memory cell generates a first memory cell current to the data line in the read operation; when the first memory cell is in the second storage state, the first memory cell generates a second memory cell current to the data line in the read operation; and the reference memory cell generates a reference memory cell current whose magnitude is between the first memory cell current and the second memory cell current; Wherein, in the reset phase, the reference data line voltage on the reference data line is reset to the ground voltage, and the comparison voltage is reset to the ground voltage; Wherein, during the charging stage, the reference memory cell current generated by the reference memory cell charges the reference data line, and the second voltage boost circuit adjusts the comparison voltage to the reference data line voltage; In the boosting stage, the second voltage boosting circuit adjusts the comparison voltage to the reference data line voltage plus a second voltage increment.

15. The sense amplifier of claim 1 , further comprising: A second memory cell is coupled to the inverted data line, wherein the first memory cell and the second memory cell form a differential memory cell; A second switch element, a first end of the second switch element is connected to the inverted data line, a second end of the second switch element is connected to the ground end, and a control end of the second switch element receives the reset signal; A second voltage boost circuit, wherein the input end of the second voltage boost circuit is connected to the inverting data line, the output end of the second voltage boost circuit is connected to the first input end of the comparator, and the output end of the second voltage boost circuit generates the comparison voltage; Wherein, in the reset phase, the inverted data line voltage on the inverted data line is reset to the ground voltage, and the comparison voltage is reset to the ground voltage; Wherein, during the charging stage, the second memory cell current generated by the second memory cell charges the inverted data line, and the second voltage boost circuit adjusts the comparison voltage to the inverted data line voltage; In the boosting stage, the second voltage boosting circuit adjusts the comparison voltage to the inverted data line voltage plus a second voltage increment.

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