Memory device for performing channel pre-charge operation and method of operating same

Abstract

The invention relates to a memory device for performing a channel pre-charge operation and an operating method thereof. A memory device includes: a memory cell array including a plurality of memory cell strings coupled between a plurality of bit lines and a common source line, and a plurality of word lines coupled to the memory cell strings; and a control circuit configured to repeat a program loop including a program pulse application operation and a verify operation until the program operation is successfully performed for memory cells coupled to the selected word line, the selected memory cell string, and the plurality of bit lines, in addition, a channel pre-charge operation is performed along with a program pulse application operation and a verify operation from the selected program cycle, and a level of a pre-charge voltage applied to the common source line in the channel pre-charge operation is changed according to an operation temperature.

Description

Technical Field

[0001] Various embodiments of the present invention relate to a semiconductor memory device, and more particularly, to a memory device for performing a channel precharge operation and a method of operating the memory device. Background Art

[0002] A memory system is a storage device specifically implemented using semiconductors such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP), etc. The memory system may include a volatile memory device or a non-volatile memory device. A volatile memory device is a memory device in which the data stored therein is lost when the power is interrupted. Representative examples of volatile memory devices include static random access memory (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), etc. A non-volatile memory device is a memory device in which the data stored therein is retained even when the power is interrupted. Representative examples of non-volatile memory devices include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase change random access memory (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), etc. The flash memory may be a NOR type memory or a NAND type memory.

[0003] A cell of a nonvolatile memory device is an element that can perform electrical program / erase operations. A nonvolatile memory device can perform program operations and erase operations on a cell by changing a threshold voltage of the cell as electrons move through a strong electric field applied to a thin oxide film of the cell.

[0004] A programming operation on a plurality of memory cells included in a nonvolatile memory device may be performed by an incremental step pulse programming (ISPP) algorithm that changes a threshold voltage of a memory cell selected as a programming target while applying a programming pulse with a gradually increasing voltage to a word line to which the memory cell selected as a programming target is connected.

[0005] Furthermore, after applying the program pulse, a verification operation of checking whether the threshold voltage level of the memory cell selected as the program target has reached the target voltage level may be performed. Herein, the verification operation may be repeated together with the program pulse applying operation by the ISPP algorithm.

[0006] In addition, a channel precharge operation for applying a precharge voltage to the common source line may be performed before the program pulse applying operation is performed again after the verification operation. Summary of the invention

[0007] Embodiments of the present invention are directed to a memory device which can change a method for performing a channel precharge operation according to an operating temperature and a method of operating the memory device.

[0008] The technical problems that are expected to be solved in the embodiments of the present invention are not limited to the above-mentioned technical problems, and a person skilled in the art to which the present invention belongs can also clearly understand other technical problems not mentioned above from the following description.

[0009] According to an embodiment of the present invention, a memory device may include: a memory cell array, which includes a plurality of memory cell strings connected between a plurality of bit lines and a common source line and a plurality of word lines connected to the memory cell strings; and a control circuit, which is configured to: repeat a programming loop including a programming pulse application operation and a verification operation until a programming operation is successfully performed on memory cells connected to a selected word line, a selected memory cell string and a plurality of bit lines, and additionally perform a channel precharge operation together with the programming pulse application operation and the verification operation starting from the selected programming loop, and change a level of a precharge voltage applied to the common source line in the channel precharge operation according to an operating temperature.

[0010] According to another embodiment of the present invention, a method for operating a memory device is provided, the memory device including a plurality of memory cell strings connected between a plurality of bit lines and a common source line and a plurality of word lines connected to the memory cell strings, the method may include the following steps: repeatedly performing a programming loop including a programming pulse applying operation and a verification operation until the programming operation for the memory cells connected to the selected word line, the selected memory cell string and the plurality of bit lines is successfully performed; additionally performing a channel precharge operation together with the programming pulse applying operation and the verification operation starting from the selected programming loop; and changing the level of a precharge voltage applied to the common source line in the channel precharge operation according to an operating temperature. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 An example of a memory device according to an embodiment of the present invention is shown.

[0012] Figure 2A and Figure 2B In the embodiment according to the present invention, Figure 1 An example of operation of changing the timing of performing a channel precharge operation according to the operating temperature in a memory device is shown.

[0013] Figure 3 is shown in an embodiment according to the present invention Figure 1 A waveform diagram showing an example of an operation of changing the level of a voltage applied to a common source line in a channel precharge operation according to an operating temperature in a memory device is shown.

[0014] Figure 4 is shown in an embodiment according to the present invention Figure 1 A waveform diagram showing an example of an operation of changing a level of a voltage applied to a dummy word line adjacent to a common source line in a channel precharge operation according to an operating temperature in a memory device is shown.

[0015] Figure 5 is shown in an embodiment according to the present invention Figure 1 Waveform diagrams showing an example of an operation of changing a level of a voltage applied to a source selection line coupled between a common source line and a plurality of word lines in a channel precharge operation according to an operating temperature in a memory device are shown.

[0016] Figure 6 is a diagram showing an embodiment according to the present invention Figure 1 A block diagram of an example of a control circuit among constituent elements of a memory device shown in FIG.

[0017] Figure 7 It is described in accordance with an embodiment of the present invention Figure 1 A flow chart showing how the operation sequence of performing a channel precharge operation in a memory device is changed according to the operation temperature.

[0018] Fig. 8A and Figure 8B A phenomenon that occurs when a channel precharge operation is performed in a memory device is shown. DETAILED DESCRIPTION

[0019] Various embodiments of the present disclosure are described below with reference to the accompanying drawings. However, the elements and features of the present disclosure may be configured or arranged differently to form other embodiments, which may be variations of any disclosed embodiment.

[0020] In the present disclosure, references to various features (e.g., elements, structures, modules, components, steps, operations, characteristics, etc.) included in “one embodiment,” “example embodiment,” “embodiment,” “another embodiment,” “some embodiments,” “various embodiments,” “other embodiments,” “alternative embodiments,” etc.) are intended to mean that any of these features are included in one or more embodiments of the present disclosure, but may not necessarily be combined in the same embodiment.

[0021] In this disclosure, the terms "include" and "comprising" are open ended. As used in the appended claims, these terms specify the presence of the elements described and do not exclude the presence or addition of one or more other elements. The terms in the claims do not exclude the device from including additional components (e.g., interface units, circuits, etc.).

[0022] In the present disclosure, various units, circuits or other components may be described or stated as being "configured to" perform tasks. In such a context, "configured to" is used to imply a structure by indicating that a block / unit / circuit / component includes a structure (e.g., a circuit) that performs one or more tasks during operation. Therefore, even when the specified block / unit / circuit / component is currently inoperable (e.g., not turned on or enabled), it can be said that the block / unit / circuit / component is configured to perform a task. The blocks / units / circuit / components used with the "configured to" language include hardware (e.g., circuits), memories storing executable program instructions to implement operations, etc. In addition, "configured to" may include a general structure (e.g., a general circuit) that is manipulated by software and / or firmware (e.g., an FPGA or a general processor that executes software) to operate in a manner that can perform the relevant tasks. "Configured to" may also include adjusting a manufacturing process (e.g., a semiconductor manufacturing facility) to manufacture a device (e.g., an integrated circuit) that implements or performs one or more tasks.

[0023] As used in this disclosure, the term "circuit" or "logic" refers to all of the following: (a) hardware circuit implementations only (e.g., implementations in analog and / or digital circuits only); and (b) combinations of circuits and software (and / or firmware), such as (applicable to): (i) a combination of processors or (ii) portions of processors / software (including digital signal processors), memory and software that work together to enable a device such as a mobile phone or server to perform various functions; and (c) circuits such as microprocessors or portions of microprocessors that require software or firmware to operate, even if the software or firmware is not actually present. This definition of "circuit" or "logic" applies to all uses of the term in this application (including in any claims). As a further example, as used in this application, the term "circuit" or "logic" also covers implementations of only a processor (or multiple processors) or a portion of a processor and its (or their) accompanying software and / or firmware. The term "circuit" or "logic" also covers (e.g., and if applicable to a particular claim element) an integrated circuit for a storage device.

[0024] As used herein, the terms "first," "second," "third," and the like are used as labels for nouns preceding the terms and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.). The terms "first" and "second" do not necessarily imply that a first value must be written before a second value. In addition, although these terms may be used herein to identify various elements, these elements are not limited by these terms. These terms are used to distinguish one element from another element that would otherwise have the same or similar names. For example, a first circuit may be distinguished from a second circuit.

[0025] In addition, the term "based on" is used to describe one or more factors that affect the determination. The term does not exclude additional factors that may affect the determination. That is, the determination may be based only on those factors or at least in part on those factors. For example, the phrase "A is determined based on B." Although in this case, B is a factor that affects the determination of A, such a phrase does not exclude that the determination of A is also based on C. In other cases, A may be determined based only on B.

[0026] Herein, a data item or data entry may be a sequence of bits. For example, a data item may include the contents of a file, a portion of a file, a page in a memory, an object in an object-oriented program, a digital message, a digital scanned image, a portion of a video or audio signal, metadata, or any other entity that may be represented by a sequence of bits. According to an embodiment, a data item may include a discrete object. According to another embodiment, a data item may include an information unit within a transmission packet between two different components.

[0027] Figure 1 An example of a memory device according to an embodiment of the present invention is shown.

[0028] Figure 2A and Figure 2B In the embodiment according to the present invention, Figure 1 An example of operation of changing the timing of performing a channel precharge operation according to the operating temperature in a memory device is shown.

[0029] Reference Figure 1 , a memory device 150 according to an embodiment of the present disclosure may include a memory cell array 201 and a control circuit 202 .

[0030] The memory cell array 201 may include a plurality of memory blocks (not shown). Each memory block may include a plurality of memory cells (not shown). One memory block may include a plurality of pages.

[0031] A storage block may be understood as a group of nonvolatile memory cells from which data is removed together by an erase operation. Each storage block may include a page (not shown), in which nonvolatile memory cells are grouped from a logical perspective, such as storing data together during a programming operation or outputting data together during a read operation. For example, a storage block may include multiple pages. A page may include multiple nonvolatile memory cells.

[0032] Different from a logical perspective such as a program operation or a read operation, from a physical perspective, one memory block may include a plurality of word lines (WL<1:n>). One word line may include a plurality of nonvolatile memory cells.

[0033] In this case, according to the number of bits that can be stored or expressed in a nonvolatile memory cell, one word line may correspond to at least one page. For example, when a nonvolatile memory cell is a single-level cell (SLC) storing one data bit, one word line may correspond to one page. When a nonvolatile memory cell is a dual-level cell (DLC) storing two data bits, one word line may correspond to two pages. When a nonvolatile memory cell is a triple-level cell (TLC) storing three data bits, one word line may correspond to three pages. When a nonvolatile memory cell is a quad-level cell (QLC) storing four data bits, one word line may correspond to four pages. In this way, when a nonvolatile memory cell is a multi-level cell storing five or more data bits, one word line may correspond to five or more pages.

[0034] More specifically, each memory block may include a 3D structure. For example, each memory block may include a plurality of memory cells stacked on a substrate. Thus, each memory block may be arranged in the +X direction, the +Y direction, and the +Z direction.

[0035] That is, each memory block may include a plurality of memory cells connected between a plurality of word lines WL<1:n> arranged in the Z direction, a plurality of bit lines BL<1:m> arranged in the X direction, and a plurality of memory cell strings CS<1:2><1:m> arranged in the Y direction.

[0036] Herein, each of the plurality of memory cell strings CS<1:2><1:m> may include at least one source select transistor SST and first to nth memory cells MC<1:n> and at least one drain select transistor DST.

[0037] Herein, each of the selection transistors SST and DST and the memory cells MC<1:n> may have a similar structure. According to an embodiment of the present invention, each of the selection transistors SST and DST and the memory cells MC<1:n> may include a channel layer, a tunneling dielectric layer, a charge storage layer, and a blocking dielectric layer. According to another embodiment of the present invention, a column for providing a channel layer may be provided in each cell string. According to another embodiment of the present invention, a column for providing at least one of a channel layer, a tunneling dielectric layer, a charge storage layer, and a blocking dielectric layer may be provided to each cell string.

[0038] The source selection transistor SST included in each of the memory cell strings CS<1:2><1:m> may be coupled between the common source line CSL and the first memory cell MC. <1> between.

[0039] According to an embodiment of the present invention, source selection transistors of cell strings arranged in the same row may be connected to a source selection line extending in the row direction, and source selection transistors of cell strings arranged in different rows may be connected to different source selection lines. In the figure, source selection transistors of cell strings CS1<1:m> in the first row may be connected to a first source selection line SSL1. Source selection transistors of cell strings CS2<1:m> in the second row may be connected to a second source selection line SSL2.

[0040] According to another embodiment of the present invention, unlike what is shown in the drawing, source selection transistors of the cell strings CS1<1:m> and CS2<1:m> may be commonly coupled to one source selection line.

[0041] First to nth memory cells MC<1:n> included in each of the memory cell strings CS<1:2><1:m> may be coupled between a source select transistor SST and a drain select transistor DST.

[0042] The drain selection transistor DST included in each of the memory cell strings CS<1:2><1:m> may be coupled between the corresponding bit line and the nth memory cell MC. <n>The cell strings arranged in the row direction may be coupled to drain selection lines extending in the row direction. The drain selection transistors of the cell strings CS1<1:m> of the first row may be coupled to the first drain selection line DSL1. The drain selection transistors of the cell strings CS2<1:m> of the second row may be coupled to the second drain selection line DSL2.

[0043] Cell strings arranged in a column direction may be coupled to bit lines extending in the column direction. In the drawing, cell strings CS11 and CS21 of a first column may be coupled to a first bit line BL1. Cell strings CS1m and CS2m of an mth column may be coupled to an mth bit line BLm.

[0044] The memory cells connected to the word lines in the cell strings arranged in the row direction may form one physical page. For example, the memory cells connected to the first word line WL1 among the cell strings CS1<1:m> of the first row may form one physical page. As another example, the memory cells connected to the first word line WL1 among the cell strings CS2<1:m> of the second row may form another physical page. The cell strings arranged in the row direction may be selected by selecting one of the drain selection lines DSL1 and DSL2. One physical page among the selected memory cell strings may be selected by selecting one of the word lines WL<1:n>.

[0045] According to an embodiment of the present invention, at least one of the first to nth memory cells MC<1:n> may be used as a dummy memory cell. For example, at least one or more dummy memory cells may be provided to reduce the electric field between the source select transistor SST and the memory cell MC<1:n>. At least one or more dummy memory cells may be provided to reduce the electric field between the drain select transistor DST and the memory cell MC<1:n>. As more dummy memory cells are provided, the size of the memory block may increase while the operational reliability of the memory block improves. As fewer memory cells are provided, the operational reliability of the memory block may deteriorate while the size of the memory block decreases.

[0046] In order to effectively control at least one or more dummy memory cells, each dummy memory cell may have a desired threshold voltage. A programming operation may be performed on all or some of the dummy memory cells before or after an erase operation on a storage block. When an erase operation is performed after a programming operation, each dummy memory cell may have a desired threshold voltage by controlling a voltage applied to a dummy word line coupled to the dummy memory cell.

[0047] The control circuit 202 may control a programming operation for programming data in a selected area of ​​the memory cell array 201. The control circuit 202 may perform a programming operation on a selected memory cell (hereinafter referred to as a "programming cell") connected to a word line selected as a programming target among a plurality of word lines WL<1:n> (hereinafter referred to as a "programming word line"), a plurality of bit lines BL<1:m>, and a selected string among a plurality of memory cell strings CS<1:2><1:m> (hereinafter referred to as a "programming string"). Herein, through the programming operation, the programming cell may have one programming state among a plurality of programming states.

[0048] According to an embodiment of the present invention, a single-level cell SLC storing one data bit may have two programming states distinguished based on one threshold voltage level. A multi-level cell MLC storing two data bits may have four programming states distinguished based on three threshold voltage levels. A three-level cell TLC storing three data bits may have eight programming states distinguished based on seven threshold voltage levels. A quad-level cell QLC storing four data bits may have 16 programming states distinguished based on 15 threshold voltage levels.

[0049] Reference Figure 2A and Figure 2B as well as Figure 1 The programming operation may include a plurality of programming loops PL1 to PL7. By repeatedly running the plurality of programming loops PL1 to PL7 one after another in a predetermined order until the programming operation is completed, the control circuit 202 may program the programming unit to have one programming state among a plurality of programming states (see Figure 1 Herein, if the program operation is not successful within a predetermined number of program loops, the control circuit 202 may determine that the program operation has failed.

[0050] According to an embodiment of the present invention, Figure 2A and Figure 2B In the example, the program operation is successfully performed at the time when the seventh program loop PL7 among the program loops PL1 to PL7 is completed. Figure 2A and Figure 2B In the embodiment, at the time when the seventh program loop PL7 among the program loops PL1 to PL7 is completed, the program cells have the target program states.

[0051] Herein, each of the programming loops PL1 to PL7 may include: a programming pulse applying operation VIO for changing a threshold voltage level of a programming cell by applying a programming pulse PGM<1:7> to a programming word line; and a verification operation VER for verifying which programming state the programming cell is in by applying a verification voltage VRY<1:7> corresponding to a target level to the programming word line.

[0052] In addition, whenever each of the programming loops PL1 to PL7 is performed, the potential level of the programming pulse may increase. As each of the programming loops PL1 to PL7 is repeatedly performed, the programming operation may increase the level of the programming voltage according to an incremental step pulse programming (ISPP) method. In this case, the number of times the programming voltage used in each of the programming loops PL1 to PL7 is applied, the level of the programming voltage, and the length of time for applying the programming voltage may be determined in various ways.

[0053] Then, the control circuit 202 may additionally perform a channel precharge operation PCG together with a program pulse applying operation VIO and a verification operation VER from among the program loops PL1 to PL7 selected according to the operating temperature of the memory device 150 (see Figure 1 Operation 20).

[0054] According to an embodiment of the present invention, the control circuit 202 may control the order of the program loop selected when the operating temperature of the memory device 150 is equal to or higher than the reference temperature to be ahead of the order of the program loop selected when the operating temperature of the memory device 150 is lower than the reference temperature.

[0055] According to an embodiment of the present invention, in the case where the operating temperature of the memory device 150 is equal to or higher than the reference temperature Figure 2A In the embodiment, the control circuit 202 may perform a channel precharge operation starting from the third program loop PL3 among the program loops PL1 to PL7. Figure 2A In the process, the control circuit 202 may perform only the programming pulse applying operation VIO and the verification operation VER in each of the first programming loop PL1 and the second programming loop PL2 among the programming loops PL1 to PL7, and perform the channel precharge operation PCG together with the programming pulse applying operation VIO and the verification operation VER in each of the third programming loop PL3 to the seventh programming loop PL7 in which the programming operation is successful.

[0056] According to another embodiment of the present invention, in the case where the operating temperature of the memory device 150 is lower than the reference temperature Figure 2B In the embodiment, the control circuit 202 may perform a channel precharge operation starting from the fifth program loop PL5 among the program loops PL1 to PL7. Figure 2B In the process, the control circuit 202 may perform only the programming pulse applying operation VIO and the verification operation VER in each of the first programming loop PL1 to the fourth programming loop PL4 among the programming loops PL1 to PL7, and perform the channel precharge operation PCG together with the programming pulse applying operation VIO and the verification operation VER in each of the fifth programming loop PL5 to the seventh programming loop PL7 in which the programming operation is successfully performed.

[0057] As mentioned above, similar to reference Figure 2A and Figure 2B The difference between the described embodiments is that as the operating temperature of the memory device 150 is relatively higher, the control circuit 202 may perform the channel precharge operation starting from a relatively fast program loop among the program loops PL1 to PL7 .

[0058] Figure 3 is shown in an embodiment according to the present invention Figure 1 A waveform diagram showing an example of an operation of changing the level of a voltage applied to a common source line in a channel precharge operation according to an operating temperature in a memory device is shown.

[0059] Reference Figure 3 as well as Figure 1 , the control circuit 202 may precharge the channels of the plurality of memory cell strings by applying a precharge voltage Vpre to the common source line CSL in a channel precharge operation. Herein, the control circuit 202 may change the level of the precharge voltage Vpre according to the operating temperature of the memory device 150.

[0060] According to an embodiment of the present invention, the control circuit 202 can control the level of the precharge voltage Vpre determined when the operating temperature of the memory device 150 is equal to or higher than the reference temperature to be relatively higher than the level of the precharge voltage Vpre determined when the operating temperature of the memory device 150 is lower than the reference temperature.

[0061] Figure 4 is shown in an embodiment according to the present invention Figure 1 A waveform diagram showing an example of an operation of changing a level of a voltage applied to a dummy word line adjacent to a common source line in a channel precharge operation according to an operating temperature in a memory device is shown.

[0062] Reference Figure 4 as well as Figure 1 , the control circuit 202 may apply the first turn-on voltage Vwtn to a predetermined number of dummy word lines DUMMY adjacent to the common source line CSL among the plurality of word lines WL<1:n> in the channel precharge operation. Herein, the predetermined number of dummy word lines DUMMY adjacent to the common source line CSL may be turned on in response to the first turn-on voltage Vwtn. The control circuit 202 may change the level of the first turn-on voltage Vwtn according to the operating temperature of the memory device 150.

[0063] According to an embodiment of the present invention, the control circuit 202 can control the level of the first on-voltage Vwtn determined when the operating temperature of the memory device 150 is equal to or higher than the reference temperature to be relatively higher than the first on-voltage Vwtn determined when the operating temperature of the memory device 150 is lower than the reference temperature.

[0064] In this article, Figure 4 An example is shown in which a predetermined number of dummy word lines adjacent to the common source line CSL among the word lines WL<1:n> include the first to third word lines WL<1:3>. This is only an embodiment, and in practice, less than or more than three word lines among the word lines WL<1:n> may also be set as dummy word lines.

[0065] Figure 5 is shown in an embodiment according to the present invention Figure 1 Waveform diagrams showing an example of an operation of changing a level of a voltage applied to a source selection line coupled between a common source line and a plurality of word lines in a channel precharge operation according to an operating temperature in a memory device are shown.

[0066] Reference Figure 5 as well as Figure 1 , the control circuit 202 may apply the second turn-on voltage Vst1 to the source selection line SSL coupled between the plurality of word lines WL<1:n> and the common source line CSL in the channel precharge operation. In this case, the source selection line SSL may be turned on in response to the second turn-on voltage Vst1. The control circuit 202 may change the level of the second turn-on voltage Vst1 according to the operating temperature of the memory device 150.

[0067] According to an embodiment of the present invention, the control circuit 202 can control the level of the second turn-on voltage Vstl determined when the operating temperature of the memory device 150 is equal to or higher than the reference temperature to be relatively higher than the level of the second turn-on voltage Vstl determined when the operating temperature of the memory device 150 is lower than the reference temperature.

[0068] In this article, Figure 5 It is shown that one source select line SSL is coupled between a plurality of word lines WL<1:n> and a common source line CSL. This is just one embodiment, and actually, more source select lines SSL may be included.

[0069] The control circuit 202 included in the memory device 150 according to the embodiment of the present invention may simultaneously perform operations of changing the order of performing the channel precharge operations PCG according to the operating temperature of the memory device 150 (see Figure 2A and Figure 2B ), an operation of changing the level of the precharge voltage Vpre according to the operating temperature of the memory device 150 in the channel precharge operation PCG (see Figure 3 ), an operation of changing the level of the first turn-on voltage Vwtn according to the operating temperature of the memory device 150 in the channel precharge operation PCG (see Figure 4 ) and an operation of changing the level of the second turn-on voltage Vst1 according to the operating temperature of the memory device 150 in the channel precharge operation PCG (see Figure 5 According to an embodiment of the present invention, an operation of changing the order of performing the channel precharge operation PCG according to the operating temperature of the memory device 150 and an operation of changing the level of the first turn-on voltage Vwtn in the channel precharge operation PCG may be performed.

[0070] Figure 6 is a diagram showing an embodiment according to the present invention Figure 1 A block diagram of an example of a control circuit among constituent elements of a memory device shown.

[0071] Reference Figure 6 , the memory device 150 may include a memory cell array 201 and a control circuit 202. The control circuit 202 may include a control operation circuit 309 and a control logic 304. The control operation circuit 309 may include a page buffer circuit 302, a checker 303, a data input / output circuit 305, a voltage supply circuit 306, and an address decoder 307. The control logic 304 may include a temperature measurer 311, a sequence controller 312, a first voltage level controller 313, a second voltage level controller 314, and a third voltage level controller 315.

[0072] The memory cell array 201 may include a plurality of memory blocks MEMORY BLOCK<1:6>. The plurality of memory blocks MEMORY BLOCK<1:6> may be connected to the address decoder 307 through row lines DSL<1:2>, WL<1:n>, SSL<1:2>, CSL. The plurality of memory blocks MEMORY BLOCK<1:6> may be connected to the page buffer circuit 302 through bit lines BL1 to BLm. Each memory block MEMORY BLOCK<1:6> may include a plurality of memory cells.

[0073] Each of the plurality of memory blocks MEMORY BLOCK<1:6> may include a 3D structure. That is, each of the plurality of memory blocks MEMORY BLOCK<1:6> may include a plurality of memory cells arranged in +X, +Y, and +Z directions as a 3D structure, which has been referred to in Figure 1 Described.

[0074] The row lines DSL<1:2>, WL<1:n>, SSL<1:2>, CSL may include at least one source select line SSL<1:2>, a plurality of word lines WL<1:n>, at least one drain select line DSL<1:2>, and a common source line CSL.

[0075] The control operation circuit 309 may perform a program operation, a read operation, or an erase operation on a selected region of the memory cell array 201. The control operation circuit 309 may drive the memory cell array 201. For example, the control operation circuit 309 may apply various operation voltages to the row lines DSL<1:2>, WL<1:n>, SSL<1:2>, CSL, and the bit lines BL1 to BLm, or discharge the applied voltages.

[0076] The control operation circuit 309 may perform a program operation on the program unit in response to the control of the control logic 304. Specifically, the control operation circuit 309 may perform a channel precharge operation PCG together with a program pulse applying operation VIO and a verification operation VER starting from a program loop selected according to the operating temperature of the memory device 150 among program loops PL1 to PL7 included in the program operation in response to the control of the control logic 304.

[0077] The address decoder 307 among the control operation circuit 309 may be connected to the memory cell array 201 through the row lines DSL<1:2>, WL<1:n>, SSL<1:2>, and CSL.

[0078] The address decoder 307 may operate in response to the control of the control logic 304. The address decoder 307 may receive the address RADD from the control logic 304.

[0079] The address decoder 307 may decode the block address in the received address RADD. The address decoder 307 may select at least one storage block among the storage blocks MEMORY BLOCK<1:6> according to the decoded block address. The address decoder 307 may decode the row address in the received address RADD. The address decoder 307 may select at least one word line among the word lines of the selected storage block according to the decoded row address. The address decoder 307 may apply the operating voltage Vop supplied from the voltage supply circuit 306 to the selected word line. Herein, the operating voltage VOP may include a precharge voltage Vpre, a first turn-on voltage Vwtn, and a second turn-on voltage Vstl.

[0080] The voltage supply circuit 306 among the control operation circuit 309 can generate a plurality of operation voltages Vop by using an external power supply voltage. The voltage supply circuit 306 can operate in response to the control of the control logic 304. In an embodiment, the voltage supply circuit 306 can adjust the external power supply voltage and generate an internal power supply voltage. In an embodiment, the voltage supply circuit 306 can generate a plurality of operation voltages Vop by using an external power supply voltage or an internal power supply voltage. The voltage supply circuit 306 may include a plurality of pump capacitors receiving the internal power supply voltage to generate a plurality of operation voltages Vop having various voltage levels, and generate a plurality of operation voltages Vop by selectively enabling a plurality of pump capacitors in response to the control of the control logic 304. The generated operation voltage Vop can be supplied to the memory cell array 201 through the address decoder 307. For example, the voltage supply circuit 306 can adjust the level and supply time of each operation voltage Vop in response to the operation signal OP_SIG.

[0081] For example, the voltage supply circuit 306 may generate the programming voltages PGM<1:7> (see Figure 2A and Figure 2B ), pass voltage, verification voltage VRY<1:7> (see Figure 2A and Figure 2B ), read voltage, erase voltage, precharge voltage Vpre, first turn-on voltage Vwtn, second turn-on voltage Vstl, etc. as operation voltage VOP, and supply the generated operation voltage VOP to address decoder 307. For example, during the programming operation, voltage supply circuit 306 may generate programming voltage, pass voltage, verification voltage, precharge voltage Vpre, first turn-on voltage Vwtn and second turn-on voltage Vstl as generated operation voltage VOP in response to operation signal OP_SIG, and supply the generated operation voltage VOP to address decoder 307. Herein, the programming voltage may be a voltage supplied to the programming word line, and the pass voltage may be a voltage supplied to the word line not selected as the programming target. The precharge voltage Vpre may be a voltage applied to the common source line CSL in the channel precharge operation PCG, and the first turn-on voltage Vwtn may be a voltage applied to a predetermined number of dummy word lines adjacent to the common source line CSL among the word lines WL<1:n> in the channel precharge operation PCG. The second turn-on voltage Vstl may be a voltage applied to the source selection line SSL<1:2> in the channel precharge operation PCG. The voltage supply circuit 306 may adjust the supply time of each operation voltage VOP according to the operation signal OP_SIG. For example, the voltage supply circuit 306 may adjust the output time of the operation voltage VOP (programming voltage, pass voltage, verification voltage, precharge voltage Vpre, first turn-on voltage Vwtn, and second turn-on voltage Vstl) according to the operation signal OP_SIG, and output the voltage according to the adjusted time.

[0082] The page buffer circuit 302 may include a plurality of page buffers PB1 to PBm. The plurality of page buffers PB1 to PBm may be connected to the memory cell array 201 through a plurality of bit lines BL1 to BLm, respectively. The plurality of page buffers PB1 to PBm may operate in response to the control of the control logic 304 .

[0083] The plurality of page buffers PB1 to PBm may communicate data DATA with the data input / output circuit 157. During a program operation, the plurality of page buffers PB1 to PBm may receive data DATA to be stored through the data input / output circuit 157 and the data lines DL.

[0084] After the program operation starts, the plurality of page buffers PB1 to PBm may store data DATA received from the outside through the data input / output circuit 305, and may transmit a program enable voltage or a program disable voltage to the bit lines BL1 to BLm in response to the stored data DATA. For example, the program enable voltage may be 0V, and the program disable voltage may be a power supply voltage.

[0085] After the read operation starts, the plurality of page buffers PB1 to PBm may sense data DATA based on voltages or currents of bit lines BL1 to BLm determined according to threshold voltages of memory cells of a selected page and may transmit the sensed data DATA to the data input / output circuit 305 through data lines DL.

[0086] After the erase operation starts, the plurality of page buffers PB1 to PBm may float the bit lines BL1 to BLm or may apply a voltage of 0V to the bit lines BL1 to BLm.

[0087] The data input / output circuit 305 may include a plurality of input / output buffers (not shown) receiving input data DATA. During a program operation, the data input / output circuit 305 may receive data DATA to be stored from the outside. The data input / output circuit 305 may output data DATA transmitted from a plurality of page buffers PB1 to PBm included in the page buffer circuit 302 to the outside during a read operation.

[0088] The checker 303 of the control operation circuit 309 may generate a reference current in response to a verification reference signal VRYBIT generated by the control logic 304 after a read operation or a verification operation starts, may compare the sensing voltage VPB received from the page buffer group 123 and a reference voltage generated from the reference current, and may output a pass signal PASS or a fail signal FAIL to the control logic 304. For example, when the level of the sensing voltage VPB is higher than or equal to the level of the reference voltage, the checker 303 may output a pass signal PASS to the control logic 304. When the level of the sensing voltage VPB is lower than the level of the reference voltage, the checker 303 may output a fail signal FAIL to the control logic 304.

[0089] The control logic 304 may be connected to the address decoder 307, the voltage supply circuit 306, the page buffer circuit 302, the data input / output circuit 305, and the checker 303 included in the control operation circuit 309. The control logic 304 may control the operation of the memory device 150. The control logic 304 may operate in response to a command CMD from an external device.

[0090] The control logic 304 may control the control operation circuit 309 by generating various signals in response to the command CMD and the address ADDR. For example, the control logic 304 may generate an operation signal OPSIG, an address RADD, a read / write control signal PBSIGNALS, and a verification reference signal VRYBIT in response to the command CMD and the address ADDR. The control logic 304 may output the operation signal OPSIG to the voltage supply circuit 306, may output the address RADD to the address decoder 307, may output the read / write control signal PBSIGNALS to the page buffer circuit 302, and may output the verification reference signal VRYBIT to the checker 303. In addition, the control logic 304 may determine whether the verification operation passes or fails in response to the pass signal PASS or the fail signal FAIL output by the checker 303.

[0091] More specifically, the temperature measurer 311 included in the control logic 304 may measure the operating temperature of the memory device 150. According to an embodiment of the present invention, the temperature measurer 311 may include a thermosensor capable of measuring the operating temperature of the memory device 150.

[0092] The sequence controller 312 included in the control logic 304 may control the operation of the control operation circuit 309 to perform program loops PL1 to PL7 (see Figure 2A and Figure 2B ) in the order corresponding to the operating temperature of the memory device 150 measured by the temperature measurer 311, and performing the channel precharge operation PCG from the selected program loop (see Figure 2A and Figure 2B ).

[0093] According to an embodiment of the present invention, the sequence controller 312 may control the operation of the control operation circuit 309 so that the order of the programming loop selected when the operating temperature of the memory device 150 measured by the temperature measurer 311 is equal to or higher than the reference temperature is placed before the order of the programming loop selected when the operating temperature of the memory device 150 is lower than the reference temperature.

[0094] According to an embodiment of the present invention, referring to Figure 2A as well as Figure 6 , when the operating temperature of the memory device 150 measured by the temperature measurer 311 is equal to or higher than the reference temperature, the sequence controller 312 may control the operation of the control operation circuit 309 to perform the channel precharge operation from the third programming loop PL3 among the programming loops PL1 to PL7. When the operating temperature of the memory device 150 measured by the temperature measurer 311 is equal to or higher than the reference temperature, the sequence controller 312 may control the operation of the control operation circuit 309 to perform only the program pulse applying operation VIO and the verification operation VER in each of the first programming loop PL1 and the second programming loop PL2 among the programming loops PL1 to PL7, and perform the channel precharge operation PCG together with the program pulse applying operation VIO and the verification operation VER in each of the third programming loop PL3 to the seventh programming loop PL7 where the programming operation is successful.

[0095] According to another embodiment of the present invention, referring to Figure 2B as well as Figure 6 , when the operating temperature of the memory device 150 measured by the temperature measurer 311 is lower than the reference temperature, the sequence controller 312 may control the operation of the control operation circuit 309 to perform the channel precharge operation from the fifth program loop PL5 among the program loops PL1 to PL7. When the operating temperature of the memory device 150 measured by the temperature measurer 311 is lower than the reference temperature, the sequence controller 312 may control the operation of the control operation circuit 309 to perform only the program pulse applying operation VIO and the verification operation VER in each of the first program loop PL1 to the fourth program loop PL4 among the program loops PL1 to PL7, and perform the channel precharge operation PCG together with the program pulse applying operation VIO and the verification operation VER in each of the fifth program loop PL5 to the seventh program loop PL7 in which the program operation is successful.

[0096] The first voltage level controller 313 included in the control logic 304 may control the level of the precharge voltage Vpre according to the operating temperature of the memory device 150 measured by the temperature measurer 311 .

[0097] According to an embodiment of the present invention, the first voltage level controller 313 can control the operation of the control operation circuit 309 so that the level of the pre-charge voltage Vpre determined when the operating temperature of the memory device 150 measured by the temperature measurer 311 is equal to or higher than the reference temperature is relatively higher than the level of the pre-charge voltage Vpre determined when the operating temperature of the memory device 150 is lower than the reference temperature.

[0098] Then, the second voltage level controller 314 included in the control logic 304 may determine the level of the first turn-on voltage Vwtn according to the operating temperature of the memory device 150 measured by the temperature measurer 311 .

[0099] According to an embodiment of the present invention, the second voltage level controller 314 can control the operation of the control operation circuit 309 so that the level of the first on-voltage Vwtn determined when the operating temperature of the memory device 150 measured by the temperature measurer 311 is equal to or higher than the reference temperature is relatively higher than the level of the first on-voltage Vwtn determined when the operating temperature of the memory device 150 is lower than the reference temperature.

[0100] The third voltage level controller 315 included in the control logic 304 may determine the level of the second turn-on voltage Vst1 according to the operating temperature of the memory device 150 measured by the temperature measurer 311.

[0101] According to an embodiment of the present invention, the third voltage level controller 315 can control the operation of the control operation circuit 309 so that the level of the second turn-on voltage Vstl determined when the operating temperature of the memory device 150 measured by the temperature measurer 311 is equal to or higher than the reference temperature is relatively higher than the level of the second turn-on voltage Vstl determined when the operating temperature of the memory device 150 is lower than the reference temperature.

[0102] Figure 7 It is described in accordance with an embodiment of the present invention Figure 1 A flow chart showing how the operation sequence of performing a channel precharge operation in a memory device is changed according to the operation temperature.

[0103] Reference Figure 7 , a program command may be input to the memory device 150 in operation S10.

[0104] In response to the input of the program command in operation S10 , a program pulse applying operation VIO included in a first program loop PL1 among a plurality of program loops PL1 to PL7 included in the program operation may be performed in operation S20 .

[0105] After operation S20 , a verification operation VER included in the first program loop PL1 may be performed in operation S30 .

[0106] After operation S30, it may be checked in operation S40 whether the programming operation is successfully performed. When the programming operation is successfully performed in operation S40 (operation S40 is yes), the programming operation may be determined to be successful and then terminated. When the programming operation is unsuccessful in operation S40 (operation S40 is no), the current programming loop count may be increased in operation S80. Herein, when the programming operation is unsuccessful in the first programming loop PL1, the current programming loop count value may be increased from the first programming loop PL1 to the second programming loop PL2 through the operation of operation S80.

[0107] After operation S80, whether the current program loop count value is the maximum program loop count value may be checked in operation S90. When the current program loop count value is found to be the maximum program loop count value in operation S90 (operation S90: Yes), the program operation may be determined to fail and then terminated.

[0108] In response to the input of the program command in operation S10 , a temperature measuring operation for measuring the operating temperature of the memory device 150 may be performed in operation S50 .

[0109] By comparing the operating temperature of the memory device 150 measured in operation S50 with a reference temperature in operation S60 , one program loop may be selected among a plurality of program loops PL1 to PL7 included in the program operation.

[0110] like Figure 2A As shown, when the operating temperature of the memory device 150 is equal to or higher than the reference temperature, the third program loop PL3 may be selected among the program loops PL1 to PL7. Figure 2B As shown, when the operating temperature of the memory device 150 is lower than the reference temperature, the fifth program loop PL5 may be selected among the program loops PL1 to PL7.

[0111] Herein, the operations of operations S20 and S30 included in the first programming loop PL1 may be performed in parallel with the operations of operations S50 and S60. Therefore, the operation of operation S60 may be completed at the moment when the operations of operations S40, S80, and S90 for checking the results of operations S20 and S30 included in the first programming loop PL1 are performed. At the moment when it is confirmed in operation S90 that the current programming loop count value is not the maximum programming loop count value (operation S90 is no), the operation of operation S60 may be in a completed state. Therefore, it may be checked in operation S70 whether the current programming loop count value after operation S90 is equal to or greater than the programming loop count value selected in operation S60.

[0112] When the current program loop count value in operation S70 is less than the program loop count value selected in operation S60 (No in operation S70), operations of operations S20, S30, S40, S80, and S90 may be sequentially performed again.

[0113] In operation S70 , when the current program loop count value is equal to or greater than the program loop count value selected in operation S60 (operation S70 : Yes), the channel precharge operation may be performed in operation S100 .

[0114] Since the current programming loop count value does not decrease until the programming operation ends, once the operation of operation S100 is performed, the operation of operation S100 can be repeatedly performed together with the operations of operations S20, S30, S40, S80 and S90 starting from a subsequent programming loop performed subsequently until the programming operation ends.

[0115] like Figure 2A As shown, when the programming loop selected in operation S60 is the third programming loop PL3, the operations of operations S20, S30, S40, S80, S90 and S70 may be sequentially performed in each of the first programming loop PL1 and the second programming loop PL2, and the operations of operations S100, S20, S30, S40, S80, S90 and S70 may be sequentially performed in each of the third programming loop PL3 to the seventh programming loop PL7.

[0116] like Figure 2B As shown, when the programming loop selected in operation S60 is the fifth programming loop PL5, the operations of operations S20, S30, S40, S80, S90 and S70 may be sequentially performed in each of the first to fourth programming loops PL1 to PL4, and the operations of operations S100, S20, S30, S40, S80, S90 and S70 may be sequentially performed in each of the fifth to seventh programming loops PL5 to PL7.

[0117] Herein, although not specifically shown in the drawings, when a channel precharge operation is performed through the operation of operation S100, when an operation of controlling the level of the precharge voltage Vpre is performed, when an operation of controlling the level of the first turn-on voltage Vwtn is performed, and when an operation of controlling the level of the second turn-on voltage Vstl is performed, reference may be made to the operating temperature of the memory device 150 measured in operation S50.

[0118] Fig. 8A and Figure 8B A phenomenon that occurs when a channel precharge operation is performed in a memory device is shown.

[0119] Reference Fig. 8A , a programming operation may be performed from a word line WLn adjacent to a drain selection line DSL to a word line WL1 adjacent to a source selection line SSL. For example, when a programming operation is performed on an (n-4)th word line WLn-4, after a verification operation included in one of a plurality of programming loops PL1 to PL7 is completed, a channel potential coupled to the memory cell string may be in a negative state.

[0120] The channel precharge operation may be performed by applying a precharge voltage Vpre to the common source line CSL in a state where the channel potential is negative.

[0121] In the channel precharge operation, the channel potential of the first word line WL1 to the (n-4)th word line WLn-4 may be increased due to the precharge voltage Vpre. For example, the channel potential of the first word line WL1 to the (n-4)th word line WLn-4 may be raised from a negative state to a positive state. However, the channel potential of the (n-3)th word line WLn-3 to the nth word line WLn may still be in a negative state without being affected by the precharge voltage Vpre. Therefore, a channel potential difference (Δ channel potential) may occur between the channel potential of the first word line WL1 to the (n-4)th word line WLn-4 and the channel potential of the (n-3)th word line WLn-3 to the nth word line WLn. In this case, due to the channel potential difference (Δ channel potential), the charge present in the channel segment of the memory cell connected to the (n-4)th word line WLn-4 (programming word line) may have high energy. Subsequently, charges with high energy may be injected into the gate of the memory cell connected to the (n-4)th word line WLn-4. This phenomenon may be referred to as hot carrier injection (HCI). As a result, the memory cell connected to the (n-4)th word line WLn-4 may experience a disturbance phenomenon in which the threshold voltage increases due to the hot carrier injection. In particular, among the memory cells connected to the (n-4)th word line WLn-4, the disturbance caused by HCI (hereinafter referred to as HCI degradation) may become more serious in the cell in the erased state.

[0122] When a program voltage is applied to the (n-4)th word line WLn-4 in a state where the channel potential is negative, Fowler Nordheim (FN) stress may be applied to a memory cell coupled to the (n-4)th word line WLn-4, and a threshold voltage of the memory cell coupled to the (n-4)th word line WLn-4 may increase due to a difference between the level of the program voltage and the channel potential of the (n-4)th word line WLn-4. That is, a disturbance phenomenon (hereinafter referred to as FN degradation) may occur due to the FN stress.

[0123] Reference Figure 8B , since the channel precharge operation is repeated by the ISPP algorithm, HCI degradation and FN degradation may have opposite characteristics. When the number of repetitions of the channel precharge operation is relatively small, the influence of FN degradation may be greater than the influence of HCI degradation. On the contrary, when the number of repetitions of the channel precharge operation is relatively large, the influence of HCI degradation may be greater than the influence of FN degradation.

[0124] On the other hand, in the case of HCI degradation, it can be seen that the degree of degradation of the memory cell corresponding to the repetition of the channel precharge operation in a state where the operating temperature of the memory device is lower than the reference temperature (dashed line) increases relatively more than the degree of degradation of the memory cell corresponding to the repetition of the channel precharge operation in a state where the operating temperature of the memory device is equal to or greater than the reference temperature (solid line).

[0125] It can be seen that the FN degradation is only affected by the number of repetitions of the channel precharge operation and has nothing to do with the operating temperature of the memory device.

[0126] Therefore, even when the operating temperature is lower than the reference temperature, the above reference Figures 1 to 7 The described memory device 150 according to the embodiment of the present invention may also operate according to the number of repetitions of the channel precharge operation to minimize the influence of HCI degradation.

[0127] According to an embodiment of the present invention, by operating a programming loop in which a channel precharge operation starts to be performed when the operating temperature is lower than a reference temperature relatively later than a programming loop in which a channel precharge operation starts to be performed when the operating temperature is equal to or higher than the reference temperature, the number of repetitions of the channel precharge operation included in the programming operation can be minimized. In this way, even when the operating temperature is lower than the reference temperature, the memory device 150 can operate according to the number of repetitions of the channel precharge operation to minimize the influence of HCI degradation.

[0128] According to an embodiment of the present invention, the level of a voltage applied to a common source line may be controlled according to the operating temperature of a memory device in a channel precharge operation.

[0129] According to an embodiment of the present invention, the level of a voltage applied to a dummy word line adjacent to a common source line may be controlled according to the operating temperature of a memory device in a channel precharge operation.

[0130] According to an embodiment of the present invention, a level of a voltage applied to a source selection line coupled between a common source line and a plurality of word lines may be controlled according to an operating temperature of a memory device in a channel precharge operation.

[0131] According to an embodiment of the present invention, the timing of performing a channel precharge operation may be adjusted according to the operating temperature of a memory device.

[0132] According to an embodiment of the present invention, a channel precharge operation may be effectively performed regardless of the operating temperature of a memory device.

[0133] Although the present invention has been described with respect to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the present invention as defined in the following claims. Furthermore, these embodiments may be combined to form additional embodiments.

[0134] For example, the positions and types of logic gates and transistors shown in the above-described embodiments of the present invention should be implemented differently depending on the polarity of an input signal.

[0135] CROSS-REFERENCE TO RELATED APPLICATIONS

[0136] This application claims priority to Korean Patent Application No. 10-2023-0075500, filed on Jun. 13, 2023, which is hereby incorporated by reference in its entirety.< / n>

Claims

1. A memory device, the memory device comprising: a memory cell array including a plurality of memory cell strings coupled between a plurality of bit lines and a common source line and a plurality of word lines coupled to the memory cell strings; as well as A control circuit, the control circuit: repeating a program loop including a program pulse applying operation and a verification operation until a program operation is successfully performed on memory cells coupled to the selected word line, the selected memory cell string, and the plurality of bit lines, In addition, a channel precharge operation is performed together with the program pulse applying operation and the verifying operation starting from the selected program loop, and A level of a precharge voltage applied to the common source line in the channel precharge operation is changed according to an operating temperature.

2. The memory device according to claim 1, wherein: The control circuit comprises: a temperature measurer that measures the operating temperature; and A first voltage level controller controls a level of the precharge voltage according to the operating temperature measured by the temperature measurer.

3. The memory device according to claim 2, wherein: The first voltage level controller controls a level of the precharge voltage determined in response to the operating temperature being equal to or higher than a reference temperature to be relatively higher than a level of the precharge voltage determined in response to the operating temperature being lower than the reference temperature.

4. The memory device according to claim 2, wherein: The control circuit changes a level of a first turn-on voltage applied to a predetermined number of dummy word lines adjacent to the common source line among the plurality of word lines according to the operating temperature measured by the temperature measurer in the channel precharge operation.

5. The memory device according to claim 4, wherein: The control circuit further comprises: a second voltage level controller that determines a level of the first turn-on voltage according to the operating temperature measured by the temperature measurer; 6. The memory device according to claim 5, wherein: The second voltage level controller controls a level of the first turn-on voltage determined in response to the operating temperature lower than a reference temperature to be relatively lower than a level of the first turn-on voltage determined in response to the operating temperature equal to or higher than the reference temperature.

7. The memory device according to claim 2, wherein: The control circuit changes a level of a second turn-on voltage applied to a source selection line coupled between the plurality of word lines and the common source line in the channel precharge operation according to the operating temperature measured by the temperature measurer.

8. The memory device according to claim 7, wherein: The control circuit further comprises: a third voltage level controller that determines a level of the second turn-on voltage according to the operating temperature measured by the temperature measurer.

9. The memory device according to claim 8, wherein: The third voltage level controller controls a level of the second turn-on voltage determined in response to the operating temperature lower than a reference temperature to be relatively lower than a level of the second turn-on voltage determined in response to the operating temperature equal to or higher than the reference temperature.

10. The memory device according to claim 2, wherein: The control circuit determines that an order in which the selected program loops to start performing the channel precharge operation is changed according to the operating temperature measured by the temperature measurer.

11. The memory device according to claim 10, wherein: The control circuit further comprises: A sequence controller determines a sequential program loop corresponding to the operating temperature measured by the temperature measurer as the selected program loop.

12. The memory device according to claim 11, wherein: The sequence controller controls the order of the selected program loop determined in response to the operating temperature being equal to or higher than a reference temperature to precede the order of the selected program loop determined in response to the operating temperature being lower than the reference temperature.

13. A method of operating a memory device, the memory device comprising a plurality of memory cell strings coupled between a plurality of bit lines and a common source line and a plurality of word lines coupled to the memory cell strings, the method comprising the steps of: repeatedly performing a program loop including a program pulse applying operation and a verification operation until a program operation for memory cells coupled to the selected word line, the selected memory cell string, and the plurality of bit lines is successfully performed; additionally performing a channel precharge operation together with the program pulse applying operation and the verifying operation starting from a selected program loop; as well as A level of a precharge voltage applied to the common source line in the channel precharge operation is changed according to an operating temperature.

14. The method according to claim 13, wherein: The step of changing the level of the pre-charge voltage comprises the following steps: The level of the precharge voltage determined in response to the operating temperature being equal to or higher than a reference temperature is changed to be relatively higher than the level of the precharge voltage determined in response to the operating temperature being lower than the reference temperature.

15. The method according to claim 13, further comprising the steps of: A first turn-on voltage whose level is changed according to the operating temperature is applied to a predetermined number of dummy word lines adjacent to the common source line among the plurality of word lines in the channel precharge operation.

16. The method according to claim 15, wherein: The step of applying the first conduction voltage comprises the following steps: A level of the first turn-on voltage determined in response to the operating temperature being equal to or higher than a reference temperature is changed to a level relatively higher than a level of the first turn-on voltage determined in response to the operating temperature being lower than the reference temperature.

17. The method according to claim 13, further comprising the steps of: A second turn-on voltage whose level varies according to the operating temperature is applied to a source selection line coupled between the plurality of word lines and the common source line in the channel precharge operation.

18. The method according to claim 17, wherein: The step of applying the second conduction voltage comprises the following steps: A level of the second turn-on voltage determined in response to the operating temperature being equal to or higher than a reference temperature is changed to a level relatively higher than a level of the second turn-on voltage determined in response to the operating temperature being lower than the reference temperature.

19. The method according to claim 13, further comprising the steps of: A sequential programming loop corresponding to the operating temperature is determined as the selected programming loop.

20. The method according to claim 19, wherein: The step of determining the programming cycle comprises the following steps: An order of the selected program loop determined in response to the operating temperature being equal to or higher than a reference temperature is determined to be relatively prior to an order of the selected program loop determined in response to the operating temperature being lower than the reference temperature.

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