Nano vacuum channel transistor and preparation method thereof

Abstract

The present invention provides a nano vacuum channel transistor and a method for preparing the same. In the nano vacuum channel transistor of the present invention, the emitter has a tip disposed opposite the collector, defining a nanometer gap between the emitter and the collector, enabling a nanoscale channel to be formed, thereby reducing the effect of vacuum on the field emission transistor. The gate electrode is disposed above, below, or on at least one of the emitter and collector electrodes, providing the device with the required gate control capability, thereby enabling high-speed switching of the device at a relatively low operating voltage. In the preparation method of the present invention, after forming the emitter using mature photolithography technology, a sacrificial sidewall structure is formed on the sidewall of the emitter. The sacrificial sidewall structure is used to define the nanometer gap between the emitter and the collector, ensuring nanoscale processing precision of the vacuum channel. This method is highly compatible with CMOS processes, significantly reducing the manufacturing cost of the device, and achieving high process consistency.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a preparation method thereof, in particular to a vacuum transistor and a preparation method thereof. Background Art

[0002] With the rapid development of the integrated circuit industry, integrated circuit manufacturing technology has entered the 5nm technology node. The continuous miniaturization of the characteristic size of semiconductor devices has approached the physical limit of size. Limited by the fact that the carrier mobility in silicon-based solid-state devices is essentially affected by lattice scattering or impurities, silicon-based devices can no longer meet the growing demand for high frequency or fast response. Compared with the situation in solid-state devices, the electron movement speed under vacuum conditions is theoretically 3×10 10 cm / s, which is about three orders of magnitude faster than its motion in semiconductors and is unaffected by collisions or scattering. Furthermore, nanoscale vacuum channel transistors (NVCTs) based on field emission principles have gained widespread attention due to their more stable performance in extreme environments (such as high temperature and high radiation).

[0003] The electron emission voltage is closely related to the size of the vacuum channel. As the operating voltage continues to decrease, if it is desired to achieve high-speed switching of the device under low voltage and non-vacuum conditions, the size of the vacuum channel needs to be at the nanometer level. Simply relying on existing photolithography technology is difficult to ensure the control accuracy of the nanometer size, so it is not easy to prepare a highly integrated NVCT chip.

[0004] Therefore, it is necessary to provide a novel nano vacuum channel transistor and a preparation method thereof.

[0005] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of this application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because these solutions are explained in the background technology part of this application. Summary of the Invention

[0006] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a nano vacuum channel transistor and a preparation method thereof, which are used to solve the problems in the existing process of vacuum channel transistors, such as the difficulty in achieving the processing accuracy and stability of the nano gap to meet application requirements and the incompatibility with CMOS processes.

[0007] To achieve the above-mentioned and other related objectives, the present invention provides a method for preparing a nano vacuum channel transistor, comprising the following steps:

[0008] Providing an SOI substrate, the SOI substrate comprising a back substrate, an insulating layer and a top functional layer, and performing a first patterning on the top functional layer to form a first electrode portion;

[0009] forming a first sacrificial spacer structure on a sidewall of the first electrode portion;

[0010] forming a first electrode material layer covering the first electrode portion and the first sacrificial spacer structure, patterning the first electrode material layer to form a first gate electrode portion, and simultaneously patterning the top functional layer a second time to form an emitter with a tip based on the first electrode portion, wherein the first gate electrode portion has an end portion adjacent to the emitter tip;

[0011] forming a second sacrificial spacer structure on the sidewall of the emitter electrode with a pointed tip and the sidewall of the first gate electrode portion, intersecting with the first sacrificial spacer structure;

[0012] A collector is formed from an intersection of the first sacrificial spacer structure and the second sacrificial spacer structure in a direction away from the emitter, the collector being adjacent to the first sacrificial spacer structure and the second sacrificial spacer structure and formed at a diagonal position of the emitter tip, and a second gate electrode portion is formed adjacent to an end of the emitter tip and opposite to the first gate electrode portion;

[0013] The first sacrificial spacer structure and the second sacrificial spacer structure are removed to release the nanogap between the emitter and the collector.

[0014] Optionally, after the step of forming the first electrode material layer, the emitter and the first gate electrode portion are formed synchronously by the following steps: the first electrode material layer is flattened so that the top surface of the obtained first electrode material layer is flush with the top surface of the first electrode portion; the first electrode portion and the first electrode material layer are anisotropically etched based on a patterned mask layer, and the patterned mask layer is formed on the first electrode portion and the first electrode material layer in a manner that a side wall is beveled on the two, so that the etched end faces of the emitter and the first gate electrode portion are coplanar.

[0015] Optionally, the step of forming the second sacrificial sidewall structure includes: forming a second sacrificial dielectric material layer covering the exposed surface of the insulating layer; performing an anisotropic etching process on the second sacrificial dielectric material layer to form a second sacrificial sidewall structure on the etched end surfaces of the emitter and the first gate electrode portion, and the second sacrificial sidewall structure intersects with the first sacrificial sidewall structure.

[0016] Optionally, after the step of forming the second sacrificial sidewall structure, it includes: forming a third electrode material layer covering the insulating layer; flattening the third electrode material layer to form a collector at a diagonal position of the emitter tip, and at the same time forming a second gate electrode portion opposite to the first gate electrode portion.

[0017] Optionally, after the step of forming the collector, a gate electrode is formed by performing the following steps, including: removing the first gate electrode portion and the second gate electrode portion; forming a third electrode material layer overlying the insulating layer; and flattening the third electrode material layer so that the top surface of the obtained third electrode material layer is flush with the top surface of the emitter and the collector, thereby forming gate electrodes on both sides of the emitter and the collector.

[0018] Optionally, before the step of forming the gate electrode, it includes: forming a gate dielectric material layer covering the emitter and the collector; performing an anisotropic etching process on the gate dielectric material layer, and forming the gate dielectric material layer retained on the side walls of the first sacrificial sidewall structure and the second sacrificial sidewall structure into a gate dielectric layer.

[0019] The present invention also provides a method for preparing a nano vacuum channel transistor, comprising the following steps:

[0020] Providing a substrate layer, forming a first insulating layer, a polycrystalline semiconductor layer, a second insulating layer and a top functional layer on the substrate layer, and patterning the top functional layer to form an emitter with a pointed tip;

[0021] forming a sacrificial sidewall structure on the sidewall of the emitter;

[0022] A collector is formed by using the sacrificial sidewall structure as a spacer and spaced apart from the emitter, wherein the collector has an end portion adjacent to the emitter tip;

[0023] Forming a gate structure, comprising the following steps: forming a gate dielectric layer based on the second insulating layer; forming a gate electrode based on the polycrystalline semiconductor layer; wherein the emitter and the collector are formed on a first main surface of the second insulating layer, and the polycrystalline semiconductor layer is formed on a second main surface of the second insulating layer opposite to the first main surface;

[0024] The sacrificial sidewall structure is removed to release the nano-gap between the collector and the emitter.

[0025] Optionally, the step of forming the sacrificial sidewall structure includes: covering the patterned top functional layer to form a sacrificial dielectric material layer; removing a portion of the sacrificial dielectric material layer through an anisotropic etching process, and retaining the sacrificial dielectric material layer covering the emitter sidewall to form the sacrificial sidewall structure.

[0026] Optionally, the step of forming the collector includes: forming an electrode material layer covering the emitter and the sacrificial sidewall structure; and flattening the electrode material layer so that the top surface of the obtained electrode material layer is flush with the top surface of the emitter and the sacrificial sidewall structure.

[0027] Optionally, a cross section of the sacrificial sidewall structure perpendicular to its extension direction is formed into a rectangle, a parallelogram or an inverted trapezoid.

[0028] Optionally, it further includes: forming a metal contact between the emitter and the collector and a metal electrode for achieving electrical extraction.

[0029] On the other hand, the present invention further provides a nano vacuum channel transistor, comprising:

[0030] substrate layer;

[0031] an insulating layer located on the substrate layer, the insulating layer having a first main surface and a second main surface opposite to each other, an emitter and a collector spaced apart and opposite to each other disposed on the first main surface of the insulating layer, the end of the emitter opposite to the collector being configured to be pointed, a nanometer gap being defined between the tip of the emitter and the end of the collector to provide a channel region for the emitter to emit electrons to the collector;

[0032] A gate electrode is disposed on the first main surface or the second main surface of the insulating layer and is located on a side adjacent to the nanogap.

[0033] Optionally, the sidewall of the collector extending toward the emitter is configured to have a concave profile substantially complementary to the emitter tip, so as to define a nanogap between opposite sidewalls of the emitter and the collector, wherein the size of the nanogap is in the range of 0.1 nm to 50 nm.

[0034] Optionally, the ends of the emitter and the collector extending toward each other are respectively configured to form sharp-angled tip structures, defining a nanogap between the opposite tips of the emitter and the collector, wherein the size of the nanogap ranges from 0.1 nm to 50 nm.

[0035] Optionally, the gate electrode is located on both sides of the emitter and the collector and is spaced apart from the emitter and the collector respectively.

[0036] Optionally, it further includes: a gate dielectric layer, which is arranged on the bottom surface and sidewalls of the gate electrode to reduce the leakage current of the gate electrode, and the cross-section of the nanogap between the emitter and the collector perpendicular to its extension direction is rectangular, parallelogram or inverted trapezoidal.

[0037] As described above, the nano vacuum channel transistor and the method for preparing the same according to the present invention have the following beneficial effects:

[0038] In the nano vacuum channel transistor of the present invention, the emitter has a tip arranged opposite to the collector, and a nanometer gap is defined between the emitter and the collector, which can realize a nanometer-scale channel, so that the influence of vacuum degree on the field emission transistor is reduced. The gate electrode is arranged at least one of the above, below and both sides of the emitter and the collector, giving the device the required gate control capability, thereby realizing high-speed switching of the device at a lower operating voltage.

[0039] In the preparation method of the nano vacuum channel transistor of the present invention, a mature photolithography technology is used to form an emitter with a pointed tip, replacing the conventional electron beam lithography or focused ion beam etching technology. After the step of forming the emitter and / or collector, a sacrificial sidewall structure is formed on the sidewall of the sacrificial sidewall structure. The sacrificial sidewall structure is used to define the nano gap between the emitter and the collector, ensuring the nanoscale processing accuracy of the vacuum channel. It is highly compatible with the CMOS process, greatly reducing the manufacturing cost of the device, and has the advantages of high process consistency, further releasing the application potential of the nano channel transistor and facilitating the realization of highly integrated NVCT chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 Shown is a process flow chart of a method for preparing a nano vacuum channel transistor in the first embodiment of the present invention.

[0041] 2 to 9 are schematic diagrams showing the structures obtained in each step of the preparation process of the nano vacuum channel transistor in the first embodiment of the present invention; wherein, Figures 2b to 9b Displayed as Figures 2a to 9a The structure shown is a cross-sectional view along section AA'. Figure 2c Display as Figure 2a Isometric view of the structure shown.

[0042] Figures 10 to 14 Shown is a schematic diagram of the structure obtained during the vacuum packaging process of the nano vacuum channel transistor in Example 1 of the present invention.

[0043] Figure 15 to Figure 17 It shows a schematic diagram of defining nanogaps of different cross-sectional shapes during the preparation process of the nano vacuum channel transistor in the first embodiment of the present invention; wherein, Figure 15b for Figure 15a The structure is shown in a cross-sectional view along section AA'.

[0044] Figure 18 Shown is a process flow chart of a method for fabricating a nano vacuum channel transistor in a second embodiment of the present invention.

[0045] 19 to 29 are schematic diagrams showing the structures obtained in each step of the preparation process of the nano vacuum channel transistor according to the second embodiment of the present invention; wherein, Figures 19b to 24b Displayed as Figures 19a to 24a A cutaway view of the structure shown along section SS';

[0046] Figure 19c and Figure 24c They are Figure 19a and Figure 24a an isometric view of the structure shown; Figures 25b to 29b They are Figures 25a to 29a A cross-sectional view of the structure shown along section AA'; Figures 25c to 29c They are Figures 19a to 24a A cross-sectional view of the structure shown along section BB'; Figures 25d to 29d They are Figures 25a to 29a A cross-sectional view of the structure shown along section CC'; Figures 25e to 29e They are Figures 25a to 29a A cross-sectional view of the structure shown along section DD'; Figure 25f 、 Figure 28f and Figure 29f They are 25a, Figure 28a and Figure 29a Isometric view of the structure shown.

[0047] 30 to 35 are schematic structural diagrams showing various stages of forming gate electrodes using the first gate electrode portion and the second gate electrode portion as dummy gates during the preparation process of the nano vacuum channel transistor according to the second embodiment of the present invention; wherein, Figures 30b to 35b They are Figures 30a to 35a A cross-sectional view of the structure shown along section AA'; Figures 30c to 35c They are Figures 30a to 35a A cross-sectional view of the structure shown along section BB'; Figures 30d to 35d They are Figures 30a to 35a A cross-sectional view of the structure shown along section CC'; Figures 30e to 35e They are Figures 30a to 35a A cross-sectional view of the structure shown along section DD'; Figure 35f for Figure 35a A cross-sectional view of the structure shown along section EE'; Figure 30f 、 Figure 34f and Figure 35g They are 30a, Figure 34a and Figure 35a Isometric view of the structure shown.

[0048] 36 to 38 are schematic diagrams showing the definition of nanogaps of different cross-sectional shapes during vacuum packaging of a nano vacuum channel transistor in the second embodiment of the present invention; wherein, Figures 36b to 38b They are Figures 36a to 38a A cross-sectional view of the structure shown along section AA'; Figures 36c to 38c They are Figures 36a to 38aA cross-sectional view of the structure shown along section BB'; Figures 36d to 38d They are Figures 36a to 38a A cross-sectional view of the structure shown along section CC'; Figures 36e to 38e They are Figures 36a to 38a A cross-sectional view of the structure shown along section DD'; Figures 36f to 38f They are Figures 36a to 38a The structure shown is a cross-sectional view along section EE'.

[0049] 39 to 42 are cross-sectional views of a nano vacuum channel transistor according to a third embodiment of the present invention; wherein, Figure 39b for Figure 39a A cross-sectional view of the structure shown along section AA'; Figure 40 and a schematic diagram of partially retaining a sacrificial dielectric material layer in a nano vacuum channel transistor as shown in FIG42 ; Figures 42b to 42f for Figure 42a The structure shown is a cross-sectional view along sections AA', BB', CC', DD' and EE'.

[0050] Component number description

[0051] 110 substrate layer

[0052] 120 first insulation layer

[0053] 130 polycrystalline semiconductor layer

[0054] 140 Second insulation layer

[0055] 150 top functional layer

[0056] 152 electrode material layer

[0057] 2520 first electrode material layer

[0058] 2530 second electrode material layer

[0059] 2540 first sacrificial dielectric material layer

[0060] 2541 First Sacrificial Side Wall Structure

[0061] 2542 second sacrificial dielectric material layer

[0062] 2545 Second sacrificial side wall structure

[0063] 310 back gate electrode

[0064] 510 emitter

[0065] 520 collector

[0066] 1540 sacrificial dielectric material layer

[0067] 1541 Sacrificial Side Wall Structure

[0068] 550 nm gap

[0069] 560 gate electrode

[0070] 561a, 561b gate dielectric layer

[0071] 5610 gate dielectric material layer

[0072] 2510 First Electrode

[0073] 2560 First gate electrode portion

[0074] 2562 Second gate electrode portion

[0075] 610 Metal Connection

[0076] 620 passivation layer

[0077] 650 top passivation layer

[0078] Steps S11 to S15, S21 to S26 DETAILED DESCRIPTION

[0079] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0080] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification for understanding and reading by those familiar with this technology, and are not used to limit the conditions for implementation of the present invention. Therefore, they have no substantial technical significance. Any modification of the structure, change in the proportional relationship, or adjustment of the size should still fall within the scope of the technical content disclosed by the present invention without affecting the efficacy and purpose that can be achieved by the present invention. At the same time, terms such as "upper", "lower", "above", "below", "middle" and "one" quoted in this specification are only for the convenience of description and are not used to limit the scope of implementation of the present invention. Changes or adjustments in their relative relationships should also be regarded as the scope of implementation of the present invention without substantially changing the technical content.

[0081] Unlike conventional solid-state transistors, where carrier migration is constrained by drift-diffusion mechanisms, the vacuum transistors of the present invention contain a channel in a vacuum state. By increasing temperature, electric field, or illumination, the potential barrier at the vacuum emitter surface can be significantly lowered. Under a strong external electric field, the height and width of the potential barrier at the emitter surface decrease, allowing electrons to potentially enter the vacuum.

[0082] The fabrication process for planar nanovacuum channel transistors (NVCTs) typically employs electron beam lithography or focused ion beam etching to form a microneedle-structured emitter and / or collector. The fabrication method for the nanovacuum channel transistor provided by the present invention employs established lithography techniques, such as ultraviolet lithography, to form a pointed emitter and a collector with its end facing the emitter tip on the top functional layer of an SOI substrate. This defines a nanometer gap between the emitter and the collector, ensuring nanoscale machining precision for the vacuum channel and high compatibility with CMOS processes. This enables high-speed switching of the field emission transistor at low voltages, even in non-vacuum conditions.

[0083] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0084] Example 1

[0085] First, see Figure 1 , performing step S11, providing a substrate layer, on which a first insulating layer, a polycrystalline semiconductor layer, a second insulating layer and a top functional layer are formed, and patterning the top functional layer to form an emitter with a pointed tip.

[0086] Figure 2a It is a schematic diagram showing the structure after forming a top functional layer on the substrate layer. Figure 2b for Figure 2aThe structure shown is a cross-sectional view along the AA' section. In step S11, a first insulating layer 120, a polycrystalline semiconductor layer 130, a second insulating layer 140, and a top functional layer 150 are sequentially formed on the substrate layer 110. The material of the polycrystalline semiconductor layer includes, but is not limited to, silicon, germanium, silicon carbide, and gallium nitride. The top functional layer 150 can be made of conventional semiconductor materials in the art, including but not limited to Group IV semiconductor materials, such as Si, Ge, and SiC; or III-V compound semiconductor materials, such as GaN. The second insulating layer can be made of a suitable gate dielectric material, including insulating materials such as silicon dioxide, zirconium dioxide, hafnium dioxide, aluminum oxide, hafnium aluminum oxide, and lanthanum aluminum oxide; or wide bandgap semiconductor materials. In some cases, the second insulating layer includes a cavity therein or at the interface. The composition of the material layer to be formed and the formation process thereof can be determined based on the desired device performance, including but not limited to: chemical vapor deposition process, plasma-enhanced chemical vapor deposition process, atomic layer deposition process, or similar processes. In this embodiment, the second insulating layer 140 has a thickness smaller than that of the first insulating layer 120 .

[0087] See also Figure 3a to Figure 3b , Figure 3a Shown is a top view of the structure obtained after patterning the top functional layer. Figure 3b for Figure 3a The structure is shown in a cross-sectional view along section AA'. Step S11, patterning the top functional layer 150, includes etching the top functional layer 150 using a patterned mask layer until the surface of the second insulating layer 140 is exposed, forming a patterned region that penetrates the top functional layer 150, and forming the emitter 510 having a pointed tip.

[0088] The patterned mask layer may include a photoresist pattern formed based on lithography technology. In this embodiment, the patterned mask layer includes a photoresist pattern formed by a photolithography process. The standard photolithography process may include processing steps such as photoresist coating, soft baking, mask alignment, exposure, post-exposure baking, development, and hard baking. Under the premise of ensuring the required emission performance, the morphology of the emitter is adjusted by adjusting the shape and / or size of the pattern defined by the photolithography. Figure 3a As shown, the resulting patterned region is formed into a sharp tip with an acute top angle, which can improve the field enhancement factor.

[0089] Next, step S12 is performed to form a sacrificial spacer structure on the sidewall of the emitter.

[0090] Specifically, see Figures 4a to 4bThe step of forming a sacrificial sidewall structure 1541 includes: forming a sacrificial dielectric material layer 1540 covering the patterned area, wherein the sacrificial dielectric material layer 1540 can be conformally deposited on the second insulating layer 140, and the sacrificial dielectric material layer can have a thickness of nanometer level. The sacrificial dielectric material layer can be deposited by chemical vapor deposition (CVD), atomic layer deposition (ALD) or similar processes, wherein the sacrificial dielectric material includes but is not limited to: SiO x 、SiN x 、SiN x O y and one of Al2O3.

[0091] Further, see Figure 5a to Figure 5b In step S12, the sacrificial dielectric material layer is anisotropically etched to remove the sacrificial dielectric material layer 1540 covering the emitter and the top surface of the second insulating layer. The sacrificial dielectric material layer covering the sidewalls of the emitter is retained to form a sacrificial sidewall structure 1541. Since the sacrificial dielectric material layer can have a thickness on the nanometer scale, the sacrificial dielectric material layer is anisotropically etched, i.e., the sacrificial dielectric material layer is etched at a higher longitudinal etching rate than a lateral etching rate. Therefore, the sacrificial sidewall structure obtained by etching can also have a nanometer-scale thickness, for example, a thickness between 0.1 nm and 50 nm.

[0092] In some embodiments, the cross-section of the sacrificial spacer structure 1541 perpendicular to its extension direction is formed into a rectangle, parallelogram, or inverted trapezoid. Ideally, the top functional layer is anisotropically etched based on a patterned mask layer to form an emitter with vertical sidewalls. In actual processes, the anisotropic etching process can be a non-ideal anisotropic etching process, such as an inductively coupled plasma (ICP) etching process or reactive ion etching (RIE) process, resulting in the emitter having inclined sidewalls. The resulting sacrificial spacer structure 1541 is formed into a cross-section having at least one oblique side perpendicular to its extension direction.

[0093] Next, step S13 is performed to form a collector separated from the emitter by using the sacrificial sidewall structure as a spacer. The collector is formed adjacent to the tip of the emitter.

[0094] Specifically, step S13 includes: covering the emitter and the sacrificial side wall structure to form an electrode material layer; flattening the electrode material layer, so that the top surface of the obtained electrode material layer is flush with the top surface of the emitter and the sacrificial side wall structure; patterning the electrode material layer to form a collector in a manner that the sacrificial side wall structure and the emitter are spaced apart, and the tip of the emitter is separated from the collector by the sacrificial side wall structure.

[0095] See also Figures 6a to 6b , is a schematic diagram of the structure obtained after forming the electrode material layer in step S13. Figure 6a As shown, the electrode material can be conformally deposited on the substrate 110 to cover the emitter 510 and the sacrificial spacer structure 1541 to form an electrode material layer 152 . The deposited electrode material layer 152 has good step coverage.

[0096] The electrode material layer 152 may be made of the same or different material as the top functional layer. The material of the electrode material layer includes, but is not limited to, one of polysilicon, Pt, Ru, Ir, Mo, Ti, Al, W, Co, Cr, Au, Cu, and Ag. For example, the electrode material layer 152 may be deposited by chemical vapor deposition (CVD), atomic layer deposition (ALD), or a similar process.

[0097] In some examples, the surface of the electrode material layer is planarized, wherein the method of planarizing the electrode material layer includes, for example, a chemical mechanical polishing (CMP) process or a similar process. Figures 7a and 7b , Figure 7a It is a top view of the structure obtained after the electrode material layer is planarized in step S13. Figure 7b for Figure 7a The structure shown is a cross-sectional view along section AA'. Figure 7b As shown, the emitter, the sacrificial sidewall structure and the top surface of the electrode material layer are made flush.

[0098] When the resulting emitter 510 is formed into an inclined sidewall, a sacrificial sidewall structure 1541 is formed on the sidewall of the emitter; the cross-section of the sacrificial sidewall structure 1541 perpendicular to its extension direction is formed into a parallelogram, which can prevent the passivation layer from entering the gap during the vacuum packaging of the nano vacuum channel transistor; or, the cross-section of the sacrificial sidewall structure 1541 perpendicular to its extension direction is formed into an inverted trapezoid in the following manner, including but not limited to, when performing the deposition step of the sacrificial dielectric material layer, the substrate layer on which the emitter is formed is tilted at a preset angle, so that in the subsequent process of removing the sacrificial sidewall structure, the etchant or corrosive liquid can more easily enter the gap, thereby improving the production yield of the device.

[0099] In applications with vacuum requirements, the device can be vacuum packaged to ensure the surface cleanliness of the emitter and the stability of the device. Figures 10 to 13 , is to vacuum package the nano vacuum channel transistor manufactured according to this embodiment. Figures 10 to 13 As shown, in Figures 6a to 6bAfter the step of forming the electrode material layer as shown, the electrode material layer 152 is patterned. The electrode material layer 152 covering the sacrificial sidewall structure may have a top surface higher than the collector. A passivation layer 620 is formed covering the emitter 510 and the patterned electrode material layer. Figure 12 As shown, the top surface of the passivation layer is higher than the top surface of the patterned electrode material layer; then, as shown Figure 13 As shown, the passivation layer 620 is planarized, wherein the method of planarizing the passivation layer 620 includes, for example, a CMP process or a similar process, so that the top surface of the resulting collector is flush with the top surface of the emitter, and the sacrificial side wall structure 1541 is exposed, which facilitates the removal of the sacrificial side wall structure in subsequent processes.

[0100] Next, step S14 is performed to remove the sacrificial sidewall structure to release the nano-gap between the collector and the emitter.

[0101] See also Figures 8a to 8b , Figure 8a The top view of the structure obtained after the nanogap is released in step S14 is shown. Figure 8b for Figure 8a The structure shown is a cross-sectional view along section AA'. Ideally, the sacrificial sidewall structure 1541 has a rectangular cross section along a plane perpendicular to its extension direction, that is, the ends of the emitter and the collector are spaced apart at approximately equal intervals.

[0102] For other examples, see Figures 16 and 17 , is a schematic diagram of forming nanogaps with different cross-sectional shapes during the fabrication of the nano vacuum channel transistor according to this embodiment. The cross-section of the sacrificial spacer structure 1541 perpendicular to its extension direction is formed into a parallelogram or an inverted trapezoid. After removing the sacrificial spacer structure 1541, the released nanogap 550 has a shape substantially consistent with the sacrificial spacer structure 1541.

[0103] Next, step S15 is performed to form a gate structure, including the following steps: forming a gate dielectric layer based on the second insulating layer; forming a gate electrode based on the polycrystalline semiconductor layer; wherein the emitter and the collector are formed on the first main surface of the second insulating layer, and the polycrystalline semiconductor layer is formed on the second main surface of the second insulating layer opposite to the first main surface.

[0104] Specifically, the step of forming the gate structure may be performed after the step of releasing the nanogap 550 , or before the step of forming the top functional layer 150 .

[0105] like Figures 8a to 8bAs shown, a first insulating layer 120, a polycrystalline semiconductor layer 130, a second insulating layer 140 and a top functional layer 150 are sequentially formed on the substrate layer 110, the polycrystalline semiconductor layer 130 is used as a back gate electrode, and the second insulating layer 140 is located between the gate electrode and the emitter and the collector, and is used as a back gate dielectric layer.

[0106] exist Figures 8a to 8b In the illustrated implementation, before the step of forming the top functional layer, a back gate structure is formed, and the back gate structure includes a back gate electrode and a back gate dielectric layer.

[0107] In another implementation, after the step of releasing the nanogap 550, a top gate structure is formed on the emitter 510 and the collector 520; wherein the step of forming the top gate structure includes: forming a second insulating layer 140 and a polycrystalline semiconductor layer 130 on the emitter 510 and the collector 520, and forming a gate dielectric layer based on the second insulating layer 140; forming a top gate electrode based on the polycrystalline semiconductor layer 130, the top gate electrode is located on the first main surface of the second insulating layer, and the top functional layer is located on the second main surface of the second insulating layer.

[0108] In a specific example, the step of forming the top gate structure includes: providing a supporting substrate, on which a polycrystalline semiconductor layer 130 and a second insulating layer 140 are sequentially formed, and transferring the polycrystalline semiconductor layer 130 and the second insulating layer 140 onto the substrate by bonding the second insulating layer 140 to the top surfaces of the emitter and the collector, wherein the polycrystalline semiconductor layer 130 can be used as a top gate electrode, and the second insulating layer 140 can be used as a gate dielectric layer.

[0109] Optionally, after step S15 , the obtained nano vacuum channel transistor is packaged.

[0110] In the application scenario of low vacuum or air environment, after the step of releasing the nano gap 550 in step S15, as shown in FIG. Figures 9a to 9b As shown, metal wires 610 may be formed at the gate electrode, the emitter 510 and the collector 520 , and the metal wires 610 form metal contacts with the gate electrode, the emitter 510 and the collector respectively.

[0111] In the application scenario with vacuum requirements, vacuum packaging can be used. After the step of releasing the nano gap 550, the resulting structure is as follows: Figure 15a and Figure 15bAs shown, a top passivation layer 650 may be formed on the emitter 510 and the collector 520 ; subsequently, openings are formed above the gate electrode, the emitter and the collector to form metal contacts and metal wiring.

[0112] As an example, the top passivation layer 650 is formed by a process including but not limited to chemical vapor deposition (CVD) or thin film bonding.

[0113] The metal connections are formed using common technical means in the art, including but not limited to etching and metal stripping.

[0114] Figure 15b 、 Figures 16 and 17 The schematic diagrams of several structures of nano vacuum channel transistors using vacuum packaging are shown. In an ideal state, the cross section of the sacrificial sidewall structure 1541 perpendicular to its extension direction is formed into a rectangle, and the resulting nano gap 550 can be seen in FIG. Figure 15b , that is, the ends of the emitter and the collector are spaced apart at approximately equal intervals. In some cases, the cross section of the sacrificial sidewall structure 1541 perpendicular to its extension direction is formed into a parallelogram or an inverted trapezoid, and the resulting nanogap 550 can be seen in FIG. Figure 16 and Figure 17 shown.

[0115] It should be noted that the above sequence does not strictly represent the execution order of the method for preparing the nano vacuum channel transistor protected by the present invention, and those skilled in the art may change the sequence of steps according to the actual process.

[0116] Example 2

[0117] This embodiment provides a method for preparing a nano vacuum channel transistor. Figure 18 , after which the preparation method of the nano vacuum channel transistor in this embodiment is described in detail.

[0118] First, step S21 is performed to provide an SOI substrate, wherein the SOI substrate includes a back substrate, an insulating layer, and a top functional layer. The top functional layer is patterned for the first time to form a first electrode portion.

[0119] See also Figures 19a to 19c , Figure 19a Shown is a top view of the SOI substrate used in step S21, Figure 19c Shown is an isometric view of the SOI substrate used in step S21, Figure 19b for Figure 19a The structure shown is a cross-sectional view along the SS' section. Figure 19bAs shown, the SOI substrate includes a back substrate 210, an insulating layer 220 and a top functional layer 250. Different from the step S11 in which the emitter 510 is formed by a single patterning of the top functional layer, the patterned region of the top functional layer obtained in step S21 is formed as a first electrode portion 2510, which covers the region where the emitter is formed. The resulting structure is as shown in FIG. Figures 20a to 20b shown.

[0120] As an example, the patterned region of the top functional layer, i.e., the first electrode portion 2510, may be formed to have vertical sidewalls; or, the first electrode portion 2510 may have inclined sidewalls, i.e., an overall trapezoidal cross-section. Similarly, ideally, based on the patterned mask layer, the top functional layer is anisotropically etched to form a first electrode portion with vertical sidewalls; in actual processes, the anisotropic etching process may be a non-ideal anisotropic etching process, such as an inductively coupled plasma (ICP) etching process or a reactive ion etching (RIE) process, so that the first electrode portion has inclined sidewalls, such as Figure 37f and Figure 38f shown.

[0121] Next, step S22 is performed to form a first sacrificial spacer structure on the sidewall of the first electrode portion.

[0122] Specifically, the step of forming the first sacrificial spacer structure 2541 includes: forming a first sacrificial dielectric material layer 2540 on the insulating layer 220; performing an anisotropic etching process on the first sacrificial dielectric material layer 2540 to form the first sacrificial spacer structure 2541 on the sidewall of the first electrode portion. Figures 21a to 22a , which are top views of the structure obtained after forming the first sacrificial dielectric material layer and the first sacrificial sidewall structure in step S22 .

[0123] Figure 21b for Figure 21a The structure shown is cut along section SS', and a first sacrificial dielectric material layer 2540 is formed covering the first electrode portion and the exposed surface of the insulating layer. In this embodiment, the first sacrificial dielectric material layer 2540 can be formed using a process similar to that described in the previous embodiment.

[0124] Figure 22b for Figure 22a In some examples, a portion of the first sacrificial dielectric material layer is removed by an anisotropic etching process, such as Figure 22bAs shown, the first sacrificial dielectric material layer overlying the first electrode portion and the insulating layer is removed, forming a first sacrificial spacer 2541. The first sacrificial spacer 2541 can define the spacing region between the gate electrode to be formed and the collector and emitter electrodes. In a specific example, the first electrode portion has inclined sidewalls, and accordingly, the first sacrificial spacer 1541 has at least one oblique side in a cross-section perpendicular to its extension direction, such as a parallelogram or an inverted trapezoid. The first sacrificial spacer structure, which had a trapezoidal cross-section perpendicular to its extension direction, is formed into an inverted trapezoid in a manner similar to the formation of the sacrificial spacer structure in the previous embodiment.

[0125] Next, step S23 is performed to form a first electrode material layer covering the first electrode portion and the first sacrificial sidewall structure, and the first electrode material layer is patterned to form a first gate electrode portion. At the same time, the top functional layer is patterned for a second time to form an emitter with a pointed tip based on the first electrode portion, and the first gate electrode portion has an end portion adjacent to the emitter tip.

[0126] Figures 23a to 23b , are top views of the structure obtained after forming the first electrode material layer in step S23. In some examples, the first electrode material layer 2520 is deposited by chemical vapor deposition (CVD) or physical vapor deposition (PVD). The first electrode material layer 2520 can be made of a material suitable for forming a collector, including but not limited to: polysilicon, Pt, Ru, Ir, Mo, Ti, Al, W, Co, Cr, Au, Cu, and Ag.

[0127] After the step of forming the first electrode material layer 2420 , an etching process is simultaneously performed on the first electrode material layer 2520 and the first electrode portion, and the etching process stops at the surface of the insulating layer. Figures 25a to 25f , are schematic diagrams of the structures obtained after the emitter and the first gate portion are formed in step S23, wherein Figures 25b to 25e They are Figure 25a The structure shown is cut along the AA', BB', CC', DD' sections. Figure 25f for Figure 25a Isometric view of the structure shown.

[0128] Before the step of patterning the first electrode portion 2510, the first electrode material layer is planarized to expose the top surface of the first electrode portion. The resulting structure is as shown in FIG. Figures 24a to 24c In a specific example, the first electrode material layer 2520 is planarized by, for example, a CMP process or a similar process, so that the top surface of the obtained first electrode material layer is flush with the top surface of the first electrode portion.

[0129] In some examples, the emitter 510 is formed by the following steps: forming a patterned mask layer on the first electrode material layer 2520, wherein the patterned mask layer overlaps with the first electrode portion 2510, etching the first electrode portion 2510 based on the patterned mask layer to form an emitter 510 with a pointed tip, and the resulting structure is as follows: Figure 25a As shown; preferably, the patterned mask layer includes a photoresist pattern formed by lithography, and the patterned mask layer is formed on the first electrode portion 2510 and the first electrode material layer 2520 in a manner such that one side wall is respectively beveled; based on the patterned mask layer, the first electrode material layer 2520 is etched, as shown Figure 25a and Figure 25f As shown, the emitter 510 is formed to have a sharp-angled tip.

[0130] like Figure 25a As shown, based on the patterned mask layer, a portion of the first electrode portion is removed through an anisotropic etching process to form an emitter 510, and at the same time, a portion of the first electrode material layer is removed to form a first gate electrode portion 2560, and the first gate electrode portion and the etched end surface of the first electrode portion have overlapping extension surfaces; preferably, the first gate electrode portion and the etched end surface of the first electrode portion are coplanar.

[0131] Next, step S24 is performed to form a second sacrificial spacer structure on the sidewall with the tip of the emitter and the sidewall of the first gate electrode portion, intersecting with the first sacrificial spacer structure.

[0132] Specifically, the step of forming the second sacrificial spacer structure 2545 includes: forming a second sacrificial dielectric material layer 2542 covering the exposed surface of the insulating layer; and performing an anisotropic etching process on the second sacrificial dielectric material layer 2542 to form the second sacrificial spacer structure 2545. The second sacrificial dielectric material layer 2542 can be formed using a process similar to that used to form the first sacrificial dielectric material layer.

[0133] See also Figures 26a to 26e , are schematic diagrams of the structure obtained after forming the second sacrificial dielectric material layer in step S24. Figure 26a As shown, the second sacrificial dielectric material layer 2542 also covers the top surface and side walls of the emitter and the first gate electrode portion. After the second sacrificial dielectric material layer covering the top surface of the emitter, the first gate electrode portion and the insulating layer is removed by an anisotropic etching process, a second sacrificial sidewall structure is formed on the pointed sidewall of the emitter and the sidewall of the first gate electrode portion, and the first sacrificial sidewall and the second sacrificial sidewall structure intersect.

[0134] like Figure 27a As shown, the second sacrificial spacer 2545 is formed on the coplanar sidewalls of the emitter and the first gate electrode portion. The first sacrificial spacer 2541 and the second sacrificial spacer 2545 define the spacing between the gate electrode to be formed, the collector, and the emitter. The second sacrificial spacer 2545 is also formed to cover the portion of the first sacrificial spacer not surrounded by the first electrode portion and the first gate electrode portion. By forming the first and second sacrificial spacer structures to intersect at an angle close to the tip of the emitter, the intersection of the first and second sacrificial spacer structures defines the channel region to be formed. Because the second sacrificial spacer structure also covers the exposed portion of the first sacrificial spacer structure away from the emitter, the distance between one side of the collector to be formed and the gate electrode is greater than the distance between the other side of the collector and the gate electrode.

[0135] Next, step S25 is performed to form a collector from the intersection of the first sacrificial sidewall structure and the second sacrificial sidewall structure in a direction away from the emitter, the collector is adjacent to the first sacrificial sidewall structure and the second sacrificial sidewall structure and is formed at a diagonal position of the emitter tip, and a second gate electrode portion is formed adjacent to the end of the emitter tip and opposite to the first gate electrode portion.

[0136] Specifically, step S25 includes: forming a second electrode material layer 2530 ; and performing a planarization process on the second electrode material layer 2530 to form a collector 520 . Figures 27a to 27e , are schematic diagrams of the structures obtained after the second electrode material layer is formed in step S25.

[0137] The second electrode material layer 2530 can be conformally deposited on the insulating layer 220, and the deposited second electrode material layer 2530 has good step coverage. Figure 27a As shown, the second electrode material layer 2530 covers the emitter 510 , the first gate electrode portion 2560 , the first sacrificial spacer structure 2541 , the second sacrificial spacer structure 2545 , and the insulating layer 220 .

[0138] As an example, the second electrode material layer 2530 can be deposited by a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process or a similar process. The material of the second electrode material layer 2530 includes but is not limited to: one of polysilicon, Pt, Ru, Ir, Mo, Ti, Al, W, Co, Cr, Au, Cu, and Ag.

[0139] At step S25, see Figures 28a to 28f, the second electrode material layer 2530 is planarized, wherein the method of planarizing the second electrode material layer 2530 includes, for example, a CMP process or a similar process, so that the top surface of the second electrode material is flush with the top surface of the emitter and the first gate electrode portion, and the intersection area of ​​the first sacrificial sidewall structure and the second sacrificial sidewall structure is used as a spacer to form a collector 520 separated from the emitter; that is, the collector 520 and the emitter 510 are diagonally arranged with respect to the intersection area of ​​the first sacrificial sidewall structure and the second sacrificial sidewall structure, and the end of the collector is also formed with a tip, and the collector and the tip of the emitter have approximately equal angles.

[0140] In one implementation, the collector 520 and the second gate electrode portion 2562 can be formed simultaneously, and accordingly, the gate electrode 560 and the collector 520 can be made of the same material, such as Figures 27a to 28a As shown, the second electrode material layer 2530 is planarized, and the top surface of the obtained second electrode material layer 2530 is flush with the top surfaces of the emitter and the first gate electrode portion, and a collector 520 is formed at the diagonal position of the emitter tip. At the same time, a second gate electrode portion 2562 is formed opposite to the first gate electrode portion, thereby forming a gate electrode 560 on both sides of the emitter and the collector. The gate electrode 560 can be separated from the emitter 510 and the collector 520 respectively via the first sacrificial sidewall structure 2541 and the second sacrificial sidewall structure 2545.

[0141] In other implementations, the step of forming the gate electrode may be performed after the step of forming the collector, the first gate electrode portion 2560 and the second gate electrode portion 2562 may both be used as dummy gates, and the gate electrode and the collector may be made of different conductive materials. Figure 28a and Figure 30a , the gate electrode is formed by performing the following steps: removing the portion of the second electrode material layer (relative to the first sacrificial sidewall structure) located on the same side of the emitter, and the first gate electrode portion 2560. Figure 28a and Figures 31a to 35a Schematic diagram of the structure obtained at different stages in the preparation process of a nano vacuum channel transistor using the first gate electrode portion and the second gate electrode portion as dummy gates. Figure 28a and Figures 30a to 33aThe first gate electrode portion 2560 and the second gate electrode portion 2562 are both used as dummy gates. The steps of forming the gate electrode 560 include the following steps: forming a third electrode material layer at least covering the insulating layer, flattening the third electrode material layer, and making the top surface of the obtained third electrode material layer flush with the top surfaces of the emitter and the collector, thereby forming gate electrodes on both sides of the emitter and the collector.

[0142] Figures 31a to 32a Schematic diagrams of the structures obtained after forming the gate dielectric material layer and the gate dielectric layer respectively. In some cases, before forming the gate electrode, a gate dielectric layer is formed on the exposed surface of the insulating layer, the exposed sidewalls of the first sacrificial spacer structure and the second sacrificial spacer structure, such as Figures 31a to 32a As shown, before the step of forming the gate electrode, the gate dielectric layers 561a and 561b are formed so that the gate electrode 560 is separated from the first sacrificial sidewall structure 2541 and the second sacrificial sidewall structure 2545 by the gate dielectric layers 561a and 561b to reduce gate leakage and ensure gate stability.

[0143] The steps of forming the gate dielectric layers 561a and 561b include: covering the emitter 510 and the collector 520 to form a gate dielectric material layer 5610; performing an anisotropic etching process on the gate dielectric material layer 5610 to retain only the gate dielectric material layer 5610 covering the side walls of the first sacrificial sidewall structure and the second sacrificial sidewall structure; then, performing an anisotropic etching process on the gate dielectric material layer 5610 to form the gate dielectric layers 561a and 561b on the side walls of the first sacrificial sidewall structure and the second sacrificial sidewall structure.

[0144] Next, step S26 is performed to remove the first sacrificial spacer structure and the second sacrificial spacer structure to release the nano-gap between the emitter and the collector.

[0145] See also Figures 29a to 29f, respectively, are schematic diagrams of the resulting structure after the first sacrificial spacer structure and the second sacrificial spacer structure are removed in step S26. As an example, the first sacrificial spacer structure 2541 and the second sacrificial spacer structure 2545 are selectively removed by dry etching or wet etching to release the nanogap 550 between the emitter and the collector, as well as the gap between the gate electrode 560 and the emitter 510 and the collector 520. After removing the first sacrificial spacer structure 2541 and the second sacrificial spacer structure 2545, the resulting gate electrode 560 has gate dielectric layers 561a and 561b formed on the sidewalls facing the emitter and the collector, and the gate dielectric layers 561a and 561b are spaced apart from the sidewalls of the emitter and the collector. In some cases, when the second sacrificial spacer structure 2545 is also formed to cover the portion of the first sacrificial spacer structure that is not surrounded by the first electrode portion and the first gate electrode portion, after removing the first sacrificial spacer structure and the second sacrificial spacer structure, the distance between the gate dielectric layer 561b and the collector 520 is greater than the distance between the gate dielectric layer 561b and the emitter 510, such as Figure 35c and Figure 35e shown.

[0146] Optionally, after step S26 , the obtained nano vacuum channel transistor is packaged.

[0147] In an application scenario with vacuum requirements, the nano vacuum channel transistor is vacuum packaged, and the resulting structure is as follows Figures 36a to 36f 、 Figures 37a to 37f and Figures 38a to 38f The packaging method described in the previous embodiment can be used to package the obtained nano vacuum channel transistor. The obtained structure is shown in the figure and will not be described in detail here.

[0148] Example 3

[0149] The present invention further provides a nano vacuum channel transistor, which is preferably prepared using the method for preparing the nano vacuum channel transistor provided in an embodiment of the present invention. Of course, other preparation methods may also be used.

[0150] The nano vacuum channel transistor of this embodiment is described in detail below. The nano vacuum channel transistor includes at least: a substrate layer, an insulating layer and a gate electrode located on the substrate layer. The insulating layer has a first and second opposing principal surfaces. An emitter electrode and a collector electrode are disposed on the first principal surface of the insulating layer, spaced apart and opposing each other. The ends of the emitter electrode and the collector electrode are configured as pointed tips, and a nanometer-scale gap is defined between the tip of the emitter electrode and the end of the collector electrode to provide a channel region for the emitter to emit electrons to the collector electrode. The gate electrode is disposed on the first or second principal surface of the insulating layer and adjacent to the nano gap, and is used to adjust the operating state of the device.

[0151] In the vacuum channel transistor shown, the emission of vacuum electrons is achieved through field emission in the following manner: when a bias voltage is applied to the gate, the electric field strength between the emission electrode 510 and the collector 520 is changed, thereby regulating the electron concentration in the emission electrode 510 and the potential barrier for electron emission, so that the gate electrode acts as a switch for electron emission, and the current density of the vacuum channel can be regulated by the voltage of the gate electrode.

[0152] The nano vacuum channel transistor is configured as a planar nano channel transistor, and the nano vacuum channel transistor includes a back gate structure or a top gate structure, and the back gate structure or the top gate structure is configured to be parallel to the plane where the emitter and the collector are located.

[0153] In one implementation, the nano vacuum channel transistor includes a back gate structure, as shown in FIG39 to FIG39. Figure 40 As shown, a first insulating layer 120, a back gate electrode 310 and a second insulating layer 140 are stacked on the substrate layer 110 from bottom to top, an emitter 510 and a collector 520 are arranged on the first main surface of the second insulating layer, and a back gate electrode 310 is arranged on the second main surface of the second insulating layer, that is, the back gate electrode 310 is separated from the emitter 510 and the collector 520 by the second insulating layer 140, and the second insulating layer 140 is used as a back gate dielectric layer.

[0154] Furthermore, the geometric shape of the emitter, especially the tip morphology, can be configured to increase the field enhancement factor and reduce the turn-on voltage of the device. Figure 41 and Figure 42aAs shown, the end of the emitter opposite the collector can be configured as a sharp-angled tip. Correspondingly, the end of the collector extending toward the emitter is configured as a concave profile that is substantially complementary to the emitter tip, thereby defining a nanogap between the ends of the emitter and the collector. By making the channel region defined between the emitter and the collector enter the nanometer scale, the nano vacuum channel transistor can achieve high-speed switching of the device at low voltages, even in non-vacuum environments. In this embodiment, the collector 520 is configured as a sidewall extending along the opening direction of the emitter vertex with a substantially constant nanogap. The nanogap defined between the emitter tip and the end of the collector can have a size range of 0.1nm-50nm.

[0155] In other examples, the nano vacuum channel transistor includes a top gate structure, the top gate structure includes a top gate electrode (not shown), the top gate electrode is located on the second main surface of the second insulating layer, and is separated from the emitter and the collector by the second insulating layer, and the second insulating layer serves as a gate dielectric layer.

[0156] In another embodiment, the nano vacuum channel transistor includes a side gate structure, the side gate structure includes a gate electrode, the gate electrode is arranged on both sides of the emitter and the collector, and the working state of the device can be adjusted by applying different bias voltages to the gates on both sides. Figure 41 As shown in FIG42 , the emitter 510, the collector 520, and the gate electrode 560 are all located on the first main surface of the insulating layer 220. Since the gate electrode can be spaced apart from the emitter and the collector at a predetermined distance, the side-gate structure can include only the gate electrode without the need for a gate dielectric layer, thereby improving gate control capability.

[0157] In some examples, the side gate structure further includes gate dielectric layers 561a and 561b, which cover the bottom surface and sidewalls of the gate electrode to reduce gate leakage and ensure gate stability. By reducing the thickness of the gate dielectric layer without increasing leakage current, the transfer characteristics of the vacuum channel transistor are improved. Figures 42a to 42f As shown, the nano vacuum channel transistor includes a side gate structure, and the ends of the emitter and the collector extending toward each other are respectively configured to form sharp-angled tips, and a nano gap is defined between the opposite tips of the emitter and the collector.

[0158] A nanogap 550 is defined between opposite ends of the emitter and the collector, as shown in FIG. 39 to FIG. Figure 40The cross section of the nanogap shown perpendicular to the extension direction is rectangular. In some cases, the nanogap 550 between the opposite ends of the emitter and the collector can have other cross-sectional shapes, such as a parallelogram or an inverted trapezoid, as opposed to a nanogap having a rectangular cross-sectional shape, such as Figure 17 、 Figure 18 、 Figure 37f and Figure 38f The cross-section of the nanogap shown is rectangular when viewed perpendicular to the extension direction. The tip of the emitter has inclined sidewalls to form a needle tip at its bottom. The needle tip-shaped end of the emitter can increase the effective emission area and improve the efficiency of electron emission.

[0159] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A method for preparing a nano vacuum channel transistor, characterized in that: The following steps are involved: Providing an SOI substrate, the SOI substrate comprising a back substrate, an insulating layer and a top functional layer, and performing a first patterning on the top functional layer to form a first electrode portion; forming a first sacrificial spacer structure on a sidewall of the first electrode portion; forming a first electrode material layer covering the first electrode portion and the first sacrificial spacer structure, patterning the first electrode material layer to form a first gate electrode portion, and simultaneously patterning the top functional layer a second time to form an emitter with a tip based on the first electrode portion, wherein the first gate electrode portion has an end portion adjacent to the emitter tip; forming a second sacrificial spacer structure on the sidewall of the emitter electrode with a pointed tip and the sidewall of the first gate electrode portion, intersecting with the first sacrificial spacer structure; A collector is formed from an intersection of the first sacrificial spacer structure and the second sacrificial spacer structure in a direction away from the emitter, the collector being adjacent to the first sacrificial spacer structure and the second sacrificial spacer structure and formed at a diagonal position of the emitter tip, and a second gate electrode portion is formed adjacent to an end of the emitter tip and opposite to the first gate electrode portion; The first sacrificial spacer structure and the second sacrificial spacer structure are removed to release the nanogap between the emitter and the collector.

2. The method for preparing a nano vacuum channel transistor according to claim 1, wherein: After the step of forming the first electrode material layer, the emitter and the first gate electrode portion are formed synchronously through the following steps: the first electrode material layer is flattened, and the top surface of the obtained first electrode material layer is flush with the top surface of the first electrode portion; the first electrode portion and the first electrode material layer are anisotropically etched based on a patterned mask layer, and the patterned mask layer is formed on the first electrode portion and the first electrode material layer in a manner that a side wall is beveled on the two, so that the etched end surfaces of the emitter and the first gate electrode portion are coplanar.

3. The method for preparing a nano vacuum channel transistor according to claim 2, wherein: The step of forming the second sacrificial sidewall structure includes: forming a second sacrificial dielectric material layer covering the exposed surface of the insulating layer; performing an anisotropic etching process on the second sacrificial dielectric material layer to form a second sacrificial sidewall structure on the etched end surfaces of the emitter and the first gate electrode portion, and the second sacrificial sidewall structure intersects with the first sacrificial sidewall structure.

4. The method for preparing a nano vacuum channel transistor according to claim 1, wherein: After the step of forming the second sacrificial sidewall structure, it includes: forming a third electrode material layer covering the insulating layer; flattening the third electrode material layer, forming a collector at the diagonal position of the emitter tip, and forming a second gate electrode portion opposite to the first gate electrode portion.

5. The method for preparing a nano vacuum channel transistor according to claim 1, wherein: After the step of forming the collector, a gate electrode is formed by performing the following steps: removing the first gate electrode portion and the second gate electrode portion; forming a third electrode material layer on the insulating layer; and flattening the third electrode material layer so that the top surface of the third electrode material layer is flush with the top surface of the emitter and the collector, thereby forming gate electrodes on both sides of the emitter and the collector.

6. The method for preparing a nano vacuum channel transistor according to claim 5, wherein: Before forming the gate electrode, the step includes: forming a gate dielectric material layer covering the emitter and the collector; performing an anisotropic etching process on the gate dielectric material layer, and forming the gate dielectric material layer retained on the side walls of the first sacrificial sidewall structure and the second sacrificial sidewall structure into a gate dielectric layer.

7. A nano vacuum channel transistor prepared by the method for preparing a nano vacuum channel transistor according to any one of claims 1 to 6, characterized in that: include: substrate layer; An insulating layer is located on the substrate layer, the insulating layer having a first main surface and a second main surface opposite to each other, an emitter and a collector spaced apart and opposite to each other are provided on the first main surface of the insulating layer, the end of the emitter opposite to the collector is configured to be a pointed tip, and a nanometer gap is defined between the tip of the emitter and the end of the collector to provide a channel region for the emitter to emit electrons to the collector.

8. The nano vacuum channel transistor according to claim 7, wherein: The sidewall of the collector extending toward the emitter is configured with a concave profile substantially complementary to the emitter tip to define a nanogap between opposite sidewalls of the emitter and the collector, wherein the size of the nanogap is in the range of 0.1 nm to 50 nm.

9. The nano vacuum channel transistor according to claim 7, characterized in that: The ends of the emitter and the collector extending toward each other are respectively configured to form sharp-angled tip structures, and a nanogap is defined between the opposite tips of the emitter and the collector, wherein the size of the nanogap ranges from 0.1 nm to 50 nm.

10. The nano vacuum channel transistor according to claim 9, characterized in that: The gate electrode is located on both sides of the emitter and the collector and is spaced apart from the emitter and the collector respectively.

11. The nano vacuum channel transistor according to claim 7, characterized in that: Also includes: A gate dielectric layer is provided on the bottom surface and sidewalls of the gate electrode to reduce leakage current of the gate electrode. The cross section of the nanogap between the emitter and the collector perpendicular to its extension direction is rectangular, parallelogram or inverted trapezoidal.

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