Method for compensating threshold voltage

Abstract

The invention provides a method for compensating threshold voltage, which comprises the following steps of: providing a semiconductor structure which comprises a substrate, a work function layer formed on the substrate, a dummy gate formed on the surface of the work function layer and an interlayer dielectric layer formed on the substrate on the side wall of the dummy gate; removing the dummy gate to form a gate opening and performing wet cleaning, the bottom of the gate opening being a work function layer; a filling layer is formed in the gate opening, the filling layer extends to the surface of the interlayer dielectric layer, and the material of the filling layer is the same as that of the work function layer; and etching back the filling layer by using etching gas with a high selection ratio for the filling layer and the interlayer dielectric layer so as to retain partial thickness of the filling layer at the bottom of the gate opening to realize compensation for the work function layer. According to the invention, the problem that the threshold voltage deviates due to the damage of the surface of the work function layer in the prior art is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a method for compensating threshold voltage. Background Art

[0002] With the development of integrated circuit technology, we have higher and higher requirements for device performance. The improvement of device performance mainly comes from the miniaturization of gate oxide thickness and gate length. However, the limitations of traditional polysilicon gates are gradually manifested, such as increased leakage, increased power consumption, poor reliability, gate depletion, poor conductivity, etc. The emergence of HKMG (high-K metal gate) process can solve the limitations of traditional polysilicon gates and further shrink the equivalent gate oxide thickness (EOT).

[0003] Threshold voltage (Vt) is one of the important indicators of integrated circuit device performance. It determines the device startup speed, gate leakage and power consumption. In the process of metal gate formation, the work function metal TiN has an important influence on the threshold voltage. However, the pseudo gate removal process and wet cleaning process will cause damage to the work function metal TiN surface (such as Figure 1 As shown in the figure, the threshold voltage is shifted and the stability of device performance is affected. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a method for compensating a threshold voltage, so as to solve the problem of threshold voltage shift caused by damage to the surface of the work function layer.

[0005] To achieve the above object and other related objects, the present invention provides a method for compensating a threshold voltage, the method comprising:

[0006] A semiconductor structure is provided, comprising a substrate, a work function layer formed on the substrate, a dummy gate formed on a surface of the work function layer, and an interlayer dielectric layer formed on the substrate at a sidewall of the dummy gate;

[0007] removing the dummy gate to form a gate opening and performing wet cleaning, wherein the bottom of the gate opening is the work function layer;

[0008] forming a filling layer in the gate opening, wherein the filling layer extends to the surface of the interlayer dielectric layer, wherein the material of the filling layer is the same as that of the work function layer;

[0009] The filling layer is etched back by using an etching gas having a high selectivity ratio between the filling layer and the interlayer dielectric layer to reserve a partial thickness of the filling layer at the bottom of the gate opening to achieve compensation for the work function layer.

[0010] Optionally, the material of the work function layer includes TiN.

[0011] Optionally, the material of the dummy gate includes polysilicon.

[0012] Optionally, the filling layer is formed by an atomic layer deposition process.

[0013] Optionally, the filling layer is etched back using Cl 2 and CH 4 .

[0014] Optionally, the semiconductor structure further includes a gate oxide layer formed on a surface of the substrate. In this case, the work function layer is formed on a surface of the gate oxide layer.

[0015] Optionally, the semiconductor structure further includes a first well region, a first source / drain doped region formed in the first well region, a source / drain silicide layer formed on a surface of the first source / drain doped region, a second well region, and a second source / drain doped region formed in the second well region.

[0016] Optionally, the first well region is an N-well, and the first well region is a P-well.

[0017] Optionally, the semiconductor structure further includes a sidewall spacer formed on a sidewall of the dummy gate.

[0018] Optionally, the semiconductor structure further includes an etch stop layer, wherein the etch stop layer is formed on the sidewalls of the spacer and between the interlayer dielectric layer and the substrate.

[0019] Optionally, the semiconductor structure further includes a shallow trench isolation structure.

[0020] As described above, the method for compensating the threshold voltage of the present invention, after removing the dummy gate and performing wet cleaning, uses a deposition process to form a filling layer (TiN layer) to compensate the work function layer (TiN layer), thereby solving the threshold voltage offset problem caused by damage to the surface of the work function layer, making the device performance more stable. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 The schematic diagram shows a cross-sectional structure of a conventional semiconductor structure in which a SiN layer is damaged.

[0022] Figure 2 to Figure 5 The cross-sectional structure diagram of the semiconductor structure is shown in the process of compensating the threshold voltage of the present invention.

[0023] Figure 6 Shown is a flow chart of a method for compensating threshold voltage of the present invention.

[0024] Description of Figure Numbers

[0025] 100: semiconductor structure; 110: substrate; 120: work function layer; 130: pseudo gate; 140: interlayer dielectric layer; 150: gate oxide layer; 161: first well region; 162: second well region; 171: first source and drain doping region; 172: second source and drain doping region; 180: source and drain silicide layer; 190: sidewall; 200: etch stop layer; 300: shallow trench isolation structure; 400: gate opening; 500: filling layer DETAILED DESCRIPTION

[0026] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0027] See also Figures 1 to 6 It should be noted that the illustrations provided in this embodiment are only schematic illustrations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation, the form, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout may also be more complicated.

[0028] like Figure 6 As shown, this embodiment provides a method for compensating a threshold voltage, the method comprising:

[0029] A semiconductor structure 100 is provided, which includes a substrate 110, a work function layer 120 formed on the substrate 110, a dummy gate 130 formed on the surface of the work function layer 120, and an interlayer dielectric layer 140 formed on the substrate 110 and on the sidewall of the dummy gate 130;

[0030] The dummy gate 130 is removed to form a gate opening 400 and wet cleaned, wherein the bottom of the gate opening 400 is the work function layer 120;

[0031] A filling layer 500 is formed in the gate opening 400 , and the filling layer 500 extends to the surface of the interlayer dielectric layer 140 , wherein the material of the filling layer 500 is the same as that of the work function layer 120 ;

[0032] The filling layer 500 is etched back using an etching gas having a high selectivity between the filling layer 500 and the interlayer dielectric layer 140 to retain a partial thickness of the filling layer 500 at the bottom of the gate opening 400 to compensate the work function layer 120 .

[0033] Specifically, the semiconductor structure 100 further includes a gate oxide layer 150 formed on the surface of the substrate 110 . At this time, the work function layer 120 is formed on the surface of the gate oxide layer 150 .

[0034] Specifically, the semiconductor structure 100 also includes a first well region 161, a first source-drain doped region 171 formed in the first well region 161, a source-drain silicide layer 180 formed on the surface of the first source-drain doped region 171, a second well region 162, and a second source-drain doped region 172 formed in the second well region 162.

[0035] More specifically, the first well region 161 is an N-well, and the first well region 162 is a P-well.

[0036] Specifically, the semiconductor structure 100 further includes a spacer 190 formed on a sidewall of the dummy gate 130 .

[0037] More specifically, the semiconductor structure 100 further includes an etch stop layer 200 . The etch stop layer 200 is formed on the sidewalls of the spacer 190 and between the interlayer dielectric layer 140 and the substrate 110 .

[0038] Specifically, the semiconductor structure 100 further includes a shallow trench isolation structure 300 .

[0039] Specifically, the material of the work function layer 120 includes TiN.

[0040] Specifically, the material of the dummy gate 130 includes polysilicon.

[0041] Specifically, the filling layer 500 is formed by an atomic layer deposition process.

[0042] Specifically, the filling layer 500 is etched back using Cl 2 and CH 4 .

[0043] In summary, the method for compensating the threshold voltage of the present invention, after removing the dummy gate and performing wet cleaning, uses a deposition process to form a filling layer (TiN layer) to compensate the work function layer (TiN layer), thereby solving the threshold voltage offset problem caused by damage to the surface of the work function metal layer TiN, making the device performance more stable. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0044] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for compensating a threshold voltage, characterized in that: The method comprises: A semiconductor structure is provided, comprising a substrate, a work function layer formed on the substrate, a dummy gate formed on a surface of the work function layer, and an interlayer dielectric layer formed on the substrate at a sidewall of the dummy gate; removing the dummy gate to form a gate opening and performing wet cleaning, wherein the bottom of the gate opening is the work function layer; forming a filling layer in the gate opening, wherein the filling layer extends to the surface of the interlayer dielectric layer, wherein the material of the filling layer is the same as that of the work function layer; The filling layer is etched back by using an etching gas having a high selectivity ratio between the filling layer and the interlayer dielectric layer to retain a partial thickness of the filling layer at the bottom of the gate opening to achieve compensation for the work function layer.

2. The method for compensating threshold voltage according to claim 1, characterized in that: The material of the work function layer includes TiN.

3. The method for compensating threshold voltage according to claim 1, characterized in that: The material of the dummy gate includes polysilicon.

4. The method for compensating threshold voltage according to claim 1, characterized in that: The filling layer is formed by an atomic layer deposition process.

5. The method for compensating threshold voltage according to claim 1, characterized in that: The filling layer is etched back using Cl2 and CH4.

6. The method for compensating threshold voltage according to claim 1, characterized in that: The semiconductor structure further includes a gate oxide layer formed on the surface of the substrate. At this time, the work function layer is formed on the surface of the gate oxide layer.

7. The method for compensating threshold voltage according to claim 1, characterized in that: The semiconductor structure also includes a first well region, a first source-drain doped region formed in the first well region, a source-drain silicide layer formed on the surface of the first source-drain doped region, a second well region, and a second source-drain doped region formed in the second well region.

8. The method for compensating threshold voltage according to claim 7, characterized in that: The first well region is an N-well, and the second well region is a P-well.

9. The method for compensating threshold voltage according to claim 1, characterized in that: The semiconductor structure further includes a sidewall spacer formed on a sidewall of the dummy gate.

10. The method for compensating threshold voltage according to claim 9, characterized in that: The semiconductor structure further includes an etch stop layer, which is formed on the sidewalls of the spacer and between the interlayer dielectric layer and the substrate.

11. The method for compensating threshold voltage according to claim 1, characterized in that: The semiconductor structure also includes a shallow trench isolation structure.

Images