Test structure of metal silicide block resistor and preparation method thereof

Abstract

The present invention provides a test structure of metal silicide block resistor and a preparation method thereof. Before performing a second ion implantation required for preparing a corresponding structure of a MOS device, a first ion implantation of the opposite ion doping type and low-temperature annealing are performed to repair the lattice damage caused by the first ion implantation and to exhaust the doping ions of the second ion implantation as much as possible, so that the silicon material in the test structure approaches the conductive characteristics of intrinsic silicon. When the metal silicide block resistor on the corresponding structure of the MOS device is measured, the measured block resistance result is only the block resistance of the metal silicide on the corresponding structure of the MOS device, thereby accurately monitoring the key process parameters such as the thickness process parameter of the metal silicide and the size of the corresponding structure of the MOS device and the uniformity of these parameters on the wafer; in addition, low-temperature annealing repairs the damage of the silicon lattice without adding additional thermal budget and affecting the electrical performance of the device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a test structure of a metal silicide block resistor and a preparation method thereof. Background Art

[0002] As the semiconductor process feature size shrinks to below deep submicron, the size of the gate, source and drain active areas of the MOS tube also shrinks accordingly, and their equivalent series resistance will increase accordingly, thus affecting the circuit speed. In addition, the size of the back-end interconnection contact hole continues to shrink. As the contact hole size continues to shrink, the contact resistance of a single contact hole continues to increase. In order to reduce the square resistance of the polysilicon gate and active area, the metal silicide process technology has been developed and widely used in semiconductor process technology. This technology uses metal to react with silicon in the active area and polysilicon gate in direct contact to form silicide. The metal will not react with dielectric materials such as silicon oxide, silicon nitride and silicon oxynitride in contact, so silicide can be well aligned with the active area and polysilicon gate. Therefore, the technology of forming silicide on the active area and polysilicon gate at the same time is also called self-aligned metal silicide (Self Aligned Silicide-Salicide).

[0003] Therefore, the square resistance of metal silicide is an important parameter in the manufacturing process of MOS devices. It can monitor the thickness process parameters of metal silicide. In addition, based on the self-aligned formation technology of metal silicide, the size of metal silicide is consistent with the size of the polysilicon gate and / or the single-crystal silicon active area below it, so it can also be used to monitor key process parameters such as the size of the polysilicon gate and / or the single-crystal silicon active area. These parameters are crucial to ensure the performance of MOS devices.

[0004] However, in the current measurement of the metal silicide block resistance on the active area and polysilicon gate of MOS devices, it is found that the wafer-map of the metal silicide block resistance on different wafers is inconsistent, especially for the different doping types of silicon (i.e., N-type and P-type), the wafer-map inconsistency of the metal silicide block resistance is more obvious, and even shows an opposite trend. Figure 1 The figure in the figure is the wafer-map of the sheet resistance of metal silicide on N-type polysilicon. Figure 2 The figure below shows the wafer-map of the sheet resistance of metal silicide on P-type polysilicon. The redder the color, the larger the sheet resistance. The sheet resistance gradually decreases as it transitions to green. The greener the color, the smaller the sheet resistance. Figure 1 The square resistance in the wafer shows a distribution phenomenon that the square resistance is high in the center of the wafer and low in the surrounding areas. Figure 2The square resistance in the wafer shows a distribution phenomenon that the square resistance is low in the center of the wafer and high in the periphery. This will make it impossible to accurately determine the square resistance of the metal silicide on the entire wafer, and thus it is impossible to accurately monitor the key process parameters such as the thickness process parameters of the metal silicide and the size of the polysilicon gate and / or silicon active area, as well as the uniformity of these parameters on the wafer. Summary of the invention

[0005] In view of the shortcomings of the prior art described above, the object of the present invention is to provide a test structure of a metal silicide block resistor and a preparation method thereof, so as to solve the problem that the prior art cannot accurately determine the metal silicide block resistor on the active area of ​​the MOS device and / or the polysilicon gate on the entire wafer, resulting in the inability to accurately monitor key process parameters such as the thickness process parameters of the metal silicide and the size of the polysilicon gate and / or the silicon active area, as well as the uniformity of these parameters on the wafer.

[0006] To achieve the above-mentioned object and other related objects, the present invention provides a method for preparing a first metal silicide block resistor test structure, the preparation method comprising the following steps:

[0007] Providing a silicon wafer, and forming a polysilicon gate of a MOS tube on a surface of the silicon wafer;

[0008] Performing a first ion implantation on the polysilicon gate and performing low temperature annealing;

[0009] Performing a second ion implantation on the polysilicon gate; wherein the ion doping type of the first ion implantation is opposite to the ion doping type of the second ion implantation, the ion implantation parameters of the second ion implantation are the same as the ion implantation parameters of the MOS tube source region and the drain region, and the ion implantation dose of the first ion implantation is 0.3 to 3 times the ion implantation dose of the second ion implantation;

[0010] Performing rapid thermal annealing on the silicon wafer;

[0011] Metal silicide is formed on the surface of the polysilicon gate.

[0012] Optionally, the ion doping type of the first ion implantation is N-type ions or P-type ions, and the ion doping type of the second ion implantation is N-type ions or P-type ions.

[0013] Optionally, the method for performing the first ion implantation on the polysilicon gate comprises the following steps:

[0014] Forming a first patterned photoresist layer on the surface of the silicon wafer, wherein the first patterned photoresist layer exposes the surface of the polysilicon gate;

[0015] Performing the first ion implantation on the polysilicon gate based on the first patterned photoresist layer;

[0016] removing the first patterned photoresist layer;

[0017] The method for performing the second ion implantation on the polysilicon gate comprises the following steps:

[0018] forming a second patterned photoresist layer on the surface of the silicon wafer, wherein the second patterned photoresist layer exposes the surface of the polysilicon gate;

[0019] Performing the second ion implantation on the polysilicon gate based on the second patterned photoresist layer;

[0020] The second patterned photoresist layer is removed.

[0021] Optionally, ion implantation parameters of the first ion implantation are the same as ion implantation parameters of the second ion implantation.

[0022] The present invention also provides a test structure for a metal silicide block resistor, which is prepared by using the method for preparing the first test structure for a metal silicide block resistor as described in any one of the above items.

[0023] The present invention also provides a method for preparing a second metal silicide block resistor test structure, the method comprising the following steps:

[0024] Providing a silicon wafer, and forming a shallow trench isolation structure in the silicon wafer, defining a silicon active region between adjacent shallow trench isolation structures, and the size of the silicon active region is the same as the size of the source region or the drain region of the MOS tube;

[0025] Performing a first ion implantation on the silicon active region and performing low temperature annealing;

[0026] Performing a second ion implantation on the silicon active area; wherein the ion doping type of the first ion implantation is opposite to the ion doping type of the second ion implantation, the ion implantation parameters of the second ion implantation are the same as the ion implantation parameters of the MOS tube source region and the drain region, and the ion implantation dose of the first ion implantation is 0.3 to 3 times the ion implantation dose of the second ion implantation;

[0027] Performing rapid thermal annealing on the silicon wafer;

[0028] A metal silicide is formed on the surface of the silicon active region.

[0029] Optionally, the ion doping type of the first ion implantation is N-type ions or P-type ions, and the ion doping type of the second ion implantation is N-type ions or P-type ions.

[0030] Optionally, the method for performing the first ion implantation on the silicon active area comprises the following steps:

[0031] Forming a first patterned photoresist layer on the surface of the silicon wafer, wherein the first patterned photoresist layer exposes the surface of the silicon active area;

[0032] Performing the first ion implantation on the silicon active area based on the first patterned photoresist layer;

[0033] removing the first patterned photoresist layer;

[0034] The method for performing the second ion implantation on the silicon active area comprises the following steps:

[0035] Forming a second patterned photoresist layer on the surface of the silicon wafer, wherein the second patterned photoresist layer exposes the surface of the silicon active area;

[0036] Performing the second ion implantation on the silicon active area based on the second patterned photoresist layer;

[0037] The second patterned photoresist layer is removed.

[0038] Optionally, ion implantation parameters of the first ion implantation are the same as ion implantation parameters of the second ion implantation.

[0039] The present invention also provides a test structure for a metal silicide block resistor, which is prepared by using the method for preparing the second test structure for a metal silicide block resistor as described in any one of the above items.

[0040] As described above, the test structure of the metal silicide block resistor of the present invention and the preparation method thereof, before the second ion implantation required for the preparation of the corresponding structure of the MOS device, the first ion implantation of the ion doping type opposite to the second ion implantation and low-temperature annealing are performed on the corresponding structure on the test structure to repair the lattice damage caused by the first ion implantation and to exhaust the doping ions of the second ion implantation as much as possible, so that the silicon material in the test structure approaches the conductive properties of intrinsic silicon, that is, high-resistance properties, so that when the metal silicide block resistor on the corresponding structure of the MOS device is measured, the parallel path of the silicon material resistance exhibits high resistance, and the measured block resistance result is only the block resistance of the metal silicide on the corresponding structure of the MOS device, avoiding the influence of the silicon material resistance on the instability of the entire measurement result, thereby obtaining the real metal silicide block resistance, and then accurately monitoring the thickness process parameters of the metal silicide and the key process parameters such as the size of the corresponding structure of the MOS device and the uniformity of these parameters on the wafer; in addition, low-temperature annealing repairs the damage of the silicon lattice without adding additional thermal budget and will not affect the electrical performance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 A wafer-map diagram showing a sheet resistance of metal silicide on N-type polysilicon according to an example of the prior art is shown.

[0042] Figure 2 A wafer-map diagram showing a sheet resistance of metal silicide on P-type polysilicon according to an example of the prior art is shown.

[0043] Figure 3 Shown is a schematic diagram of the cross-sectional structure of metal silicide on a silicon-doped layer.

[0044] Figure 4 Display as Figure 3 Equivalent circuit diagram of metal silicide on a silicon-doped layer during sheet resistance measurement.

[0045] Figures 5 to 12 It is a schematic diagram of the cross-sectional structure of each step in the preparation process of the test structure of the metal silicide block resistor according to the first embodiment of the present invention.

[0046] Figures 13 to 20 It is a schematic diagram of the cross-sectional structure of each step in the preparation process of the test structure of the metal silicide block resistor according to the second embodiment of the present invention.

[0047] Component number description

[0048] 10 silicon wafer, 11 polysilicon gate, 110 gate dielectric layer, 111 gate polysilicon layer, 112 sidewall, 12 first photoresist layer, 120 first patterned photoresist layer, 13 second photoresist layer, 130 second patterned photoresist layer, 14 metal silicide, 15 shallow trench isolation structure, 16 silicon active area, 17 doped layer, 18 silicon doped layer, 19 metal silicide resistor, 20 silicon doped layer resistor. DETAILED DESCRIPTION

[0049] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0050] See also Figures 3 to 20 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0051] As described in the background technology, it is currently found in the measurement of the metal silicide block resistance on the active area and polysilicon gate of the MOS device that there is inconsistency in the wafer map (wafer-map) of the metal silicide block resistance on different wafers, especially for the different doping types of silicon (i.e., N-type and P-type), the inconsistency of the wafer-map of the metal silicide block resistance corresponding to the wafer is more obvious, and even shows an opposite trend. Based on this phenomenon, the inventor conducted an in-depth study. In the actual process of manufacturing MOS tubes, a gate-first process is generally used, that is, the gate is prepared first, and then the self-aligned source and drain are heavily doped based on the gate. In order to avoid the inaccuracy of the overlay precision, this process will also produce corresponding heavy doping on the polysilicon gate. Therefore, when the block resistance of the metal silicide formed on the source, drain and gate is measured subsequently, the actual physical structure of the block resistance measurement is as follows Figure 3 As shown, it includes both the metal silicide 14 located on the upper layer and the silicon doped layer 18 thereunder. Its equivalent circuit diagram is shown in Figure 4 As shown in the figure, the actual metal silicide block resistance is composed of two parts of resistance in parallel: one is the metal silicide resistance 19 itself, and the other is the silicon doping layer resistance 20 after ion implantation. Therefore, the resistance value of the silicon doping layer resistance 20 will affect the measurement result of the actual metal silicide block resistance. Based on this, the inventors further studied that when silicon is intrinsic silicon and not doped, it is similar to an insulator, so Figure 4 The current path of the silicon doped layer resistor 20 is disconnected, and the actual metal silicide block resistor is only composed of the metal silicide resistor 19. When silicon is doped, the silicon doped layer resistor 20 is greatly reduced. Figure 4 The current path of the silicon doped layer resistor 20 is turned on, and the actual metal silicide block resistor is composed of the metal silicide resistor 19 and the silicon doped layer resistor 20 in parallel. The resistance of the silicon doped layer resistor 20 is mainly determined by the activated doped ions therein, and the activation efficiency of the doped ions is controlled by many factors, mainly including: the ion implantation process itself has regional non-uniformity. In addition, during the annealing activation process, the annealing itself also has regional non-uniformity, which leads to uneven distribution of activated doped ions, and then leads to regional non-uniformity of the silicon doped layer resistor 20; on this basis, for N-type doped ions and P-type doped ions, the reaction to heat during the annealing activation process is also different. Combined with the non-uniformity of the annealing temperature itself, the wafer-map inconsistency of the metal silicide block resistors corresponding to different doping types is more obvious; another reason is that different test structures are set at different positions on the wafer, and the density of the patterns around different positions is inconsistent, resulting in inconsistent heat absorption during the annealing activation process, causing uneven distribution of activated doped ions.

[0052] Based on the above analysis, two test structures are proposed in this embodiment, in order to accurately monitor the metal silicide block resistance on the active area and polysilicon gate of the MOS device when measuring it, reduce or even avoid the influence of the silicon doping layer on the block resistance result, and thus obtain the distribution of the real metal silicide block resistance on the entire wafer. Embodiment 1

[0053] This embodiment provides a method for preparing a test structure of a metal silicide block resistance. The test structure prepared by the preparation method can realize accurate monitoring of the metal silicide block resistance on the polysilicon gate of a MOS tube. The preparation method comprises the following steps:

[0054] S1, providing a silicon wafer, and forming a polysilicon gate of a MOS tube on a surface of the silicon wafer;

[0055] S2, performing a first ion implantation on the polysilicon gate and performing low temperature annealing to repair polysilicon lattice damage caused by the first ion implantation;

[0056] S3, performing a second ion implantation on the polysilicon gate; wherein the ion doping type of the first ion implantation is opposite to the ion doping type of the second ion implantation, the ion implantation parameters of the second ion implantation are the same as the ion implantation parameters of the MOS tube source region and the drain region, and the ion implantation dose of the first ion implantation is 0.3 to 3 times the ion implantation dose of the second ion implantation; the ion implantation parameters of the second ion implantation are set to be the same as the ion implantation parameters of the MOS tube source region and the drain region in order to achieve the test of the metal silicide block resistance on the corresponding MOS tube gate;

[0057] S4, performing rapid thermal annealing on the silicon wafer;

[0058] S5, forming metal silicide on the surface of the polysilicon gate.

[0059] The preparation method of the metal silicide block resistance test structure of the present embodiment is to perform a first ion implantation of the ion doping type opposite to the second ion implantation on the polysilicon gate on the test structure and perform low temperature annealing before performing a second ion implantation required for preparing the source region and drain region of the MOS device on the polysilicon gate, so as to repair the damage of the polysilicon lattice and deplete the doping ions of the second ion implantation as much as possible, so that the polysilicon in the polysilicon gate approaches the conductive property of intrinsic silicon, that is, the high resistance property, so as to test the metal silicide block resistance on the polysilicon gate. When measuring, the parallel path of the polysilicon resistors in the polysilicon gate appears as high resistance, and the measured block resistance result is only the block resistance of the metal silicide on the polysilicon gate, avoiding the instability of the polysilicon gate resistance on the entire measurement result, thereby obtaining the true metal silicide block resistance, and then accurately monitoring the key process parameters such as the thickness process parameters of the metal silicide and the size of the polysilicon gate and the uniformity of these parameters on the wafer; in addition, low-temperature annealing repairs the damage of the polysilicon lattice without adding additional thermal budget and will not affect the electrical performance of the device.

[0060] The method for preparing the test structure of the metal silicide block resistor of this embodiment is described in detail below with reference to the specific drawings.

[0061] like Figure 5 As shown, step S1 is first performed to provide a silicon wafer 10 and form a polysilicon gate 11 of a MOS tube on the surface of the silicon wafer 10 .

[0062] As an example, the silicon wafer 10 may be single crystal silicon, polycrystalline silicon, amorphous silicon, or silicon on insulator (SOI).

[0063] The polysilicon gate 11 includes a gate dielectric layer 110, a gate polysilicon layer 111, and a sidewall 112 formed on the sidewalls of the gate dielectric layer 110 and the gate polysilicon layer 111. The size parameters of the polysilicon gate 11 are set according to the actual requirements of the MOS tube device and are selected according to actual needs.

[0064] It should be noted that other devices and / or test structures may also be formed on the silicon wafer 10. For ease of understanding, the drawings of this embodiment only show structures related to the present invention.

[0065] like Figure 7 As shown, step S2 is then performed to perform a first ion implantation on the polysilicon gate 11 and perform low temperature annealing.

[0066] The purpose of the first ion implantation is to exhaust the doping ions of the subsequent second ion implantation as much as possible, so that the gate polysilicon layer 111 in the polysilicon gate 11 after the subsequent second ion implantation tends to be an intrinsic semiconductor material after rapid annealing, so that the gate polysilicon layer 111 tends to be in a high resistance state. Since the activated doping ions determine the conductivity of the semiconductor, the ion implantation dose of the first ion implantation is selected to be 0.3 to 3 times the ion implantation dose of the subsequent second ion implantation. Within this dose range, the doping ions of the first ion implantation can produce a significant depletion effect on the doping ions of the second ion implantation after being activated.

[0067] As a preferred example, the parameters of the first ion implantation, such as ion implantation dose, ion implantation energy and ion implantation angle, are kept consistent with the parameters of the subsequent second ion implantation.

[0068] After the first ion implantation, low temperature annealing of the polysilicon gate 11 can repair the polysilicon lattice damage caused by the first ion implantation. Generally, the temperature of the low temperature annealing is not greater than 500° C. The low temperature annealing can be performed by, for example, RTP (rapid thermal process).

[0069] The ion doping type of the first ion implantation can be N-type or P-type, as long as it is opposite to the ion doping type of the subsequent second ion implantation. Generally, the N-type doping ions are selected as phosphorus ions, but it is not limited to this, and other N-type ions are also possible; the P-type doping ions are selected as boron ions, but it is not limited to this, and other P-type ions are also possible.

[0070] As a specific example, the method for performing the first ion implantation on the polysilicon gate 11 includes the following steps:

[0071] like Figure 6As shown, a first photoresist layer 12 is first formed on the surface of the silicon wafer 10; Figure 7 As shown, the first photoresist layer 12 is then patterned to form a first patterned photoresist layer 120, wherein the first patterned photoresist layer 120 exposes the surface of the polysilicon gate 11, and mainly exposes the surface of the gate polysilicon layer 111 in the polysilicon gate 11; then, based on the first patterned photoresist layer 120, the first ion implantation is performed on the polysilicon gate 11 to convert the gate polysilicon layer 111 into a doped gate polysilicon layer; Figure 8 As shown, the first patterned photoresist layer 120 is finally removed.

[0072] like Fig.10 As shown, step S3 is then performed to perform a second ion implantation on the polysilicon gate 11; wherein the ion doping type of the first ion implantation is opposite to the ion doping type of the second ion implantation, the ion implantation parameters of the second ion implantation are the same as the ion implantation parameters of the MOS tube source region and the drain region, and the ion implantation dose of the first ion implantation is 0.3 to 3 times the ion implantation dose of the second ion implantation.

[0073] The purpose of this ion implantation is to simultaneously form the source region and the drain region of the MOS tube, so the parameters of the ion implantation are set according to the doping requirements of the actual source region and the drain region of the MOS tube.

[0074] As a specific example, the method for performing the second ion implantation on the polysilicon gate 11 includes the following steps:

[0075] like Fig. 9 As shown, a second photoresist layer 13 is first formed on the surface of the silicon wafer 10; Fig.10 As shown, the second photoresist layer 13 is then patterned to form a second patterned photoresist layer 130, wherein the second patterned photoresist layer 130 exposes the surface of the polysilicon gate 11, and mainly exposes the surface of the gate polysilicon layer 111 in the polysilicon gate 11; then, based on the second patterned photoresist layer 130, the polysilicon gate 11 is subjected to the second ion implantation to transform the gate polysilicon layer 111 into a second doped gate polysilicon layer; Fig.11 As shown, the second patterned photoresist layer 130 is finally removed.

[0076] The ion doping type of the second ion implantation can be either N-type or P-type, as long as it is opposite to the ion doping type of the first ion implantation. Generally, the N-type doping ions are selected as phosphorus ions, but not limited thereto, and other N-type ions are also acceptable; the P-type doping ions are selected as boron ions, but not limited thereto, and other P-type ions are also acceptable.

[0077] like Fig.11 As shown, step S4 is then performed to perform rapid thermal annealing on the silicon wafer 10 so that the two different doping types of ions injected twice into the polysilicon gate 11 are activated, and the electrons and holes are neutralized after activation.

[0078] As an example, the rapid thermal annealing may be performed by spike annealing or laser annealing, etc. For example, when spike annealing is performed, the peak annealing temperature is selected to be 1050°C to 1080°C, and the heating step frequency may be selected to be 80°C, 180°C, or 220°C, etc.

[0079] like Fig.12 As shown, step S5 is finally performed to form a metal silicide 14 on the surface of the polysilicon gate 11, and finally the desired test structure is obtained.

[0080] The Salicide process technology used in this step to form the metal silicide 14 includes: firstly, using the physical vapor deposition process (PVD) to deposit a metal layer, such as Ti, Co, NiPt, etc., on the polysilicon gate; then performing two rapid thermal annealing processes to form the metal silicide 14, such as TiSi2, CoSi2, NiPtSi. This process uses the fact that metal will not react with dielectric materials to form metal silicide, but will only react with silicon materials in direct contact to form metal silicide.

[0081] The present embodiment also provides a test structure for metal silicide block resistance, which is prepared by the preparation method of the test structure for metal silicide block resistance of the present embodiment, and can realize accurate monitoring of the metal silicide block resistance on the polysilicon gate of the MOS tube. Embodiment 2

[0082] This embodiment provides a method for preparing a test structure of a metal silicide block resistor. The test structure prepared by the preparation method can realize accurate monitoring of the metal silicide block resistor on the source region and / or drain region of a MOS tube. The preparation method comprises the following steps:

[0083] S1, providing a silicon wafer, and forming a shallow trench isolation structure in the silicon wafer, defining a silicon active region between adjacent shallow trench isolation structures, and the size of the silicon active region is the same as the size of the source region or the drain region of the MOS tube;

[0084] S2, performing a first ion implantation on the silicon active region and performing low temperature annealing;

[0085] S3, performing a second ion implantation on the silicon active area; wherein the ion doping type of the first ion implantation is opposite to the ion doping type of the second ion implantation, the ion implantation parameters of the second ion implantation are the same as the ion implantation parameters of the MOS tube source region and the drain region, and the ion implantation dose of the first ion implantation is 0.3 to 3 times the ion implantation dose of the second ion implantation; the ion implantation parameters of the second ion implantation are set to be the same as the ion implantation parameters of the MOS tube source region and the drain region in order to achieve the test of the metal silicide block resistance on the corresponding MOS tube source region and the drain region;

[0086] S4, performing rapid thermal annealing on the silicon wafer;

[0087] S5, forming metal silicide on the surface of the silicon active area.

[0088] The preparation method of the metal silicide block resistor test structure of the present embodiment is to perform a first ion implantation of the ion doping type opposite to the second ion implantation and perform low temperature annealing on the silicon active region on the test structure before performing a second ion implantation required for preparing the source region and drain region of the MOS device on the silicon active region, so as to repair the damage of the silicon active region lattice and deplete the doping ions of the second ion implantation as much as possible, so that the silicon material in the silicon active region approaches the conductive property of intrinsic silicon, that is, the high resistance property, so as to improve the metal silicide block resistor on the silicon active region. When measuring, the parallel path of the silicon active area resistance shows high resistance, and the measured block resistance result is only the block resistance of the metal silicide on the silicon active area, avoiding the instability of the silicon active area resistance on the entire measurement result, thereby obtaining the true metal silicide block resistance, and then accurately monitoring the thickness process parameters of the metal silicide and the key process parameters such as the size of the source area and / or drain area and the uniformity of these parameters on the wafer; in addition, low-temperature annealing repairs the damage to the silicon active area lattice without adding additional thermal budget and will not affect the electrical performance of the device.

[0089] The method for preparing the test structure of the metal silicide block resistor of this embodiment is described in detail below with reference to the specific drawings.

[0090] like Fig.13 As shown, step S1 is first performed to provide a silicon wafer 10 and form a shallow trench isolation structure 15 in the silicon wafer 10, and a silicon active area 16 is defined between adjacent shallow trench isolation structures 15, and the size of the silicon active area 16 is the same as the size of the source area or drain area of ​​the MOS tube.

[0091] As an example, the silicon wafer 10 may be single crystal silicon, polycrystalline silicon, amorphous silicon, or silicon on insulator (SOI).

[0092] As an example, the shallow trench isolation structure 15 is prepared by a conventional process, for example, first etching a trench and then filling the trench with an insulating material to obtain the shallow trench isolation structure 15 .

[0093] It should be noted that other devices and / or test structures may also be formed on the silicon wafer 10. For ease of understanding, the drawings of this embodiment only show structures related to the present invention.

[0094] like Fig.15 As shown, step S2 is then performed to perform a first ion implantation on the silicon active region 16 and perform low temperature annealing.

[0095] The purpose of the first ion implantation is to deplete the doping ions of the subsequent second ion implantation as much as possible, so that the silicon active region 16 after the subsequent second ion implantation tends to be an intrinsic semiconductor material after rapid annealing, so that the silicon active region 16 tends to be in a high resistance state. Since the activated doping ions determine the conductivity of the semiconductor, the ion implantation dose of the first ion implantation is selected to be 0.3 to 3 times the ion implantation dose of the subsequent second ion implantation. Within this dose range, the doping ions of the first ion implantation can produce a significant depletion effect on the doping ions of the second ion implantation after being activated.

[0096] As a preferred example, the parameters of the first ion implantation, such as ion implantation dose, ion implantation energy and ion implantation angle, are kept consistent with the parameters of the subsequent second ion implantation.

[0097] After the first ion implantation, low temperature annealing of the silicon active region 16 can repair the lattice damage of the silicon active region 16 caused by the first ion implantation. Generally, the temperature of the low temperature annealing is not greater than 500° C. The low temperature annealing can be performed by, for example, RTP (rapid thermal process).

[0098] The ion doping type of the first ion implantation can be N-type or P-type, as long as it is opposite to the ion doping type of the subsequent second ion implantation. Generally, the N-type doping ions are selected as phosphorus ions, but it is not limited to this, and other N-type ions are also possible; the P-type doping ions are selected as boron ions, but it is not limited to this, and other P-type ions are also possible.

[0099] As a specific example, the method for performing the first ion implantation on the silicon active area 16 includes the following steps:

[0100] like Fig.14 As shown, a first photoresist layer 12 is first formed on the surface of the silicon wafer 10; Fig.15As shown, the first photoresist layer 12 is then patterned to form a first patterned photoresist layer 120, wherein the first patterned photoresist layer 120 exposes the surface of the silicon active area 16. Since the shallow trench isolation structure is filled with an insulating material, it is not strictly required that the first patterned photoresist layer 120 only exposes the surface of the silicon active area 16, and it is also acceptable to expose part of the surface of the shallow trench isolation structure. Next, the first ion implantation is performed on the silicon active area 16 based on the first patterned photoresist layer 120 to form a doping layer 17 in the silicon active area 16. Fig.16 As shown, the first patterned photoresist layer 120 is finally removed.

[0101] like Fig.18 As shown, step S3 is then performed to perform a second ion implantation on the silicon active area 16; wherein the ion doping type of the first ion implantation is opposite to the ion doping type of the second ion implantation, the ion implantation parameters of the second ion implantation are the same as the ion implantation parameters of the MOS tube source and drain regions, and the ion implantation dose of the first ion implantation is 0.3 to 3 times the ion implantation dose of the second ion implantation.

[0102] The purpose of this ion implantation is to simultaneously form the source region and the drain region of the MOS tube, so the parameters of the ion implantation are set according to the doping requirements of the actual source region and the drain region of the MOS tube.

[0103] As a specific example, the method for performing the second ion implantation on the silicon active area 16 includes the following steps:

[0104] like Fig.17 As shown, a second photoresist layer 13 is first formed on the surface of the silicon wafer 10; Fig.18 As shown, the second photoresist layer 13 is then patterned to form a second patterned photoresist layer 130, and the second patterned photoresist layer 130 exposes the surface of the silicon active area 16. Since the shallow trench isolation structure is filled with an insulating material, it is not strictly required that the second patterned photoresist layer 130 only exposes the surface of the silicon active area 16, and it is also acceptable to expose part of the surface of the shallow trench isolation structure; then, based on the second patterned photoresist layer 130, the silicon active area 16 is subjected to the second ion implantation, so as to deplete the doping layer 17 formed by the first ion implantation after the subsequent rapid thermal annealing process; as shown Fig.19 As shown, the second patterned photoresist layer 130 is finally removed.

[0105] The ion doping type of the second ion implantation can be either N-type or P-type, as long as it is opposite to the ion doping type of the first ion implantation. Generally, the N-type doping ions are selected as phosphorus ions, but not limited thereto, and other N-type ions are also acceptable; the P-type doping ions are selected as boron ions, but not limited thereto, and other P-type ions are also acceptable.

[0106] like Fig.19 As shown, step S4 is then performed to perform rapid thermal annealing on the silicon wafer 10 so that the two different doping types of ions injected twice into the silicon active region 16 are activated, and the electrons and holes are neutralized after activation.

[0107] As an example, the rapid thermal annealing may be performed by spike annealing or laser annealing, etc. For example, when spike annealing is performed, the peak annealing temperature is selected to be 1050°C to 1080°C, and the heating step frequency may be selected to be 80°C, 180°C, or 220°C, etc.

[0108] like Fig. 20 As shown, step S5 is finally performed to form a metal silicide 14 on the surface of the silicon active region 16, and finally the desired test structure is obtained.

[0109] The Salicide process technology used in this step to form the metal silicide 14 includes: firstly, using a physical vapor deposition process (PVD) to deposit a metal layer, such as Ti, Co, NiPt, etc., on the silicon active region 16; then performing two rapid thermal annealing processes to form the metal silicide 14, such as TiSi2, CoSi2, NiPtSi. This process uses the fact that metal will not react with dielectric materials to form metal silicide, but will only react with silicon materials in direct contact to form metal silicide.

[0110] The present embodiment also provides a test structure for metal silicide block resistors, which is prepared using the preparation method for the test structure for metal silicide block resistors of the present embodiment, and can achieve accurate monitoring of the metal silicide block resistors on the source region or drain region of the MOS tube.

[0111] In summary, the test structure of the metal silicide block resistor of the present invention and the preparation method thereof, before the second ion implantation required for the preparation of the corresponding structure of the MOS device, the first ion implantation of the ion doping type opposite to the second ion implantation and low-temperature annealing are performed on the corresponding structure on the test structure to repair the lattice damage caused by the first ion implantation and deplete the doping ions of the second ion implantation as much as possible, so that the silicon material in the test structure approaches the conductive properties of intrinsic silicon, that is, high-resistance properties, so that when the metal silicide block resistor on the corresponding structure of the MOS device is measured, the parallel path of the silicon material resistance exhibits high resistance, and the measured block resistance result is only the block resistance of the metal silicide on the corresponding structure of the MOS device, avoiding the influence of the silicon material resistance on the instability of the entire measurement result, thereby obtaining the real metal silicide block resistance, and then accurately monitoring the thickness process parameters of the metal silicide and the key process parameters such as the size of the corresponding structure of the MOS device and the uniformity of these parameters on the wafer; in addition, low-temperature annealing repairs the damage of the silicon lattice without adding additional thermal budget and will not affect the electrical performance of the device. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0112] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for preparing a test structure of a metal silicide sheet resistor, characterized in that: The preparation method comprises the following steps: Providing a silicon wafer, and forming a polysilicon gate of a MOS tube on a surface of the silicon wafer; Performing a first ion implantation on the polysilicon gate and low-temperature annealing, wherein the temperature of the low-temperature annealing is not greater than 500° C.; Performing a second ion implantation on the polysilicon gate; wherein the ion doping type of the first ion implantation is opposite to the ion doping type of the second ion implantation, the ion implantation parameters of the second ion implantation are the same as the ion implantation parameters of the MOS tube source region and the drain region, and the ion implantation dose of the first ion implantation is 0.3 to 3 times the ion implantation dose of the second ion implantation; Performing rapid thermal annealing on the silicon wafer; Metal silicide is formed on the surface of the polysilicon gate.

2. The method for preparing a test structure of a metal silicide sheet resistor according to claim 1, characterized in that: The ion doping type of the first ion implantation is N-type ions or P-type ions, and the ion doping type of the second ion implantation is N-type ions or P-type ions.

3. The method for preparing a test structure of a metal silicide sheet resistor according to claim 1, characterized in that: The method for performing the first ion implantation on the polysilicon gate comprises the following steps: Forming a first patterned photoresist layer on the surface of the silicon wafer, wherein the first patterned photoresist layer exposes the surface of the polysilicon gate; Performing the first ion implantation on the polysilicon gate based on the first patterned photoresist layer; removing the first patterned photoresist layer; The method for performing the second ion implantation on the polysilicon gate comprises the following steps: forming a second patterned photoresist layer on the surface of the silicon wafer, wherein the second patterned photoresist layer exposes the surface of the polysilicon gate; Performing the second ion implantation on the polysilicon gate based on the second patterned photoresist layer; The second patterned photoresist layer is removed.

4. The method for preparing a test structure of a metal silicide sheet resistor according to claim 1, characterized in that: The ion implantation parameters of the first ion implantation are the same as the ion implantation parameters of the second ion implantation.

5. A metal silicide block resistor test structure, prepared by the method for preparing a metal silicide block resistor test structure as claimed in any one of claims 1 to 4.

6. A method for preparing a test structure of a metal silicide sheet resistor, characterized in that: The preparation method comprises the following steps: Providing a silicon wafer, and forming a shallow trench isolation structure in the silicon wafer, defining a silicon active region between adjacent shallow trench isolation structures, and the size of the silicon active region is the same as the size of the source region or the drain region of the MOS tube; Performing a first ion implantation on the silicon active region and low temperature annealing, wherein the temperature of the low temperature annealing is not greater than 500° C.; Performing a second ion implantation on the silicon active area; wherein the ion doping type of the first ion implantation is opposite to the ion doping type of the second ion implantation, the ion implantation parameters of the second ion implantation are the same as the ion implantation parameters of the MOS tube source region and the drain region, and the ion implantation dose of the first ion implantation is 0.3 to 3 times the ion implantation dose of the second ion implantation; Performing rapid thermal annealing on the silicon wafer; A metal silicide is formed on the surface of the silicon active region.

7. The method for preparing a test structure of a metal silicide sheet resistor according to claim 6, characterized in that: The ion doping type of the first ion implantation is N-type ions or P-type ions, and the ion doping type of the second ion implantation is N-type ions or P-type ions.

8. The method for preparing a test structure of a metal silicide sheet resistor according to claim 6, characterized in that: The method for performing the first ion implantation on the silicon active area comprises the following steps: Forming a first patterned photoresist layer on the surface of the silicon wafer, wherein the first patterned photoresist layer exposes the surface of the silicon active area; Performing the first ion implantation on the silicon active area based on the first patterned photoresist layer; removing the first patterned photoresist layer; The method for performing the second ion implantation on the silicon active area comprises the following steps: Forming a second patterned photoresist layer on the surface of the silicon wafer, wherein the second patterned photoresist layer exposes the surface of the silicon active area; Performing the second ion implantation on the silicon active area based on the second patterned photoresist layer; The second patterned photoresist layer is removed.

9. The method for preparing a test structure of a metal silicide sheet resistor according to claim 6, characterized in that: The ion implantation parameters of the first ion implantation are the same as the ion implantation parameters of the second ion implantation.

10. A metal silicide block resistor test structure, prepared by the method for preparing a metal silicide block resistor test structure according to any one of claims 6 to 9.

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