Semiconductor element and manufacturing method thereof

Abstract

The invention discloses a semiconductor element and a manufacturing method thereof, and the method for manufacturing the semiconductor element mainly comprises the steps: providing a substrate comprising a medium-voltage region and a low-voltage region, forming a plurality of fin-shaped structures in the low-voltage region, forming a dielectric layer between the fin-shaped structures, forming a hard mask on the low-voltage region, a gate dielectric layer is formed in the medium-voltage region, and then a heat treatment process is performed in the medium-voltage region. Wherein when the hard mask in the medium-voltage region is removed, preferably, a protruding part is formed on the surface of the substrate in the medium-voltage region, and the protruding part comprises a first protruding part arranged on one side of the substrate in the medium-voltage region and a second protruding part arranged on the other side of the substrate in the medium-voltage region.

Description

Technical Field

[0001] The invention relates to a method for manufacturing a semiconductor element, and in particular to a method for protecting a fin structure in a low voltage area by using a hard mask when a gate dielectric layer is formed in a medium voltage area by using a thermal manufacturing process. Background Art

[0002] With the current semiconductor technology level, the industry has been able to integrate control circuits, memory, low-voltage operating circuits, and high-voltage operating circuits and components on a single chip, thereby reducing costs and improving operating performance. Among them, high-voltage components such as vertical double-diffusion metal-oxide-semiconductor (VDMOS), insulated gate bipolar transistor (IGBT) and lateral-diffusion metal-oxide-semiconductor (LDMOS) are more commonly used because of their better switching efficiency. As known to those familiar with the art, the aforementioned high-voltage components are often required to withstand a higher breakdown voltage and operate at a lower resistance.

[0003] In addition, as the size of components continues to shrink, the development of existing planar field effect transistor components has faced the limit of manufacturing process. In order to overcome the limitation of manufacturing process, it has become the current mainstream development trend to replace planar transistor components with non-planar field effect transistor components, such as fin field effect transistor (Fin FET) components. Since the three-dimensional structure of the fin field effect transistor component can increase the contact area between the gate and the fin structure, the gate can further increase the control of the carrier channel region, thereby reducing the drain induced barrier lowering (DIBL) effect faced by small-sized components and suppressing the short channel effect (SCE). Furthermore, since the fin field effect transistor component has a wider channel width at the same gate length, it can obtain double the drain drive current. Even more, the threshold voltage of the transistor component can be regulated by adjusting the work function of the gate.

[0004] However, as the size of components continues to shrink, there are still many challenges in integrating the existing high-voltage components with the fin structure, such as the control of leakage current and breakdown voltage, etc. Therefore, how to improve the existing high-voltage component architecture is an important issue today. Summary of the invention

[0005] An embodiment of the present invention discloses a method for manufacturing a semiconductor element, which mainly provides a substrate including a medium voltage region and a low voltage region, then forms a plurality of fin-shaped structures in the low voltage region, forms a dielectric layer between the plurality of fin-shaped structures, forms a hard mask on the low voltage region, forms a gate dielectric layer in the medium voltage region, and then performs a heat treatment process in the medium voltage region. When removing the hard mask in the medium voltage region, a protrusion is preferably formed on the surface of the substrate in the medium voltage region, and the protrusion includes a first protrusion disposed on one side of the substrate in the medium voltage region and a second protrusion disposed on the other side of the substrate in the medium voltage region.

[0006] Another embodiment of the present invention discloses a semiconductor element, which mainly includes a substrate having a medium voltage area and a low voltage area, a first protrusion disposed on the substrate in the medium voltage area and a gate electrode disposed on the first protrusion, wherein the protrusion includes a first ring shape in a top view.

[0007] Another embodiment of the present invention discloses a semiconductor element, which mainly includes a substrate having a medium voltage area and a low voltage area, a first protrusion is arranged on one side of the substrate in the medium voltage area, a second protrusion is arranged on the other side of the substrate in the medium voltage area, and a gate electrode is arranged on the first protrusion and the second protrusion. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figures 1 to 5 A schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0009] Figure 6 It is a schematic diagram of a three-dimensional structure in which a protrusion is formed on the substrate surface and the gate dielectric layer surface in the medium voltage region according to an embodiment of the present invention;

[0010] Figure 7 Continuation of an embodiment of the present invention Figure 6 A schematic diagram of a structure in which a gate structure is formed in a medium voltage region and a low voltage region;

[0011] Figure 8 FIG. 1 is a top view of a gate structure formed in a medium voltage region according to an embodiment of the present invention.

[0012] Explanation of symbols

[0013] 12: Base

[0014] 16: Medium pressure area

[0015] 18: Low pressure area

[0016] 22: Base

[0017] 24: Fin structure

[0018] 26: cushion layer

[0019] 28: Insulation layer

[0020] 30: Shallow Trench Isolation

[0021] 32: Hard mask

[0022] 34: Gate dielectric layer

[0023] 36: protrusion

[0024] 38: protrusion

[0025] 40: protrusion

[0026] 42: Rapid thermal oxidation process

[0027] 46: protrusion

[0028] 48: protrusion

[0029] 50: protrusion

[0030] 52: Gate dielectric layer

[0031] 54: Gate electrode

[0032] 56: Gate electrode

[0033] 58: Source / drain region

[0034] 62: Active area DETAILED DESCRIPTION

[0035] Please refer to Figures 1 to 5 , Figures 1 to 5 FIG. 1 is a schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention, wherein Figure 1 The three-dimensional structure diagram of a semiconductor device manufactured according to an embodiment of the present invention is shown in FIG. Figures 2 to 5 Along Figure 1 A schematic cross-sectional view of a semiconductor device made along the tangent line AA'. Figure 1 to Figure 2 As shown, a substrate 12 is first provided, such as a silicon substrate or a silicon-on-insulator (SOI) substrate, on which more than two transistor regions are defined, such as a medium voltage region 16 and a low voltage region 18, wherein the medium voltage region 16 is provided with medium voltage components disposed on the active region 62, and the low voltage region 18 may further include a core region and / or an input / output (I / O) region, and the low voltage region 18 is provided with low voltage components. It should be noted that Figures 2 to 5 The left half is a schematic diagram of a method for manufacturing semiconductor components in the medium voltage region 14, and Figures 2 to 5 The right half is a schematic diagram of the method for manufacturing semiconductor components in a low-voltage region.

[0036] In this embodiment, the medium voltage region 16 and the low voltage region 18 may include transistor regions of the same conductivity type or different conductivity types, for example, each may be a PMOS transistor region and / or an NMOS transistor region, and the two regions are respectively predetermined to be gate structures of different threshold voltages to be subsequently fabricated. In this embodiment, a P-type deep well region may be first formed in the medium voltage region 16 using an ion implantation process and an N-type deep well region may be formed in the low voltage region 18, but the conductivity types of each region are not limited thereto.

[0037] Then, a base 22 can be formed on the substrate 12 in the medium-pressure area 16, and a plurality of fin structures 24 can be formed on the substrate 12 in the low-pressure area 18. According to a preferred embodiment of the present invention, the fin structure 24 is preferably obtained by sidewall image transfer (SIT) technology, and the procedure generally includes: providing a layout pattern to a computer system, and defining the corresponding pattern in a photomask through appropriate calculations. Subsequently, a plurality of equidistant and equal-width patterned sacrificial layers or mandrels can be formed on the substrate through photolithography and etching processes, so that their individual appearances are strip-shaped. Thereafter, deposition and etching processes are sequentially performed to form spacers on each sidewall of the patterned sacrificial layer. Subsequently, the patterned sacrificial layer is removed, and an etching process is performed under the coverage of the spacers, so that the pattern formed by the spacers is transferred to the substrate, and then a fin structure cutting process (fin cut) is performed to obtain the desired patterned structure, such as a strip-shaped patterned fin structure.

[0038] In addition, the formation method of the base 22 and the fin-shaped structure 24 may include first forming a patterned mask (not shown) on the substrate 12, and then performing an etching process to transfer the pattern of the patterned mask to the substrate 12 to form the base 22 and the fin-shaped structure 24. In addition, the formation method of the base 22 and the fin-shaped structure 24 may also include first making a patterned hard mask layer (not shown) on the substrate 12, and using an epitaxial process to grow a semiconductor layer such as silicon germanium on the substrate 12 exposed to the patterned hard mask layer, and this semiconductor layer can serve as the corresponding base 22 and the fin-shaped structure 24. These embodiments of forming the base 22 and the fin-shaped structure 24 are all within the scope of the present invention.

[0039] In this embodiment, each base 22 and fin structure 24 top surface may be provided with at least one liner layer 26 made of silicon oxide and one liner layer (not shown) made of silicon nitride on the substrate 12 during the patterning process. In the medium voltage region 16, the liner layer 26 preferably completely covers the entire active region 62 surface.

[0040] Then as Figure 2 As shown, a flowable chemical vapor deposition (FCVD) process is performed to form an insulating layer 28 composed of silicon oxide on the base 22 and the fin structure 24 and fill the groove between the base 22 and the fin structure 24, and then a planarization process is performed, such as chemical mechanical polishing (CMP) to remove part of the insulating layer 28 to form a shallow trench isolation (STI) 30. The liner layer composed of silicon nitride can then be removed to expose the liner layer 26 composed of silicon oxide underneath. It should be noted that in order to highlight the subsequent process performed on the surface of the substrate 12 in the medium-voltage area 16, the liner layer 26 in the low-voltage area 18 is preferably omitted in the subsequent figures so that the liner layer 26 only appears on the surface of the substrate 12 in the medium-voltage area 16.

[0041] like Figure 3 As shown, a hard mask 32 is then formed on the medium voltage region 16 and the low voltage region 18 and covers the liner layer 26 of the medium voltage region 16 and the low voltage region 18. In this embodiment, the hard mask 32 preferably comprises a dielectric material such as silicon oxide, silicon nitride, silicon carbide, or preferably silicon nitride, but is not limited thereto.

[0042] As shown in FIG. 4 , a photolithography and etching process is then performed. For example, a patterned mask (not shown) such as a patterned photoresist can be used as a mask to remove the hard mask 32 and the liner layer 26 of the medium voltage region 16 and expose the surface of the substrate 12. It should be noted that when etching is used to remove the hard mask 32 composed of silicon nitride and the liner layer 26 composed of silicon oxide in the medium voltage region 16 at this stage, it is preferred to remove all the hard masks 32 first and then remove most of the liner layer 26. More specifically, after the hard mask 32 is completely removed, a portion of the liner layer 26 composed of silicon oxide remains on both sides of the substrate 12 near the corners where the substrate 12 contacts the shallow trench isolation 30. From a cross-sectional view, the surface of the substrate 12 in the medium voltage region 16 is still a flat surface, but the top surface of the remaining liner layer 26 at the corners of the substrate 12 and the shallow trench isolation 30 may present an inclined surface or a curved surface. If viewed from a top view, the remaining liner layer 26 at this time point preferably forms an annular active area 62 disposed on the base 12 of the medium pressure area 16 and surrounds four edges of the active area 62 .

[0043] like Figure 5As shown, an oxide growth process or more specifically a rapid thermal oxidation (RTO) process 42 is then performed to form a gate dielectric layer 34 composed of silicon oxide on the substrate 12 of the medium voltage region 16. It is worth noting that since the aforementioned liner layer 26 composed of silicon oxide is filled in the corner gap between the substrate 12 and the shallow trench isolation 30, the oxygen introduced during the rapid thermal oxidation process 42 in this stage preferably first reacts with the surface of the substrate 12 or the surface of the active region 62 relatively in the center to form the gate dielectric layer 34 composed of silicon oxide, and then slowly reacts with the surface of the active region 62 outside the center of the substrate 12 and finally with the surface of the edge to form the gate dielectric layer 34.

[0044] Overall, since the relatively central area on the substrate 12 of the medium-voltage region 16 is reacted first to form a gate dielectric layer 34 composed of silicon oxide and the edge area is reacted later to form a gate dielectric layer 34, in this stage, the rapid thermal oxidation process 42 is used to oxidize the surface of the substrate 12 of the medium-voltage region 16, and it is better to form a protrusion 36 on the surface of the substrate 12, wherein the protrusion 36 is formed by the raised portion of the edge of the substrate 12 and therefore preferably contains the same material as the substrate 12.

[0045] In addition, since the gate dielectric layer 34 is formed during the process of forming the protrusion 36 on the surface of the substrate 12, the protrusions 46 are preferably formed on both sides of the top surface of the gate dielectric layer 34 and the underlying surface of the substrate 12. Similarly, since the protrusion 46 is formed by the raised edge of the gate dielectric layer 34, it is preferably made of the same material as the gate dielectric layer 34.

[0046] Please refer to Figure 5 and Figure 6 ,in Figure 5 FIG. 1 is a cross-sectional view of forming protrusions 36 and 46 on the surface of the substrate 12 and the surface of the gate dielectric layer 34 in the medium voltage region 16 according to an embodiment of the present invention. Figure 6 FIG. 1 is a schematic diagram of a three-dimensional structure of a protrusion formed on the surface of the substrate 12 and the surface of the gate dielectric layer 34 in the medium voltage region 16 according to an embodiment of the present invention. Figure 5 As shown in the cross-section of the left half, the protrusion 36 on the surface of the base 12 of the middle pressure zone 16 may include a protrusion 38 disposed on one side of the base 12 such as the left side and a protrusion 40 disposed on the other side of the base 12 such as the right side, wherein the top surface of each protrusion 38, 40 may present various shapes such as an inclined surface, a curved surface, an L-shape or a V-shape.

[0047] Similarly, the protrusion 46 on the top surface of the gate dielectric layer 34 in the medium voltage region 16 may include a protrusion 48 disposed on one side of the gate dielectric layer 34, such as the left side, and a protrusion 50 disposed on the other side of the gate dielectric layer 34, such as the right side, wherein the top surface of each protrusion 48, 50 may present various shapes such as an inclined surface, a curved surface, an L shape or a V shape. Figure 6 From a top-view angle, the protrusion 36 on the surface of the base 22 or the active region 62 includes four edges that surround the entire active region 62 in a ring shape in a top-view angle. Similarly, the protrusion 46 on the surface of the gate dielectric layer 34 above the substrate 12 also preferably includes four edges that surround the entire active region 62 in a ring shape in a top-view angle, wherein the ring shape formed by the protrusion 46 on the surface of the gate dielectric layer 34 may completely overlap or partially overlap the ring shape formed by the protrusion 36 on the surface of the underlying substrate 12. In other words, the ring area formed by the protrusion 46 on the surface of the gate dielectric layer 34 may be greater than, equal to, or less than the ring area formed by the protrusion 36 on the surface of the underlying substrate 12 according to the manufacturing process requirements, all of which are within the scope of the present invention.

[0048] Please continue to refer to Figures 7 and 8 , Figure 7 Continuation of an embodiment of the present invention Figure 6 A schematic diagram of a structure in which a gate structure is formed in the medium voltage region 16 and the low voltage region 18, Figure 8 1 is a top view of a gate structure formed in the medium voltage region 16. Figure 7 As shown, the hard mask 32 and part of the shallow trench isolation 30 in the low voltage region 18 may be removed first to make the top surface of the shallow trench isolation 30 slightly lower than the top surface of the fin structure 24, and then another oxidation process such as an in-situ steam growth process (ISSG) may be performed to form a gate dielectric layer 52 composed of silicon oxide on the surface of the fin structure 24 in the low voltage region 18. Then, a gate structure or gate electrode 54, 56 may be formed on the base 22 and the fin structure 24 in the medium voltage region 16 and the low voltage region 18, respectively, wherein the gate electrodes 54, 56 may be fabricated by a gate first process, a high-k first process of a gate last process, or a high-k last process of a gate last process according to the process requirements.

[0049] Afterwards, a standard transistor manufacturing process may be performed according to the manufacturing process or product requirements, such as forming source / drain regions 58 in the substrate 12 on both sides of each gate electrode 54, 56. Since the manufacturing of standard metal oxide semiconductor transistors is a well-known technique in the art, it will not be further described here. Figure 8From a top-down perspective, after the gate electrode 54 is formed on the medium-voltage region 16, the protrusion 36 on the surface of the substrate 12 is still located at and surrounds the four edges of the entire active region 62, while the protrusion 46 on the surface of the gate dielectric layer 34 can be selected according to the manufacturing process to still overlap the protrusion 36 on the surface of the entire substrate 12, or be patterned together with the gate electrode 54 as shown in the figure and only located at the edge of the active region 62 directly below the gate electrode 54, all of which are within the scope of the present invention.

[0050] In summary, the present invention mainly forms shallow trench isolation around the substrate of the medium voltage region and the fin structure of the low voltage region, and then forms a hard mask made of silicon nitride in the medium voltage region and the low voltage region, and then removes the hard mask of the medium voltage region and forms a gate dielectric layer on the substrate surface of the medium voltage region by using a rapid thermal oxidation process 42. Since the fin structure of the low voltage region is already covered with a hard mask 32 during the rapid thermal oxidation process 42, the high temperature associated with the rapid thermal oxidation process 42 will not affect the density composition of the fin structure, causing the fin structure to shrink in width, thereby affecting the performance of subsequent transistors.

[0051] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: Include: Providing a substrate including a medium pressure area and a low pressure area; forming a plurality of fin-shaped structures in the low-pressure area; forming an insulating layer between the plurality of fin structures; forming a hard mask on the low voltage region; as well as A thermal oxidation process is performed to form a gate dielectric layer in the middle voltage region.

2. The method of claim 1, further comprising: forming a liner layer on the substrate; forming the insulating layer in the medium voltage region and the low voltage region; planarizing the insulating layer to form shallow trench isolation; forming the hard mask on the liner layer; removing the hard mask and the liner layer in the medium voltage region; as well as The gate dielectric layer is formed on the substrate in the medium voltage region. The method of claim 2 , wherein the liner layer comprises silicon oxide.

4. The method of claim 2, further comprising: The hard mask and the liner layer are removed to form a protrusion in the middle pressure area.

5. The method of claim 4, wherein the protrusion further comprises: A first protrusion is disposed on one side of the base of the medium pressure area; and The second protrusion is arranged on the other side of the base of the middle pressure area. The method of claim 4 , wherein the protrusion comprises a ring shape in a top view. The method according to claim 1 , wherein the gate dielectric layer in the medium voltage region comprises a protrusion.

8. The method of claim 7, wherein the protrusion further comprises: A first protrusion is disposed on one side of the gate dielectric layer in the medium voltage region; and The second protrusion is arranged on the other side of the gate dielectric layer in the medium voltage region.

9. The method of claim 7, wherein the protrusion comprises a ring shape in a top view.

10. A semiconductor element, characterized in that: Include: The base includes a medium pressure area and a low pressure area; A first protrusion is disposed on the base of the medium pressure area, wherein the protrusion comprises a first ring shape in a top view; and The gate electrode is disposed on the first protrusion. 11 . The semiconductor device as claimed in claim 10 , further comprising a gate dielectric layer disposed between the substrate and the gate electrode, wherein the gate dielectric layer comprises a second protrusion. 12 . The semiconductor device as claimed in claim 11 , wherein the second protrusion comprises a second ring shape in a plan view. The semiconductor device as claimed in claim 12 , wherein the second ring shape overlaps the first ring shape. The semiconductor device as claimed in claim 12 , wherein the first protrusion and the substrate comprise the same material.

15. A semiconductor device, characterized in that: Include: The base includes a medium pressure area and a low pressure area; A first protrusion is provided on one side of the base of the medium pressure area; A second protrusion is provided on the other side of the base of the medium pressure area; as well as The gate electrode is disposed on the first protrusion and the second protrusion.

16. The semiconductor device according to claim 15, further comprising: A gate dielectric layer is disposed between the substrate and the gate electrode; A third protrusion is disposed on one side of the gate dielectric layer; and The fourth protrusion is arranged on the other side of the gate dielectric layer. The semiconductor device as claimed in claim 15 , wherein the first protrusion and the substrate comprise the same material. The semiconductor device as claimed in claim 15 , wherein the second protrusion and the substrate comprise the same material.

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