Electronic device and manufacturing method thereof

Abstract

The invention provides an electronic device and a manufacturing method thereof. The electronic device comprises a circuit structure, a plurality of electronic elements and a structural unit. The circuit structure includes a plurality of conductive layers and at least one insulating layer, and two adjacent conductive layers are electrically connected through a plurality of through holes in the at least one insulating layer. The plurality of electronic components are electrically connected with the circuit structure and overlapped with the circuit structure. The structural unit is disposed adjacent to the electronic components, and in a top view of the electronic device, at least a portion of the structural unit is located between two adjacent ones of the electronic components.

Description

Technical Field

[0001] The invention relates to an electronic device and a manufacturing method thereof, and in particular to a packaged electronic device and a manufacturing method thereof. Background Art

[0002] In panel level package (PLP) technology, there is often a problem of warping of the substrate and the circuit structure thereon. When the warping is too large, it will affect the subsequent processes, for example, the solder ball mounting process cannot be carried out normally, or the electronic component bonding process cannot be carried out normally, or the stress is too large to cause circuit damage, thereby reducing the yield or reliability. Therefore, how to solve the warping problem is a technical problem that needs to be solved at present. Summary of the invention

[0003] The object of the present invention is to provide an electronic device and a manufacturing method thereof.

[0004] The present invention provides a method for manufacturing an electronic device, which comprises the following steps: providing a carrier board. Arranging a circuit structure on the carrier board, which comprises alternately arranging a plurality of conductive layers and a plurality of insulating layers on the carrier board, and two adjacent ones of the plurality of conductive layers are electrically connected through a plurality of through holes in one of the plurality of insulating layers. Arranging a structural unit on one side of the circuit structure. The structural unit has a first thermal expansion coefficient, one of the plurality of conductive layers in the circuit structure has a second thermal expansion coefficient, and a ratio of the first thermal expansion coefficient to the second thermal expansion coefficient is greater than or equal to 1.2 and less than or equal to 2.

[0005] The present invention further provides a method for manufacturing an electronic device, which includes the following steps: providing a carrier board. Arranging a circuit structure and a structural unit on the carrier board, and the structural unit is arranged in the circuit structure. Arranging the circuit structure includes alternately arranging multiple conductive layers and multiple insulating layers on the carrier board, and two adjacent ones of the multiple conductive layers are electrically connected through multiple through holes in one of the multiple insulating layers. The structural unit has a first thermal expansion coefficient, one of the multiple conductive layers in the circuit structure has a second thermal expansion coefficient, and a ratio of the first thermal expansion coefficient to the second thermal expansion coefficient is greater than or equal to 0.1 and less than or equal to 0.8.

[0006] The present invention further provides an electronic device, which includes a circuit structure, a plurality of electronic components and a structural unit. The circuit structure includes a plurality of conductive layers and at least one insulating layer, and the plurality of conductive layers are electrically connected through a plurality of through holes in the at least one insulating layer. The electronic component is electrically connected to the circuit structure and overlaps with the circuit structure. The structural unit is disposed adjacent to the electronic component, wherein in a top view of the electronic device, at least a portion of the structural unit is located between two adjacent electronic components. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figures 1 to 3 FIG. 1 is a schematic diagram of a method for manufacturing an electronic device according to a first embodiment of the present invention.

[0008] Figure 4 FIG. 1 is a flowchart of the manufacturing method of the electronic device according to the first embodiment.

[0009] Figures 5 to 7 FIG. 4 is a schematic diagram of a method for manufacturing an electronic device according to a second embodiment of the present invention.

[0010] Figures 8 to 10 FIG. 4 is a schematic diagram of a method for manufacturing an electronic device according to a third embodiment of the present invention.

[0011] Fig.11 FIG. 1 is a flowchart of a method for manufacturing an electronic device according to a third embodiment of the present invention.

[0012] Figure 12 to Figure 14 FIG. 4 is a schematic diagram of a method for manufacturing an electronic device according to a fourth embodiment of the present invention.

[0013] Fig.15 FIG. 1 is a schematic structural diagram of a method for manufacturing an electronic device according to a fifth embodiment of the present invention before a cutting process is performed.

[0014] Fig.16 FIG. 1 is a top view of a sixth embodiment of the present invention in which a structural unit and an electronic component are arranged on a carrier board.

[0015] Fig.17 FIG. 1 is a top view of a seventh embodiment of the present invention showing a structure unit and an electronic component arranged on a carrier board.

[0016] Fig.18 FIG. 1 is a top view of a structure unit and an electronic component arranged on a carrier board according to an eighth embodiment of the present invention.

[0017] Fig.19 FIG. 1 is a schematic top view of a structural unit and electronic components in an electronic device according to a ninth embodiment of the present invention.

[0018] Fig. 20 FIG. 4 is a cross-sectional diagram of an electronic device according to a ninth embodiment of the present invention.

[0019] Fig.21 FIG. 1 is a top view of a structural unit and electronic components in an electronic device according to a tenth embodiment of the present invention.

[0020] Fig. 22 FIG. 1 is a cross-sectional schematic diagram of an electronic device according to a tenth embodiment of the present invention.

[0021] Explanation of reference numerals: 10 ~ electronic device; 100, 130 ~ carrier; 100S, 118S, 130S ~ surface; 102, 128 ~ release layer; 104 ~ circuit structure; 1040, 1042 ~ circuit structure part; 106, 110, 114, 118, 121 ~ insulating layer; 108, 112, 116, 120 ~ conductive layer; 108e ~ electrode; 1101, 1141, 1181 ~ through hole; 114O, GO ~ opening; 119 ~ connecting conductive material; 120p ~ contact pad; 122, 1320, 1322, 1324, 1326 ~ electronic component; 122T, 124T, 126T ~maximum thickness; 123~insulating structure; 124~structural unit; 1240-1248, 1244-1, Qa-Qd~part; 100U~subunit; 125~conductive connector; 126~packaging layer; 1260, 1262~packaging layer part; 134~solder element; A1, A2~virtual line; CM~attachment material; DA, DM~diagonal line; DAR~non-packaging area; DG1, DG2~diagonal area; HS~heat dissipation element; PAR~packaging area; R1~first area; R2~second area; S~section; S101, S103, S105, S201, S203~step; X, Y, V~direction. DETAILED DESCRIPTION

[0022] The present invention can be understood by referring to the following detailed description in conjunction with the accompanying drawings. It should be noted that in order to make it easier for readers to understand and for the simplicity of the drawings, the multiple drawings in the present invention only depict a portion of the electronic device, and specific elements in the drawings are not drawn according to the actual scale. In addition, the number and size of each element in the figure are only for illustration and are not intended to limit the scope of the present invention.

[0023] Certain words are used throughout the specification and the appended claims to refer to specific components. It should be understood by those skilled in the art that electronic equipment manufacturers may refer to the same components by different names. The present invention is not intended to distinguish between components that have the same function but different names. The following description lists various embodiments of the present case to introduce the basic concepts of the present case, and is not intended to limit the content of the present case. The actual scope of the invention should be defined in accordance with the claims. The following will refer to exemplary embodiments of the present invention in detail, and examples of exemplary embodiments are illustrated in the accompanying drawings. Whenever possible, the same element symbols are used in the drawings and descriptions to represent the same or similar parts.

[0024] The directional terms mentioned in the present invention, such as "up", "down", "front", "back", "left", "right", etc., are only reference directions of the drawings. Therefore, the directional terms used are for illustration, not for limiting the present invention. In the accompanying drawings, each figure illustrates the general characteristics of the methods, structures and / or materials used in a specific embodiment. However, these drawings should not be interpreted as defining or limiting the scope or properties covered by these embodiments. For example, for the sake of clarity, the relative size, thickness and position of each film layer, region and / or structure may be reduced or enlarged. The present invention can be understood by referring to the following detailed description in conjunction with the accompanying drawings. It should be noted that in order to make it easy for readers to understand and for the simplicity of the drawings, the multiple drawings in the present invention only depict a portion of the electronic device, and specific elements in the drawings are not drawn according to the actual scale. In addition, the number and size of each element in the figure are only for illustration and are not intended to limit the scope of the present invention.

[0025] In the present specification and claims, the words “including” and “comprising” are open-ended words, and thus should be interpreted as meaning “including but not limited to…”.

[0026] It should be understood that when an element or a film layer is referred to as being "on" or "connected to" another element or film layer, it may be directly on or directly connected to the other element or layer, or there may be an intervening element or film layer between the two (indirect case). Conversely, when an element is referred to as being "directly on" or "directly connected to" another element or film layer, there may be no intervening element or film layer between the two.

[0027] In some embodiments of the present invention, terms such as "connection" and "interconnection" related to bonding and connection, unless otherwise defined, may refer to two structures being in direct contact, or may also refer to two structures not being in direct contact, wherein another structure is disposed between the two structures. Such terms related to bonding and connection may also include situations where both structures are movable, or both structures are fixed. In addition, the terms "electrically connected" or "electrically coupled" include any direct and indirect electrical connection methods.

[0028] Although the terms first, second, third, etc. can be used to describe a variety of components, the components are not limited to these terms. These terms are only used to distinguish a single component from other components in the specification. The same terms may not be used in the claims, but may be replaced by first, second, third, etc. according to the order in which the components are declared in the claims. Therefore, in the specification of the present invention, the first component may be the second component in the claims.

[0029] In the present specification, roughness is defined as: when observed with a scanning electron microscope (SEM), on the surface of a given element, the peaks and valleys of the surface undulations can be seen to have a distance difference of 0.15 microns to 0.5 microns. The measurement of roughness may include using a scanning electron microscope, a transmission electron microscope (TEM), etc. to observe the surface undulations at the same appropriate magnification. And the undulations are compared by capturing a unit length (e.g., 10 microns). Here, "appropriate magnification" means that at least one surface can see at least 10 undulating peaks under the field of view of this magnification. The distance between the aforementioned elements can be measured, for example, with a ruler of a scanning electron microscope on a cross-sectional view.

[0030] It should be noted that the following embodiments may be implemented by replacing, reorganizing, or mixing the technical features in several different embodiments without departing from the spirit of the present invention to complete other embodiments.

[0031] The terms "approximately", "equal to", "equal to" or "same", "substantially" or "approximately" are generally interpreted as within 20% of a given value or range, or as within 10%, 5%, 3%, 2%, 1% or 0.5% of a given value or range. In the present invention, the phrases "a given range is from a first value to a second value", "a given range falls within the range from a first value to a second value" indicate that the given range includes the first value, the second value and other values ​​therebetween.

[0032] Furthermore, any two values ​​or directions used for comparison may have a certain error. If the first value is equal to the second value, it implies that there may be an error of about 10% between the first value and the second value; if the first direction is perpendicular or "approximately" perpendicular to the second direction, the angle between the first direction and the second direction may be between 80 degrees and 100 degrees; if the first direction is parallel or "approximately" parallel to the second direction, the angle between the first direction and the second direction may be between 0 degrees and 10 degrees.

[0033] The electronic device described in the present invention can be applied to power modules, semiconductor packaging devices, display devices, light-emitting devices, backlight devices, antenna devices, sensing devices or splicing devices, but is not limited thereto. In the present invention, the electronic device includes various electronic components, semiconductor packaging components, display devices, light-emitting devices, sensing devices, antenna devices, bendable electronic devices, spliced ​​electronic devices or flexible electronic devices, but is not limited thereto.

[0034] The electronic device includes a semiconductor die, or a stack formed by interlacing multiple metal layers (copper layer and seed layer) and multiple insulating layers, such as a redistribution layer (RDL), but is not limited thereto. The term "flexible / bendable" herein means that the material can be curved, bent, folded, rolled, flexed, stretched, and / or other similar deformations to represent at least one of the above possible deformation modes, and "flexible / bendable" is not limited to the above deformation modes.

[0035] The antenna device may be a liquid crystal type antenna device or a non-liquid crystal type antenna device, and the sensing device may be a sensing device that senses capacitance, light, heat energy, or ultrasound, but is not limited thereto.

[0036] Electronic components may include passive components, active components, or a combination thereof, such as capacitors, resistors, inductors, varactors, variable capacitors, filters, diodes, transistors, sensors, micro-electromechanical system components (MEMS), liquid crystal chips, etc., but are not limited thereto. Diodes may include light-emitting diodes or non-light-emitting diodes. Diodes may include PN junction diodes, PIN diodes, or constant current diodes. Light-emitting diodes may include, for example, organic light emitting diodes (OLED), sub-millimeter light-emitting diodes (mini LED), micro LEDs, quantum dot LEDs, fluorescence diodes, phosphor diodes, or other suitable materials, or a combination thereof, but are not limited thereto.

[0037] The sensor may include, for example, capacitive sensors, optical sensors, electromagnetic sensors, fingerprint sensors (FPS), touch sensors, antennas, or styluses, but is not limited thereto.

[0038] The electronic component may include a chip (die) or a light emitting diode chip (LED die), which may be a chip made of silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), sapphire (Sapphire) or a glass substrate, but is not limited thereto. In one embodiment, the chip includes a semiconductor package component, such as a ball grid array (BGA) package component, a chip size package (CSP) component, a flip chip or a 2.5D / 3D semiconductor package component, but is not limited thereto. In another embodiment, the chip may be any flip chip bonding component, such as an integrated circuit (IC), a transistor, a thyristor rectifier, a valve, a thin film transistor, a capacitor, an inductor, a variable capacitor, a filter, a resistor, a diode, a micro-electromechanical system component (MEMS), a liquid crystal chip, etc., but is not limited thereto. The chip includes, for example, a diode or a semiconductor chip (semiconductor die), but is not limited thereto. The chip may be a known good die (KGD), which may include various electronic components, such as (but not limited to) wires, transistors, circuit boards, etc. Adjacent chips may have different functions, such as integrated circuits, RFICs, D-RAMs, but not limited thereto.

[0039] If the electronic device is used in packaging, it can be applicable to packaging such as panel level packaging (PLP), ball grid array packaging (BGA), chip scale package (CSP), chip on wafer on substrate (CoWoS), etc. For example, it can include packaging methods such as chip-first or redistribution layer first (RDL first), but the present invention is not limited thereto.

[0040] It should be noted that the electronic device can be any combination of the above, but is not limited thereto. The various embodiments of the present invention illustrate a combination of a plurality of electronic units packaged by packaging materials, a redistribution structure, a metal layer, an insulating layer, a terminal shaft, a bonding element, and an input / output bonding pad (I / O pad). The electronic unit of the present invention can be an electronic device packaged in a fan-out type (Fan-Out) as an example, but is not limited thereto.

[0041] The following will use the electronic device of the packaging device as an example to illustrate the content of the present invention, but it is not limited to this. The dielectric material of the circuit redistribution layer may include an organic dielectric material, an inorganic dielectric material, or a combination of the above dielectric materials that can be used for packaging, but it is not limited to this. Organic dielectric materials include, for example, polybenzoxazole (PBO), benzocyclobutene (BCB), acrylic, ABF carrier, polyimide (PI), polyamide, other suitable materials, or a combination of the above organic dielectric materials that can be used for packaging, but it is not limited to this. Inorganic dielectric materials may include, for example, silicon oxide, silicon nitride, aluminum oxide, siloxane, other suitable materials, or a combination of the above inorganic dielectric materials that can be used for packaging, but the present invention is not limited to this.

[0042] The following figures indicate directions V, X, and Y. Direction V may be a top-down direction or a direction perpendicular to the surface 100S of the carrier 100, and direction X and direction Y may be directions parallel to the surface 100S of the carrier 100. Direction X and direction Y may be perpendicular to direction V. The following figures may describe the spatial relationship of the structures based on direction V, direction X, and direction Y.

[0043] Please refer to Figures 1 to 4 , Figures 1 to 3 FIG. 1 is a schematic diagram of a method for manufacturing an electronic device according to a first embodiment of the present invention. Figure 4 FIG. 1 is a flowchart of the steps of the method for manufacturing an electronic device according to the first embodiment. It should be understood that Figure 4 The steps shown in the embodiment may not be exhaustive, and other steps may be performed before, after, or between any of the steps shown. In addition, some steps may be performed simultaneously or in a sequential manner. Figure 4 The order shown in the figure is different from the order in which it is executed.

[0044] First, step S101 may be performed to provide a carrier 100. The carrier material of the present invention includes a substrate having support properties, such as an organic or inorganic material substrate, which may include a glass substrate, a ceramic substrate, a plastic substrate, a copper substrate, a steel plate, a polyimide (PI) substrate, a polyethylene terephthalate (PET) substrate, a wafer or other suitable materials or a combination thereof. The top view shape of the substrate 110 may include a rectangle, a square, a circle, a polygon or a free-shape, but is not limited thereto.

[0045] Next, a release layer 102 may be formed on the carrier 100. The adhesion of the release layer 102 may be changed, for example, by irradiating a specific light or heating to change its quality, so as to facilitate the peeling of the circuit structure 104 from the carrier 100, but the invention is not limited thereto. The "release layer" described in the present invention may include an adhesive material, including a glue material that can be separated by laser, light or thermal decomposition, but the invention is not limited thereto. In some embodiments (not shown), an anti-warping layer (not shown) may be selectively added between the release layer 102 and the carrier 100.

[0046] Next, step S103 may be performed to arrange a circuit structure 104 on the carrier 100. The circuit structure 104 may be a redistribution layer (RDL), but is not limited thereto. For example, a plurality of conductive layers and a plurality of insulating layers may be alternately arranged on the carrier 100, and two adjacent ones of the plurality of conductive layers may be electrically connected through a plurality of through holes in one of the plurality of insulating layers. Figure 1 Regarding “multiple conductive layers and multiple insulating layers are alternately arranged”, for example, the circuit structure 104 may include an insulating layer 106, a conductive layer 108, an insulating layer 110, a conductive layer 112, an insulating layer 114, a conductive layer 116, an insulating layer 118 and a conductive layer 120 formed in sequence, but is not limited thereto.

[0047] The circuit structure 104 can be used as a redistribution layer (RDL). The circuit structure 104 can be electrically connected to each electronic component through a bonding pad, and can include at least one conductive layer and at least one insulating layer. The circuit structure 104 can, for example, increase the fan-out area of ​​the circuit, or different electronic components can be electrically connected to each other through the circuit structure 104.

[0048] For example, an insulating layer 106 is first formed on the release layer 102, and a plurality of openings are formed in the insulating layer 106, and a conductive layer 108 is formed in the plurality of openings of the insulating layer 106. The conductive layer 108 may include a plurality of contact pads. Next, an insulating layer 110 is formed on the insulating layer 106 and the conductive layer 108, and a plurality of through holes 1101 are formed in the insulating layer 110, and a conductive layer 112 is formed on the insulating layer 110, and a portion of the conductive layer 112 is located in the plurality of through holes 1101. Next, this method is repeated to sequentially form an insulating layer 114, a plurality of through holes 1141 in the insulating layer 114, a conductive layer 116, an insulating layer 118, a plurality of through holes 1181 in the insulating layer 118, and a conductive layer 120, but the invention is not limited thereto. The number of stacking layers of the conductive layer and the insulating layer can be adjusted according to requirements, and the order of the above process is only an example, and the order can be adjusted according to requirements. The circuit structure 104 is not limited to the above manufacturing method.

[0049] The insulating layer in the circuit structure 104 includes an organic material or an inorganic material, such as photosensitive polyimide (PSPI), polyethylene (PE), polyethylene terephthalate (PET), polycarbonate (PC), polytetrafluoroethylene (PTFE), polystyrene (PS), acrylonitrile butadiene styrene (ABS), other suitable materials, or any combination thereof, but not limited thereto. In some embodiments, the insulating layer in the circuit structure 104 may include, for example (but not limited to), polyimide, epoxy resin, silicon nitride (SiNx), silicon oxide (SiOx), or a combination thereof.

[0050] Any conductive layer in the circuit structure 104 may include a seed layer and / or a metal material layer, and the seed layer may include, for example, titanium, copper or nickel, but is not limited thereto. The above conductive layers may include, for example, a single layer or a multi-layer stack, and examples include copper (Cu), aluminum (Al), molybdenum (Mo), tungsten (W), gold (Au), chromium (Cr), nickel (Ni), platinum (Pt), titanium (Ti), silver (Ag), tantalum (Ta), other suitable metal materials or any combination thereof. In some embodiments, such as Figure 1 The conductive layer 120 may include an under bump metallization (UBM), but is not limited thereto.

[0051] Next, step S105 may be performed to set a structural unit 124 on one side of the circuit structure 104. In some embodiments, a plurality of electronic components 122 and / or structural units 124 may be set after the circuit structure 104 is set. The plurality of electronic components 122 and the structural unit 124 are set on one side (such as the upper side) of the circuit structure 104 in the direction V, but not limited thereto. The plurality of electronic components 122 and the structural unit 124 may be set on the insulating layer 118. The plurality of electronic components 122 and the structural unit 124 at least partially overlap in a direction parallel to a surface 100 of the carrier 100. The plurality of electronic components 122 may be electrically connected to the conductive layer 120 through a plurality of connecting conductive materials 119, respectively, but not limited thereto. An insulating layer 121 covering the connecting conductive material 119 may be formed around the connecting conductive material 119, and the insulating layer 121 may be used to protect the connecting conductive material 119 and / or improve the bonding yield of the electronic components 122. In some embodiments (not shown), the insulating layer 121 may selectively contact the side surface of the electronic element 122 .

[0052] like Figure 1 , the electronic element 122 may be defined as being disposed in a first region R1 of the cross-sectional structure, and the circuit structure 104 may be defined as being disposed in a second region R2 of the cross-sectional structure. Figure 1 In the embodiment, the circuit structure 104 is disposed between the electronic component 122 and the carrier 100, and the boundary between the first region R1 and the second region R2 can be defined by, for example, the upper surface (e.g., the upper surface 118S) of the uppermost insulating layer (e.g., the insulating layer 118) in the circuit structure 104, but not limited thereto. In some embodiments, the structural unit 124 can be disposed in the first region R1, but not limited thereto.

[0053] In a cross-sectional view (such as Figure 1 ), the plurality of electronic components 122 and the structural unit 124 may at least partially overlap in a direction parallel to the surface 110S of the carrier 100 (such as direction X or direction Y), and the plurality of electronic components 122 and the structural unit 124 may not overlap in a direction V perpendicular to the surface 110S of the carrier 100. The structural unit 124 and a portion of the conductive layer 120 may, for example, be disposed on the upper surface 118S of the insulating layer 118 and may be substantially coplanar, but is not limited thereto. In some embodiments, the structural unit 124 and a portion of the conductive layer 120 (i.e., a portion of the conductive layer 120 disposed in the through hole 1181 of the insulating layer 118) may not be coplanar. In a cross-sectional view (such as Figure 1 ), the structural unit 124 may at least partially overlap with a portion of the conductive layer 120, the connecting conductive material 119, the insulating layer 121 and / or the electronic component 122 in a direction parallel to the surface 110S of the carrier 100 (such as direction X or direction Y), but is not limited thereto.

[0054] In this embodiment, in the cross-sectional view, the maximum thickness 124T of the structural unit 124 may be greater than or equal to the maximum thickness 122T of the electronic component 122, but is not limited thereto. In some embodiments, in the cross-sectional view, the maximum thickness 124T of the structural unit 124 may not be equal to the maximum thickness 122T of the electronic component 122. In some embodiments, in the cross-sectional view, the ratio of the maximum thickness 126T of the encapsulation layer 126 to the maximum thickness 124T of the structural unit 124 may be greater than or equal to 1.5 and less than or equal to 6, or may be greater than or equal to 2 and less than or equal to 5, but is not limited thereto. In some embodiments, in the cross-sectional view, the shape of the structural unit 124 may be rectangular, but is not limited thereto, and may be adjusted to other shapes (trapezoidal), arc-shaped or irregular shapes according to requirements. In other embodiments, the maximum thickness 124T of the structural unit 124 may be less than the maximum thickness 122T of the electronic component 122.

[0055] The carrier 100 may include a package area PAR and a non-package area DAR, and the non-package area DAR may be located on at least one side of the package area PAR or surround the package area PAR. The electronic component 122 and / or the conductive layer in the circuit structure 104 may be disposed in the package area PAR, and the structural unit 124 may be disposed in the non-package area DAR, but is not limited thereto. In other embodiments (not shown), the conductive layer in the circuit structure 104 may also be selectively disposed in the non-package area DAR, and may selectively contact the structural unit 124, but is not limited thereto. Figure 1 In some embodiments, the plurality of electronic components 122 may be disposed between a portion 1240 and another portion 1242 of the structural unit 124 in the direction X (or the direction Y), but is not limited thereto.

[0056] The structural unit 124 has a first thermal expansion coefficient, one of the plurality of conductive layers in the circuit structure 104 (for example, one of the conductive layer 108, the conductive layer 112, the conductive layer 116, and the conductive layer 120) has a second thermal expansion coefficient, and the first thermal expansion coefficient and the second thermal expansion coefficient are different, for example, a ratio of the first thermal expansion coefficient to the second thermal expansion coefficient (first thermal expansion coefficient / second thermal expansion coefficient) is greater than or equal to 1.2 and less than or equal to 2. By designing the ratio of the first thermal expansion coefficient to the second thermal expansion coefficient, the warping direction of the structure in the non-packaging area DAR can be, for example, opposite to the warping direction of the structure in the packaging area PAR, thereby suppressing the warping of the overall structure.

[0057] like Figure 1 When the structure unit 124 is disposed in the first region R1, or when the structure unit 124 is disposed on one side (e.g., the upper side) of the circuit structure 104 in the direction V (i.e., the direction perpendicular to the surface 100S of the carrier 100), or when the structure unit 124 at least partially overlaps with the plurality of electronic components 122 in the direction parallel to the surface 100S of the carrier 100 (e.g., the direction X or the direction Y), a ratio of the first thermal expansion coefficient of the material of the structure unit 124 to the second thermal expansion coefficient of the material of one of the conductive layers in the circuit structure 104 (the first thermal expansion coefficient / the second thermal expansion coefficient) is greater than or equal to 1.2 and less than or equal to 2, but is not limited thereto. The above ratio may also be greater than or equal to 1.3 and less than or equal to 1.9, or may be greater than or equal to 1.4 and less than or equal to 1.8. When the material of the structure unit 124 and the material of one of the conductive layers in the circuit structure 104 meet the above ratio range of the thermal expansion coefficients, the warping of the overall structure can be effectively suppressed, thereby improving the yield or reliability of the electronic device.

[0058] In some embodiments, the structural unit 124 may include copper, aluminum, copper alloy, other suitable metal materials with high thermal expansion coefficient, or a combination thereof, but not limited thereto. In some embodiments, the first thermal expansion coefficient of the structural unit 124 may be greater than or equal to 20.4 ppm / °C and less than or equal to 34 ppm / °C, but not limited thereto. In some embodiments, the first thermal expansion coefficient of the structural unit 124 may be greater than or equal to 22 ppm / °C and less than or equal to 32 ppm / °C, but not limited thereto. In some embodiments, the first thermal expansion coefficient of the structural unit 124 may be greater than or equal to 20 ppm / °C and less than or equal to 30 ppm / °C, but not limited thereto.

[0059] Next, a packaging layer 126 is formed on the electronic element 122, the structural unit 124 and the circuit structure 104. By setting the packaging layer 126, it is possible to reduce the contact or penetration of water vapor or oxygen with the corresponding element, thereby improving the reliability of the element or stacking. According to some embodiments, the packaging layer 126 may include organic resin, epoxy resin, epoxy molding compound (EMC), ceramic, poly(methyl methacrylate) (PMMA), polydimethylsiloxane (PDMS), other suitable materials or combinations of the above materials, but is not limited thereto.

[0060] Then, if Figure 2 , removable Figure 1 Then, the release layer 102 and the carrier 100 are formed. Figure 3 The electronic components 122 and the structural units 124 can be separated from each other by a cutting process, and the cutting process can be cut along the direction V, and a plurality of electronic devices 10 can be obtained after the cutting process. The cutting process can include a laser cutting process or other suitable cutting processes, but is not limited thereto.

[0061] like Figure 3 Each electronic device 10 may include at least one electronic component 122, a packaging layer portion 1260 corresponding to the at least one electronic component 122, and a circuit structure portion 1040 corresponding to the electronic component 122, wherein the packaging layer portion 1260 is Figure 2 The encapsulation layer 126 is a part of the circuit structure portion 1040. Figure 2 In the figures of the similar embodiment of the present case, although the electronic components 122 in the plurality of electronic devices 10 obtained after the cutting process are electrically connected to the circuit structure 1040 only through one connecting conductive material 119, this is only an example, and in fact, the electronic components 122 in the electronic device 10 can be electrically connected to the circuit structure 1040 through multiple connecting conductive materials 119.

[0062] In addition, the structural unit 124 (such as the portion 1240 and the portion 1242), the packaging layer portion 1262 corresponding to the structural unit 124, and the circuit structure portion 1042 corresponding to the structural unit 124 can be selectively removed. Figure 2 The encapsulation layer 126 is a part of the circuit structure portion 1042. Figure 2 A part of the circuit structure 104, but not limited to this.

[0063] Therefore, in some embodiments, the manufacturing method of the electronic device 10 may include but is not limited to the following steps:

[0064] Step S101: providing a carrier board;

[0065] Step S103: disposing a circuit structure on the carrier, which includes alternately disposing a plurality of conductive layers and a plurality of insulating layers on the carrier, and two adjacent ones of the plurality of conductive layers are electrically connected through a plurality of through holes in one of the plurality of insulating layers; and

[0066] Step S105: A structural unit is set on one side of the circuit structure, wherein the structural unit has a first thermal expansion coefficient, one of the conductive layers in the circuit structure has a second thermal expansion coefficient, and a ratio of the first thermal expansion coefficient to the second thermal expansion coefficient is greater than or equal to 1.2 and less than or equal to 2.

[0067] The electronic device and the manufacturing method of the present invention are not limited to the above-mentioned embodiments. Other embodiments of the present invention will be disclosed below. However, in order to simplify the description and highlight the differences between the embodiments, the present invention uses the same reference numerals to mark the same elements and does not repeat the repeated parts.

[0068] Please refer to Figures 5 to 7 , Figures 5 to 7 FIG. 1 is a schematic diagram of a method for manufacturing an electronic device according to a second embodiment of the present invention. The difference from the first embodiment is that, in this embodiment, a plurality of electronic components 122 and structural units 124 are provided before the circuit structure 104 is provided. In this embodiment, Figure 5, firstly, a carrier 100 is provided, and a release layer 102 is formed on the carrier 100. Then, a plurality of electronic components 122 and a structural unit 124 are arranged on the release layer 102. The plurality of electronic components 122 and the structural unit 124 at least partially overlap in a direction parallel to the surface 100S of the carrier 100 (such as direction X or direction Y), and the plurality of electronic components 122 and the structural unit 124 do not overlap in a direction perpendicular to the surface 100S of the carrier 100 (such as direction V). A plurality of insulating structures 123 may be respectively arranged between the electronic components 122 and the release layer 102 or between the electronic components 122 and the carrier 100. The plurality of insulating structures 123 may be separated from each other and have no contact, and overlap on different electronic components 122, but is not limited thereto. The insulating structure 123 may include an insulating material (such as an inorganic or organic insulating material), but is not limited thereto. In some embodiments, the insulating structure 123 may include an ABF (Ajinomoto Build-Up Film) carrier, but is not limited thereto. Next, a packaging layer 126 is formed on the electronic components 122 and the structural units 124, and the packaging layer 126 can cover a plurality of electronic components 122 and the structural units 124. Next, a release layer 128 and a carrier board 130 are sequentially formed on the packaging layer 126.

[0069] Next, you can Figure 5 The structure is flipped 180 degrees and the release layer 102 and the carrier 100 are removed. Figure 6 , forming the circuit structure 104 on the electronic element 122 and the structural unit 124. For example, the conductive layer 108, the insulating layer 110, the through hole 1101 in the insulating layer 110, the conductive layer 112, the insulating layer 114, the through hole 1141 in the insulating layer 114, the conductive layer 116, the insulating layer 118, the through hole 1181 in the insulating layer 118 and the conductive layer 120 may be formed in sequence on the insulating structure 123 and the structural unit 124, but the present invention is not limited thereto. The arrangement of the circuit structure 104 may refer to the aforementioned Figure 1 In this embodiment, when an insulating structure 123 is provided between the circuit structure 104 and the electronic element 122, the boundary between the first region R1 and the second region R2 may be the interface between the insulating layer 110 and the insulating structure 123, but the present invention is not limited thereto. The conductive layer 108 may include a plurality of electrodes 108e, and the electronic element 122 may be electrically connected to the electrode 108e of the conductive layer 108 through a conductive connection 125 formed in the insulating structure 123, but the present invention is not limited thereto.

[0070] In addition, the conductive layer 120 may include a plurality of contact pads 120p, but the present invention is not limited thereto. In the direction X (or direction Y), the width of the contact pad 120p may be greater than the width of the electrode 108e, and the contact pad 120p and the electrode 108e may partially overlap, but the present invention is not limited thereto. Figure 6), the structural unit 124 may at least partially overlap with a portion of the insulating structure 123, the conductive connector 125 and / or the electronic component 122 in a direction parallel to the surface 130S of the carrier 130 (such as direction X or direction Y), but is not limited thereto.

[0071] In this embodiment, in the cross-sectional view, the maximum thickness 124T of the structure unit 124 may be greater than or equal to the maximum thickness 122T of the electronic component 122. In some embodiments, in the cross-sectional view, the maximum thickness 124T of the structure unit 124 may not be equal to the maximum thickness 122T of the electronic component 122. In some embodiments, in the cross-sectional view, the ratio of the maximum thickness 126T of the encapsulation layer 126 to the maximum thickness 124T of the structure unit 124 may be greater than or equal to 1.5 and less than or equal to 6, or may be greater than or equal to 2 and less than or equal to 5, but is not limited thereto. In other embodiments (not shown), in the cross-sectional view, the maximum thickness 124T of the structure unit 124 may be less than the maximum thickness 122T of the electronic component 122. In some embodiments, in the cross-sectional view, the shape of the structure unit 124 may be rectangular, but is not limited thereto, and may be adjusted to other shapes (trapezoidal), arc-edged, or irregular shapes according to needs.

[0072] like Figure 6 When the structure unit 124 is disposed in the first region R1, or when the structure unit 124 is disposed on one side (such as the lower side) of the circuit structure 104 in the direction V perpendicular to the surface 130S of the carrier 130, or when the structure unit 124 at least partially overlaps with the plurality of electronic components 122 in the direction (such as the direction X or the direction Y) parallel to the surface 130S of the carrier 130, the ratio of the first thermal expansion coefficient of the material of the structure unit 124 to the second thermal expansion coefficient of the material of one of the conductive layers in the circuit structure 104 is greater than or equal to 1.2 and less than or equal to 2, but is not limited thereto. The above ratio may also be greater than or equal to 1.3 and less than or equal to 1.9, or may be greater than or equal to 1.4 and less than or equal to 1.8. When the material of the structure unit 124 and the material of one of the conductive layers in the circuit structure 104 meet the above ratio range of the thermal expansion coefficients, the warping of the overall structure can be suppressed, thereby improving the yield or reliability of the product. The material of the structural unit 124 and the material of the conductive layer in the circuit structure 104 have been described in the first embodiment and will not be described in detail herein.

[0073] Next, the release layer 128 and the carrier 130 may be removed. Figure 7, the electronic component 122 and the structural unit 124 can be separated from each other by a cutting process, the cutting process can be cut along the direction V, and a plurality of electronic devices 10 can be obtained after the cutting process. For example, each electronic device 10 may include at least one electronic component 122, a packaging layer portion 1260 corresponding to the at least one electronic component 122, and a circuit structure portion 1040 corresponding to the electronic component 122, the packaging layer portion 1260 is Figure 6 The encapsulation layer 126 is a part of the circuit structure portion 1040. Figure 6 A part of the circuit structure 104, but not limited to this.

[0074] In addition, the structural unit 124 (such as the portion 1240 and the portion 1242), the encapsulation layer portion 1262 corresponding to the structural unit 124, and the circuit structure portion 1042 corresponding to the structural unit 124 can be removed. Figure 6 Another part of the packaging layer 126, and the circuit structure portion 1042 is Figure 6 Another part of the circuit structure 104, but not limited to this.

[0075] In the figures of similar embodiments of the present case, although the electronic components 122 in the multiple electronic devices 10 are electrically connected to the circuit structure 1040 only through one conductive connecting member 125 after the cutting process, this is only an example. In fact, the electronic components 122 in the electronic device 10 can be electrically connected to the circuit structure 1040 through multiple conductive connecting members 125.

[0076] Please refer to Figures 8 to 11 , Figures 8 to 10 FIG. 1 is a schematic diagram of a method for manufacturing an electronic device according to a third embodiment of the present invention. Fig.11 FIG. 1 is a flowchart of the steps of the method for manufacturing an electronic device according to the third embodiment. It should be understood that Fig.11 The steps shown in the embodiment may not be exhaustive, and other steps may be performed before, after, or between any of the steps shown. In addition, some steps may be performed simultaneously or in a sequential manner. Fig.11 The difference from the first embodiment is that the structure unit 124 of this embodiment can be arranged in the second region R2, or the structure unit 124 can be arranged in the circuit structure 104.

[0077] First, if Figure 8 , step S201 may be performed to provide a carrier 100, and then a release layer 102 may be formed on the carrier 100. Then, step S203 may be performed to arrange a circuit structure 104 and a structural unit 124 on the carrier 100, and the structural unit 124 may be arranged in the circuit structure 104. Figure 8, multiple conductive layers and multiple insulating layers may be alternately disposed on the carrier 100, and two adjacent ones of the multiple conductive layers are electrically connected through multiple through holes in one of the multiple insulating layers. For example, the insulating layer 106, the conductive layer 108, the insulating layer 110, the through hole 1101 in the insulating layer 110, the conductive layer 112, the insulating layer 114, the through hole 1141 in the insulating layer 114, the conductive layer 116, the insulating layer 118, the through hole 1181 in the insulating layer 118, and the conductive layer 120 may be sequentially formed on the carrier 100, but the present invention is not limited thereto. The number of stacking layers of the conductive layer and the insulating layer may be adjusted according to requirements, and the order of the above-mentioned processes is only an example and may be adjusted according to requirements.

[0078] In addition, when forming any insulating layer (such as the insulating layer 114) in the circuit structure 104, at least one opening (such as the opening 114O) may be formed in the insulating layer (such as the insulating layer 114), and the at least one opening (such as the opening 114O) is located in the non-encapsulation area DAR. Then, a structural unit 124 is formed in the at least one opening (such as the opening 114O), that is, the structural unit 124 may be disposed in the insulating layer 114 and disposed in the non-encapsulation area DAR. In the cross-sectional view, the maximum thickness 124T of the structural unit 124 and the thickness (not indicated) of the opening 114O of the insulating layer where the structural unit 124 is located may be the same or different. It should be noted that the shape of the at least one opening (such as the opening 114O) formed in any insulating layer (such as the insulating layer 114) is exemplified as a rectangle, but is not limited thereto, and may be adjusted to other shapes according to needs, such as a trapezoid, or having an arc edge or an irregular shape. In some embodiments, in the cross-sectional view, the shape of the structural unit 124 may be a rectangle, but is not limited thereto, and may be adjusted to other shapes such as a trapezoid, or a shape with curved edges or an irregular shape according to needs.

[0079] There are many ways to dispose the structural unit 124 in the second region R2. The structural unit 124 can be disposed in at least one insulating layer in the circuit structure 104. For example, the structural unit 124 can be disposed in an opening of at least one layer of the insulating layer 110, the insulating layer 114, and the insulating layer 118, or the structural unit 124 can be disposed in an opening of any two layers of the insulating layer 110, the insulating layer 114, and the insulating layer 118.

[0080] like Figure 8, the structural unit has a first thermal expansion coefficient, and one of the plurality of conductive layers in the circuit structure 104 has a second thermal expansion coefficient. When the structural unit 124 is disposed in the second region R2, or when the structural unit 124 is disposed in the circuit structure 104, or when the structural unit 124 and the electronic component 122 do not overlap in a direction parallel to the surface 100S of the carrier 100 (such as direction X or direction Y), the ratio of the first thermal expansion coefficient of the material of the structural unit 124 to the second thermal expansion coefficient of the material of one of the conductive layers in the circuit structure 104 (first thermal expansion coefficient / second thermal expansion coefficient) is greater than or equal to 0.1 and less than or equal to 0.8, but is not limited thereto. The above ratio may also be greater than or equal to 0.15 and less than or equal to 0.75, or may be greater than or equal to 0.2 and less than or equal to 0.7. When the material of the structural unit 124 and the material of one of the conductive layers in the circuit structure 104 meet the above ratio range of the thermal expansion coefficients, the warping of the overall structure can be suppressed, thereby improving the yield or reliability of the product.

[0081] In some embodiments, the structural unit 124 may include glass, silicon nitride, silicon oxide, other suitable ceramic materials with low thermal expansion coefficients, or combinations thereof, but not limited thereto. In some embodiments, the first thermal expansion coefficient of the structural unit 124 may be greater than or equal to 1.7 ppm / °C and less than or equal to 13.6 ppm / °C, or may be greater than or equal to 1.7 ppm / °C and less than or equal to 11 ppm / °C, or may be greater than or equal to 1.7 ppm / °C and less than or equal to 9 ppm / °C, or may be greater than or equal to 1.7 ppm / °C and less than or equal to 7 ppm / °C, but not limited thereto. The ratio of the first thermal expansion coefficient of the structural unit 124 to the second thermal expansion coefficient of the material of one of the conductive layers in the circuit structure 104 is designed, and the warping direction of the structure in the non-packaging area DAR may be, for example, opposite to the warping direction of the structure in the packaging area PAR, thereby suppressing the warping of the overall structure.

[0082] Next, after the circuit structure 104 and the structural unit 124 are provided, the electronic component 122 may be provided. For example, the electronic component 122 may be provided on the insulating layer 118 and the conductive layer 120, and the electronic component 122 may be electrically connected to the conductive layer 120 by connecting the conductive material 119, but is not limited thereto. In addition, in the direction perpendicular to the surface 100S of the carrier 100 (direction V) and in the direction parallel to the surface 100S of the carrier 100 (direction X or direction Y), the plurality of electronic components 122 and the structural unit 124 do not overlap. In this embodiment, in the cross-sectional view (the scale is for reference only), the maximum thickness 124T of the structural unit 124 may be less than or equal to the maximum thickness 122T of the electronic component 122. In some embodiments, in the cross-sectional view (the scale is for reference only), the maximum thickness 124T of the structural unit 124 may not be equal to the maximum thickness 122T of the electronic component 122.

[0083] Next, a packaging layer 126 is formed on the electronic element 122. In this embodiment, the first thermal expansion coefficient of the structural unit 124 may be smaller than the thermal expansion coefficient of the packaging layer 126, but is not limited thereto. Fig. 9 , removable Figure 8 Then, the release layer 102 and the carrier 100 are formed. Fig.10 , the electronic component 122 and the structural unit 124 can be separated from each other by a cutting process, and the cutting process can be cut along the direction V. After the cutting process, multiple electronic devices 10 can be obtained, and the structural unit 124 (such as part 1240 and part 1242) are removed. In the figures of the similar embodiment of the present case, although the electronic component 122 in the multiple electronic devices 10 obtained after the cutting process is electrically connected to the circuit structure 1040 only through one connecting conductive material 119, it is only an example. In fact, the electronic component 122 in the electronic device 10 can be electrically connected to the circuit structure 1040 through multiple connecting conductive materials 119.

[0084] Therefore, in some embodiments, the manufacturing method of the electronic device 10 may include but is not limited to the following steps:

[0085] Step S201: providing a carrier board; and

[0086] Step S203: A circuit structure and a structural unit are arranged on a carrier, and the structural unit is arranged in the circuit structure, wherein the circuit structure is arranged including alternately arranging a plurality of conductive layers and a plurality of insulating layers on the carrier, and two adjacent ones of the plurality of conductive layers are electrically connected through a plurality of through holes in one of the plurality of insulating layers, wherein the structural unit has a first thermal expansion coefficient, one of the plurality of conductive layers in the circuit structure has a second thermal expansion coefficient, and a ratio of the first thermal expansion coefficient to the second thermal expansion coefficient is greater than or equal to 0.1 and less than or equal to 0.8.

[0087] Please refer to Figure 12 to Figure 14 , Figure 12 to Figure 14 FIG. 1 is a schematic diagram of a method for manufacturing an electronic device according to a fourth embodiment of the present invention. The difference from the third embodiment is that the electronic component 122 is arranged before the circuit structure 104 is arranged in this embodiment. The difference from the second embodiment is that the structural unit 124 of this embodiment can be arranged in the second region R2, or the structural unit 124 can be arranged in the circuit structure 104. First, as Fig.12 , provide a carrier 100, and form a release layer 102 on the carrier 100. Then, an electronic component 122 is disposed on the release layer 102. The insulating structure 123 can be disposed between the electronic component 122 and the release layer 102 or between the electronic component 122 and the carrier 100. The material of the insulating structure 123 can refer to the aforementioned Figure 5Next, a packaging layer 126 is formed on the electronic element 122 and the structural unit 124. Next, a release layer 128 and a carrier 130 are sequentially formed on the packaging layer 126.

[0088] Next, you can Fig.12 The structure is flipped 180 degrees and the release layer 102 and the carrier 100 are removed. Fig.13 , a circuit structure 104 and a structural unit 124 are arranged on the carrier 130. In detail, the circuit structure 104 and the structural unit 124 can be formed on the electronic element 122 and the packaging layer 126. For example, a conductive layer 108, an insulating layer 110, a through hole 1101 in the insulating layer 110, a conductive layer 112, an insulating layer 114, a through hole 1141 in the insulating layer 114, a conductive layer 116, an insulating layer 118, a through hole 1181 in the insulating layer 118, and a conductive layer 120 can be sequentially formed on the insulating structure 123 and the packaging layer 126, but the present invention is not limited thereto. The number of stacking layers of the conductive layer and the insulating layer can be adjusted according to requirements, and the order of the above process is only an example and can be adjusted according to requirements.

[0089] In addition, when forming any insulating layer (e.g., insulating layer 114) in the circuit structure 104, at least one opening (e.g., opening 114O) may be formed in the insulating layer (e.g., insulating layer 114), and the at least one opening (e.g., opening 114O) is located in the non-encapsulation region DAR. Then, a structural unit 124 is formed in the at least one opening (e.g., opening 114O), that is, the structural unit 124 may be disposed in the insulating layer 114 and disposed in the non-encapsulation region DAR. In the cross-sectional view, the maximum thickness 124T of the structural unit 124 may be the same as or different from the maximum thickness of the opening (e.g., opening 114O) of the insulating layer where the structural unit 124 is located.

[0090] There are many ways to dispose the structural unit 124 in the second region R2. The structural unit 124 can be disposed in at least one insulating layer in the circuit structure 104. For example, the structural unit 124 can be disposed in an opening of at least one layer of the insulating layer 110, the insulating layer 114, and the insulating layer 118, or the structural unit 124 can be disposed in an opening of any two layers of the insulating layer 110, the insulating layer 114, and the insulating layer 118.

[0091] like Fig.13, the electronic component 122 and the structure unit 124 do not overlap in the direction V perpendicular to the surface 130S of the carrier 130 and in the direction X (or direction Y) parallel to the surface 130S of the carrier 130, but the present invention is not limited thereto. When the structure unit 124 is disposed in the second region R2, or when the structure unit 124 is disposed in the circuit structure 104, or when the structure unit 124 and the electronic component 122 do not overlap in the direction parallel to the surface 130S of the carrier 130 (such as direction X or direction Y), the ratio of the first thermal expansion coefficient of the material of the structure unit 124 to the second thermal expansion coefficient of the material of one of the conductive layers in the circuit structure 104 (first thermal expansion coefficient / second thermal expansion coefficient) is greater than or equal to 0.1 and less than or equal to 0.8, but the present invention is not limited thereto. The above ratio may also be greater than or equal to 0.15 and less than or equal to 0.75, or may be greater than or equal to 0.2 and less than or equal to 0.7. When the material of the structural unit 124 and the material of one of the conductive layers in the circuit structure 104 meet the above ratio range of thermal expansion coefficients, the warping of the overall structure can be effectively suppressed, thereby improving the yield or reliability of the product.

[0092] In some embodiments, the structural unit 124 may include glass, silicon nitride, silicon oxide, other suitable ceramic materials with low thermal expansion coefficients, or a combination thereof, but not limited thereto. In some embodiments, the first thermal expansion coefficient of the structural unit 124 may be greater than or equal to 1.7 ppm / °C and less than or equal to 13.6 ppm / °C, or may be greater than or equal to 1.7 ppm / °C and less than or equal to 11 ppm / °C, or may be greater than or equal to 1.7 ppm / °C and less than or equal to 9 ppm / °C, or may be greater than or equal to 1.7 ppm / °C and less than or equal to 7 ppm / °C, but not limited thereto. When the material of the structural unit 124 and the material of one of the conductive layers in the circuit structure 104 meet the above-mentioned ratio range of thermal expansion coefficients, the warping direction of the structure in the non-encapsulation area DAR may be, for example, opposite to the warping direction of the structure in the encapsulation area PAR, thereby suppressing the warping of the overall structure.

[0093] Next, the release layer 128 and the carrier 130 may be removed. Fig.14 , the electronic component 122 and the structural unit 124 can be separated from each other by a cutting process, and the cutting process can be cut along the direction V. After the cutting process, multiple electronic devices 10 can be obtained, and the structural unit 124 (such as part 1240 and part 1242) can be removed. In the figures of the similar embodiment of the present case, although the electronic component 122 in the multiple electronic devices 10 obtained after the cutting process is electrically connected to the circuit structure 1040 only through one conductive connecting member 125, it is only an example. In fact, the electronic component 122 in the electronic device 10 can be electrically connected to the circuit structure 1040 through multiple connected conductive connecting members 125.

[0094] Please refer to Fig.15 , Fig.15 FIG. 1 is a schematic structural diagram of a method for manufacturing an electronic device according to a fifth embodiment of the present invention before a cutting process is performed. Fig.15 The structure in the figure may be, for example, a structure after the release layer 128 and the carrier 130 are removed and before the cutting process is performed. In the present embodiment, the structural unit 124 may include a portion 1240, a portion 1241, a portion 1242 and / or a portion 1243. The portion 1240 and the portion 1242 may be, for example, disposed in the first region R1 and located in the non-encapsulation area DAR, and the portion 1240 and the portion 1242 may be, for example, disposed in the second region R2 and located in the non-encapsulation area DAR, but is not limited thereto.

[0095] The portion 1241 and the portion 1243 may be, for example, located in openings of the multi-layer insulation layer in the circuit structure 104, such as in the opening (not labeled) of the insulation layer 114 and the opening (not labeled) of the insulation layer 118. The opening (not labeled) of the insulation layer 114 and the opening (not labeled) of the insulation layer 118 may be, for example, merged into a large opening GO, and the portion 1241 and the portion 1243 may be, for example, located in different openings GO, respectively, but not limited thereto. In other words, the portion 1241 and the portion 1243 may be disposed in the multi-layer insulation layer (such as the insulation layer 114 and the insulation layer 118), but not limited thereto.

[0096] In some embodiments, the thermal expansion coefficient of the material of portion 1240 and / or portion 1242 of structure unit 124 is different from the thermal expansion coefficient of the material of portion 1241 and / or portion 1243 of structure unit 124 .

[0097] In some embodiments, the ratio of the thermal expansion coefficient of the material of the portion 1240 and / or portion 1242 of the structural unit 124 to the thermal expansion coefficient of the material of one of the conductive layers in the circuit structure 104 is greater than or equal to 1.2 and less than or equal to 2, but is not limited thereto. The above ratio may also be greater than or equal to 1.3 and less than or equal to 1.9, or may be greater than or equal to 1.4 and less than or equal to 1.8. In some embodiments, the ratio of the thermal expansion coefficient of the material of the portion 1241 and portion 1243 of the structural unit 124 to the thermal expansion coefficient of the material of one of the conductive layers in the circuit structure 104 is greater than or equal to 0.1 and less than or equal to 0.8, but is not limited thereto. The above ratio may also be greater than or equal to 0.15 and less than or equal to 0.75, or may be greater than or equal to 0.2 and less than or equal to 0.7. Through the design of the above-mentioned portions of the structural unit 124, the warping direction of the structure in the non-encapsulation area DAR and the warping direction of the structure in the encapsulation area PAR can be opposite, thereby suppressing the warping of the overall structure.

[0098] In some embodiments, in direction V, portion 1240 of structure unit 124 may overlap or not overlap portion 1241. In some embodiments, in direction V, portion 1242 of structure unit 124 may overlap or not overlap portion 1243. In some embodiments, in direction X (or direction Y), the width (not labeled) of portion 1240 and the width (not labeled) of portion 1241 may be the same or different. In some embodiments, in direction X (or direction Y), the width (not labeled) of portion 1242 and the width (not labeled) of portion 1243 may be the same or different. In some embodiments, in a cross-sectional view, the maximum thickness (not labeled) of portion 1240 and the maximum thickness (not labeled) of portion 1241 may be the same or different. In some embodiments, in a cross-sectional view, the maximum thickness (not labeled) of portion 1242 and the maximum thickness (not labeled) of portion 1243 may be the same or different. In some embodiments, in the cross-sectional view, the maximum thickness (not labeled) of the portion 1240 or the portion 1242 may be greater than or equal to the maximum thickness (not labeled) of the electronic component 122. In some embodiments, in the cross-sectional view and in the direction X, the minimum distance between the portion 1240 (or the portion 1242) and the electronic component 122 may be different from (e.g., greater than or less than) the minimum distance between adjacent electronic components 122.

[0099] Please refer to Fig.16 , Fig.16 FIG. 1 is a schematic top view of a sixth embodiment of the present invention in which a structural unit and an electronic component are arranged on a carrier. In some embodiments, in a top view (such as in direction V) or in a top view (such as in direction V) of the electronic component 122 and the structural unit 124, Fig.16 ), multiple parts of the structure unit 124 (such as the oblique line part) can surround the electronic component 122. Compared with the corner warping amount generated by the design without the structure unit 124 and the electronic components 122 are arranged all over the carrier 100, the design of this embodiment can reduce the corner warping amount. In some embodiments, the multiple electronic components 122 can be arranged in sequence along the direction X and the direction Y, for example, and the multiple electronic components 122 can be arranged in an array, but is not limited thereto. In some embodiments, the multiple parts of the structure unit 124 can be arranged in sequence along the direction X and the direction Y, for example. In the top view, the multiple parts of the structure unit 124 can, for example, surround the multiple electronic components 122. Fig.16 The arrangement of the multiple electronic components 122 and the multiple parts of the multi-structure unit 124 is only an example, and can be designed differently according to the appearance or size of the carrier 100. It should be noted that Fig.16 The top view diagram can be applied to the above Figures 1 to 15 Any embodiment of the invention.

[0100] In some embodiments, multiple parts (such as the oblique line parts) of the structural unit 124 can be connected to each other to form a ring-shaped structural unit, but is not limited thereto. For example, Fig.16 A virtual line A1 (e.g., a virtual line extending along direction Y) passes through a plurality of electronic components 122 and portions of two structural units 124, but is not limited thereto. The number of portions of the structural units 124 that the virtual line A1 passes through may vary according to the design. For example, Fig.16 The virtual line A2 in FIG. 1 (e.g., a virtual line extending along the direction X) passes through a plurality of electronic components 122 and portions of two structural units 124, but is not limited thereto. The number of portions of the structural units 124 through which the virtual line A2 passes may vary according to the design. In some embodiments, portions of a plurality of structural units 124 may be connected to each other.

[0101] Please refer to Fig.17 , Fig.17 Shown is a top view schematic diagram of the seventh embodiment of the present invention in which the structural units and electronic components are arranged on a carrier. In some embodiments, the carrier 100 may include two diagonal areas (such as a diagonal area DG1 and a diagonal area DG2), and at least a portion of the structural unit 124 is located in the two diagonal areas. For example, a portion of the structural unit 124 may be located in the diagonal area DG1, and another portion of the structural unit 124 may be located in the diagonal area DG2. In some embodiments, the shape of the structural unit 124 may be approximately X-shaped, but is not limited to this. Compared to the corner warping caused by a design without a structural unit 124 and in which the electronic components 122 are distributed throughout the carrier 100, the design of this embodiment can reduce the warping of the corners and the warping of the edges, thereby reducing the overall warping. It should be noted that Fig.17 The top view diagram can be applied to the above Figures 1 to 15 Any embodiment of the invention.

[0102] In some embodiments, the carrier 100 may be a non-rectangular shape (e.g., a circle, an ellipse, a polygon, or an irregular shape). In this case, a minimum virtual rectangle that can frame the carrier can be defined, and the diagonal lines of the virtual rectangle are used to define the diagonal areas DG1 and DG2.

[0103] Please refer to Fig.18 , Fig.18 FIG. 8 is a top view of the structure unit and the electronic components of the eighth embodiment of the present invention disposed on the carrier. The difference from the seventh embodiment is that the area occupied by the structure unit 124 in the diagonal area DG1 and the diagonal area DG2 of the eighth embodiment is smaller, and the overall number of electronic components 122 can be increased, so that the yield can be higher.

[0104] like Fig.18As shown, the electronic components 122 and the parts of the structural unit 124 (such as the oblique line parts) can be arranged as follows: a diagonal line DA can be defined on the carrier 100, and the diagonal line DA can extend from the upper right corner of the carrier 100 to the lower left corner of the carrier 100, that is, the diagonal line DA can be a connecting line of two diagonals of the carrier 100. In addition, the carrier 100 is divided into a plurality of sub-units 100U, and taking one of the sub-units 100U as an example, the sub-unit 100U can be divided into four equal parts along a direction perpendicular to the diagonal line DA (such as part Qa, part Qb, part Qc and part Qd arranged in sequence).

[0105] When the diagonal line DA passes through the portion Qb or the portion Qc located in the middle, it means that the warpage can be effectively reduced when a portion of the structural unit 124 is set in this sub-unit 100U, but it is not limited to this. Compared with the diagonal line DA passing through the portion Qb or the portion Qc located in the middle, when the diagonal line DA passes through the portion Qa or the portion Qd, it means that the degree of reduction in warpage when a portion of the structural unit 124 is set in this sub-unit 100U is smaller. If production capacity is considered, this sub-unit 100U may, for example, give priority to setting the electronic component 122, but it is not limited to this. By designing the layout of the portion of the structural unit 124 and the electronic component 122 according to this rule, in addition to reducing the warpage of the overall structure, the number of electronic components 122 that can be set can be increased. For example, compared to a design without a portion of the structural unit 124 and distributing the electronic components 122 throughout the entire carrier 100, the number of electronic components 122 in this embodiment can be reduced by only about 7.7%, but the warpage of the corners and the edge can also be reduced, thereby reducing the overall warpage. It should be noted that Fig.18 The top view diagram can be applied to the above Figures 1 to 15 Any embodiment of the invention.

[0106] Please refer to Fig.19 and Fig. 20 , Fig.19 FIG. 1 is a schematic top view of a structural unit and electronic components in an electronic device according to a ninth embodiment of the present invention. Fig. 20 FIG. 2 is a cross-sectional schematic diagram of an electronic device according to a ninth embodiment of the present invention. Fig.19, the electronic device 10 may include a plurality of electronic components, such as an electronic component 1320, an electronic component 1322, an electronic component 1324 and / or an electronic component 1326, but not limited thereto, and the number of electronic components may be increased or decreased according to demand. For example, the electronic component 1320 may be a Micro Electro Mechanical Systems (MEMS) component, the electronic component 1322 may be a Radio Frequency (RF) component, the electronic component 1324 may be a memory component, and the electronic component 1326 may be a logic component, but not limited thereto, and the types or functions of the above electronic components may be adjusted according to demand, and the arrangement relationship or size relationship of the above electronic components is only an example and may be adjusted according to demand.

[0107] The structure unit 124 is disposed adjacent to a plurality of electronic components, for example, adjacent to the electronic component 1320, the electronic component 1322, the electronic component 1324, and the electronic component 1326. When viewed from a top view direction (for example, direction V) of the electronic device or in a top view, at least a portion of the structure unit 124 is located between two adjacent electronic components. Fig.19 Different parts of the structural unit 124, such as the left side part (diagonal part) or the right side part (diagonal part) of multiple electronic components, can be arranged on both sides of at least two adjacent electronic components in direction X, and different parts of the structural unit 124, such as the left side part (diagonal part) or the right side part (diagonal part) of multiple electronic components can respectively include parts arranged along direction Y, but are not limited to this.

[0108] Fig. 20 The cross-sectional structure can correspond to Fig.19 The electronic device 10 may include a circuit structure 104, and a plurality of electronic components (eg, electronic component 1320, electronic component 1322, electronic component 1324, and electronic component 1326) are electrically connected to the circuit structure 104. Fig. 20 , a plurality of electronic components (e.g., electronic component 1320, electronic component 1322, electronic component 1324, and electronic component 1326) overlap with the circuit structure 104. The circuit structure 104 includes a plurality of conductive layers and at least one insulating layer, and the conductive layers are electrically connected through a plurality of through holes in the insulating layer. For example, the circuit structure 104 may include a conductive layer 108, an insulating layer 110, a through hole 1101 in the insulating layer 110, a conductive layer 112, an insulating layer 114, a through hole 1141 in the insulating layer 114, a conductive layer 116, an insulating layer 118, a through hole 1181 in the insulating layer 118, and a conductive layer 120, but is not limited thereto. The method for manufacturing the circuit structure 104 may refer to the previous embodiment.

[0109] In addition, the conductive layer 108 may include a plurality of contact pads, and the electronic device 10 may include a plurality of solder elements 134 (e.g., solder balls) disposed on one side of the contact pads of the conductive layer 108 and electrically connected to the conductive layer 108. The plurality of electronic elements and the structural unit 104 at least partially overlap on a cross section S of the cross section of the electronic device, and the cross section S is, for example, substantially parallel to the surface of any insulating layer or any conductive layer in the circuit structure 104 of the electronic device 10. The cross section S of the cross section is substantially parallel to the plane formed by the direction X and the direction Y.

[0110] The structure unit 124 has a first thermal expansion coefficient, one of the plurality of conductive layers in the circuit structure 104 has a second thermal expansion coefficient, and a ratio of the first thermal expansion coefficient to the second thermal expansion coefficient is greater than or equal to 1.2 and less than or equal to 2.

[0111] In some embodiments, electronic component 1320, electronic component 1322, electronic component 1324 and electronic component 1326 may be electrically connected to circuit structure 104 via at least one interposer (not shown), and the interposer (not shown) may be disposed between circuit structure 104 and a plurality of electronic components (e.g., electronic component 1320, electronic component 1322, electronic component 1324 and electronic component 1326), but is not limited thereto.

[0112] In the present embodiment, the structural unit 124 may be disposed in the first region R1, and the structural unit 124 may be selectively electrically connected to the conductive layer in the circuit structure 104, but is not limited thereto. In the present embodiment, the encapsulation layer 126 may be disposed adjacent to the structural unit 124 and a plurality of electronic components (e.g., electronic components 1320, 1322, 1324, or 1326), and the encapsulation layer 126 may at least surround the side surfaces of the structural unit 124 and the plurality of electronic components (e.g., electronic components 1320, 1322, 1324, or 1326), and the surface of the encapsulation layer 126 away from the circuit structure 104 may be, for example, substantially flush with the plurality of electronic components (e.g., electronic components 1320, 1322, 1324, and 1326) or the structural unit 124, but is not limited thereto.

[0113] In this embodiment, a heat dissipation element HS may be disposed on the packaging layer 126, the structural unit 124, and a plurality of electronic components (e.g., electronic components 1320, 1322, 1324, and 1326), and an adhesive material CM may be selectively disposed between the heat dissipation element HS and the packaging layer 126, the structural unit 124, and the plurality of electronic components. The adhesive material CM may be used to fix the heat dissipation element HS to the structural unit 124 and the plurality of electronic components.

[0114] In some embodiments, the attachment material CM (e.g., conductive silver paste or other suitable materials) may have conductive properties, but is not limited thereto. The attachment material CM may contact the heat dissipation element HS, the structural unit 124, and multiple electronic components. The heat dissipated by the multiple electronic components is transferred to the heat dissipation element HS through the attachment material CM to conduct the heat away, but is not limited thereto. In some embodiments, the heat dissipation element HS, for example, includes a metal plate, and its material includes, for example, aluminum, copper, other metal materials, or a combination thereof. In some embodiments, the heat dissipation element HS, for example, includes heat dissipation materials related to other non-metallic materials.

[0115] In some embodiments, the structural unit 124 may have good thermal conductivity, for example, including metal materials, such as aluminum, copper, other metal materials, or a combination thereof. The thermal conductivity of the structural unit 124 may be greater than or equal to 200W / mK and less than or equal to 600W / mK, but is not limited thereto. The thermal conductivity of the structural unit 124 may be greater than or equal to 250W / mK and less than or equal to 550W / mK, or may be greater than or equal to 250W / mK and less than or equal to 500W / mK, or may be greater than or equal to 300W / mK and less than or equal to 450W / mK. In some embodiments, the thermal conductivity of the structural unit 124 may be greater than or equal to the thermal conductivity of the electronic component (e.g., the electronic component 1320, the electronic component 1322, the electronic component 1324, or the electronic component 1326). In some embodiments, the thermal conductivity of the structural unit 124 may be greater than or equal to the thermal conductivity of the packaging layer 126.

[0116] In other embodiments (not shown), the structural unit 124 may be disposed in the second region R2, or the structural unit 124 may be embedded in the circuit structure 104, the structural unit 124 has a first thermal expansion coefficient, one of the multiple conductive layers in the circuit structure 104 has a second thermal expansion coefficient, and a ratio of the first thermal expansion coefficient to the second thermal expansion coefficient is greater than or equal to 0.1 and less than or equal to 0.8. The selection of the material, the design of the thermal expansion coefficient, or the design of the size (such as the maximum thickness) of the structural unit 124 disposed in the second region R2 can refer to the above. There are many ways to dispose the structural unit 124 in the second region R2. The structural unit 124 can be disposed in an opening of at least one insulating layer in the circuit structure 104, and the details can refer to the above.

[0117] The structural unit 124 can suppress the warping of the overall structure, or can be used to transfer heat energy and conduct the heat energy to the heat dissipation element HS, but is not limited thereto. When the structural unit 124 is disposed in the first region R1, or when the structural unit 124 is disposed on one side (e.g., the upper side) of the circuit structure 104 in the direction V, or when the structural unit 124 at least partially overlaps with a plurality of electronic components (e.g., the electronic component 1320, the electronic component 1322, the electronic component 1324, or the electronic component 1326) in the direction X (or the direction Y), a ratio of a first thermal expansion coefficient of a material of the structural unit 124 to a second thermal expansion coefficient of a material of one of the conductive layers in the circuit structure 104 (the first thermal expansion coefficient / the second thermal expansion coefficient) can be greater than or equal to 1.2 and less than or equal to 2, but is not limited thereto, and the above ratio can also be greater than or equal to 1.3 and less than or equal to 1.9, or can be greater than or equal to 1.4 and less than or equal to 1.8.

[0118] When the material of the structural unit 124 and the material of one of the conductive layers in the circuit structure 104 meet the above-mentioned ratio range of the thermal expansion coefficient, the warping of the overall structure can be suppressed, thereby improving the yield or reliability of the product. In some embodiments, when the structural unit 124 is disposed in the first region R1, the structural unit 124 may include a passive element such as a capacitor, a resistor, or an inductor, but is not limited thereto. In some embodiments, the passive element may be electrically connected to the circuit structure 104, but is not limited thereto.

[0119] In some embodiments (not shown), when the structural unit 124 is disposed in the second region R2, or when the structural unit 124 is embedded in the circuit structure 104, or when the structural unit 124 and multiple electronic components do not overlap in direction X (or direction Y), the ratio of the first thermal expansion coefficient of the material of the structural unit 124 to the second thermal expansion coefficient of the material of one of the conductive layers in the circuit structure 104 may be greater than or equal to 0.1 and less than or equal to 0.8, but is not limited to this. The above ratio may also be greater than or equal to 0.15 and less than or equal to 0.75, or may be greater than or equal to 0.2 and less than or equal to 0.7.

[0120] Please refer to Fig.21 and Fig. 22 , Fig.21 FIG. 1 is a top view of a structural unit and electronic components in an electronic device according to a tenth embodiment of the present invention. Fig. 22FIG. 1 is a cross-sectional schematic diagram of an electronic device according to a tenth embodiment of the present invention. The difference from the ninth embodiment is that, in the top view of the electronic device 10 of this embodiment, a portion of the structural unit 124 may be located in the diagonal area DG1, another portion of the structural unit 124 may be located in the diagonal area DG2, and at least a portion of the structural unit 124 may be located between two adjacent electronic components (e.g., electronic component 1320, electronic component 1322, electronic component 1324, and electronic component 1326). For example, a portion 1244 of the structural unit 124 may be located between the electronic component 1320 and the electronic component 1326 in the direction X. For example, a portion 1244 of the structural unit 124 may be located between the electronic component 1322 and the electronic component 1324 in the direction Y, but is not limited thereto.

[0121] In addition, a portion 1245 of the structural unit 124 may be located between the electronic component 1320 and the electronic component 1324 in the direction Y, and a portion 1246 of the structural unit 124 may be located between the electronic component 1322 and the electronic component 1320 in the direction Y. A portion 1247 of the structural unit 124 may be located between the electronic component 1324 and the electronic component 1326 in an oblique direction, and a portion 1248 of the structural unit 124 may be located between the electronic component 1322 and the electronic component 1326 in another oblique direction, and the oblique direction is not parallel to the direction X and the direction Y, and the oblique direction is perpendicular to the direction V. For example, the angle between the oblique direction and the direction X may be about 45 degrees.

[0122] In some embodiments, in the direction X (or direction Y), the maximum width of the portion 1244 may be less than or equal to the maximum width of the electronic component 1322 and / or the maximum width of the electronic component 1324, but not limited thereto. In some embodiments, in the cross-sectional view, the maximum thickness of the portion 1244 may be less than or equal to the maximum thickness of the electronic component 1322 and / or the thickness of the electronic component 1324, but not limited thereto. In some embodiments (not shown), in the cross-sectional view, the maximum thickness of the portion 1244 may be greater than or equal to the maximum thickness of the electronic component 1322 and / or the maximum thickness of the electronic component 1324, but not limited thereto. In some embodiments, in the cross-sectional view, the maximum thickness of the electronic component 1322 and the maximum thickness of the electronic component 1324 may be the same or different. In some embodiments, in the top view, portions of the plurality of structural units 124 (including the portion 1244) are located between two adjacent electronic components. In some embodiments, the spacing between the structural unit 124 and the electronic components (e.g., the electronic components 1320, 1322, 1324, and 1326) in the direction X or direction Y is greater than 0. In some embodiments (not shown), Fig. 22 The electronic device may also be similar to Fig. 20The structural unit 124 may be selectively electrically connected to the circuit structure 104, but is not limited thereto.

[0123] Fig. 22 The cross-sectional structure can correspond to Fig.21 In the tangent line BB' in FIG, the structural unit 124 of the present embodiment is disposed in the first region R1, and a portion of the structural unit 124 (e.g., portion 1244) is disposed on one side (e.g., the upper side) of the circuit structure 104 in the direction V. Another portion of the structural unit 124 (e.g., portion 1244-1) is disposed in the second region R2 in the direction V. In some embodiments, a portion of the structural unit 124 (e.g., portion 1244) and a plurality of electronic components (e.g., electronic components 1320, electronic components 1322, electronic components 1324, and electronic components 1326) may at least partially overlap in the direction X or direction Y (i.e., a direction perpendicular to the top-view direction (direction V)), and the structural unit 124 and the plurality of electronic components (e.g., electronic components 1320, electronic components 1322, electronic components 1324, and electronic components 1326) do not overlap in the top-view direction (e.g., direction V).

[0124] exist Fig. 22 In an embodiment (not shown), the structural unit 124 (e.g., portion 1244) may be selectively electrically connected to the circuit structure 104, but is not limited thereto. Similarly, the encapsulation layer 126 may be disposed adjacent to the structural unit 124 and a plurality of electronic components (e.g., electronic components 1320, 1322, 1324, and 1326), and the encapsulation layer 126 may at least surround the side surfaces of the structural unit 124 (e.g., portion 1244) and a plurality of electronic components (e.g., electronic components 1320, 1322, 1324, and 1326).

[0125] Although Fig. 22 Not shown, but may be similar to Fig. 20 The surface of the encapsulation layer 126 away from the circuit structure 104 may be selectively substantially aligned with the plurality of electronic components (eg, the electronic component 1320 , the electronic component 1322 , the electronic component 1324 , and the electronic component 1326 ) or the structural unit 124 .

[0126] Although Fig. 22 Not shown, but may be similar to Fig. 20 The heat dissipation element HS can be selectively disposed on the packaging layer 126, the structural unit 124 and the plurality of electronic components, and the adhesive material CM can be selectively disposed between the heat dissipation element HS and the packaging layer 126, the structural unit 124 and the plurality of electronic components. The materials or properties of the adhesive material CM and the heat dissipation element HS can be referred to above.

[0127] In some embodiments, the structural unit 124 (e.g., portion 1244-1) may be disposed in the second region R2, or the structural unit 124 (e.g., portion 1244-1) may be embedded in the circuit structure 104, and the selection of the material, the design of the thermal expansion coefficient, or the design of the size (e.g., the maximum thickness) of the structural unit 124 (e.g., portion 1244-1) disposed in the second region R2 may refer to the above. The structural unit 142 (e.g., portion 1244-1) has a first thermal expansion coefficient, one of the plurality of conductive layers in the circuit structure has a second thermal expansion coefficient, and a ratio of the first thermal expansion coefficient to the second thermal expansion coefficient is greater than or equal to 0.1 and less than or equal to 0.8. There may be multiple ways to dispose the structural unit 124 (e.g., portion 1244-1) in the second region R2. The structural unit 124 may be disposed in an opening of at least one insulating layer (e.g., insulating layer 118) in the circuit structure 104, and the details may refer to the above.

[0128] The structural unit 124 can suppress the warping of the overall structure, or can be used to transfer heat energy to the heat dissipation element HS, but is not limited thereto. The structural unit 124 has a first thermal expansion coefficient, and one of the multiple conductive layers in the circuit structure has a second thermal expansion coefficient. When the structural unit 124 is disposed in the first region R1, or when the structural unit 124 is disposed on the circuit structure 104 in the direction V, or when multiple electronic components and the structural unit 124 at least partially overlap in the cross section S of the cross section, the ratio of the first thermal expansion coefficient of the material of the structural unit 124 to the second thermal expansion coefficient of the material of one of the conductive layers in the circuit structure 104 can be greater than or equal to 1.2 and less than or equal to 2, but is not limited thereto. The above ratio can also be greater than or equal to 1.3 and less than or equal to 1.9, or can be greater than or equal to 1.4 and less than or equal to 1.8.

[0129] When the material of the structural unit 124 and the material of one of the conductive layers in the circuit structure 104 meet the above-mentioned ratio range of the thermal expansion coefficient, the warping of the overall structure can be suppressed, thereby improving the yield or reliability of the product. In some embodiments, when the structural unit 124 is disposed in the first region R1, the structural unit 124 may include a passive element such as a capacitor, a resistor, or an inductor, but is not limited thereto. In some embodiments, the passive element may be electrically connected to the circuit structure 104, but is not limited thereto.

[0130] In some embodiments, when the structure unit 124 (for example, the structure unit 1244-1) is disposed in the second region R2, or when the structure unit 124 (for example, the structure unit 1244-1) is embedded in the circuit structure 104, or when the structure unit 124 and multiple electronic components do not overlap in direction X (or direction Y), the ratio of the first thermal expansion coefficient of the material of the structure unit 124 to the second thermal expansion coefficient of the material of one of the conductive layers in the circuit structure 104 is greater than or equal to 0.1 and less than or equal to 0.8, but is not limited to this. The above ratio is also greater than or equal to 0.15 and less than or equal to 0.75, or greater than or equal to 0.2 and less than or equal to 0.7.

[0131] In summary, in the electronic device and the manufacturing method thereof of the present invention, the structural unit is used to suppress the warping of the overall structure, thereby effectively improving the yield or reliability of the product. The structural unit can be removed during the manufacturing process or retained in the completed electronic device.

[0132] The above description is only an embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for manufacturing an electronic device, characterized in that: include: Providing a carrier board; A circuit structure is arranged on the carrier, which includes a plurality of conductive layers and a plurality of insulating layers alternately arranged on the carrier, and two adjacent ones of the plurality of conductive layers are electrically connected through a plurality of through holes in one of the plurality of insulating layers; as well as A structural unit is arranged on one side of the circuit structure, The structural unit has a first thermal expansion coefficient, one of the multiple conductive layers in the circuit structure has a second thermal expansion coefficient, and a ratio of the first thermal expansion coefficient to the second thermal expansion coefficient is greater than or equal to 1.2 and less than or equal to 2.

2. The method for manufacturing an electronic device according to claim 1, wherein: After setting the circuit structure, a plurality of electronic components are set, wherein the plurality of electronic components at least partially overlap with the structural unit in a direction parallel to a surface of the carrier, and the plurality of electronic components do not overlap with the structural unit in another direction perpendicular to the surface of the carrier.

3. The method for manufacturing an electronic device according to claim 2, wherein: In a top view, the structural unit surrounds the plurality of electronic components.

4. The method for manufacturing an electronic device according to claim 2, wherein: The carrier board includes two diagonal areas, wherein at least a portion of the structural unit is located within the two diagonal areas.

5. The method for manufacturing an electronic device according to claim 1, wherein: A plurality of electronic components are arranged before the circuit structure is arranged, wherein the plurality of electronic components at least partially overlap with the structural unit in a direction parallel to a surface of the carrier, and the plurality of electronic components do not overlap with the structural unit in another direction perpendicular to the surface of the carrier.

6. The method for manufacturing an electronic device according to claim 1, wherein: The first thermal expansion coefficient is greater than or equal to 20.4 ppm / °C and less than or equal to 34 ppm / °C.

7. A method for manufacturing an electronic device, characterized in that: include: Providing a carrier board; as well as A circuit structure and a structural unit are arranged on the carrier, and the structural unit is arranged in the circuit structure, wherein the circuit structure is arranged including alternately arranging a plurality of conductive layers and a plurality of insulating layers on the carrier, and two adjacent ones of the plurality of conductive layers are electrically connected through a plurality of through holes in one of the plurality of insulating layers, The structural unit has a first thermal expansion coefficient, one of the plurality of conductive layers in the circuit structure has a second thermal expansion coefficient, and a ratio of the first thermal expansion coefficient to the second thermal expansion coefficient is greater than or equal to 0.1 and less than or equal to 0.

8.

8. The method for manufacturing an electronic device according to claim 7, wherein: After the circuit structure is arranged, a plurality of electronic components are arranged, wherein in a direction perpendicular to a surface of the carrier, the plurality of electronic components and the structural unit do not overlap.

9. The method for manufacturing an electronic device according to claim 8, wherein: In a top view, the structural unit surrounds the plurality of electronic components.

10. The method for manufacturing an electronic device according to claim 7, wherein: The carrier board includes two diagonal areas, wherein at least a portion of the structural unit is located within the two diagonal areas.

11. The method for manufacturing an electronic device according to claim 7, wherein: A plurality of electronic components are arranged before the circuit structure is arranged, wherein in a direction perpendicular to a surface of the carrier, the plurality of electronic components and the structural unit do not overlap.

12. The method for manufacturing an electronic device according to claim 7, wherein: The first thermal expansion coefficient is greater than or equal to 1.7 ppm / °C and less than or equal to 13.6 ppm / °C.

13. An electronic device, characterized in that: include: A circuit structure comprising a plurality of conductive layers and at least one insulating layer, wherein the plurality of conductive layers are electrically connected through a plurality of through holes in the at least one insulating layer; a plurality of electronic components electrically connected to the circuit structure and overlapping with the circuit structure; as well as A structural unit is disposed adjacent to the plurality of electronic components, wherein in a top view of the electronic device, at least a portion of the structural unit is located between two adjacent ones of the plurality of electronic components.

14. The electronic device according to claim 13, wherein: The multiple electronic components and the structural unit at least partially overlap in a cross-section of the cross-section of the electronic device, wherein the structural unit has a first thermal expansion coefficient, and one of the multiple conductive layers in the circuit structure has a second thermal expansion coefficient, and a ratio of the first thermal expansion coefficient to the second thermal expansion coefficient is greater than or equal to 1.2 and less than or equal to 2.

15. The electronic device as claimed in claim 13, wherein: The structural unit is embedded in the circuit structure, wherein the structural unit has a first thermal expansion coefficient, one of the multiple conductive layers in the circuit structure has a second thermal expansion coefficient, and a ratio of the first thermal expansion coefficient to the second thermal expansion coefficient is greater than or equal to 0.1 and less than or equal to 0.8.

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