Package substrate and manufacturing method thereof

Abstract

The invention discloses a packaging substrate and a manufacturing method thereof. Comprising the following steps: printing anti-plating ink in a first preset area of a core plate, and laminating to obtain a to-be-treated plate; manufacturing at least two through holes; the through holes are filled with anti-plating ink; a through groove is formed in the to-be-processed board, the groove wall of the through groove axially penetrates through the through holes, copper deposition processing is conducted on the to-be-processed board, and a copper layer enabling the core boards to be interconnected is formed on the groove wall of the through groove; removing oil to remove the anti-plating ink and copper on the surface of the anti-plating ink, and carrying out electroplating treatment to form a conductive circuit between two adjacent through holes on the groove wall; the conductive circuit is disconnected in each first preset area; and manufacturing an outer layer circuit on the surface of the to-be-processed board, and connecting the outer layer circuit with the conductive circuit. According to the method, the anti-plating ink is pre-printed in the first preset area where the conductive circuit needs to be disconnected, so that the manufactured conductive circuit can be completely disconnected at a specified position, impedance fluctuation of the packaging substrate is avoided, and integrity of signal transmission of the packaging substrate is guaranteed.

Description

Technical Field

[0001] The present application relates to the technical field of packaging substrate processing, and in particular to a packaging substrate and a method for manufacturing the same. Background Art

[0002] With the iterative development of products, the demand for signal transmission speed of electronic products is becoming higher and higher. Among them, ensuring the integrity of signal transmission during the signal transmission process is a key link in improving the signal transmission rate.

[0003] The existing interconnection production of the package substrate of the multi-layer core board is to first make a through groove, then perform copper plating and then perform regional disconnection. Among them, if mechanical drilling is used for regional disconnection, the position of the disconnection area lacks a force point, and uneven force will occur when drilling, which can easily cause the drilling to be offset, resulting in unsatisfactory disconnection effect and impedance fluctuation of the package substrate. If laser cutting is used for regional disconnection, it will also be due to the limitation of the ability of laser processing to ablate the medium and copper layer, resulting in the inability to achieve effective disconnection of the local area after processing, and the problem of impedance fluctuation of the package substrate.

[0004] The above processing solutions will all lead to discontinuous impedance of the via hole and affect the integrity of signal transmission of the packaging substrate. Summary of the invention

[0005] The main technical problem solved by the present application is to provide a packaging substrate and a manufacturing method thereof, so as to avoid impedance fluctuation of the packaging substrate and ensure the integrity of signal transmission.

[0006] In order to solve the above technical problems, the first technical solution adopted in the present application is to provide a method for manufacturing a packaging substrate, which method includes: obtaining a number of core boards, printing anti-plating ink on the first preset area of ​​the core board, and performing a lamination process to obtain a board to be processed; making at least two through holes on the board to be processed; making the through holes pass through the first preset area, and filling the anti-plating ink in the through holes; making a through groove on the board to be processed, wherein the groove wall of the through groove axially passes through each of the through holes, and the groove wall of the through groove passes through the anti-plating ink on each of the core boards; performing a copper plating process on the board to be processed to form a copper layer on the groove wall of the through groove to interconnect each of the core boards; performing an oil removal process to remove the anti-plating ink and the copper on the surface of the anti-plating ink, and performing an electroplating process to form a conductive circuit located between two adjacent through holes on the groove wall; and the conductive circuit is disconnected in each of the first preset areas.

[0007] In a possible embodiment, the step of making at least two through holes on the plate to be processed specifically includes: determining the line width of the conductive circuit according to the impedance requirement of the packaging substrate; determining at least two second preset areas on the plate to be processed according to the line width; wherein the spacing between two adjacent second preset areas is the line width; the first preset area covers the projection of the second preset area on the core board; and the through hole is made in the second preset area.

[0008] In a possible embodiment, the step of printing the anti-plating ink in the first preset area of ​​the core board specifically includes: determining the required connection relationship between each of the core boards; printing the anti-plating ink on the surface opposite to the other core board of at least one of the two adjacent core boards at the position where the conductive circuit needs to be disconnected.

[0009] In a possible implementation, a plurality of the second preset areas are determined on the plate to be processed, and the through holes are respectively made in each of the second preset areas to form a plurality of the conductive paths located between a plurality of adjacent groups of the through holes.

[0010] In a possible implementation manner, the step of obtaining a plurality of core boards specifically includes: obtaining a copper clad board and making a pattern to obtain the core board.

[0011] In a possible implementation manner, before the step of laminating, the method further includes: performing browning treatment on each of the core boards.

[0012] In a possible implementation, after the step of performing electroplating to form a conductive circuit between two adjacent through holes on the groove wall, the step further includes: performing resin plugging treatment on the plate to be treated.

[0013] In a possible embodiment, after the electroplating step, it also includes: making an outer layer circuit on the surface of the plate to be treated, so that the outer layer circuit is connected to the conductive circuit, and the step of making the outer layer circuit specifically includes: laminating, exposing, developing, etching and electroplating in sequence.

[0014] In a possible implementation manner, after the step of making the outer layer circuit, the method further includes: making a solder resist layer on the surface of the plate to be processed.

[0015] In order to solve the above technical problem, the second technical solution adopted by the present application is to provide a packaging substrate. The packaging substrate is manufactured by the above packaging substrate manufacturing method.

[0016] The beneficial effect of the present application is as follows: Different from the prior art, the present application provides a packaging substrate and a manufacturing method thereof, the manufacturing method comprising: obtaining a plurality of core boards, printing anti-plating ink on a first preset area of ​​the core board, and performing a lamination process to obtain a board to be processed; making at least two through holes on the board to be processed; making the through holes pass through the first preset area, and filling the through holes with anti-plating ink; making a through groove on the board to be processed, wherein the groove wall of the through groove axially passes through each through hole, and the groove wall of the through groove passes through the anti-plating ink on each core board; performing a copper plating process on the board to be processed to form a copper layer on the groove wall of the through groove to interconnect each core board; performing an oil removal process to remove the anti-plating ink and the copper on the surface of the anti-plating ink, and performing an electroplating process to form a conductive circuit on the groove wall located between two adjacent through holes; and the conductive circuit is disconnected in each first preset area; making an outer layer circuit on the surface of the board to be processed, so that the outer layer circuit is connected to the conductive circuit. The above method pre-prints anti-plating ink in the first preset area where the conductive circuit needs to be disconnected, so that the manufactured conductive circuit can be completely disconnected at the specified position, avoiding impedance fluctuation of the packaging substrate and ensuring the integrity of the signal transmission of the packaging substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0018] Figure 1 It is a flow chart of an embodiment of a method for manufacturing a packaging substrate of the present application;

[0019] Figure 2 yes Figure 1 Schematic diagram of the cross-sectional structure of the S11 core board after printing the anti-plating ink;

[0020] Figure 3 yes Figure 1 Schematic diagram of the cross-sectional structure of the plate to be processed after lamination of the S11 core plate;

[0021] Figure 4 yes Figure 1 Schematic diagram of the cross-sectional structure of the S12 plate to be processed after through-holes are made;

[0022] Figure 5 yes Figure 1 A schematic diagram of the structure of the S12 plate to be processed after the through-holes are made;

[0023] Figure 6 yes Figure 1 Schematic diagram of the cross-sectional structure of the S12 plate to be treated after the through-holes are filled with anti-plating ink;

[0024] Figure 7 Figure 1 A schematic diagram of the top view of the structure of the S12 plate to be treated after the through-holes are filled with anti-plating ink;

[0025] Figure 8 yes Figure 1 S13 is a schematic diagram of the structure of the plate to be processed after the through groove is made;

[0026] Fig. 9 yes Figure 1 Schematic diagram of the cross-sectional structure of the S14 plate to be processed after copper deposition;

[0027] Fig.10 yes Figure 1 Schematic diagram of the top view of the partial structure of the S14 plate to be processed after copper deposition;

[0028] Fig.11 yes Figure 1 Schematic diagram of the cross-sectional structure of the S15 plate to be treated after degreasing treatment;

[0029] Fig.12 yes Figure 1 Schematic diagram of the top view of the partial structure of the S15 plate to be treated after degreasing treatment;

[0030] Fig.13 yes Figure 1 A schematic flow chart of an implementation method of S11;

[0031] Fig.14 yes Figure 1 A schematic flow chart of an implementation method of S12;

[0032] Fig.15 yes Figure 1 A schematic diagram of the cross-sectional structure of the plate to be treated after the holes are plugged with resin;

[0033] Fig.16 The method for manufacturing the packaging substrate of the present application is Figure 1 Schematic diagram of the process after S15;

[0034] Fig.17 yes Fig.16 Schematic diagram of the top view of the structure of the plate to be processed after S16.

[0035] Among them, 10, core board; 11, dielectric layer; 12, copper layer; 20, anti-plating ink; 30, through hole; 40, through groove; 50, conductive circuit. DETAILED DESCRIPTION

[0036] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0037] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms of "a", "said", and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless otherwise clearly indicated above, and "multiple" generally includes at least two, but does not exclude the inclusion of at least one.

[0038] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0039] It should be understood that the terms "include", "comprises" or any other variations used herein are intended to cover non-exclusive inclusion, so that a process, method, article or device that includes a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of more restrictions, the elements defined by the sentence "includes..." do not exclude the presence of other identical elements in the process, method, article or device that includes the elements.

[0040] In the production of existing packaging substrates, mechanical drilling or laser cutting is used to disconnect regions. Both methods will cause impedance fluctuations in the packaging substrate, affecting the integrity of signal transmission.

[0041] Based on the above problems, the present application proposes a packaging substrate and a method for manufacturing the same, by printing anti-plating ink on the core board, making through holes after lamination, filling the anti-plating ink, making through grooves, and copper deposition and degreasing, so that the manufactured packaging substrate can effectively solve the above problems.

[0042] A packaging substrate and a manufacturing method thereof provided by the present application are described in detail below in conjunction with the accompanying drawings and embodiments.

[0043] See also Figures 1 to 12 , Figure 1 It is a flow chart of an embodiment of a method for manufacturing a packaging substrate of the present application. Figure 2 yes Figure 1 Schematic diagram of the cross-sectional structure of the S11 core board after printing the anti-plating ink; Figure 3 yes Figure 1 Schematic diagram of the cross-sectional structure of the plate to be processed after lamination of the S11 core plate; Figure 4 yes Figure 1 Schematic diagram of the cross-sectional structure of the S12 plate to be processed after through-holes are made; Figure 5 yes Figure 1 A schematic diagram of the structure of the S12 plate to be processed after the through-holes are made; Figure 6 yes Figure 1 Schematic diagram of the cross-sectional structure of the S12 plate to be treated after the through-holes are filled with anti-plating ink; Figure 7 Figure 1 A schematic diagram of the top view of the structure of the S12 plate to be treated after the through-holes are filled with anti-plating ink; Figure 8 yes Figure 1 S13 is a schematic diagram of the structure of the plate to be processed after the through groove is made; Fig. 9 yes Figure 1 Schematic diagram of the cross-sectional structure of the S14 plate to be processed after copper deposition; Fig.10 yes Figure 1 Schematic diagram of the top view of the partial structure of the S14 plate to be processed after copper deposition; Fig.11 yes Figure 1 Schematic diagram of the cross-sectional structure of the S15 plate to be treated after degreasing treatment;

[0044] Fig.12 yes Figure 1 S15 is a schematic diagram of a top view of a partial structure of a plate to be processed after degreasing. In a specific embodiment, the manufacturing method may include:

[0045] S11: obtaining a plurality of core boards, printing anti-plating ink on a first preset area of ​​the core board, and performing lamination treatment to obtain a board to be processed.

[0046] The high-density package substrate is composed of multiple layers of core boards 10, wherein the number of core boards 10 can be 2, 5, 8, 11 or dozens of core boards 10, and the specific number of core boards 10 is not limited. The high-density package substrate composed of multiple layers of core boards 10 can arrange more circuits on the substrate of the same area, thereby improving the circuit density. In this embodiment, 7 core boards 10 are obtained.

[0047] Please refer to Fig.13 , Fig.13 yes Figure 1 A flow chart of an implementation method of S11; in a specific implementation method, S11 may include:

[0048] S111: Determine the required connection relationship between the core boards.

[0049] The multilayer core board 10 in the high-density packaging substrate needs to be punched and grooved to make longitudinal conductive lines 50, and each core board 10 is connected between layers through the conductive lines 50. Determining the required connection relationship between the core boards 10 specifically determines the position where the conductive lines 50 to be made later need to be disconnected.

[0050] S112: Printing anti-plating ink on the surface of at least one core board opposite to the other core board of two adjacent core boards at the position where the conductive circuit needs to be disconnected.

[0051] The first preset area (not marked) is the area where the conductive circuit 50 needs to be disconnected. The first preset area covers the projection of the conductive circuit 50 on the core board 10.

[0052] In this embodiment, before punching and grooving to produce the longitudinal conductive circuit 50, anti-plating ink 20 is pre-printed on the surface of the core board 10 at the position where the longitudinal conductive circuit 50 needs to be disconnected. The anti-plating ink 20 can prevent thick copper from being deposited during electroplating after copper deposition, so that thick copper will not be deposited on the core board 10 at the position where the conductive circuit 50 needs to be disconnected. As mentioned above, the first preset area is the area where the conductive circuit 50 needs to be disconnected. In a preferred embodiment, the first preset area is the area covering the projection of the conductive circuit 50 on the core board 10. This setting ensures that the conductive circuit 50 can be completely disconnected in the first preset area after the subsequent degreasing treatment. Avoid problems such as incomplete disconnection and impedance fluctuations of the packaging substrate.

[0053] In this embodiment, the anti-plating ink 20 is printed on the surface of one core board 10 opposite to the other core board 10 of the two adjacent core boards 10 at the location where the conductive circuit 50 needs to be disconnected. In some other embodiments, the anti-plating ink 20 can also be printed on both opposite surfaces of the two adjacent core boards 10 at the location where the conductive circuit 50 needs to be disconnected. The conductive circuit 50 passes through the anti-plating ink 20.

[0054] In some embodiments, the step of obtaining a plurality of core boards 10 specifically includes: obtaining a copper clad laminate, and making a pattern to obtain the core board 10. Specifically, the copper clad laminate can be a double-sided copper clad laminate, a single-sided copper clad laminate, etc., without specific limitation. In the present embodiment, the core board 10 is a double-sided copper clad laminate, so that more circuits can be arranged in a packaging substrate of the same area, thereby improving the circuit density. The double-sided copper clad laminate includes a dielectric layer 11 located in the middle and a copper layer 12 located on both sides of the dielectric layer 11. Making the pattern specifically involves making a circuit on the copper layer 12 on both sides of the dielectric layer 11. Among them, the specific steps of pattern making may include sequentially performing film lamination, exposure, development, etching, and electroplating, etc., without specific limitation.

[0055] After printing the anti-plating ink 20 on the core board 10, the core boards 10 are laminated together in a preset order. When laminating the core boards 10, a dielectric layer 11 is also arranged between two adjacent core boards 10 for lamination. The purpose of this arrangement is to separate the circuits respectively located on the two core boards 10 and to improve the strength of the packaging substrate.

[0056] In some embodiments, before the step of laminating, it also includes: browning each core board 10. Specifically, the browning treatment can be performed by soaking the surface of the core board 10 in a solution containing sulfuric acid, hydrogen peroxide, etc., so that the circuit made on the surface of the core board 10 forms an oxide layer. The oxide layer can be used as an intrinsic impedance matching layer to reduce reflection and loss during signal transmission and ensure the integrity of signal transmission. On the other hand, the browning treatment can form a microscopically rough copper surface. This structure can greatly improve the mechanical bite force and chemical bonding force between subsequent laminate layers, thereby enhancing the bonding strength and effectively preventing the occurrence of delamination.

[0057] S12: making at least two through holes on the plate to be processed; making the through holes penetrate the first preset area, and filling the through holes with anti-plating ink.

[0058] The two through holes 30 penetrate the first preset area, and this arrangement ensures that the area between the two through holes 30 can be completely isolated by the anti-plating ink 20 in the first preset area.

[0059] Please refer to Fig.14 , Fig.14 yes Figure 1 A flow chart of an implementation method of S12; in a specific implementation method, S12 may include:

[0060] S121: Determine the line width of the conductive line according to the impedance requirement of the package substrate.

[0061] The line width of the conductive line 50 is related to its impedance. Generally speaking, the larger the line width, the lower the impedance, and the smaller the line width, the greater the impedance. The line width of the conductive line 50 can be calculated according to the impedance requirement.

[0062] S122: Determine at least two second preset areas on the plate to be processed according to the line width; wherein the distance between two adjacent second preset areas is the line width; and the first preset area covers the projection of the second preset area on the core plate.

[0063] The core boards 10 of the package substrate are usually connected to each other through a plurality of different conductive lines 50. The impedance values ​​of the different conductive lines 50 can be the same or different, and the line width of each conductive line 50 is calculated according to the impedance value of each conductive line 50.

[0064] Among them, the number of second preset areas (not marked) is at least 2, and the number of second preset areas can be any reasonable number such as 2, 3, 4, 8, etc., which is not specifically limited here. When the number of second preset areas is 2, there is at most one group of adjacent through holes 30 after punching, and the number of conductive circuits 50 produced is one. In this embodiment, multiple second preset areas are determined on the plate to be processed, and through holes 30 are made in each second preset area to form multiple conductive circuits 50 located between multiple groups of adjacent through holes 30. The number of second preset areas is 8, and the 8 second preset areas are arranged in two columns, so that there are six groups of adjacent second preset areas, and six conductive circuits 50 are produced. Among them, the spacing between each group of adjacent second preset areas can be the same or different, so that each conductive circuit 50 has the same or different line width.

[0065] Different conductive circuits 50 may need to be disconnected at different core plates 10, and the first preset area is the area on the core plate 10 where the conductive circuits 50 need to be disconnected. Each group of second preset areas has a corresponding first preset area, so that the conductive circuits 50 corresponding to each group of second preset areas are disconnected at the corresponding first preset areas.

[0066] S123: Making a through hole in the second preset area.

[0067] The through hole 30 can be made by mechanical drilling, laser drilling, etc., which is not limited to the specific method.

[0068] S13: making a through groove on the plate to be processed, wherein the groove wall of the through groove axially penetrates each through hole, and the groove wall of the through groove penetrates the anti-plating ink on each core plate.

[0069] Specifically, the through groove 40 can be made at a designated position by mechanical processing or laser ablation. The manufacturing method of the through groove 40 is not specifically limited, wherein the groove wall of the through groove 40 is perpendicular to the surface of the plate to be processed. The opening shape of the through groove 40 is not specifically limited. For example, the opening shape of the through groove 40 can be square, triangular, irregular polygonal, etc. In the present embodiment, the opening shape of the through groove 40 is arched. The groove wall of the through groove 40 needs to axially penetrate each through hole 30 so that a conductive circuit 50 located between each group of through holes 30 and separated by the through holes 30 can be subsequently made on the groove wall. The groove wall of the through groove 40 needs to penetrate the anti-plating ink 20 on each core board 10 so that the conductive circuit 50 made on the groove wall can be disconnected in the first preset area.

[0070] S14: copper deposition is performed on the plate to be processed to form a copper layer on the groove wall of the through groove to interconnect the core plates.

[0071] Specifically, copper deposition is performed on the entire board, so that the groove wall of the through groove 40 forms a copper layer that interconnects each core board 10, and at the same time, the two surfaces of the plate to be treated will also form a copper layer on the entire board. Among them, a thin layer of copper will also be deposited on the groove wall of the through groove 40 at the through hole 30. The steps of copper deposition treatment specifically include: pre-treating the plate to be treated, and the pre-treatment is to ensure that the surface of the plate to be treated is clean and has good activation performance through alkaline degreasing, micro-etching, pre-impregnation, activation and other steps, so as to prepare for the subsequent copper deposition. Then copper deposition is performed. Copper deposition can deposit a uniform copper layer on the groove wall and surface of the plate to be treated by chemical reaction through solutions containing copper salts, reducing agents, chelating agents, etc. The copper ions are reduced to metallic copper under the chemical reduction reaction and deposited on the groove wall and surface. After the copper layer is deposited, a cleaning treatment is performed to remove excess chemicals.

[0072] After the copper deposition process, each core board 10 is interconnected through the deposited copper layer.

[0073] S15: performing degreasing treatment to remove the resist ink and the copper on the surface of the resist ink, and performing electroplating treatment to form a conductive circuit between two adjacent through holes on the groove wall; and the conductive circuit is disconnected in each first preset area.

[0074] Specifically, the degreasing treatment can be carried out by chemical degreasing or physical degreasing. Chemical degreasing can use an alkaline or acidic degreasing liquid to soak or spray the plate to be treated, so that the anti-plating ink 20 dissolves or separates from the plate to be treated. Among them, the chemical degreasing method needs to control the time and temperature to ensure that the anti-plating ink 20 is completely removed without affecting the plate to be treated. Physical degreasing can remove the anti-plating ink 20 by ultrasonic cleaning, high-pressure water washing or mechanical brushing. The specific method of degreasing treatment is not limited. Among them, after the degreasing treatment is completed, the plate to be treated needs to be cleaned and dried to ensure that the residue of the anti-plating ink 20 is completely removed.

[0075] After the degreasing treatment, the anti-plating ink 20 filled in the through hole 30 is removed, and the thin copper attached to the copper plating at the through hole 30 is also removed. The anti-plating ink 20 in each first preset area is removed, and the thin copper attached to the copper plating at the first preset area is also removed.

[0076] After the degreasing treatment, electroplating is performed. In the electroplating process, there will be no copper deposition in the area where the thin copper is removed together with the anti-plating ink 20. After the electroplating is completed, a conductive circuit 50 is formed between each group of adjacent through holes 30. The line width of the conductive circuit 50 formed in this way is determined by the through hole 30 to control the perforation spacing. The line width of the conductive circuit 50 is better controlled, so that the impedance of the conductive circuit 50 can meet the impedance requirements of the package substrate.

[0077] In the above-mentioned electroplating process to form the conductive circuit 50, copper cannot be electroplated in the first preset area, so that the formed conductive circuit 50 is completely disconnected in the first preset area. Compared with the existing disconnection method, the conductive circuit 50 disconnection method does not have the problems of drilling deviation and unsatisfactory disconnection effect, and can ensure effective disconnection of the local area, ensure the continuity of the via impedance of the packaging substrate and the integrity of the signal transmission.

[0078] In some embodiments, after the step of performing electroplating to form a conductive line 50 between two adjacent through holes 30 on the groove wall, the process further includes: performing resin plugging on the plate to be processed. Fig.15 , Fig.15 yes Figure 1 The purpose of resin plugging is to separate the conductive lines 50 to avoid the risk of short circuit and to protect the conductive lines 50.

[0079] Please refer to Fig.16 and Fig.17 , Fig.16 The method for manufacturing the packaging substrate of the present application is Figure 1 Schematic diagram of the process after S15; Fig.17 yes Fig.16 A schematic diagram of a top view of the plate to be processed after S16. In some embodiments, after the electroplating step, the process further includes:

[0080] S16: making an outer circuit on the surface of the plate to be processed, so that the outer circuit is connected to the conductive circuit.

[0081] Specifically, in the previous copper electroplating process, copper has been deposited on the surface of the plate to be processed, and a pattern is produced on the copper layer to obtain an outer layer circuit, wherein this step may include: laminating, exposing, developing, etching and electroplating in sequence.

[0082] S17: Make a solder mask layer on the surface of the board to be processed.

[0083] The solder mask is used to isolate the external environment and protect the outer circuit on the surface of the board to be processed.

[0084] Different from the prior art, the present application provides a method for manufacturing a package substrate, which is a method for laminating a core board 10 after printing a plating-resistant ink 20 in a first preset area of ​​the core board 10, and then opening a through hole 30 on the plate to be processed and filling the plating-resistant ink 20, and then making a through groove 40 and performing copper deposition, oil removal, and electroplating. The core board 10 is interconnected between layers through a conductive circuit 50, and the conductive circuit 50 is completely disconnected in the first preset area, avoiding the problem of incomplete disconnection of the conductive circuit 50 and impedance fluctuation in the existing disconnection method.

[0085] Correspondingly, the present application also proposes a packaging substrate, which is manufactured by the above-mentioned packaging substrate manufacturing method.

[0086] The above descriptions are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent principle transformation made using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A method for manufacturing a packaging substrate, characterized in that: include: Obtaining a plurality of core boards, printing anti-plating ink on first preset areas of the core boards, and performing lamination treatment to obtain boards to be treated; Making at least two through holes on the plate to be processed; making the through holes pass through the first preset area, and filling the anti-plating ink in the through holes; Making a through groove on the plate to be processed, wherein the groove wall of the through groove axially penetrates each of the through holes, and the groove wall of the through groove penetrates the anti-plating ink on each of the core plates; Performing copper deposition treatment on the plate to be processed, so as to form a copper layer on the groove wall of the through groove to interconnect the core plates; Degreasing treatment is performed to remove the anti-plating ink and the copper on the surface of the anti-plating ink, and electroplating treatment is performed to form a conductive circuit located between two adjacent through holes on the groove wall; and the conductive circuit is disconnected in each of the first preset areas.

2. The method according to claim 1, characterized in that: The step of making at least two through holes on the plate to be processed specifically includes: Determining the line width of the conductive line according to the impedance requirement of the packaging substrate; At least two second preset areas are determined on the plate to be processed according to the line width; wherein the distance between two adjacent second preset areas is the line width; and the first preset area covers the projection of the second preset area on the core plate; The through hole is made in the second preset area.

3. The method according to claim 2, characterized in that: The step of printing the anti-plating ink in the first preset area of ​​the core board specifically includes: Determining the required connection relationship between the core plates; The anti-plating ink is printed on a surface of at least one of the two adjacent core boards at a location where the conductive circuit needs to be disconnected and which is opposite to the other core board.

4. The method according to claim 3, characterized in that: A plurality of the second preset areas are determined on the plate to be processed, and the through holes are respectively made in each of the second preset areas to form a plurality of the conductive lines located between a plurality of adjacent groups of the through holes.

5. The method according to claim 1, characterized in that: The step of obtaining a plurality of core plates specifically includes: A copper clad laminate is obtained and patterned to obtain the core board.

6. The method according to claim 1, characterized in that: Before the step of laminating, the method further comprises: Each of the core boards is subjected to browning treatment.

7. The manufacturing method according to claim 1, characterized in that: After the step of performing electroplating to form a conductive circuit between two adjacent through holes on the groove wall, the method further includes: The plate to be processed is subjected to resin plugging treatment.

8. The manufacturing method according to claim 1, characterized in that: After the electroplating step, the method further comprises: An outer circuit is made on the surface of the plate to be processed, so that the outer circuit is connected to the conductive circuit. The steps for making the outer layer circuit include: The film lamination, exposure, development, etching and electroplating are carried out in sequence.

9. The manufacturing method according to claim 8, characterized in that: After the step of making the outer layer circuit, the method further includes: A solder resist layer is formed on the surface of the plate to be processed.

10. A packaging substrate, characterized in that: The packaging substrate is manufactured by the manufacturing method according to any one of claims 1 to 9.

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