A chip microchannel heat dissipation packaging structure

Abstract

The present invention discloses a microfluidic heat dissipation packaging structure of a chip, comprising a substrate, an insulating layer 1 is arranged on the substrate, a microfluidic channel 2 is arranged in the insulating layer 1, a heat dissipation layer is arranged on the insulating layer 1, the heat dissipation layer comprises heat dissipation plates arranged on the upper and lower sides of a rewiring layer, a microfluidic channel 1 is arranged in the heat dissipation plate, a through hole 1 is arranged in the rewiring layer and is respectively connected with the microfluidic channel 1 in the upper and lower heat dissipation plates, the microfluidic channel 1 in the lower heat dissipation plate is connected with the microfluidic channel 2, an insulating layer 2 is arranged on the heat dissipation layer, a through hole 7 is arranged in the insulating layer 2 and is connected with the microfluidic channel 1 in the upper heat dissipation plate, a plastic sealing layer is arranged on the insulating layer 2, a chip is plastic-sealed in the plastic sealing layer, a microfluidic channel 3 connected with the through hole 7 is also arranged in the plastic sealing layer, a heat spreader is arranged on the plastic sealing layer, a microfluidic channel 4 connected with the microfluidic channel 3 is arranged in the heat spreader, and a return channel is connected at the output end of the microfluidic channel 2, and the chip is connected to the substrate through the rewiring layer.

Description

Technical Field

[0001] The invention relates to the technical field of semiconductor packaging, in particular to a microchannel heat dissipation packaging structure of a chip. Background Art

[0002] In today's rapidly developing semiconductor industry, chip design is evolving towards higher integration, higher performance, and lower power consumption. However, as chip functions become increasingly powerful and power consumption increases dramatically, heat dissipation has become a key factor restricting further improvement of chip performance. Traditional heat dissipation methods, such as fan cooling and active heat dissipation devices such as heat sinks, have alleviated the heat dissipation pressure of chips to a certain extent, but when faced with high-power, high-density integrated multi-chip systems, their heat dissipation efficiency can no longer meet the needs, and may even cause chip overheating due to heat accumulation, affecting the stability and reliability of the equipment.

[0003] Therefore, it is necessary to provide a microchannel heat dissipation packaging structure for a chip to solve the problems raised in the above background technology. Summary of the invention

[0004] To achieve the above-mentioned purpose, the present invention provides the following technical solutions: a microfluidic heat dissipation packaging structure of a chip, comprising a substrate, an insulating layer 1 is provided on the substrate, a microchannel 2 is provided in the insulating layer 1, a heat dissipation layer is provided on the insulating layer 1, the heat dissipation layer comprises heat dissipation plates arranged above and below a rewiring layer, a microchannel 1 is provided in the heat dissipation plate, a through hole 1 is provided in the rewiring layer and is respectively connected to the microchannel 1 in the upper and lower heat dissipation plates, the microchannel 1 in the lower heat dissipation plate is connected to the microchannel 2, an insulating layer 2 is provided on the heat dissipation layer, a through hole 7 is provided in the insulating layer 2 and is connected to the microchannel 1 in the upper heat dissipation plate, a plastic sealing layer is provided on the insulating layer 2, a chip is plastic-sealed in the plastic sealing layer, a microchannel 3 connected to the through hole 7 is also provided in the plastic sealing layer, a heat spreader is provided on the plastic sealing layer, a microchannel 4 connected to the microchannel 3 is provided in the heat spreader, and a return channel is connected to the output end of the microchannel 2, and the chip is connected to the substrate through the rewiring layer.

[0005] Furthermore, the heat sink is provided with an orifice 1, microchannel 2 is connected to microchannel 1 in the lower heat sink through orifice 1 in the lower heat sink, and through hole 7 is connected to microchannel 1 in the upper heat sink through orifice 1 in the upper heat sink.

[0006] Furthermore, the through hole 1 is provided in plurality.

[0007] Furthermore, the insulating layer one is provided with a through hole six for connecting to the substrate, the through hole six is ​​provided with a conductor two, the insulating layer two is provided with a through hole eight for connecting to the chip, the through hole eight is provided with a conductor three, the heat sink is provided with a through hole four, the through hole four is provided with a conductor one, the conductor three is connected to the top of the rewiring layer through the conductor one in the upper heat sink, and the conductor two is connected to the bottom of the rewiring layer through the conductor one in the lower heat sink.

[0008] Furthermore, the microchannel three is arranged on the periphery of the chip, the heat spreader is provided with a second orifice, and the microchannel four is connected to the microchannel three through the second orifice.

[0009] Furthermore, the microchannel four is provided with an S-shaped grating bar, and the grating bar divides the microchannel four into an S-shaped channel. The heat spreader is provided with an orifice two, and the S-shaped channel is connected to the microchannel three through the orifice two. The heat spreader is also provided with an inlet connected to the S-shaped channel.

[0010] Furthermore, an insulating frame is provided on the periphery of the rewiring layer.

[0011] Furthermore, the insulating outer frame is provided with through hole three, the heat sink is provided with through hole five connected to through hole three, the through hole five in the lower heat sink is connected to microchannel two, the insulating layer two is provided with through hole nine connected to through hole five in the upper heat sink, the plastic sealing layer is provided with through hole ten connected to through hole nine, the heat spreader is provided with an outlet connected to through hole ten, and the through hole three, through hole five, through hole ten and the outlet constitute a reflow channel.

[0012] Furthermore, a heat-conducting wall is formed on the inner wall of the microchannel three.

[0013] Compared with the prior art, the present invention provides a microchannel heat dissipation packaging structure of a chip, which has the following beneficial effects:

[0014] In the present invention, the structural design of the heat dissipation layer, the insulating layer one, the insulating layer two, the plastic sealing layer, the heat spreader and the return channel makes the microfluidic heat dissipation packaging structure for the chip more precise. By forming an inlet as the inlet of the heat dissipation fluid, it passes through microchannel four, microchannel three, microchannel one and microchannel two in sequence and flows out of the return channel, so that the chip, the redistribution layer and the substrate can be fully dissipated, so that the heat exchange area is greatly increased, and the heat transfer path from the chip to the coolant is shortened, the thermal resistance is effectively reduced, and the heat dissipation efficiency and heat dissipation effect are further improved. In particular, the design of the heat dissipation layer can enable the heat dissipation fluid to fully absorb the heat between the chip and the substrate. The design of microchannel three can also fully absorb the heat around the chip, thereby achieving the effect of efficient heat dissipation of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 The schematic diagram of the microchannel heat dissipation packaging structure of the present invention is shown in FIG. Figure 1 ;

[0016] Figure 2 The schematic diagram of the microchannel heat dissipation packaging structure of the present invention is shown in FIG. Figure 2 ;

[0017] Figure 3 It is a schematic diagram of the structure of the heat sink of the present invention;

[0018] Figure 4 It is a schematic diagram of preparing the plastic sealing layer of the present invention;

[0019] Figure 5 It is a schematic diagram of preparing the second insulating layer of the present invention;

[0020] Figure 6 It is a schematic diagram of preparing the heat dissipation plate of the present invention;

[0021] Figure 7 It is a schematic diagram of preparing the heat dissipation layer of the present invention;

[0022] Figure 8 It is a schematic diagram of preparing an insulating layer 1 of the present invention;

[0023] In the figure: 1, substrate; 2, rewiring layer; 3, heat dissipation layer; 4, insulation layer 1; 5, insulation layer 2; 6, plastic layer; 7, chip; 8, heat spreader; 9, return channel; 10, carrier plate; 21, through hole 1; 22, insulation frame; 23, through hole 2; 24, convex cover; 25, insulation wall; 221, through hole 3; 31, heat dissipation plate; 32, conductor 1; 33, through hole 4; 34, Through hole five; 35, orifice one; 311, microchannel one; 41, microchannel two; 42, conductor two; 43, through hole six; 51, through hole seven; 52, conductor three; 53, through hole eight; 54, through hole nine; 61, microchannel three; 62, through hole ten; 64, heat conductor; 65, heat conductive wall; 81, microchannel four; 82, grille bar; 83, outlet; 84, orifice two; 85, inlet. DETAILED DESCRIPTION

[0024] Reference Figure 1-Figure 8The present invention provides a technical solution: a microfluidic heat dissipation packaging structure of a chip, comprising a substrate 1, an insulating layer 4 is provided on the substrate 1, a microfluidic channel 2 41 is provided in the insulating layer 4, a heat dissipation layer 3 is provided on the insulating layer 4, the heat dissipation layer 3 comprises a heat dissipation plate 31 arranged on the upper and lower sides of a rewiring layer 2, a microfluidic channel 1 311 is provided in the heat dissipation plate 31, a through hole 21 is provided in the rewiring layer 2, which is respectively connected to the microfluidic channel 1 311 in the upper and lower heat dissipation plates 31, and the microfluidic channel 1 311 in the lower heat dissipation plate 31 is connected to the microfluidic channel 2 41, An insulating layer 2 5 is provided on the heat dissipation layer 3, and a through hole 7 51 is provided in the insulating layer 2 5 and is connected to the microchannel 1 311 in the upper heat dissipation plate 31. A plastic sealing layer 6 is provided on the insulating layer 2 5, and a chip 7 is plastic-sealed in the plastic sealing layer 6. The plastic sealing layer 6 is also provided with a microchannel 3 61 connected to the through hole 7 51. A heat spreader 8 is provided on the plastic sealing layer 6, and a microchannel 4 81 connected to the microchannel 3 61 is provided in the heat spreader 8. The output end of the microchannel 2 41 is connected to the return channel 9. The chip 7 is connected to the substrate 1 through the rewiring layer 2.

[0025] In this embodiment, combined with Figure 5 As shown, the processing steps of the insulating layer 2 5 are as follows: forming the insulating layer 2 5 on the carrier plate 10 by a chemical vapor deposition process or a physical vapor deposition process, then etching the insulating layer 2 5 by a deep reactive ion etching process, forming a corresponding through hole 8 53 on the insulating layer 2 5, then forming a conductor 3 52 in the through hole 8 53 by a chemical vapor deposition process or a physical vapor deposition process, and then etching the insulating layer 2 5 by a deep reactive ion etching process, forming a corresponding through hole 9 54 and through hole 7 51 on the insulating layer 2 5;

[0026] In this embodiment, combined with Figure 4 As shown, the processing steps of the plastic sealing layer 6 are as follows: the chip 7 is plastic-sealed to form the plastic sealing layer 6, and the plastic sealing layer 6 is etched by a deep reactive ion etching process to form a corresponding microchannel three 61 on the plastic sealing layer 6, and then a heat conductor 64 is formed in the microchannel three 61 by a chemical vapor deposition process or a physical vapor deposition process, and then the plastic sealing layer 6 and the heat conductor 64 are etched separately by a deep reactive ion etching process to form a through hole ten 62 and a heat conducting wall 65.

[0027] In this embodiment, the heat sink 31 is provided with an orifice 35, the microchannel 2 41 is connected to the microchannel 1 311 in the lower heat sink 31 through the orifice 35 in the lower heat sink 31, and the through hole 7 51 is connected to the microchannel 1 311 in the upper heat sink 31 through the orifice 35 in the upper heat sink 31; wherein, the combination Figure 6As shown, the processing steps of the heat sink 31 are as follows: combine the heat sink 31 with the carrier plate 10, etch the heat sink 31 through a deep reactive ion etching process to form a corresponding through hole four 33 on the heat sink 31, then form a conductor one 32 in the through hole four 33 through a chemical vapor deposition process or a physical vapor deposition process, and then etch the heat sink 31 through a deep reactive ion etching process to form a through hole five 34, a microchannel one 311 and an orifice one 35 on the heat sink 31; wherein the number of the orifice one 35 is set to one.

[0028] In this embodiment, the through hole 21 is provided in plurality; wherein, Figure 7 and Figure 1 As shown, the processing steps of the rewiring layer 2, the insulating outer frame 22 and the heat sink 31 are as follows: the rewiring layer 2 is combined with the carrier plate 10, and the insulating outer frame 22 is formed on the periphery of the rewiring layer 2 by a chemical vapor deposition process or a physical vapor deposition process, and then the rewiring layer 2 is etched by a deep reactive ion etching process to form a corresponding through hole 23 on the rewiring layer 2, and then the chemical vapor deposition process or the physical vapor deposition process, and the deep reactive ion etching process are sequentially performed to form a microchannel 311 on the rewiring layer 2. The mating convex cover 24 and the filled through-hole 2 23 are then combined with the rewiring layer 2 with the convex cover 24 on one side and the microchannel 1 311 of the heat sink 31, and then the convex cover 24 mating with the microchannel 1 311, the through-hole 3 211 mating with the through-hole 5 34, and the insulating wall 25 are formed on the rewiring layer 2 in sequence through chemical vapor deposition process or physical vapor deposition process and deep reactive ion etching process. At this time, another heat sink 31 is combined with the rewiring layer 2.

[0029] In this embodiment, the insulating layer 1 4 is provided with a through hole 6 43 for connecting to the substrate 1, and the through hole 6 43 is provided with a conductor 2 42. The insulating layer 2 5 is provided with a through hole 8 53 for connecting to the chip 7, and the through hole 8 53 is provided with a conductor 3 52. The heat sink 31 is provided with a through hole 4 33, and the through hole 4 33 is provided with a conductor 1 32. The conductor 3 52 is connected to the upper surface of the rewiring layer 2 through the conductor 1 32 in the upper heat sink 31, and the conductor 2 42 is connected to the lower surface of the rewiring layer 2 through the conductor 1 32 in the lower heat sink 31, wherein the combination Figure 8 As shown, the processing steps of the insulating layer 4 are as follows: forming the insulating layer 4 on the carrier plate 10 by chemical vapor deposition process or physical vapor deposition process in sequence, then etching the insulating layer 4 by deep reactive ion etching process, forming corresponding through hole 6 43 on the insulating layer 4, then forming conductor 2 42 in the through hole 6 43 by chemical vapor deposition process or physical vapor deposition process, and then etching the insulating layer 4 by deep reactive ion etching process, forming microchannel 2 41 on the insulating layer 4.

[0030] In this embodiment, the microchannel three 61 is arranged on the periphery of the chip 7, and the heat spreader 8 is provided with a second orifice 84, and the microchannel four 81 is connected to the microchannel three 61 through the second orifice 84; that is, the number of the second orifice 84 is set to one.

[0031] In this embodiment, the microchannel four 81 is provided with S-shaped partition bars 82, and the partition bars 82 separate the microchannel four 81 to form an S-shaped channel. The heat spreader 81 is provided with an orifice two 84, and the S-shaped channel is connected to the microchannel three 61 through the orifice two 84. The heat spreader 81 is also provided with an inlet 85 connected to the S-shaped channel.

[0032] In this embodiment, an insulating outer frame 22 is provided on the outer periphery of the rewiring layer 2 .

[0033] In this embodiment, the insulating outer frame 22 is provided with a through hole three 221, the heat sink 31 is provided with a through hole five 34 connected to the through hole three 221, the through hole five 34 in the lower heat sink 31 is connected to the microchannel two 41, the insulating layer two 5 is provided with a through hole nine 54 connected to the through hole five 34 in the upper heat sink 31, the plastic sealing layer 6 is provided with a through hole ten 62 connected to the through hole nine 54, the heat spreader 8 is provided with an outlet 83 connected to the through hole ten 62, and the through hole three 221, the through hole five 34, the through hole ten 62 and the outlet 83 constitute a reflow channel 9.

[0034] In this embodiment, a heat-conducting wall 65 is formed on the inner wall of the microchannel three 61 .

[0035] In specific implementation, it includes the following steps:

[0036] Step 1: prefabricate the heat sink 8;

[0037] Step 2: Plastic-encapsulating the chip 7 to form a plastic-encapsulating layer 6;

[0038] Step 3: prefabricate the insulating layer 2 5;

[0039] Step 4: prefabricate a combination of the rewiring layer 2 and the heat dissipation plates 31 above and below the rewiring layer 2 to form a heat dissipation layer 3;

[0040] Step 5: prefabricate the insulating layer 4;

[0041] Step 6: Prepare and package the insulating layer 1 4 and the substrate 1, encapsulate the heat dissipation layer 3 on the insulating layer 1 4, encapsulate the insulating layer 2 5 on the heat dissipation layer 3, encapsulate the plastic sealing layer 6 on the insulating layer 2 5, and encapsulate the heat spreader 8 on the plastic sealing layer 6, forming an inlet 83 as the inlet of the heat dissipation fluid, which passes through the microchannel 4 81, the microchannel 3 61, the microchannel 1 311 and the microchannel 2 41 in sequence, and flows out from the return channel 9, thereby fully dissipating the heat of the chip 7, the redistribution layer 2 and the substrate 1.

[0042] The above description is only a preferred specific implementation manner of the invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes according to the technical scheme and inventive concept of the present invention within the technical scope disclosed by the invention, which should be covered by the protection scope of the present invention.

Claims

1. A microchannel heat dissipation packaging structure for a chip, comprising a substrate (1), characterized in that: The substrate (1) is provided with an insulating layer 1 (4) on the top, a microchannel 2 (41) is provided in the insulating layer 1 (4), a heat dissipation layer (3) is provided on the top of the insulating layer 1 (4), the heat dissipation layer (3) comprises heat dissipation plates (31) arranged above and below the rewiring layer (2), a microchannel 1 (311) is provided in the heat dissipation plate (31), the rewiring layer (2) is provided with a through hole 1 (21) which is respectively connected to the microchannel 1 (311) in the upper and lower heat dissipation plates (31), the microchannel 1 (311) in the lower heat dissipation plate (31) is connected to the microchannel 2 (41), the heat dissipation layer (3) is provided with an insulating layer 2 (5) on the top, and the insulating layer (4) is provided with a heat dissipation layer (3). The second insulating layer (5) is provided with a through hole seven (51) connected to the microchannel one (311) in the upper heat dissipation plate (31); a plastic sealing layer (6) is provided on the upper surface of the second insulating layer (5); a chip (7) is plastic-sealed in the plastic sealing layer (6); a microchannel three (61) connected to the through hole seven (51) is also provided in the plastic sealing layer (6); a heat spreader (8) is provided on the upper surface of the plastic sealing layer (6); a microchannel four (81) connected to the microchannel three (61) is provided in the heat spreader (8); an output end of the microchannel two (41) is connected to a return channel (9); and the chip (7) is connected to the substrate (1) via a rewiring layer (2).

2. The microchannel heat dissipation packaging structure of a chip according to claim 1, characterized in that: The heat sink (31) is provided with an orifice 1 (35), the microchannel 2 (41) is connected to the microchannel 1 (311) in the lower heat sink (31) via the orifice 1 (35) in the lower heat sink (31), and the through hole 7 (51) is connected to the microchannel 1 (311) in the upper heat sink (31) via the orifice 1 (35) in the upper heat sink (31).

3. The microchannel heat dissipation packaging structure of a chip according to claim 1, characterized in that: The through hole one (21) is provided in plurality.

4. The microchannel heat dissipation packaging structure of a chip according to claim 1, characterized in that: The insulating layer 1 (4) is provided with a through hole 6 (43) for connecting to the substrate (1), and the through hole 6 (43) is provided with a conductor 2 (42); the insulating layer 2 (5) is provided with a through hole 8 (53) for connecting to the chip (7), and the through hole 8 (53) is provided with a conductor 3 (52); the heat sink (31) is provided with a through hole 4 (33), and the through hole 4 (33) is provided with a conductor 1 (32); the conductor 3 (52) is connected to the upper surface of the rewiring layer (2) through the conductor 1 (32) in the upper heat sink (31), and the conductor 2 (42) is connected to the lower surface of the rewiring layer (2) through the conductor 1 (32) in the lower heat sink (31).

5. The microchannel heat dissipation packaging structure of a chip according to claim 1, characterized in that: The microchannel three (61) is arranged on the periphery of the chip (7), the heat spreader (8) is provided with a second orifice (84), and the microchannel four (81) is connected to the microchannel three (61) via the second orifice (84).

6. The microchannel heat dissipation packaging structure of a chip according to claim 1, characterized in that: The microchannel four (81) is provided with an S-shaped grating bar (82), and the grating bar (82) separates the microchannel four (81) to form an S-shaped channel. The heat spreader (8) is provided with an orifice two (84), and the S-shaped channel is connected to the microchannel three (61) through the orifice two (84). The heat spreader (8) is also provided with an inlet (85) connected to the S-shaped channel.

7. The microchannel heat dissipation packaging structure of a chip according to claim 1, characterized in that: An insulating outer frame (22) is provided on the outer periphery of the rewiring layer (2).

8. The microchannel heat dissipation packaging structure of a chip according to claim 7, characterized in that: The insulating outer frame (22) is provided with a through hole three (221), the heat sink (31) is provided with a through hole five (34) connected to the through hole three (221), the through hole five (34) in the lower heat sink (31) is connected to the microchannel two (41), the insulating layer two (5) is provided with a through hole nine (54) connected to the through hole five (34) in the upper heat sink (31), the plastic sealing layer (6) is provided with a through hole ten (62) connected to the through hole nine (54), the heat spreader (8) is provided with an outlet (83) connected to the through hole ten (62), and the through hole three (221), the through hole five (34), the through hole ten (62) and the outlet (83) constitute a return channel (9).

9. The microchannel heat dissipation packaging structure of a chip according to claim 1, characterized in that: The inner wall of the microchannel three (61) is formed with a heat-conducting wall (65).

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