Light detection apparatus and light detection system

Abstract

The invention relates to a light detection apparatus and a light detection system. Provided are a light detection device and a photoelectric conversion system including the light detection device, the light detection device including an avalanche diode, the avalanche diode includes a first semiconductor region having a first conductivity type disposed at a first depth, a second semiconductor region having a second conductivity type disposed at a second depth deeper than the first depth with respect to the first surface, a third semiconductor region disposed at a third depth deeper than the second depth with respect to the first surface and in contact with the second semiconductor region; and a first separation region and a second separation region each extending from the first depth to the third depth. The second semiconductor region and the third semiconductor region each extend from the first separation region to the second separation region. The first semiconductor region, the second semiconductor region, and the third semiconductor region have portions overlapping each other in a plan view.

Description

[0001] This application is a divisional application of the invention patent application with application number 201910902187.7, application date September 24, 2019, and invention name “Light detection device and light detection system”. Technical Field

[0002] The present invention relates to a light detection device that performs photoelectric conversion, and a light detection system. Background Art

[0003] Conventionally, there is known a light detection device capable of detecting weak light at a single photon level using avalanche (electron avalanche) multiplication.

[0004] Japanese Patent Application Laid-Open No. 2018-64086 discloses a single-photon avalanche diode (SPAD) that generates avalanche multiplication by photocharge caused by a single photon in a PN junction region of a semiconductor region constituting a photoelectric conversion unit.

[0005] In addition, the SPAD discussed in Japanese Patent Laid-Open No. 2018-64086 contains a region with a low impurity concentration in a portion of a second semiconductor region having a second conductivity type disposed below a first semiconductor region having a first conductivity type. Thus, a structure is provided in which charges generated in a third semiconductor region below the second semiconductor region are easily collected in the first semiconductor region. Summary of the invention

[0006] According to one aspect of the present disclosure, a light detection device includes: a semiconductor substrate including a first surface and a second surface opposite to the first surface; and a pixel area, in which a plurality of pixels are arranged on the semiconductor substrate, each pixel including an avalanche diode, wherein the avalanche diode includes a first semiconductor region having a first conductivity type arranged at a first depth, a second semiconductor region having a second conductivity type arranged at a second depth deeper than the first depth relative to the first surface, a third semiconductor region arranged at a third depth deeper than the second depth relative to the first surface and in contact with the second semiconductor region, and a first separation region and a second separation region each extending from the first depth to the third depth, wherein the second semiconductor region and the third semiconductor region each extend from the first separation region to the second separation region, and wherein the first semiconductor region, the second semiconductor region, and the third semiconductor region have overlapping portions in a plan view.

[0007] Further features of the present disclosure will become apparent from the following description of exemplary embodiments with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a block diagram illustrating a configuration of a light detection device.

[0009] Figure 2 is a block diagram illustrating the structure of a pixel.

[0010] Figure 3 is a cross-sectional diagram of an avalanche diode.

[0011] Figure 4A , Figure 4B and Figure 4C is a top view of an avalanche diode.

[0012] Figure 5 is a graph illustrating the potential of an avalanche diode.

[0013] Fig. 6A and Figure 6B Graphs illustrating the impurity concentration of an avalanche diode and graphs illustrating the electric field strength of an avalanche diode are respectively.

[0014] 7A to 7F is a diagram illustrating a method of manufacturing an avalanche diode.

[0015] Figure 8 is a block diagram illustrating the configuration of a photoelectric conversion system.

[0016] Fig. 9 is a block diagram illustrating the configuration of a photoelectric conversion system.

[0017] Fig. 10A and Fig. 10B is a block diagram illustrating a configuration of a moving object. DETAILED DESCRIPTION

[0018] In the structure described in Japanese Patent Laid-Open No. 2018-64086, a low impurity concentration in a region of a portion of the second semiconductor region may cause a strong local electric field between the first semiconductor region and the second semiconductor region. Noise may be generated by the strong electric field, and the signal accuracy of the single photon avalanche diode (SPAD) may be reduced.

[0019] The technology described below relates to a light detection device that reduces noise while having a structure in which charges generated in a third semiconductor region can be easily collected in a first semiconductor region, and a photoelectric conversion system.

[0020] Hereinafter, a light detection device according to an exemplary embodiment will be described with reference to the accompanying drawings. It should be noted that the conductivity type of the transistor in the exemplary embodiment described below is merely an example, and the embodiment is not limited to the conductivity type described in the exemplary embodiment. With respect to the conductivity type described in the exemplary embodiment, the conductivity type can be appropriately changed, and the potential of the gate, source, and drain of the transistor can be appropriately changed according to the change of the conductivity type. For example, if the transistor operates as a switch, the low level potential and the high level potential to be supplied to the gate can be reversed with respect to the description in the exemplary embodiment.

[0021] Reference Figures 1 to 7F A light detection device according to a first exemplary embodiment of the present disclosure is described.

[0022] Figure 1 is a block diagram of a light detection device 1010 according to the present exemplary embodiment. The light detection device 1010 includes a pixel region 506 , a control pulse generation unit 509 , a horizontal scanning circuit unit 504 , a column circuit 505 , a signal line 507 , and a vertical scanning circuit unit 503 .

[0023] A plurality of pixels 500 are arranged in a matrix in a pixel region 506. One pixel 500 includes a photoelectric conversion element 501 and a pixel signal processing unit 502. The photoelectric conversion element 501 converts light into an electric signal. The pixel signal processing unit 502 outputs the converted electric signal to a column circuit 505.

[0024] The vertical scanning circuit unit 503 receives the control pulse supplied from the control pulse generating unit 509 and supplies the control pulse to each pixel 500. The vertical scanning circuit unit 503 may include a logic circuit such as a shift register or an address decoder.

[0025] The signal line 507 supplies a signal output from the pixel 500 selected by the vertical scanning circuit unit 503 to a circuit in a subsequent stage of the pixel 500 as a potential signal.

[0026] The column circuit 505 receives a signal of each pixel 500 through a signal line 507 and performs a predetermined process. The predetermined process is a process for performing noise removal, amplification, signal correction, etc. of an input signal and converting the signal into a form to be output to the outside of the sensor. For example, the column circuit 505 includes a parallel-serial conversion circuit.

[0027] The horizontal scanning circuit unit 504 supplies a control pulse to the column circuit 505 for sequentially outputting the signals processed by the column circuit 505 to the output circuit 508 .

[0028] The output circuit 508 includes a buffer amplifier and a differential amplifier, and outputs the signal output from the column circuit 505 to a recording unit or a signal processing unit outside the light detection device 1010 .

[0029] Figure 1 The pixels 500 in the pixel area 506 in the pixel region 506 may be arranged in one dimension, or only a single pixel may be arranged. Moreover, the vertical scanning circuit unit 503, the horizontal scanning circuit unit 504, and the column circuit 505 may be arranged for each block of the pixel area 506, each block including a plurality of pixel columns. Alternatively, the vertical scanning circuit unit 503, the horizontal scanning circuit unit 504, and the column circuit 505 may be arranged in each pixel column.

[0030] It is not necessary to provide the function of the pixel signal processing unit 502 for each pixel 500 one by one. For example, one pixel signal processing unit 502 may be shared by a plurality of pixels 500, and signal processing may be performed sequentially. In addition, the pixel signal processing unit 502 may be provided in a semiconductor substrate different from the semiconductor substrate in which the photoelectric conversion element 501 is provided, so as to increase the aperture ratio of the photoelectric conversion element 501. In this case, the photoelectric conversion element 501 and the pixel signal processing unit 502 are electrically connected to each other via connection wiring provided for each pixel. The vertical scanning circuit unit 503, the horizontal scanning circuit unit 504, the signal line 507, and the column circuit 505 may also be provided in a semiconductor substrate different from the semiconductor substrate in which the photoelectric conversion element 501 is provided as described above.

[0031] Figure 2 An example of a block diagram of a pixel 500 including an equivalent circuit according to the present exemplary embodiment is illustrated. Figure 2 In the embodiment, one pixel 500 has a photoelectric conversion element 501 and a pixel signal processing unit 502 .

[0032] The photoelectric conversion element 501 includes a photoelectric conversion unit 601 and a quenching element (control unit) 602 .

[0033] The photoelectric conversion unit 601 generates a charge pair corresponding to incident light by photoelectric conversion. An avalanche diode is used as the photoelectric conversion unit 601.

[0034] A potential based on a potential VH higher than a potential VL supplied to the anode of the photoelectric conversion unit 601 is supplied to the cathode of the photoelectric conversion unit 601. Therefore, the potential is supplied to the anode of the photoelectric conversion unit 601 so as to apply a reverse bias between the anode and the cathode, so that the photoelectric conversion unit 601 becomes an avalanche diode. By performing photoelectric conversion in a state where a reverse bias potential is supplied, charges generated by incident light cause avalanche multiplication to generate an avalanche current.

[0035] When the potential difference between the anode and cathode is greater than the breakdown voltage when a reverse bias potential is supplied, the avalanche diode changes to Geiger mode operation. A photodiode that detects weak signals at the level of single photons at high speed by using Geiger mode operation is a SPAD.

[0036] In addition, when the potential difference between the anode and cathode of the photoelectric conversion unit 601 is equal to or greater than the potential difference that causes avalanche multiplication of the charge generated in the photoelectric conversion unit 601 and is less than or equal to the breakdown voltage, the avalanche diode operates in a linear mode. An avalanche diode that performs light detection in a linear mode is called an avalanche diode (APD). In this exemplary embodiment, the photoelectric conversion unit 601 can operate as either a single photon avalanche diode or an avalanche diode. The potential difference that causes avalanche multiplication will be described below.

[0037] The quenching element 602 is connected between the power supply voltage portion supplying the high potential VH and the photoelectric conversion unit 601. The quenching element 602 has a function of converting a change in the avalanche current generated in the photoelectric conversion unit 601 into a voltage signal. In addition, the quenching element 602 serves as a load circuit (quenching circuit) when a signal is multiplied by avalanche multiplication, and suppresses the voltage supplied to the photoelectric conversion unit 601 to suppress avalanche multiplication (quenching operation). As the quenching element 602, for example, an active quenching circuit or a resistance element that actively suppresses avalanche multiplication by performing feedback control based on detection of an increase in the avalanche current is used.

[0038] The pixel signal processing unit 502 includes a waveform shaping unit 603, a counter circuit 609, and a selection circuit 606. The waveform shaping unit 603 shapes the voltage change obtained when the photon level signal is detected, and outputs a pulse signal. For example, an inverter circuit is used as the waveform shaping unit 603. Although an example using one inverter is shown as the waveform shaping unit 603, a circuit in which a plurality of inverters are connected in series may be used, or another circuit having a waveform shaping effect may be used.

[0039] The pulse signal output from the waveform shaping unit 603 is counted by the counter circuit 609. When the counter circuit 609 is, for example, an N-bit counter (N: a positive integer), it is possible to count the pulse signal of a single photon to about 2 to the Nth power. The counted signal is held as a detected signal. When a control pulse pRES is supplied through the driving line 607, the detected signal held in the counter circuit 609 is reset.

[0040] The control pulse pSEL is transmitted from the drive line 608 via the Figure 1The vertical scanning circuit unit 503 shown in FIG. 5 is supplied to the selection circuit 606, and switches the electrical connection and disconnection between the counter circuit 609 and the signal line 507. For example, a transistor, a buffer circuit for outputting a signal outside the pixel, or the like is used for the selection circuit 606.

[0041] A switch such as a transistor may be provided between the quenching element 602 and the photoelectric conversion unit 601 or between the photoelectric conversion element 501 and the pixel signal processing unit 502 to switch the electrical connection. Similarly, a switch such as a transistor may be used to electrically switch the supply of a high potential VH to the quenching element 602 or the supply of a low potential VL to the photoelectric conversion element 501.

[0042] In the pixel area 506 in which a plurality of pixels 500 are arranged in a matrix form, a captured image can be acquired by a rolling shutter operation, wherein the count of the counter circuit 609 can be sequentially reset for each row, and a detected signal held in the counter circuit 609 can be sequentially output for each row.

[0043] Alternatively, the captured image may be acquired by a global electronic shutter operation in which the counts of the counter circuits 609 of all pixel rows are reset simultaneously and the detected signals held in the counter circuits 609 are sequentially output for each row. In the case of performing the global electronic shutter operation, it is preferable to provide a switching device to switch between a case of counting and a case of not counting by the counter circuits 609. The switching device is, for example, the above-mentioned switch.

[0044] In the present exemplary embodiment, a configuration is described in which a captured image is acquired by using the counter circuit 609. However, instead of the counter circuit 609, a time-to-digital converter (hereinafter, TDC) and a memory may be used as the light detection device 1010 to acquire pulse detection timing.

[0045] At this time, the generation timing of the pulse signal output from the waveform shaping unit 603 is converted into a digital signal by the TDC. The control pulse pREF (reference signal) is transmitted from the drive line Figure 1 The vertical scanning circuit unit 503 is supplied to the TDC for measuring the timing of the pulse signal. When the input timing of the signal output from each pixel via the waveform shaping unit 603 is the relative time of the reference control pulse pREF, the TDC acquires the signal as a digital signal.

[0046] For the TDC circuit, a delay line method in which a buffer circuit is connected in series to provide a delay, a loop TDC method in which a delay line is connected in a loop, etc. are used. Although another method may be used, it is preferable to adopt a circuit method capable of achieving a time resolution higher than or equal to that of the photoelectric conversion unit 601.

[0047] The digital signal representing the pulse detection timing obtained by the TDC is held in one or more memories. When multiple memories are arranged, it is possible to control the output to the signal line 507 for each memory by supplying multiple signals to the selection circuit 606 when the digital signal held in the memory is output to the signal line 507.

[0048] Next, we will refer to Figure 3 The light detection device 1010 according to the present exemplary embodiment is described.

[0049] The light detection device 1010 according to the present exemplary embodiment has a pixel including an avalanche diode. Among the charge pairs generated in the avalanche diode, the conductivity type in which the charge used as the signal charge is the main carrier charge is referred to as the first conductivity type (N type). In addition, the conductivity type opposite to the first conductivity type is referred to as the second conductivity type (P type).

[0050] Figure 3 1 is a cross-sectional view schematically illustrating an avalanche diode in the present exemplary embodiment. The avalanche diode according to the present exemplary embodiment is placed in a semiconductor substrate 100. The semiconductor substrate 100 has a first surface and a second surface opposite to the first surface. For example, the first surface is the front surface of the semiconductor substrate 100, and the second surface is the rear surface of the semiconductor substrate 100. In the present exemplary embodiment, the depth direction is defined as from the first surface to the second surface. The gate electrode of the transistor and the multilayer wiring structure are arranged on the front side of the semiconductor substrate 100.

[0051] exist Figure 3 In the region between the separation portion 204-1 and the separation portion 204-2 in the embodiment, the first semiconductor region 101 and the second semiconductor region 102 having the first conductivity type are provided, and the third semiconductor region 103 having the second conductivity type and the fourth semiconductor region 104 having the second conductivity type are provided. At this time, the third semiconductor region 103 and the fourth semiconductor region 104 have the same depth and the same impurity concentration. Usually, the third semiconductor region 103 and the fourth semiconductor region 104 are formed integrally.

[0052] The first semiconductor region 101 and the second semiconductor region 102 having the first conductivity type and the eighth semiconductor region 203 having the second conductivity type are arranged at a first depth A indicated by a line segment AA'. The first semiconductor region 101 and the second semiconductor region 102 are in contact with each other in a plan view, and the second semiconductor region 102 and the eighth semiconductor region 203 are in contact with each other in a plan view. In the present exemplary embodiment, the expression "the first semiconductor region 101 and the second semiconductor region 102 are arranged at a first depth A" means that the concentration peak of the ion-implanted impurities is arranged at the first depth A, for example. However, the concentration peak is not necessarily arranged at the first depth A, and design errors and manufacturing errors are also allowed.

[0053] The second depth B indicated by the line segment BB' is located at a position deeper than the first depth A relative to the first surface, and places the third semiconductor region 103 and the fourth semiconductor region 104 having the second conductivity type. In addition, a strong electric field region 150 for avalanche multiplication is formed between the first semiconductor region 101 having the first conductivity type and the third semiconductor region 103 having the second conductivity type.

[0054] The third depth C indicated by the line segment CC′ is located at a position deeper than the second depth B with respect to the first surface, and the fifth semiconductor region 105 is provided at the third depth C. Preferably, the fifth semiconductor region 105 has the first conductivity type.

[0055] FIG. 4A to FIG. 4C yes Figure 3 A schematic plan view of Figure 4A yes Figure 3 A schematic plan view at a first depth A of Figure 4B yes Figure 3 A schematic plan view at a second depth B of Figure 4C yes Figure 3 A schematic plan view at the third depth C of FIG. FIG. 4A to FIG. 4C The boundary of each semiconductor region in FIG. 1 is drawn in a circular shape, but exemplary embodiments are not limited thereto.

[0056] exist Figure 4A In the embodiment, the first semiconductor region 101 is placed in the second semiconductor region 102, and the second semiconductor region 102 is placed in the eighth semiconductor region 203. In addition, the area of ​​the second semiconductor region 102 is larger than that of the first semiconductor region 101.

[0057] exist Figure 4BIn the embodiment, the third semiconductor region 103 is placed in the fourth semiconductor region 104, and the fourth semiconductor region 104 is placed in the seventh semiconductor region 202. In addition, the third semiconductor region 103 and the fourth semiconductor region 104 are formed at the same depth and with the same impurity concentration.

[0058] exist Figure 4C In the embodiment, the fifth semiconductor region 105 is placed in the P-type semiconductor region 202. Figure 4B and Figure 4C When overlapping, the third semiconductor region 103 and the fourth semiconductor region 104 overlap with the fifth semiconductor region 105 in a plan view.

[0059] Figure 5 yes Figure 3 Potential diagram of an avalanche diode shown in .

[0060] exist Figure 5 In FIG. 1 , the dotted line 20 indicates the potential distribution of the line segment FF′, and the solid line 21 indicates Figure 3 Potential distribution of line segment EE' in . Figure 5 The diagram shows the potential referenced to electrons, which are the major charge carriers of an N-type semiconductor region. When the major charge carriers are holes, the relationship between the high level potential and the low level potential is reversed. In addition, Figure 5 The depth A in Figure 3 Similarly, depth B corresponds to line segment BB', depth C corresponds to line segment CC', and depth D corresponds to line segment DD', respectively.

[0061] exist Figure 5 , at depth A, the potential height of the solid line 21 is represented by A1 and the potential height of the dotted line 20 is represented by A2, and at depth B, the potential height of the solid line 21 is represented by B1 and the potential height of the dotted line 20 is represented by B2. In addition, at depth C, the potential height of the solid line 21 is represented by C1 and the potential height of the dotted line 20 is represented by C2, and at depth D, the potential height of the solid line 21 is represented by D1 and the potential height of the dotted line 20 is represented by D2.

[0062] refer to Figure 3 and Figure 5 The potential height of the first semiconductor region 101 corresponds to A1, and the potential height of the third semiconductor region 103 corresponds to B1. In addition, the potential height of the second semiconductor region 102 corresponds to A2, and the potential height of the fourth semiconductor region 104 corresponds to B2.

[0063] about Figure 5As shown in the dotted line 20 in FIG. 1 , the potential gradually decreases from the depth D to the depth C. Then, the potential gradually increases from the depth C to the depth B, and the potential becomes the B2 level at the depth B. Then, the potential decreases from the depth B to the depth A, and becomes the A2 level at the depth A.

[0064] On the other hand, regarding the solid line 21 , the potential gradually decreases from the depth D to the depth C and from the depth C to the depth B, and becomes the B1 level at the depth B. Then, the potential sharply decreases from the depth B to the depth A, and becomes the A1 level at the depth A.

[0065] At the depth D, the potentials of the dotted line 20 and the solid line 21 are approximately equal to each other, and in the region indicated by the line segment EE' and the line segment FF', there is a potential gradient that gradually decreases toward the first surface side of the semiconductor substrate 100. Therefore, the charges generated in the light detection device 1010 move to the first surface side due to the slow potential gradient.

[0066] In the present exemplary embodiment, as described above, the third semiconductor region 103 and the fourth semiconductor region 104 are formed at the same depth and at the same concentration. In the avalanche diode according to the present exemplary embodiment, the impurity concentration of the third semiconductor region 103 having the second conductivity type is lower than the impurity concentration of the first semiconductor region 101 having the first conductivity type, and the potential is supplied to the first semiconductor region 101 and the third semiconductor region 103 so as to reverse bias them to each other. Thus, a depletion layer region is formed on the third semiconductor region 103 side. With this structure, the potential height of the first conductivity type charge as a signal charge is lower in the third semiconductor region 103 than in the fourth semiconductor region 104. Thus, the fourth semiconductor region becomes a potential barrier for the charge photoelectrically converted in the fifth semiconductor region 105, so that the charge may be collected in the third semiconductor region.

[0067] In addition, due to the potential difference between the third semiconductor region 103 and the fourth semiconductor region 104, the potential Figure 3 The depth C in becomes lower in the direction from the line segment FF′ to the line segment EE′. Thus, in the process that the charges photoelectrically converted in the fifth semiconductor region 105 move to the first surface of the semiconductor substrate 100 , the charges are easily moved in the direction of the third semiconductor region 103 .

[0068] The charges moved to the vicinity of the third semiconductor region 103 are Figure 5 The steep potential gradient from depth B to depth A in the solid line 21 is accelerated, ie, accelerated by a strong electric field, and avalanche multiplication occurs.

[0069] On the other hand, existence does not Figure 3between the second semiconductor region 102 in the embodiment and the fourth semiconductor region 104 having the second conductivity type (ie, between Figure 5 A potential distribution that causes avalanche multiplication from depth B to depth A on the dotted line 20 in FIG. 10A . Therefore, the charges generated in the fifth semiconductor region 105 can be counted as signal charges without increasing the area of ​​the strong electric field region 150 relative to the size of the photodiode.

[0070] In addition, due to Figure 5 The potential gradient from the depth B to the depth C of the midpoint line 20, the charge photoelectrically converted in the fourth semiconductor region 104 flows into the fifth semiconductor region 105. Due to the above reasons, the charge in the fifth semiconductor region 105 is easily transferred to the third semiconductor region 103. Therefore, the charge photoelectrically converted in the fourth semiconductor region 104 is transferred to the first semiconductor region 101 via the third semiconductor region 103, and is detected as a signal charge by avalanche multiplication. Therefore, the charge photoelectrically converted in the fourth semiconductor region 104 can be detected as sensitivity.

[0071] Hereinafter, exemplary embodiments including values ​​of (one or more) of impurity concentration will be described in detail. Although a configuration in which the signal charge carriers are electrons will be described here, the exemplary embodiments discussed herein are also applicable to the case in which the signal charge carriers are holes. In that case, each semiconductor region and potential relationship is reversed.

[0072] Reference Figure 3 Schematic cross-sectional views and schematic plan views are described of exemplary embodiments of the present disclosure.

[0073] In this exemplary embodiment, in order to make the description easy to understand, Figure 3 , the description will be given assuming that the first semiconductor region 101 is N-type, the second semiconductor region 102 is N-type, and the third semiconductor region 103 is P-type. In addition, the description will be given assuming that the fourth semiconductor region 104 is P-type, the fifth semiconductor region 105 is N-type, and the sixth semiconductor region 201, the seventh semiconductor region 202, and the eighth semiconductor region 203 are P-type, respectively.

[0074] Figure 3 The separation parts 204-1 and 204-2 in the embodiment are formed by P-type semiconductor regions arranged in the depth direction from the first surface. More specifically, the P-type semiconductor region 203 and the P-type semiconductor region 202 are arranged in sequence in the depth direction from the first surface and contact each other. The P-type semiconductor region 202 is electrically connected to the P-type semiconductor region 104 and the P-type semiconductor region 201.

[0075] The impurity concentration of the P-type semiconductor region 203 is higher than the impurity concentration of each of the P-type semiconductor regions 202, 201, and 104. For example, the impurity concentration of the P-type semiconductor region 203 is about 1×10^19 to 10^20 [atoms / (cm^3)]. It should be noted that in this specification, the symbol "^" represents a power. More specifically, 10^19 represents 10 to the 19th power. This allows the contact resistance to be reduced by connecting the P-type semiconductor region 203 and the contact plug 302, compared to the contact resistance by connecting the P-type semiconductor region 202 to the contact plug 302.

[0076] The N-type semiconductor region 101 is a region with a higher impurity concentration than the N-type semiconductor region 105. For example, the impurity concentration of the N-type semiconductor region 101 is 1×10^18 [atoms / (cm^3)] or more, and a potential that is a reverse bias for the separation portions 204-1 and 204-2 is supplied to the N-type semiconductor region 101.

[0077] The impurity concentration of the N-type semiconductor region 102 is lower than the impurity concentration of the N-type semiconductor region 101. For example, the impurity concentration of the N-type semiconductor region 102 is about 1×10^16 to 5×10^17 [atoms / (cm^3)]. If the second semiconductor region 102 is a P-type, an avalanche multiplication electric field is formed between the first semiconductor region 101 and the second semiconductor region 102 depending on the impurity concentration of the second semiconductor region 102, and the avalanche multiplication electric field becomes a factor of noise deterioration.

[0078] The impurity concentration of the P-type semiconductor region 104 is lower than the impurity concentration of the P-type semiconductor region 202, and the P-type semiconductor region 103 and the P-type semiconductor region 104 have the same impurity concentration. For example, the impurity concentration of the P-type semiconductor regions 103 and 104 is approximately 1×10^16 to 1×10^17 [atoms / (cm^3)].

[0079] A PN junction is formed between the P-type semiconductor region 103 and the N-type semiconductor region 101. As described above, by lowering the impurity concentration of the P-type semiconductor region 103 compared to the N-type semiconductor region 101, the entire P-type semiconductor region 103 becomes a depletion layer region.

[0080] In addition, the depletion layer region extends to a partial region of the N-type semiconductor region 101, and a strong electric field is induced in the extended depletion layer region. The strong electric field causes avalanche multiplication in the depletion layer region extending to the partial region of the N-type semiconductor region 101, and a current based on the amplified charge is output as a signal charge through the contact plug 301.

[0081] Next, the impurity concentrations of the N-type semiconductor region 101, the P-type semiconductor region 103, and the P-type semiconductor region 104 will be described. When a potential difference that causes avalanche multiplication in a depletion layer region generated in a local portion of the N-type semiconductor region 101 is supplied, the impurity concentration of each semiconductor region is set to the impurity concentration of a portion of the depletion layer region that does not reach the first surface of the N-type semiconductor region 101. This is because, when the depletion layer region expands so as to contact the first surface of the semiconductor substrate 100, the possibility of noise caused by dangling bonds or the like on the surface of the semiconductor substrate 100 being mixed into the depletion layer region from the first surface increases.

[0082] Thus, the potential difference between the N-type semiconductor region 101 and the separation portions 204-1 and 204-2 is set so that the electric field in the depth direction induced in the depletion layer becomes sufficiently large. In the present exemplary embodiment, the potential difference at which the electric field becomes sufficiently large is a potential difference at which the charges affected by the electric field cause avalanche multiplication. In other words, the potential difference indicates the potential difference between the N-type semiconductor region 101 and the P-type semiconductor region 203, at which the light detection element of the present structure realizes operation as an avalanche diode (APD or SPAD).

[0083] Specifically, the potential difference between the N-type semiconductor region 101 and the P-type semiconductor region 104 is 6 V or more. At this time, as described above, all regions of the P-type semiconductor region 103 electrically connected to the P-type semiconductor region 104 become depletion layer regions, and in the depletion layer regions extending to the local regions of the N-type semiconductor region 101, a strong electric field is generated so that avalanche multiplication occurs.

[0084] In addition, it is more preferable that the potential difference between the N-type semiconductor region 101 and the P-type semiconductor region 104 is 10 V or more and 30 V or less. At this time, for example, a potential of 10 V or more is supplied to the N-type semiconductor region 101, and a potential of 0 V or less is supplied to the P-type semiconductor region 203. However, when the potential difference is 6 V or more, the value of the potential is not limited to this example.

[0085] exist Figure 3In the embodiment, it is assumed that the N-type semiconductor region 105 having an impurity concentration lower than that of the N-type semiconductor region 101 is placed immediately below the N-type semiconductor region 101 having a high impurity concentration, and the P-type semiconductor regions 103 and 104 are not provided. In this case, it is possible to generate charges in the N-type semiconductor region 105 and read out the charges from the N-type semiconductor region 101. However, it is difficult to cause avalanche multiplication under voltage conditions equivalent to those of the present exemplary embodiment. This is because most of the potential difference applied between the N-type semiconductor region 101 and the P-type semiconductor region 203 is applied to the depletion layer region of the N-type semiconductor region 105, and the potential difference applied to the avalanche multiplication region near the N-type semiconductor region 101 is reduced. On the other hand, in the present exemplary embodiment, since the N-type semiconductor region 105 is surrounded by the P-type semiconductor region in each direction, the potential in the N-type semiconductor region 105 becomes a level closer to the P-type semiconductor region than the N-type semiconductor region 101 at its periphery. Therefore, by suppressing the excessive extension of the depletion layer into the deep part of the substrate by the P-type semiconductor region 104, it is possible to concentrate most of the above-mentioned potential difference on the avalanche multiplication region near the N-type semiconductor region 101. As a result, the photoelectric charge can avalanche multiply at a lower voltage. At this time, the impurity concentration of the N-type semiconductor region 105 must be lower than the impurity concentration of the N-type semiconductor region 101.

[0086] refer to Figure 3 , an example in which the N-type semiconductor region 105 has the same impurity concentration is described. However, it is preferable that the N-type semiconductor region 105 has a gradient of impurity concentration to have a potential structure so that the charge moves to the first surface side of the semiconductor substrate 100. By providing a gradient of impurity concentration, it is possible to easily move the charge to the N-type semiconductor region 101.

[0087] Furthermore, in the case where the gradient of the impurity concentration is made into a potential structure in which the charge moves to the first surface side of the semiconductor substrate 100, in the region in which the N-type semiconductor region 105 is provided, the first surface side may be the N-type semiconductor region, and the second surface side may be the P-type semiconductor region. Alternatively, a P-type semiconductor region having an impurity concentration lower than that of the P-type semiconductor region 104 may be provided in place of the N-type semiconductor region 105. Even in this case, it is preferable to have a gradient of the impurity concentration so as to provide a potential structure in which the charge moves to the first surface side of the semiconductor substrate 100.

[0088] The P-type semiconductor region 201 is disposed at a position deeper than the N-type semiconductor region 105 and defines the depth of the photoelectric conversion region. The N-type semiconductor region 105 forms a PN junction with each of the P-type semiconductor regions 103, 104, 201, and 202. The impurity concentration of the P-type semiconductor region 201 is higher than the impurity concentration of the P-type semiconductor region 104. Therefore, the charges generated near the P-type semiconductor region 201 are likely to move toward the first surface direction.

[0089] The contact plug 301 is also connected to the N-type semiconductor region 101 , and the contact plug 302 is connected to the P-type semiconductor region 203 .

[0090] refer to Figure 3 , the contact plug 302 has been described as being disposed on the first surface side. However, the contact plug 302 may be disposed on the second surface side.

[0091] When the contact plug 302 is provided on the second surface side, it is preferable that the impurity concentration in a portion of the P-type semiconductor region 201 in which the contact plug 302 is provided is higher than the impurity concentration of the P-type semiconductor region 201. In other words, the impurity concentration is set to a semiconductor region corresponding to the P-type semiconductor region 203 of the structure in which the contact plug 302 is provided on the first surface side.

[0092] Even in the case where the separation portions 204 - 1 and 204 - 2 have the insulating separation portion on the first surface side, the contact plug 302 may be placed on the second surface side.

[0093] Next, we will refer to Figure 5 The potential structure in the present exemplary embodiment is described. Here, it is assumed that the charge carrier used as a signal is an electron.

[0094] Figure 5 The solid line 21 in the figure indicates the Figure 3 The cross-sectional potential of the line segment EE' in the solid line 21. Figure 3 In , the point where line segment AA' and line segment EE' intersect is represented by A1, the point where line segment BB' and line segment EE' intersect is represented by B1, the point where line segment CC' and line segment EE' intersect is represented by C1, and the point where line segment DD' and line segment EE' intersect is represented by D1. Figure 3 The photoelectrically converted electrons in the N-type semiconductor region 105 in Figure 5 The potentials D1 to C1 and C1 to B1 in FIG. 1 are moved, and are avalanche multiplied by the steep potential gradient from B1 to A1. Then, after passing through the N-type semiconductor region 101, the electrons reach the contact plug 301 and are detected as signal charges.

[0095] Figure 5 The dotted line 20 in FIG. Figure 3 The cross-sectional potential of the line segment FF' in the figure. At point 20, Figure 3 In , the point where line segment AA' and line segment FF' intersect is represented by A2, the point where line segment BB' and line segment FF' intersect is represented by B2, the point where line segment CC' and line segment FF' intersect is represented by C2, and the point where line segment DD' and line segment FF' intersect is represented by D2. Figure 3 The photoelectrically converted electrons in the N-type semiconductor region 105 in Figure 5 The potential in D2 moves to C2. However, because the potential between C2 and B2 becomes a barrier for the electron, the electron cannot overcome the barrier. Therefore, the electron moves to Figure 3 The electrons then travel along the N-type semiconductor region 105 near the center indicated by the line segment EE'. Figure 5 Then, the electrons are avalanche multiplied by the steep potential gradient from B1 to A1, pass through the N-type semiconductor region 101, reach the contact plug 301, and are detected as signal charges.

[0096] in addition, Figure 3 The charges generated near the boundary between the P-type semiconductor region 104 and the N-type semiconductor region 105 in Figure 5 The potential gradient moves from potential B2 to potential C2. Thereafter, as described above, the charge moves to Figure 3 The charge is then avalanche multiplied by the steep potential gradient from B1 to A1. The avalanche multiplied charge passes through the N-type semiconductor region 101, reaches the contact plug 301, and is then detected as a signal charge.

[0097] In other words, a gentle potential gradient is formed from the portion near the separation portions 204-1 and 204-2 toward the portion away from the separation portions 204-1 and 204-2 with respect to the N-type semiconductor region 105. Therefore, the charges photoelectrically converted in the N-type semiconductor region 105 are finally Figure 5 The potential in the vicinity of B1 is collected.

[0098] Next, we will refer to Fig. 6A and Figure 6B describe Figure 3 The reason why the P-type semiconductor region 103 in FIG. 1 is set to have the same impurity concentration as that of the P-type semiconductor region 104 .

[0099] Fig. 6A The diagram shows a semiconductor substrate 100 starting from the first surface along the Figure 3 The impurity concentration distribution of line segment EE' in the depth direction. Fig. 6A, impurity concentration profile 30 illustrates that the peak of the N-type impurity concentration profile is at depth A, and impurity concentration profiles 31 and 32 illustrate that the peak of the P-type impurity concentration profile is at depth B. In addition, a point where the N-type impurity intersects the P-type impurity is a PN junction portion.

[0100] In this exemplary embodiment, Fig. 6A The depth A in Figure 3 The point where the line segments AA' and EE' intersect, and the depth B is Figure 3 The point where line segments BB' and EE' intersect.

[0101] In addition, Fig. 6A , P-type impurity concentration distributions 31 and 32 represent differences in P-type impurity concentrations. A lower peak concentration is represented by P-type impurity concentration distribution 31, and a higher peak concentration is represented by P-type impurity concentration distribution 32.

[0102] The P-type impurity concentration distribution 32 shows Figure 3 The P-type semiconductor region 104 in FIG. 1 has the same impurity concentration as the P-type semiconductor region 103. On the other hand, the P-type impurity concentration distribution 31 illustrates a case where the P-type impurity concentration in the region serving as a flow path for signal charges is lower than the P-type impurity concentration in the peripheral region.

[0103] Figure 6B The diagram shows the horizontal axis with Fig. 6A The electric field intensity distribution at the same depth.

[0104] exist Figure 6B In FIG. 4 , the electric field intensity distribution 41 is shown schematically. Fig. 6A The P-type impurity concentration distribution of FIG. 3 is the case of the P-type impurity concentration distribution 31, and the electric field intensity distribution 42 illustrates the Fig. 6A The P-type impurity concentration distribution of φ is the case of the P-type impurity concentration distribution 32 .

[0105] exist Fig. 6A In the case of the P-type impurity concentration distribution 31 in FIG. 1 , the concentration of the lower doping side of the PN junction is lower than that in the case of the P-type impurity concentration distribution 32. Therefore, in order to obtain the strong electric field required for avalanche multiplication, it is necessary to set the applied voltage higher. When the applied voltage increases, a local strong electric field region is formed, such as Figure 6B The electric field strength distribution in FIG41 is shown, and causes noise degradation.

[0106] On the other hand, in the case where the P-type impurity concentration profile is the P-type impurity concentration profile 32, the concentration of the lower doping side of the PN junction is higher than that in the case of the P-type impurity concentration profile 31. Therefore, the voltage applied to obtain the strong electric field required for avalanche multiplication can be lower than in the above case. When the applied voltage is reduced, as Figure 6B As shown in the electric field intensity distribution 42, compared with the electric field intensity distribution 41, it is less likely to form a local strong electric field region, so noise can be suppressed.

[0107] Next, we will refer to 7A to 7F Description Manufacturing Figure 3 For steps not described in order, the order may be changed appropriately. In addition, it is possible to apply known manufacturing methods to 7A to 7F A process not described in .

[0108] like Fig. 7A As shown in FIG. 1 , impurities (eg, boron) are ion-implanted from the normal direction of the first surface of the semiconductor substrate 100 into a region to be a P-type semiconductor region 201. Thus, the P-type semiconductor region 201 is formed at a deep position relative to the first surface of the semiconductor substrate 100.

[0109] Next, if Figure 7B As shown in , impurities (e.g., boron) are ion-implanted from the normal direction of the first surface of the semiconductor substrate 100. Thus, the P-type semiconductor region 202 is formed at a position shallower than the P-type semiconductor region 201. At this time, the P-type semiconductor region 202 is formed so that a portion of the P-type semiconductor region 202 and a portion of the P-type semiconductor region 201 are connected to each other. In addition, the P-type semiconductor region 202 is formed so that the impurity concentration of the P-type semiconductor region 201 is higher than the impurity concentration of the P-type semiconductor region 202.

[0110] Next, if Figure 7C As shown in , impurities (e.g., phosphorus or arsenic) are ion-implanted from the normal direction of the first surface of the semiconductor substrate 100 to form an N-type semiconductor region 105. In addition, P-type semiconductor regions 104 and 103 are formed by ion-implanting impurities (e.g., boron) from the normal direction of the first surface of the semiconductor substrate 100. At this time, the N-type semiconductor region 105 is formed at a position deeper than the P-type semiconductor regions 103 and 104. In addition, since the P-type semiconductor regions 103 and 104 are formed at the same depth and the same impurity concentration, the P-type semiconductor regions 103 and 104 can be formed by using the same photomask pattern.

[0111] Next, if Fig.7D As shown in , P-type ion implantation is performed in the normal direction of the first surface of the semiconductor substrate 100 to form a P-type semiconductor region 203. At this time, the P-type semiconductor region 203 is formed shallower than the P-type semiconductor region 202, and a portion of the P-type semiconductor region 203 is connected to the P-type semiconductor region 202.

[0112] Next, if Fig. 7EAs shown in , N-type ion implantation is performed in the normal direction of the first surface of the semiconductor substrate 100 to form N-type semiconductor regions 101 and 102. At this time, the N-type semiconductor region 101 is formed at a position shallower than the P-type semiconductor region 103, and the N-type semiconductor region 102 is formed at a position shallower than the P-type semiconductor region 104.

[0113] Next, if Figure 7F As shown in FIG. 1 , the contact plug 301 is provided so as to be in contact with the N-type semiconductor region 101, and the contact plug 302 is provided so as to be in contact with the P-type semiconductor region 203. The signal charge detected by the avalanche multiplication is transferred to the photon counting processing circuit through the contact plug 301.

[0114] In the light detection device 1010 according to the present exemplary embodiment, the P-type semiconductor regions 103 and 104 have the same depth and the same impurity concentration. The avalanche multiplication in the present exemplary embodiment is generated due to the voltage difference between the N-type semiconductor region 101 and the P-type semiconductor region 104. If the concentration of the P-type semiconductor region 103 is lower than the concentration of the P-type semiconductor region 104, the relative positions of the N-type semiconductor region 101 and the P-type semiconductor region 104 may be misaligned due to manufacturing errors, etc. In this case, the voltage difference between the N-type semiconductor region 101 and the P-type semiconductor region 104 is changed, so that the avalanche multiplication is weakened or enhanced. Thus, the accuracy of the signal of the pixel 500 is reduced.

[0115] However, as in the case of the present exemplary embodiment, when the P-type semiconductor regions 103 and 104 are at the same depth and at the same concentration, relative displacement with the N-type semiconductor region 101 is unlikely to occur. Therefore, the voltage difference between the N-type semiconductor region 101 and the P-type semiconductor regions 103 and 104 does not easily fluctuate. Thus, the light detection device 1010 according to the present exemplary embodiment has the effect of suppressing a decrease in the signal accuracy of the pixel 500.

[0116] The light detecting device 1010 described in the present exemplary embodiment may be applied to a surface illumination type in which light is incident from a first surface or a rear surface illumination type in which light is incident from a second surface.

[0117] In the second exemplary embodiment, an example of a light detection system using the light detection device 1010 of each exemplary embodiment will be described. Figure 8 An invisible light detection system and a medical diagnosis system such as a positron emission tomography (PET) system are described as examples of the light detection system.

[0118] The pixel 500 according to the second exemplary embodiment has a TDC and a memory instead of Figure 2 Here, description will be given assuming that the TDC is referred to as TDC 204 and the memory is referred to as memory 205.

[0119] Figure 8 is a block diagram illustrating a configuration of an invisible light detection system. The invisible light detection system includes a wavelength conversion unit 1201 , a data processing unit 1207 , and a plurality of light detection devices 1010 (ie, light detection devices 1010A and 1010B).

[0120] The irradiation object 1200 outputs light in the wavelength band of invisible light. Each wavelength conversion unit 1201 receives the light in the wavelength band of invisible light output from the irradiation object 1200 and emits visible light.

[0121] The visible light emitted from each wavelength conversion unit 1201 is incident on the photoelectric conversion unit 601, and the photoelectric conversion unit 601 performs photoelectric conversion on the incident visible light. Then, the light detection devices 1010 each hold a digital signal of a signal generated based on the photoelectrically converted charge in the memory 205 through the quenching element 602, the waveform shaping unit 603, and the TDC 204. A plurality of light detection devices 1010 may be formed as one device, or may be formed by arranging a plurality of devices.

[0122] The plurality of digital signals held in the memories 205 of the plurality of light detection devices 1010 are subjected to signal processing by the data processing unit 1207. The data processing unit 1207 as a signal processing means performs synthesis processing of a plurality of images obtained from the plurality of digital signals.

[0123] Next, the structure of a medical diagnosis system such as a PET system will be described as a specific example of the invisible light detection system.

[0124] The subject as the irradiation object 1200 outputs a radiation pair from inside the living body. Each wavelength conversion unit 1201 constitutes a scintillator, and when the radiation output from the subject is incident on the scintillator, the scintillator emits visible light.

[0125] Each photoelectric conversion unit 601 irradiated with visible light emitted from the scintillator performs photoelectric conversion of the visible light, and each light detection device 1010 holds a digital signal of a signal generated based on the charge subjected to the photoelectric conversion in the memory 205 through the quenching element 602, the waveform shaping unit 603, and the TDC 204. In other words, each light detection device 1010 is arranged to detect the arrival time of radiation output from the subject, and detect the visible light irradiated from the scintillator, and hold the digital signal in the memory 205.

[0126] The digital signals held in the memory 205 of the plurality of light detection devices 1010 are processed by the data processing unit 1207. As a signal processing device, the data processing unit 1207 performs synthesis processing such as image reconstruction using a plurality of images obtained from the plurality of digital signals to form an image of the living body interior of the subject.

[0127] In the third exemplary embodiment, an example of a light detection system using the light detection device 1010 of each exemplary embodiment will be described.

[0128] refer to Fig. 9 , a distance detection system will be described as an example of a light detection system. The pixel 500 according to the third exemplary embodiment has the TDC and the memory described in the first exemplary embodiment, instead of Figure 2 Here, a description will be given assuming that the TDC will be referred to as TDC 204 instead of the counter circuit 609 and the memory will be referred to as memory 205.

[0129] Reference Fig. 9 An example of a block diagram of a distance detection system according to the third exemplary embodiment is described. The distance detection system includes a light source control unit 1301 , a light emitting unit 1302 , an optical member 1303 , a light detection device 1010 , and a distance calculation unit 1309 .

[0130] The light source control unit 1301 controls driving of the light emitting unit 1302. When the light emitting unit 1302 receives a signal from the light source control unit 1301, the light emitting unit 1302 emits short pulses (pulse trains) of light with respect to the imaging direction.

[0131] The light emitted from the light emitting unit 1302 is reflected by the subject 1304. The reflected light is received by the photoelectric conversion unit 601 of the light detection device 1010 through the optical member 1303, and a signal based on the photoelectrically converted charge is input to the TDC 204 via the waveform shaping unit 603.

[0132] The TDC 204 compares the signal obtained from the light source control unit 1301 with the signal input from the waveform shaping unit 603. Then, the time required to receive the reflected light reflected from the subject 1304 after the light emitting unit 1302 emits the pulse light is converted into a digital signal with high accuracy. The digital signal output from the TDC 204 is held in the memory 205.

[0133] The distance calculation unit 1309 calculates the distance from the light detection device 1010 to the object based on the digital signals of the plurality of measurements held in the memory 205. The distance detection system can be used for a vehicle, for example.

[0134] Next, Fig. 10A and Fig. 10B Illustration of the use Figure 2 An example of a light detection system in the case of the counter circuit 609. Fig. 10A and Fig. 10B In the following, a description will be given of a light detection system for a vehicle-mounted camera as an example of the light detection system.

[0135] The light detection system 1000 is a light detection system including a distance measuring pixel and an imaging pixel according to the present exemplary embodiment. The light detection system 1000 has an image processing unit 1030 for performing image processing on a plurality of digital signals acquired by the light detection device 1010. In addition, the light detection system 1000 has a parallax calculation unit 1040 for calculating parallax (phase difference of parallax images) from a plurality of images acquired by the image processing unit 1030.

[0136] The light detection system 1000 further includes: a distance measurement unit 1050 for calculating the distance to the object based on the calculated parallax amount; and a collision judgment unit 1060 for determining whether there is a possibility of a collision based on the calculated distance. In the present exemplary embodiment, the parallax calculation unit 1040 and the distance measurement unit 1050 are examples of a distance information acquisition device for acquiring distance information related to the distance to the object. The distance information is information related to parallax, defocus amount, distance to the object, etc.

[0137] The collision judgment unit 1060 may determine the collision probability using any one of the parallax amount, the defocus amount, the distance to the object, etc. The distance information acquisition device may be implemented by specially designed hardware, by a software module, or by a combination thereof. In addition, the distance information acquisition device may be implemented by a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc. It may also be implemented by any combination of these items.

[0138] The light detection system 1000 is connected to the vehicle information acquisition device 1310, and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The light detection system 1000 is also connected to a control electronic control unit (ECU) 1410, which is a control device for outputting a control signal for generating a braking force on the vehicle based on the determination result of the collision judgment unit 1060.

[0139] The light detection system 1000 is also connected to a warning device 1420 that issues an alert to the driver based on the determination result of the collision judgment unit 1060. For example, when the possibility of a collision is high as a determination result of the collision judgment unit 1060, the control ECU 1410 performs vehicle control for avoiding the collision and reducing damage by applying the brakes, returning the accelerator, suppressing the engine output, etc. The warning device 1420 provides a warning to the user by emitting a warning sound, displaying a warning message on the screen of the car navigation system, and vibrating the seat belt or the steering gear.

[0140] In the present exemplary embodiment, light detection system 1000 captures a surrounding image of a vehicle, such as the front or rear of the vehicle. Fig. 10B The light detection system 1000 is illustrated when the front of the vehicle is imaged. Control for avoiding collision with another vehicle has been described above. However, the light detection system can also be used in control for autonomous driving to follow another vehicle, control for autonomous driving to avoid leaving the lane, and the like. In addition, the use of the light detection system 1000 is not limited to vehicles such as personal transport vehicles, and the light detection system 1000 can be used for moving bodies (mobile devices) such as ships, airplanes, and industrial robots, for example. In addition, the use of the light detection system 1000 is not limited to moving bodies, but can include devices using object recognition such as intelligent transportation systems (ITS).

[0141] The present exemplary embodiment provides a light detection device and a photoelectric conversion system with reduced noise.

[0142] While the present disclosure has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments.The scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions.

Claims

1. A light detection device, comprising: A semiconductor substrate including a first surface; as well as a pixel region in which a plurality of pixels are arranged on a semiconductor substrate, each pixel including an avalanche diode, Among them, in the cross-sectional view, the avalanche diode includes: a first semiconductor region of a first conductivity type disposed at a first depth; a second semiconductor region of a second conductivity type disposed at a second depth relative to the first surface that is deeper than the first depth, an avalanche multiplication region being formed between the first semiconductor region and the second semiconductor region; a third semiconductor region of the first conductivity type disposed at a third depth deeper than the second depth relative to the first surface and in contact with the second semiconductor region; and a first separation region and a second separation region, each extending from a first depth to a third depth, wherein the second semiconductor region extends from the first separation region to the second separation region, and In the avalanche diode, in the plan view The area of ​​the first semiconductor region is smaller than the area of ​​the second semiconductor region, and The first semiconductor region, the second semiconductor region, and the third semiconductor region have portions overlapping each other. 2 . The light detecting device according to claim 1 , wherein each of the first separation region and the second separation region is a semiconductor region of the second conductivity type. 3 . The light detecting device according to claim 2 , wherein the first separation region and the second separation region are connected to a contact plug to which a predetermined potential is applied. 4 . The light detecting device according to claim 1 , further comprising a semiconductor region of a first conductivity type having an impurity concentration lower than that of the first semiconductor region and contacting the first semiconductor region and the first separation region at a first depth. 5 . The light detecting device according to claim 4 , further comprising a semiconductor region of a first conductivity type having an impurity concentration lower than that of the first semiconductor region and contacting the first semiconductor region and the second separation region at a first depth.

6. The light detection device according to claim 2, wherein: The avalanche diode includes a fourth semiconductor region of the second conductivity type, the fourth semiconductor region being disposed at a fourth depth deeper than the third depth relative to the first surface in a cross-sectional view.

7. The light detection device according to claim 6, wherein: The fourth semiconductor region is in contact with the first separation region and the second separation region.

8. The light detection device according to claim 7, wherein The impurity concentration of the fourth semiconductor region is higher than the impurity concentration of the second semiconductor region.

9. The light detection device according to claim 1, wherein: The area of ​​the third semiconductor region is larger than that of the first semiconductor region in a plan view.

10. The light detection device according to claim 7, wherein The area of ​​the third semiconductor region is larger than that of the first semiconductor region in a plan view.

11. The light detection device according to claim 1, in, The semiconductor substrate includes a second surface opposite to the first surface, and The second surface is a light incident surface.

12. The light detection device according to claim 7, in, The semiconductor substrate includes a second surface opposite to the first surface, and The second surface is a light incident surface.

13. A light detection system, comprising the light detection device according to any one of claims 1 to 12, the light detection system comprising: a wavelength conversion unit configured to convert light in a first wavelength band into light in a second wavelength band different from the first wavelength band; as well as a signal processing unit configured to synthesize a plurality of images obtained from a plurality of digital signals held in the light detection device, The light in the second wavelength band output from the wavelength conversion unit is incident on the plurality of light detection devices.

14. A light detection system, comprising the light detection device according to any one of claims 1 to 12, the light detection system comprising: a light emitting unit configured to emit light detected by the light detecting device; as well as The distance calculation unit is configured to perform distance calculation using the digital signal held in the light detection device.

15. A light detection system, comprising the light detection device according to any one of claims 1 to 12, the light detection system comprising: A signal processing unit is configured to process the signal from the light detection device.

16. A mobile object, comprising: The light detection device according to any one of claims 1 to 12; a distance information acquisition unit configured to acquire distance information related to a distance to an object using a signal from the light detection device; as well as The control unit is configured to control the moving object based on the distance information.

Images