An encapsulation method and an encapsulation structure

Abstract

An embodiment of the present application provides a packaging method and a packaging structure, which relate to the field of semiconductor technology. The method includes: providing a module to be processed, where the module to be processed includes a wafer (103); the first surface of the wafer (103) has an induction area and metal electrodes (104); a hole structure is formed on the second surface of the wafer (103), and the hole structure exposes the metal electrodes (104); then the hole structure is filled to obtain a larger available area, improving the situation of tight chip area for high-performance and high-pixel chips. High-performance and high-pixel chips can use a larger area to arrange solder balls and other components for connection with external circuits. Moreover, this packaging method focuses on two times of re-wiring to ensure the original electrical connection relationship and original functions.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular, to a packaging method and a packaging structure. Background Art

[0002] An image sensor chip, which can convert an optical image into an electrical signal, has a sensing area. When packaging an image sensor chip using the existing wafer-level chip packaging technology, in order to protect the above-mentioned sensing area from damage and contamination during the packaging process, an upper cover substrate is usually formed at the position of the sensing area. After the wafer-level chip packaging is completed, the upper cover substrate can be retained to continue protecting the sensing area from damage and contamination during the use of the image sensor chip.

[0003] The current technology conducts the electrodes of the image sensor chip to the back of the chip through TSV (Through-Silicon Via) technology. The disadvantages of this technology are as follows: The TSV etching method will reduce the usage area of silicon, thus limiting the usage area of the solder ball arrangement after re-wiring. Because the minimum interval required for the solder ball arrangement is limited, the number of solder ball arrangements is small, so high-performance and high-pixel chips cannot be packaged at the wafer level through TSV technology.

[0004] Therefore, how to improve the situation of tight chip area for high-performance and high-pixel chips is a technical problem that needs to be solved. Summary of the Invention

[0005] The purpose of the present application is to provide a packaging method and a packaging structure to solve the technical problem of how to improve the situation of tight chip area for high-performance and high-pixel chips in the prior art.

[0006] To achieve the above purpose, the embodiments of the present application adopt the following technical solutions.

[0007] In a first aspect, an embodiment of the present application provides a packaging method, including:

[0008] Providing a module to be processed, where the module to be processed includes a wafer (103); a first surface of the wafer (103) has a sensing area and metal electrodes (104);

[0009] Opening a hole structure on a second surface of the wafer (103), where the hole structure exposes the metal electrodes (104); the second surface of the wafer (103) is the side opposite to the first surface of the wafer (103);

[0010] Laying a first insulating material (106) on the second surface, where a vacant part of the first insulating material (106) exposes the metal electrodes (104);

[0011] Rerouting is performed on the first insulating material (106) to obtain a first rerouting layer (107) for leading the metal electrode to a first pad position on the surface of the first insulating material (106);

[0012] The hole structure is filled with a second insulating material (108) to flatten the second surface of the wafer (103), and the second insulating material (108) exposes the first pad position;

[0013] Rerouting is performed again on the second surface of the wafer (103) to obtain a second rerouting layer (109).

[0014] Optionally, after the step of forming a hole structure on the second surface of the wafer (103), the packaging method further includes:

[0015] Removing the oxide layer between the metal electrode (104) and silicon.

[0016] Optionally, before the step of filling the hole structure with the second insulating material (108), the packaging method further includes:

[0017] Cutting at a width greater than the final cutting width at the position of the hole structure on the second surface of the wafer (103) so that the subsequent second insulating material (108) fills the cutting position, and after the final cutting, the second insulating material (108) covers the wafer substrate material.

[0018] Optionally, the step of laying the first insulating material (106) on the second surface includes:

[0019] Laying the first insulating material (106) on the second surface and opening the first insulating material (106) above the metal electrode by means of exposure and development.

[0020] Optionally, in the step of performing rerouting on the first insulating material (106), the minimum pitch of the rerouting lines is smaller than the size of the subsequent solder balls.

[0021] Optionally, the step of filling the hole structure with the second insulating material (108) includes:

[0022] Filling the hole structure with the second insulating material (108) by means of screen printing.

[0023] Optionally, after the step of performing rerouting again on the second surface of the wafer (103), the packaging method further includes:

[0024] Coating solder mask on the surface of the second rerouting layer (109) and opening the second pad position (110) by means of exposure and development.

[0025] Optionally, after the step of opening the second pad position (110), the encapsulation method further includes:

[0026] Fabricating solder ball bumps at the second pad position (110).

[0027] Optionally, the step of providing the module to be processed includes:

[0028] Providing a capping substrate (101) having a dam structure (102) on a first surface thereof;

[0029] Providing a wafer (103) having a sensing region and metal electrodes (104) on a first surface thereof;

[0030] Aligning the sensing region of the wafer (103) with the region surrounded by the dam structure (102), and bonding the first surface of the wafer (103) to the first surface of the capping substrate (101) to form the module to be processed.

[0031] In a second aspect, an embodiment of the present application provides an encapsulation structure, the encapsulation structure including a wafer (103);

[0032] The first surface of the wafer (103) has a sensing region and metal electrodes (104);

[0033] The second surface of the wafer (103) has a hole structure, and the depth of the hole structure extends up to the metal electrodes (104); the second surface of the wafer (103) is the surface opposite to the first surface of the wafer (103);

[0034] A first insulating material (106) is disposed on the second surface, and a vacant portion of the first insulating material (106) exposes the metal electrodes (104);

[0035] A first redistribution layer (107) is provided on the first insulating material (106) to lead out the metal electrodes to a first pad position on the surface of the first insulating material (106);

[0036] A second insulating material (108) is filled in the hole structure to make the second surface of the wafer (103) flat, and the second insulating material (108) exposes the first pad position;

[0037] A second redistribution layer (109) is provided on the second surface of the wafer (103), and the second redistribution layer (109) is connected to the first pad position through a vacant portion of the second insulating material (108), the first pad position is connected to the first redistribution layer (107), and the first redistribution layer (107) is connected to the metal electrodes.

[0038] Compared with the prior art, the present application has the following beneficial effects:

[0039] The encapsulation method provided by the embodiment of the present application fills the hole structure to obtain a larger available area, improves the situation of tight chip area for high-performance and high-pixel chips. High-performance and high-pixel chips can use a larger area to arrange solder balls and other connections to external circuits, and this encapsulation method focuses on two times of re-wiring to ensure the original electrical connection relationship and original functions. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required in the embodiments. It should be understood that the following drawings only show some embodiments of the present application, and thus should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative efforts.

[0041] Figure 1 Schematic diagram of a module to be processed provided by an embodiment of the present application;

[0042] Figure 2 Schematic diagram of opening a hole structure on the second surface of a wafer 103 provided by an embodiment of the present application;

[0043] Figure 3 Schematic diagram of a pre-cutting provided by an embodiment of the present application;

[0044] Figure 4 Schematic diagram of laying a first insulating material 106 on the second surface provided by an embodiment of the present application;

[0045] Figure 5 Schematic diagram of performing re-wiring on the first insulating material 106 to obtain a first re-wiring layer 107 provided by an embodiment of the present application;

[0046] Figure 6 For Figure 5 Partial enlarged schematic diagram;

[0047] Figure 7 Schematic diagram of filling a second insulating material 108 in the hole structure to flatten the second surface of the wafer 103 provided by an embodiment of the present application;

[0048] Figure 8 For Figure 7 Partial enlarged schematic diagram;

[0049] Figure 9 Schematic diagram of performing re-wiring again on the second surface of the wafer 103 to obtain a second re-wiring layer 109 provided by an embodiment of the present application;

[0050] Figure 10 Schematic diagram provided by an embodiment of the present application, showing a layer of solder mask material 1091 coated on the basis of the second wiring layer 109 and the second pad position 110 opened by exposure and development;

[0051] Figure 11 Schematic diagram provided by an embodiment of the present application, showing the production of solder ball bumps at the second pad position 110;

[0052] Figure 12 is Figure 11 Partial enlarged schematic diagram;

[0053] Figure 13 Schematic diagram provided by an embodiment of the present application, showing the encapsulated chip cut according to the reserved scribe lane position of the chip to obtain single chips.

[0054] Explanation of reference numerals:

[0055] 101 Capping substrate

[0056] 102 Cofferdam structure

[0057] 103 Wafer

[0058] 1031 Sensing area

[0059] 104 Metal electrode

[0060] 105 Pre-cutting position

[0061] 106 First insulating material

[0062] 107 First wiring layer

[0063] 1071 First pad position

[0064] 108 Second insulating material

[0065] 109 Second wiring layer

[0066] 1091 Solder mask material

[0067] 110 Second pad position Detailed implementation manners

[0068] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. The described embodiments are some, but not all, of the embodiments of the present application. Usually, the components of the embodiments of the present application described in the accompanying drawings here can be arranged and designed in various different configurations.

[0069] Accordingly, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the claimed present application, but merely represents selected embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts fall within the scope of protection of the present application. Without conflict, the following embodiments and the features in the embodiments may be combined with each other.

[0070] In the description of the present application, it should be noted that relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. The term "connection" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected, or indirectly connected through an intermediate medium.

[0071] Regarding the packaging of the image sensor chip, the existing packaging method is to use the TSV (Through-Silicon Via) technology to conduct the electrodes of the image sensor chip to the back of the chip, but this hole reduces the available area. However, for high-performance and high-pixel chips, using this packaging method results in overly tight area, and even solder balls cannot be arranged.

[0072] To overcome the above problems, the embodiments of the present application provide a packaging method, and the following introduces each step of the packaging method.

[0073] Step 1: Provide a module to be processed.

[0074] As Figure 1 , the module to be processed includes a wafer 103, Figure 1 shows a partial view of the wafer 103, Figure 1 shows a schematic diagram of two symmetric chips on the left and right.

[0075] The module to be processed may further include a support structure under the wafer. Step 1 may include:

[0076] Step 1.1: As Figure 1 , provide a capping substrate 101. The first surface of the capping substrate 101 has a weir structure 102. The first surface of the capping substrate 101 is the Figure 1 upper surface of the capping substrate 101 in

[0077] The capping substrate 101 may be glass; Figure 1 Step 1.2: Provide a wafer 103. The first surface of the wafer 103 has a sensing area 1031 and metal electrodes. The metal electrodes are located at the circled positions pointed to by 104 in Figure 1The lower surface of the wafer 103, the second surface of the wafer 103 is the side opposite to the first surface of the wafer 103, and the second surface of the wafer 103 is Figure 1 the upper surface of the wafer 103 in;

[0078] Step 1.3: Align the sensing area 1031 of the wafer 103 with the area surrounded by the cofferdam structure 102, and attach the first surface of the wafer 103 to the first surface of the capping substrate 101 to form the module to be processed. The cofferdam structure 102 and the capping substrate 101 can protect the sensing area 1031.

[0079] The steps in this encapsulation method are not limited in order, that is, the steps can be interchanged without conflict. For example, step 1.2 can be before step 1.1.

[0080] Step 2, such as Figure 2 , open a hole structure on the second surface of the wafer 103, and the hole structure exposes the metal electrode 104; the surface of the hole structure can be inclined, that is, an inclined hole structure.

[0081] Step 2 can use photolithography plus dry etching. After etching off the silicon, it may be necessary to remove the oxide layer between the metal electrode 104 and the silicon to expose the metal. Then, the oxide layer between the metal electrode 104 and the silicon can be removed by a proprietary silicon oxide etching machine tool to expose the surface metal.

[0082] Such as Figure 2 , etching can also be performed between the metal electrodes 104 of the two chips to obtain an inclined hole, and then cutting again as Figure 3 , this cutting is a pre-cutting, and the pre-cutting position 105 is also the cutting position for finally cutting and separating individual chips. The width of the pre-cutting is greater than the width of the final cutting. The beneficial effect of this is that the space left by the pre-cutting can be filled with the subsequent second insulating material, so that the second insulating material can cover the internal silicon substrate after the final cutting, avoiding exposing the silicon substrate after cutting. This step can improve the warping of the entire wafer and enhance the reliability of the chip. The pre-cutting is an optional step, that is, this step can be omitted.

[0083] Step 3, such as Figure 4 , lay the first insulating material 106 on the second surface, and the vacant part of the first insulating material 106 exposes the metal electrode 104. The function of the first insulating material 106 is to prevent the subsequent metal re-wiring from short-circuiting with the silicon.

[0084] It can be laid and the metal electrode 104 can be exposed in the following way: first lay the first insulating material 106 on the second surface, and then open the first insulating material 106 above the metal electrode by exposure and development.

[0085] Step 4, such asFigure 5 On the first insulating material 106, redistribution is performed to obtain a first redistribution layer 107, so as to lead out the metal electrode to the first pad position on the surface of the first insulating material 106. The first pad position is used to connect the metal electrode to the subsequent second redistribution layer. The first pad position is located on the upper surface plane and outside the hole structure. At this time, the hole structure can be filled with an insulating material.

[0086] Figure 6 Shows Figure 5 A partial enlarged schematic diagram. The first redistribution layer 107 is above the first insulating material 106, and the circled position pointed to by 1071 can be used as the first pad position.

[0087] For this redistribution (the first redistribution layer 107), it is not necessary to make the pad as large as the size of the solder ball, that is, it is not necessary to be limited by the minimum gap between the solder balls. It only needs to meet the minimum line pitch. The minimum line pitch of the redistribution can be smaller than the size of the subsequent solder balls. Therefore, even if a part of the available area is lost due to the hole structure, the remaining planar area is still relatively loose, which is convenient for wiring.

[0088] Step 5, as Figure 7 , fill the hole structure with a second insulating material 108 to make the second surface of the wafer 103 flat. The second insulating material 108 exposes the first pad position 1071. The enlarged schematic diagram of this position is as Figure 8 . At this time, the hole structure has been filled.

[0089] The second insulating material can be filled in the hole structure by means of stencil printing or screen printing. The second insulating material 108 can be an insulating glue.

[0090] Since the hole structure has been filled, the available area on the chip surface has reached the chip area when there is no original hole structure. On this surface basis, the solder ball gap can be reserved according to the solder ball arrangement rule and redistribution can be performed again.

[0091] Step 6, as Figure 9 , perform redistribution again on the second surface of the wafer 103 to obtain a second redistribution layer 109.

[0092] Step 7, as Figure 10 , coat a layer of green oil material 1091 on the basis of the second redistribution layer 109 and open the second pad position 110 by means of exposure and development, which can prevent the oxidation of the second redistribution layer 109 and can also prepare for the subsequent production of solder ball bumps.

[0093] Step 8, make solder ball bumps at the second pad position 110. The solder ball bumps can be made by printing or ball placement, as Figure 11 , this step is an optional step. If there is no such step, it is a solder ball-free design.Figure 12 shows Figure 11 a partially enlarged schematic view of

[0094] Step 9, wafer dicing, dicing the packaged chip according to the dicing lane position reserved for the chip to obtain single chips, as shown in Figure 13 .

[0095] Based on the above embodiments, the embodiments of the present application further provide a packaging structure, which can be packaged by the above packaging method.

[0096] Referring to Figure 10 or Figure 11 , the packaging structure includes a wafer 103;

[0097] The first surface of the wafer 103 has a sensing area 1031 and a metal electrode 104;

[0098] The second surface of the wafer 103 has a hole structure, and the depth of the hole structure reaches up to the metal electrode 104; the second surface of the wafer 103 is the side opposite to the first surface of the wafer 103;

[0099] A first insulating material 106 is laid on the second surface, and the vacant part of the first insulating material 106 exposes the metal electrode 104 to the first redistribution layer 107;

[0100] There is a first redistribution layer 107 on the first insulating material 106 to lead out the metal electrode 104 to the position of the first pad on the surface of the first insulating material 106;

[0101] The hole structure is filled with a second insulating material 108 to make the second surface of the wafer 103 flat, and the second insulating material 108 exposes the position of the first pad to the second redistribution layer 109;

[0102] There is a second redistribution layer 109 on the second surface of the wafer 103. The second redistribution layer 109 is connected to the position of the first pad through the vacant part of the second insulating material 108. The position of the first pad is connected to the first redistribution layer 107, and the first redistribution layer 107 is connected to the metal electrode.

[0103] The beneficial effects of the packaging method and the packaging structure provided by the embodiments of the present application are as follows:

[0104] It can adapt to higher pixel and more metal electrode chips for TSV packaging development;

[0105] The height difference of the product is optimized, and the stress of the chip will be greatly reduced, improving reliability;

[0106] To match the application requirements of different products, the solder balls can also be replaced with solderless ball designs.

[0107] The device and system embodiments described above are merely illustrative. One can select some or all of the modules according to actual needs to achieve the objectives of the solutions in this embodiment. Those of ordinary skill in the art can understand and implement this without creative efforts.

[0108] The above is only a preferred specific implementation manner of this application, but the protection scope of this application is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed in this application should be covered within the protection scope of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claims.

Claims

1. A packaging method, characterized in that, include: A module to be processed is provided, the module to be processed comprising a wafer (103); a first surface of the wafer (103) has a sensing area and a metal electrode (104); A hole structure is provided on the second surface of the wafer (103), wherein the hole structure exposes the metal electrode (104); the second surface of the wafer (103) is a surface opposite to the first surface of the wafer (103); Laying a first insulating material (106) on the second surface, the metal electrode (104) being exposed at a vacant portion of the first insulating material (106); Performing redistribution on the first insulating material (106) to obtain a first redistribution layer (107) to lead the metal electrode to a first pad position on the surface of the first insulating material (106); Filling the hole structure with a second insulating material (108) to make the second surface of the wafer (103) flat, the hole structure has been filled, and the available area of the chip surface has reached the chip area of the original non-hole structure; the second insulating material (108) exposes the first pad position; Rewiring is performed again on the filled and leveled second surface of the wafer (103) to obtain a second redistribution layer (109), wherein a portion of the second redistribution layer (109) is located on the surface of the second insulating material (108); Green oil is coated on the surface of the second redistribution layer (109), and then the second pad position (110) is opened by exposure and development.

2. The encapsulation method according to claim 1, wherein After the step of opening a hole structure on the second surface of the wafer (103), the packaging method further comprises: The oxide layer between the metal electrode (104) and silicon is removed.

3. The encapsulation method according to claim 1, wherein, Before the step of filling the hole structure with a second insulating material (108), the packaging method further comprises: Pre-cutting is performed at the final cutting position with a width greater than the final cutting width, so that the subsequent second insulating material (108) fills this cutting position, and after the final cutting, the second insulating material (108) covers the wafer substrate material.

4. The encapsulation method according to claim 1, wherein The step of laying a first insulating material (106) on the second surface comprises: A first insulating material (106) is laid on the second surface, and the first insulating material (106) above the metal electrode is opened by exposure and development.

5. The encapsulation method according to claim 1, characterized in that, In the step of performing rewiring on the first insulating material (106), the minimum spacing of the rewiring lines is smaller than the size of subsequent solder balls.

6. The encapsulation method according to claim 1, wherein The step of filling the hole structure with a second insulating material (108) comprises: The hole structure is filled with a second insulating material (108) by screen printing.

7. The encapsulation method according to claim 1, wherein After the step of opening the second pad position (110), the packaging method further comprises: A solder ball bump is made at the second pad position (110).

8. The encapsulation method according to claim 1, characterized in that The steps of providing a module to be processed include: Providing a cover substrate (101), wherein a first surface of the cover substrate (101) has a cofferdam structure (102); Providing a wafer (103), wherein a first surface of the wafer (103) has a sensing area and a metal electrode (104); Align the sensing area of the wafer (103) with the area enclosed by the dam structure (102), and bond the first surface of the wafer (103) to the first surface of the cover substrate (101) to form the module to be processed.

9. A packaging structure, characterized in that, The packaging structure includes a wafer (103); The first surface of the wafer (103) has a sensing area and metal electrodes (104); The second surface of the wafer (103) has a hole structure, and the depth of the hole structure extends up to the metal electrodes (104); the second surface of the wafer (103) is the surface opposite to the first surface of the wafer (103); A first insulating material (106) is laid on the second surface, and the vacant part of the first insulating material (106) exposes the metal electrodes (104) to the first redistribution layer (107); There is a first redistribution layer (107) on the first insulating material (106) to lead out the metal electrodes (104) to the first pad position on the surface of the first insulating material (106); The hole structure is filled with a second insulating material (108) to make the second surface of the wafer (103) flat, the hole structure has been filled, and the available area of the chip surface has reached the chip area when there was no hole structure originally; There is a second redistribution layer (109) on the second surface of the wafer (103), the second redistribution layer (109) is located on the plane after the filling of the second insulating material (108), a part of the second redistribution layer (109) is located on the surface of the second insulating material (108), the second redistribution layer (109) is connected to the first pad position through the vacant part of the second insulating material (108), the first pad position is connected to the first redistribution layer (107), and the first redistribution layer (107) is connected to the metal electrodes; Green oil is coated on the surface of the second redistribution layer (109), and the green oil at the second pad position (110) on the surface of the second redistribution layer (109) is opened.

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