A wide band gap trench MOSFET device and method of manufacturing the same

Abstract

The application discloses a wide-band-gap trench MOSFET device and a manufacturing method thereof, which can be used in the field of semiconductor devices. In the device, an N-type epitaxial layer, a P-base region and a source region are sequentially arranged on one side of an N-type substrate; a drain electrode is arranged on the other side of the N-type substrate; an N-accumulation channel is arranged on the inner surface of a trench of the P-base region and is in contact with a gate region, the P-base region and an N channel respectively; the depth of the trench is smaller than the thickness of the P-base region; the N channel is arranged on the lower surface of the trench, penetrates through the P-base region and is in contact with the N-type epitaxial layer, the gate region and the N-accumulation channel respectively; and the gate region is arranged in the trench and is in contact with the N channel, the N-accumulation channel and the source region. In this way, the on-state characteristics of the device are improved by constructing the P-base region which is deeper than the trench and the conductive channel formed by the N-accumulation channel and the N channel at the bottom, and the gate region is well protected.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor devices, in particular to a wide band gap trench MOSFET device and a manufacturing method thereof. BACKGROUND

[0002] Silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), diamond (C), and aluminum nitride (AlN) are widely used in new energy fields as new ultra-wide band gap semiconductor materials, which have advantages of ultra-wide band gap, ultra-high breakdown field strength, and electron saturation drift speed better than silicon (Si).

[0003] The existing wide band gap trench MOSFET design has poor resistance to electrostatic effects in harsh environments and high voltage spikes in circuits, and the electron mobility at the channel is very low, which degrades the on-state characteristics of the device.

[0004] Therefore, how to improve the on-state characteristics of the device while providing good protection for the gate region is a problem that needs to be solved by those skilled in the art. SUMMARY

[0005] Based on the above problems, the present application provides a wide band gap trench MOSFET device and a manufacturing method thereof, which improves the on-state characteristics of the device while providing good protection for the gate region by constructing a P-base region deeper than the trench, and a conductive channel formed by an N accumulation type channel and an N channel at the bottom.

[0006] In a first aspect, the embodiments of the present application provide a wide band gap trench MOSFET device, which comprises an N-type substrate, an N-type epitaxial layer, an N channel, an N accumulation type channel, a P-base region, a source region, a drain electrode, and a gate region.

[0007] The N-type epitaxial layer, the P-base region, and the source region are sequentially arranged on one side of the N-type substrate; and the drain electrode is arranged on the other side of the N-type substrate.

[0008] The N accumulation type channel is arranged on the inner surface of the trench of the P-base region and contacts the gate region, the P-base region, and the N channel respectively; and the depth of the trench is less than the thickness of the P-base region.

[0009] The N channel is arranged on the lower surface of the trench and penetrates the P-base region, and contacts the N-type epitaxial layer, the gate region, and the N accumulation type channel respectively.

[0010] The gate region is arranged in the interior of the trench and contacts the N channel, the N accumulation type channel, and the source region respectively.

[0011] Optionally, the gate region comprises: an interlayer dielectric layer, a gate dielectric layer, and a gate electrode.

[0012] The gate dielectric layer, the gate electrode, and the interlayer dielectric layer are sequentially arranged in the trench from bottom to top.

[0013] The gate electrode is wrapped by the gate dielectric layer and the interlayer dielectric layer.

[0014] Optionally, the width of the gate electrode is wider than the width of the N-channel.

[0015] Optionally, the source region comprises: an N-type source and a P-type source.

[0016] The N-type source is close to the trench and in contact with the interlayer dielectric layer; and the P-type source is away from the trench and in contact with the N-type source.

[0017] Optionally, the N-type doping concentration of the N-type source is higher than the N-type doping concentration of the N-channel.

[0018] The P-type doping concentration of the P-type source is higher than the P-type doping concentration of the P-base region.

[0019] Optionally, the P-base region comprises: a P-base1 region arranged in an upper layer and a P-base2 region arranged in a lower layer.

[0020] The P-type doping concentration of the P-base2 region is higher than the P-type doping concentration of the P-base1 region.

[0021] Optionally, the N-type doping concentration of the N-channel is higher than the N-type doping concentration of the N-accumulation channel.

[0022] Optionally, the device further comprises: a source electrode.

[0023] The source electrode is arranged on the other side of the source region and in contact with the source region and the interlayer dielectric layer, respectively.

[0024] In a second aspect, the embodiments of the present application provide a manufacturing method of a wide-bandgap trench MOSFET device, which is used to manufacture the wide-bandgap trench MOSFET device as described above, and the method comprises:

[0025] Providing an N-type substrate;

[0026] Growing an N-type epitaxial layer on the N-type substrate;

[0027] Forming a P-base region and the source region on the N-type epitaxial layer in sequence;

[0028] The source region is patterned and etched until a portion of the P-base region is etched away, forming a trench; the depth of the trench is less than the thickness of the P-base region.

[0029] Based on the ion implantation process, an N-type accumulation channel is formed on the inner surface of the trench, and an N-type channel is formed at the bottom of the trench; the N-type doping concentration of the N-type channel is higher than that of the N-type accumulation channel.

[0030] A gate region is grown within the groove;

[0031] Based on the deposition process, a source electrode is formed on the gate region and a drain electrode is formed under the N-type substrate.

[0032] Optionally, growing the gate region within the groove includes:

[0033] A gate dielectric layer is formed on the inner surface of the groove;

[0034] Polysilicon is grown on the gate dielectric and patterned by etching to form the gate.

[0035] An insulating dielectric is grown on the gate and patterned by etching to form an interlayer dielectric; the width of the gate dielectric is greater than the width of the gate, and the width of the interlayer dielectric is greater than the width of the gate.

[0036] As can be seen from the above technical solutions, compared with the prior art, this application has the following advantages:

[0037] The wide bandgap trench MOSFET device provided in this application includes: an N-type substrate, an N-type epitaxial layer, an N-channel, an N-accumulation channel, a P-base region, a source region, a drain electrode, and a gate region. The N-type epitaxial layer, the P-base region, and the source region are sequentially disposed on one side of the N-type substrate; the drain electrode is disposed on the other side of the N-type substrate; the N-accumulation channel is disposed on the inner surface of the trench in the P-base region and contacts the gate region, the P-base region, and the N-channel, respectively; the depth of the trench is less than the thickness of the P-base region; the N-channel is disposed on the lower surface of the trench, penetrates the P-base region, and contacts the N-type epitaxial layer, the gate region, and the N-accumulation channel, respectively; the gate region is disposed inside the trench and contacts the N-channel, the N-accumulation channel, and the source region, respectively. Thus, by constructing a P-base region deeper than the trench, and a conductive channel formed by the N-accumulation channel and the bottom N-channel, the conduction characteristics of the device are improved while providing good protection for the gate region. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 A schematic diagram of a wide bandgap trench MOSFET device provided in this application embodiment;

[0040] Figure 2 A schematic diagram of the structure of a gate region provided in an embodiment of this application;

[0041] Figure 3 A schematic diagram of a source region structure provided in an embodiment of this application;

[0042] Figure 4 A schematic diagram of the structure of a P-base region provided in an embodiment of this application;

[0043] Figure 5 This is a schematic diagram of the structure of a source electrode provided in an embodiment of this application;

[0044] Figure 6 A schematic diagram illustrating the blocking characteristics of a device provided in an embodiment of this application;

[0045] Figure 7 A schematic diagram illustrating the conduction characteristics of a device provided in an embodiment of this application;

[0046] Figure 8 This is a schematic diagram of an N-channel design provided in an embodiment of this application;

[0047] Figure 9 A schematic diagram of another N-channel design provided in this application embodiment;

[0048] Figure 10 A flowchart illustrating a method for manufacturing a wide bandgap trench MOSFET device, provided for embodiments of this application;

[0049] Figure 11 A flowchart illustrating another method for constructing an N-channel according to an embodiment of this application;

[0050] Figure 12 This is a schematic diagram of another N-channel design provided in an embodiment of this application. Detailed Implementation

[0051] As mentioned earlier, existing wide-bandgap trench MOSFET designs suffer from poor high-voltage spike withstand capability and low electron mobility at the channel. Specifically, the high electric field in the drift region of the wide-bandgap semiconductor material in existing designs leads to a very high electric field on the gate dielectric layer. This problem is exacerbated at the trench corners, causing rapid breakdown of the gate dielectric layer under high drain electrode voltages, resulting in poor high-voltage spike withstand capability. Furthermore, the excessively high interface state density at the interface between the wide-bandgap semiconductor material and silicon dioxide (SiO2) in existing designs leads to very low electron mobility at the channel, thus degrading the device's conduction characteristics.

[0052] To address the aforementioned issues, this application provides a wide bandgap trench MOSFET device and its manufacturing method. The device includes: an N-type substrate, an N-type epitaxial layer, an N-channel, an N-accumulation channel, a P-base region, a source region, a drain electrode, and a gate region. The N-type epitaxial layer, the P-base region, and the source region are sequentially disposed on one side of the N-type substrate; the drain electrode is disposed on the other side of the N-type substrate; the N-accumulation channel is disposed on the inner surface of the trench in the P-base region and contacts the gate region, the P-base region, and the N-channel, respectively; the depth of the trench is less than the thickness of the P-base region; the N-channel is disposed on the lower surface of the trench, penetrating the P-base region, and contacts the N-type epitaxial layer, the gate region, and the N-accumulation channel, respectively; the gate region is disposed inside the trench and contacts the N-channel, the N-accumulation channel, and the source region, respectively.

[0053] Thus, by constructing a P-base region that is deeper than the trench, and a conductive channel formed by the N-accumulation channel and the N-channel at the bottom, the conduction characteristics of the device are improved while providing good protection for the gate region.

[0054] It should be noted that the wide bandgap trench MOSFET device and its manufacturing method provided in this application can be applied to the field of semiconductor devices. The above is merely an example and does not limit the application field of the wide bandgap trench MOSFET device and its manufacturing method provided in this application.

[0055] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0056] Figure 1 This is a schematic diagram of a wide bandgap trench MOSFET device provided as an embodiment of this application. (Combined with...) Figure 1As shown, the device includes: an N-type substrate 100, an N-type epitaxial layer 200, an N-channel 300, an N-accumulation channel 400, a P-base region 500, a source region 600, a drain electrode 700, and a gate region 800.

[0057] The N-type epitaxial layer 200, the P-base region 500, and the source region 600 are sequentially disposed on one side of the N-type substrate 100; the drain electrode 700 is disposed on the other side of the N-type substrate 100.

[0058] The N-accumulation channel 400 is disposed on the inner surface of the trench of the P-base region 500, and contacts the gate region 800, the P-base region 500 and the N-channel 300 respectively; the depth of the trench is less than the thickness of the P-base region 500.

[0059] The N-channel 300 is disposed on the lower surface of the trench, penetrates the P-base region 500, and contacts the N-type epitaxial layer 200, the gate region 800, and the N-accumulation channel 400 respectively.

[0060] The gate region 800 is disposed inside the trench and is in contact with the N channel 300, the N accumulation channel 400 and the source region 600, respectively.

[0061] Specifically, the problem of high electric field on the gate dielectric layer due to the high electric field in the drift region of the wide bandgap semiconductor material is more obvious at the trench corner. Therefore, this application constructs a P-base region 500 that is deeper than the trench, so that the P-base region 500 covers the trench corner, and forms a conductive channel through the N-accumulation channel 400 and the N-channel 300, which improves the conduction characteristics of the device and provides good protection for the gate region 800.

[0062] Figure 2 This is a schematic diagram of a gate region provided in an embodiment of this application. (In conjunction with...) Figure 2 As shown, the gate region 800 includes: an interlayer dielectric layer 801, a gate dielectric layer 802, and a gate 803;

[0063] The gate dielectric layer 802, the gate 803, and the interlayer dielectric layer 801 are sequentially disposed inside the trench from bottom to top;

[0064] The gate 803 is enclosed by the gate dielectric layer 802 and the interlayer dielectric layer 801.

[0065] Specifically, the gate dielectric layer 802, the gate 803, and the interlayer dielectric layer 801 are arranged sequentially from bottom to top, with the gate 803 encased between the gate dielectric layer 802 and the interlayer dielectric layer 801. The gate dielectric layer 802 is formed based on the deposition or thermal oxidation of an insulating dielectric layer, the interlayer dielectric layer 801 is formed based on the deposition of an insulating dielectric layer, and the gate 803 is formed based on polysilicon deposition.

[0066] In addition, regarding the design of the gate 803, the width of the gate 803 is wider than the width of the N channel 300.

[0067] Specifically, gate dielectric layer 802 and gate 803 are disposed sequentially from bottom to top in the trench, and interlayer dielectric layer 801 is disposed above gate 803. The widths of gate dielectric layer 802, gate 803, and interlayer dielectric layer 801 are all wider than the width of N-channel 300.

[0068] Figure 3 This is a schematic diagram of a source region structure provided in an embodiment of this application. (Combined with...) Figure 3 As shown, the source region 600 includes: an N-type source 601 and a P-type source 602;

[0069] The N-type source 601 is close to the trench and in contact with the interlayer dielectric layer 801; the P-type source 602 is away from the trench and in contact with the N-type source 601.

[0070] Specifically, the N-type source 601 and the P-type source 602 are formed by ion implantation or secondary epitaxy. The lower surface of the P-type source 602 is in contact with the P-base region 500, and one side of its surface is in contact with one side of the N-type source 601. The lower surface of the N-type source 601 is in contact with both the P-base region 500 and the N-accumulation channel 400, and the other side is in contact with the gate dielectric layer 802.

[0071] In addition, regarding the design of the P-type source 602 and the N-type source 601, the N-type doping concentration of the N-type source 601 is higher than that of the N-channel 300.

[0072] The P-type doping concentration of the P-type source 602 is higher than that of the P-base region 500.

[0073] Specifically, highly doped P-type source 602 and N-type source 601 can increase the carrier concentration in the source region 600, thereby reducing the contact resistance between the source metal and the semiconductor material and improving the conductivity of the material.

[0074] Figure 4 This is a schematic diagram of a P-base region provided in an embodiment of this application. (Combined with...) Figure 4As shown, the P-base area 500 includes: a P-base1 area 501 disposed on the upper layer and a P-base2 area 502 disposed on the lower layer;

[0075] The P-type doping concentration of the P-base2 region 502 is higher than that of the P-base1 region 501.

[0076] Specifically, the trench is located within the P-base1 region 501, and the trench depth is less than the thickness of the P-base1 region 501. Among the different doping concentrations, the P-base1 region 501 with a lower doping concentration is more likely to invert and form an N-accumulation channel 400, improving the conduction characteristics of the device. The P-base2 region 502 with a higher doping concentration can provide good protection for the gate oxide layer (gate dielectric layer 802) within the device trench.

[0077] Furthermore, regarding the design of the N-channel 300 and the N-accumulation channel 400, the N-type doping concentration of the N-channel 300 is higher than that of the N-accumulation channel 400.

[0078] Specifically, the difference in doping concentration between the N-channel 300 and the N-accumulation channel 400 makes it more advantageous for the current path to be pinched off during reverse breakdown.

[0079] Figure 5 This is a schematic diagram of a source electrode provided in an embodiment of this application. (Combined with...) Figure 5 As shown, the device further includes: a source electrode 900;

[0080] The source electrode 900 is located on the other side of the source region 600 and is in contact with both the source region 600 and the interlayer dielectric layer 801.

[0081] Specifically, a thicker metal film can be deposited and patterned on top of the N-type source 601 and the P-type source 602 to serve as a thickened electrode for the source.

[0082] Figure 6 This is a schematic diagram illustrating the blocking characteristics of a device according to an embodiment of this application. (In conjunction with...) Figure 6 As shown, taking SiC material as an example, the wide bandgap trench MOSFET device provided in this application has a breakdown voltage of 1747V. The inset diagram shows the electric field distribution of the device at 1200V. It can be seen that the peak electric field position has shifted from the trench corner to the bottom of the trench, avoiding the high peak electric field caused by electric field accumulation at the corner. The electric field between the P-base region 500 and the N-type epitaxial layer 200 is 2.87MV / cm. The peak electric field of the gate dielectric layer 802 at the bottom of the trench is 1.19MV / cm, which is far lower than the 2.5MV / cm that is considered to affect the reliability of the gate dielectric layer 802 in the industry.

[0083] Figure 7 This is a schematic diagram illustrating the conduction characteristics of a device according to an embodiment of this application. (In conjunction with...) Figure 7 As shown, taking SiC material as an example, the wide bandgap trench MOSFET device provided in this application has a calculated specific on-resistance of 1.58 mΩ·cm. 2 This is lower than the 2.2mΩ·cm achieved by common brands. 2 and 2.6 mΩ·cm 2 Therefore, it has better conduction characteristics.

[0084] Figure 8 This is a schematic diagram of an N-channel design provided in an embodiment of this application. (Combined with...) Figure 8 As shown, a is a top view of a wide bandgap trench MOSFET device, and b and c are cross-sectional views of the device at two different locations. A shielding layer (P+Shield layer) can be introduced by ion implantation at the bottom of the trench and inside the N-channel accumulation layer, thereby further increasing the N-channel 300 concentration while maintaining or even reducing the peak electric field of the gate 803.

[0085] Figure 9 This is a schematic diagram of another N-channel design provided in an embodiment of this application. (Combined with...) Figure 9 As shown, by adjusting the width of the hard mask on the sidewall of the trench during ion implantation, the width of the N-channel 300 under the trench can be adjusted. When there is no hard mask on the sidewall of the trench, the left and right sides of the N-channel 300 will be flush with the sides of the trench.

[0086] In summary, the wide bandgap trench MOSFET device provided in this application includes: an N-type substrate, an N-type epitaxial layer, an N-channel, an N-accumulation channel, a P-base region, a source region, a drain electrode, and a gate region; the N-type epitaxial layer, the P-base region, and the source region are sequentially disposed on one side of the N-type substrate; the drain electrode is disposed on the other side of the N-type substrate; the N-accumulation channel is disposed on the inner surface of the trench in the P-base region and contacts the gate region, the P-base region, and the N-channel, respectively; the depth of the trench is less than the thickness of the P-base region; the N-channel is disposed on the lower surface of the trench, penetrates the P-base region, and contacts the N-type epitaxial layer, the gate region, and the N-accumulation channel, respectively; the gate region is disposed inside the trench and contacts the N-channel, the N-accumulation channel, and the source region, respectively. Thus, by constructing a P-base region deeper than the trench, and a conductive channel formed by the N-accumulation channel and the bottom N-channel, the conduction characteristics of the device are improved while providing good protection for the gate region.

[0087] Figure 10This is a flowchart illustrating a method for manufacturing a wide bandgap trench MOSFET device, as provided in an embodiment of this application. (In conjunction with...) Figure 10 As shown, the method may include:

[0088] S1: Provides an N-type substrate.

[0089] In practical applications, N-type substrates can be N-type doped SiC, GaN, Ga2O3, C, and AlN, etc.

[0090] S2: An N-type epitaxial layer is grown on the N-type substrate.

[0091] In practical applications, an N-type epitaxial layer is grown on an N-type substrate. The doping concentration in the N-type epitaxial layer is lower than that in the N-type substrate.

[0092] S3: A P-base region and a source region are sequentially formed on the N-type epitaxial layer.

[0093] In practical applications, P-base regions can be formed on N-type epitaxial layers using methods such as ion implantation and secondary epitaxy. The P-base region comprises an upper P-base1 region and a lower P-base2 region, with the P-type doping concentration in P-base2 being higher than that in P-base1. Subsequently, source regions are formed above the P-base1 region using ion implantation and secondary epitaxy. These source regions include an N-type source near the trench and a P-type source away from the trench, with the N-type doping concentration in the N-type source higher than that in the N-channel, and the P-type doping concentration in the P-type source higher than that in the P-base region.

[0094] S4: Perform pattern etching on the source region until a portion of the P-base region is etched away, forming a trench; the depth of the trench is less than the thickness of the P-base region.

[0095] In practical applications, a photolithography process is performed above the source region to create the etched area and protect the unetched area. Then, dry etching is performed to remove the source at the center of the device and part of the P-base1 region, forming a gate trench within the P-base1 region.

[0096] S5: Based on the ion implantation process, an N-type accumulation channel is formed on the inner surface of the trench, and an N-type channel is formed at the bottom of the trench; the N-type doping concentration of the N-type channel is higher than that of the N-type accumulation channel.

[0097] In practical applications, N-accumulation channels and N-channels are formed through ion implantation. The N-accumulation channels have a lower N-type doping concentration, which can prevent excessive leakage current of the device. The N-channels have a higher N-type doping concentration, which is beneficial to improving the conduction characteristics of the device.

[0098] S6: Grow a gate region within the groove.

[0099] In practical applications, gate regions are formed within trenches by combining deposition, growth, and etching processes.

[0100] S7: Based on the deposition process, a source electrode is formed on the gate region and a drain electrode is formed under the N-type substrate.

[0101] Finally, a drain electrode is formed below the N-type substrate by metal thin film deposition, and a source electrode is formed above the source region by metal thin film deposition and etching.

[0102] Furthermore, since the gate region design methods are not entirely the same, the embodiments of this application can be described with respect to one possible design method.

[0103] In one instance, growing the gate region within the groove includes:

[0104] A gate dielectric layer is formed on the inner surface of the groove;

[0105] Polysilicon is grown on the gate dielectric and patterned by etching to form the gate.

[0106] An insulating dielectric is grown on the gate and patterned by etching to form an interlayer dielectric; the width of the gate dielectric is greater than the width of the gate, and the width of the interlayer dielectric is greater than the width of the gate.

[0107] In practical applications, it is necessary to first grow an insulating dielectric layer on the inner surface of the trench, that is, to grow the gate dielectric. Then, the gate polysilicon is grown and etched on the gate dielectric in the trench to form the gate. Finally, the interlayer dielectric is deposited and etched on the gate to obtain a complete gate region.

[0108] Figure 11 A flowchart illustrating another method for constructing an N-channel according to an embodiment of this application. (In conjunction with...) Figure 11 As shown, the N-channel can be formed in two stages. The first stage (a) involves growing a hard mask on the device's upper surface and inside the trench, forming a T-type N-channel through etching, followed by ion implantation to form a partial N-channel. The second stage (b) builds upon the first stage by increasing the thickness of the sidewall hard mask through sidewall growth, thus forming a narrower T-type N-channel. This enhances the protection of the gate oxide without increasing the length of the low-concentration N-accumulation channel, thereby avoiding significant degradation of the conduction characteristics. Then, as shown in c, the hard mask is removed, and the construction of other layers continues, as shown in d, resulting in a complete wide-bandgap trench MOSFET device.

[0109] Figure 12This is a schematic diagram of another N-channel design provided in an embodiment of this application. (Combined with...) Figure 12 As shown, a is a top view of the wide bandgap trench MOSFET device, and b and c are cross-sectional views of the device at two different locations. Thus, this application further... Figure 11 Based on the wide bandgap trench MOSFET device shown in d, a P+Shield of the same T-type design is added at the bottom of the trench by ion implantation to enhance the electric field shielding effect and achieve grounding in three dimensions.

[0110] In summary, this application provides a method for manufacturing a wide bandgap trench MOSFET device, comprising: providing an N-type substrate; growing an N-type epitaxial layer on the N-type substrate; sequentially forming a P-base region and a source region on the N-type epitaxial layer based on processes such as ion implantation and secondary epitaxy; patterning the source region until a portion of the P-base region is etched away, forming a trench; the depth of the trench is less than the thickness of the P-base region; forming an N-accumulation channel on the inner surface of the trench based on an ion implantation process, and forming an N-channel at the bottom of the trench; the N-type oxide doping concentration of the N-channel is higher than that of the N-accumulation channel; growing a gate region within the trench; and forming a source electrode on the gate region based on a deposition process, and forming a drain electrode under the N-type substrate. Thus, by constructing a P-base region deeper than the trench, and the conductive channel formed by the N-accumulation channel and the bottom N-channel, the conduction characteristics of the device are improved while providing good protection for the gate region.

[0111] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A wide bandgap trench MOSFET device, characterized in that, The device includes: an N-type substrate, an N-type epitaxial layer, an N-channel, an N-accumulation channel, a P-base region, a source region, a drain electrode, and a gate region; The N-type epitaxial layer, the P-base region, and the source region are sequentially disposed on one side of the N-type substrate; the drain electrode is disposed on the other side of the N-type substrate. The N-accumulation channel is disposed on the inner surface of the trench in the P-base region and contacts the gate region, the P-base region and the N-channel respectively; the depth of the trench is less than the thickness of the P-base region; The N-channel is disposed on the lower surface of the trench, penetrates the P-base region, and contacts the N-type epitaxial layer, the gate region, and the N-accumulation channel respectively; The gate region is disposed inside the trench and is in contact with the N-channel, the N-accumulation channel and the source region, respectively. The N-type doping concentration of the N-channel is higher than that of the N-accumulation channel; At the bottom of the trench, a shielding area is provided inside the N-accumulation channel; the shielding area is connected to the N-channel.

2. The device according to claim 1, characterized in that, The gate region includes: an interlayer dielectric layer, a gate dielectric layer, and a gate; The gate dielectric layer, the gate, and the interlayer dielectric layer are sequentially disposed inside the trench from bottom to top; The gate is enclosed by the gate dielectric layer and the interlayer dielectric layer.

3. The device according to claim 2, characterized in that, The width of the gate is wider than the width of the N-channel.

4. The device according to claim 2, characterized in that, The source region includes: an N-type source and a P-type source; The N-type source electrode is close to the trench and in contact with the interlayer dielectric layer; the P-type source electrode is far from the trench and in contact with the N-type source electrode.

5. The device according to claim 4, characterized in that, The N-type doping concentration of the N-type source is higher than that of the N-channel; The P-type doping concentration of the P-type source is higher than that of the P-base region.

6. The device according to claim 1, characterized in that, The P-base area includes: a P-base1 area located at the upper layer and a P-base2 area located at the lower layer; The P-type doping concentration in the P-base2 region is higher than that in the P-base1 region.

7. The device according to claim 1, characterized in that, The device further includes: a source electrode; The source electrode is located on the other side of the source region and is in contact with both the source region and the interlayer dielectric layer.

8. A method for manufacturing a wide bandgap trench MOSFET device, characterized in that, The method for manufacturing a wide bandgap trench MOSFET device as described in any one of claims 1 to 7 comprises: Provide N-type substrates; An N-type epitaxial layer is grown on the N-type substrate; A P-base region and a source region are sequentially formed on the N-type epitaxial layer; The source region is patterned and etched until a portion of the P-base region is etched away, forming a trench; the depth of the trench is less than the thickness of the P-base region. Based on the ion implantation process, an N-type accumulation channel is formed on the inner surface of the trench, and an N-type channel is formed at the bottom of the trench; the N-type doping concentration of the N-type channel is higher than that of the N-type accumulation channel. A shielding layer is formed at the bottom of the trench and inside the N-accumulation channel using an ion implantation process; the shielding area is connected to the N-channel. A gate region is grown within the trench; Based on the deposition process, a source electrode is formed on the gate region and a drain electrode is formed under the N-type substrate.

9. The method according to claim 8, characterized in that, The growth of the gate region within the trench includes: A gate dielectric layer is formed on the inner surface of the trench; Polysilicon is grown on the gate dielectric and patterned by etching to form the gate. An insulating dielectric is grown on the gate and patterned by etching to form an interlayer dielectric; the width of the gate dielectric is greater than the width of the gate, and the width of the interlayer dielectric is greater than the width of the gate.

Images