VCSEL integrated wafer and manufacturing method thereof

Abstract

The invention discloses a VCSEL (Vertical Cavity Surface Emitting Laser) integrated wafer and a manufacturing method thereof, the VCSEL integrated wafer comprises at least one VCSEL chip, at least one photodiode chip spaced from the VCSEL chip, and a thermoelectric refrigeration structure integrated on the VCSEL chip at a wafer level, and each VCSEL chip comprises at least one VCSEL luminous point; the VCSEL chip and the photodiode chip share a substrate layer; the thermoelectric refrigeration structure comprises a plurality of thermocouple pairs, and each thermocouple pair comprises a P-type structure and an N-type structure which are electrically connected with each other.

Description

Technical Field

[0001] The present application relates to the field of semiconductor lasers, and more specifically to a VCSEL integrated wafer and a manufacturing method thereof. Background Art

[0002] VCSEL (Vertical-Cavity Surface-Emitting Laser) is a low-cost, high-performance semiconductor laser with great application potential in communications, daily consumption, and automotive fields. Currently, VCSEL products have been widely used in short-distance fiber-optic communications, face recognition, 3D sensing and other application scenarios.

[0003] In the actual industry, VCSEL lasers are often used as basic components (for example, as light sources) and are assembled into modules with other devices. For example, when VCSEL lasers are used in depth camera modules, VCSEL lasers are assembled with circuit boards, brackets, optical diffraction elements, metal protective covers, photodiodes, optical lenses, filters and other devices to form a depth camera module, wherein VCSEL lasers are assembled with circuit boards, brackets, optical diffraction elements, metal protective covers and other devices into the laser projection unit of the depth camera module, and photodiodes, optical lenses, filters and other devices are assembled into the camera unit of the depth camera module.

[0004] There are problems with assembly stability and installation accuracy in the process of assembling the VCSEL laser and other devices. For example, as VCSEL technology matures, more high-power and high-power density applications are gradually developed. The multi-junction technology that has gradually matured in recent years can meet the application of automotive laser radar. However, the working environment of VCSEL used in automotive laser radar is relatively harsh. When the working environment temperature of VCSEL is 85℃ to 105℃, the optical power will drop rapidly. Figure 1 As shown in FIG. 1 , based on the thermal sensitivity, the performance of VCSEL deteriorates as the temperature increases. In order to reduce the operating temperature of the VCSEL laser, a semiconductor cooler can be assembled on the VCSEL laser. Currently, the semiconductor cooler is mainly assembled on the packaged VCSEL laser by mounting.

[0005] However, when the semiconductor cooler is mounted on the packaged VCSEL laser by mounting, the bonding stability between the semiconductor cooler and the VCSEL laser is poor and the semiconductor cooler is easy to fall off.

[0006] It is worth mentioning that in the actual industry, VCSEL lasers are usually provided by chip manufacturers, while the assembly of VCSEL packaged products is completed by packaging plants. That is, from VCSEL lasers to VCSEL packaged products, there are two nodes in the industrial chain. Moreover, in the actual industry, packaging plants may purchase VCSEL lasers provided by different manufacturers. At the same time, problems such as uneven assembly accuracy may occur during the assembly process, making it difficult to ensure the consistency of the final VCSEL packaged products. Summary of the invention

[0007] One advantage of the present application is that it provides a VCSEL integrated wafer and a method for manufacturing the same, wherein the VCSEL integrated wafer forms a VCSEL chip and a photodiode chip on the same wafer and integrates a thermoelectric cooling structure at the wafer level.

[0008] Another advantage of the present application is that it provides a VCSEL integrated wafer and a method for manufacturing the same, wherein in the VCSEL integrated wafer, a thermoelectric cooling structure is integrated into the VCSEL chip and / or the photodiode chip at the wafer level, which can improve the combination stability of the thermoelectric cooling structure and the VCSEL chip and / or the photodiode chip.

[0009] Another advantage of the present application is that it provides a VCSEL integrated wafer and a manufacturing method thereof, wherein the VCSEL integrated wafer can realize the manufacturing of VCSEL chips and photodiode chips in a chip manufacturing plant, as well as the assembly of thermoelectric cooling structures with VCSEL chips and / or photodiode chips, thereby improving industrial efficiency.

[0010] Another advantage of the present application is that it provides a VCSEL integrated wafer and a manufacturing method thereof, wherein the VCSEL chip, the thermoelectric cooling structure and the photodiode chip in the VCSEL integrated wafer are completed in the same chip manufacturing plant, which can improve the structural uniformity between each VCSEL chip, the structural uniformity between each photodiode chip, and the uniformity of assembly precision between the VCSEL chip and / or the photodiode chip and the thermoelectric cooling structure.

[0011] In order to achieve at least one of the above advantages or other advantages and purposes, according to one aspect of the present application, a VCSEL integrated wafer is provided, comprising: At least one VCSEL chip, each VCSEL chip comprising at least one VCSEL light emitting point; at least one photodiode chip spaced apart from the VCSEL chip, the VCSEL chip and the photodiode chip sharing a substrate layer; and A thermoelectric cooling structure is integrated into the VCSEL chip at the wafer level, wherein the thermoelectric cooling structure includes a plurality of thermocouple pairs, and each thermocouple pair includes a P-type structure and an N-type structure electrically connected to each other.

[0012] In the VCSEL integrated wafer according to the present application, each of the VCSEL light-emitting points includes a VCSEL body, and a VCSEL positive electrode and a VCSEL negative electrode electrically connected to the VCSEL body, each of the VCSEL bodies includes the substrate layer, a first reflective layer, an active region, a restriction layer having a restriction hole, and a second reflective layer, each of the photodiode chips includes at least one photodiode, each of the photodiodes includes a diode body, a diode positive electrode and a diode negative electrode electrically connected to the diode body, and each of the diode bodies includes the substrate layer, a first type doped semiconductor layer, an inner depletion layer, a second type doped semiconductor layer, and an anti-reflection layer.

[0013] In the VCSEL integrated wafer according to the present application, the thermoelectric cooling structure is arranged on the backlight side of the active area of ​​the VCSEL chip.

[0014] In the VCSEL integrated wafer according to the present application, the substrate layer of the VCSEL light-emitting point, the first reflective layer, the active area and the second reflective layer are arranged in sequence from bottom to top, the confinement layer is located on the upper side of the active area and / or the lower side of the active area, the substrate layer of the photodiode chip, the first type doped semiconductor layer, the internal depletion layer, the second type doped semiconductor layer and the anti-reflection layer are arranged in sequence from bottom to top, the light emitting direction of the VCSEL light-emitting point is from the active area to the second reflective layer, and the thermoelectric cooling structure is located below the first reflective layer.

[0015] In the VCSEL integrated wafer according to the present application, the thermoelectric cooling structure is formed below the substrate layer.

[0016] In the VCSEL integrated wafer according to the present application, the thermoelectric cooling structure is formed between the first reflective layer and the substrate layer.

[0017] In the VCSEL integrated wafer according to the present application, the first reflective layer is an N-DBR layer, the second reflective layer is a P-DBR layer, the first type doped semiconductor layer is an N-type doped semiconductor layer, and the second type doped semiconductor layer is a P-type doped semiconductor layer.

[0018] In the VCSEL integrated wafer according to the present application, the first reflective layer is a P-DBR layer, the second reflective layer is an N-DBR layer, the first type doped semiconductor layer is a P type doped semiconductor layer, and the second type doped semiconductor layer is an N type doped semiconductor layer.

[0019] In the VCSEL integrated wafer according to the present application, the thermoelectric cooling structure also includes a thermoelectric positive electrode electrically connected to one of the thermocouple pairs and a thermoelectric negative electrode electrically connected to the other thermocouple, and the thermoelectric positive electrode and the thermoelectric negative electrode are configured to control the hot end of the thermoelectric cooling structure to be formed at the bottom of the thermoelectric cooling structure.

[0020] In the VCSEL integrated wafer according to the present application, the substrate layer of the VCSEL light-emitting point, the first reflective layer, the active area and the second reflective layer are arranged in sequence from bottom to top, the confinement layer is located on the upper side of the active area and / or the lower side of the active area, the substrate layer of the photodiode chip, the first type doped semiconductor layer, the internal depletion layer, the second type doped semiconductor layer and the anti-reflection layer are arranged in sequence from bottom to top, the light emitting direction of the VCSEL light-emitting point is from the active area to the first reflective layer, and the thermoelectric cooling structure is located above the second reflective layer.

[0021] In the VCSEL integrated wafer according to the present application, the first reflective layer is an N-DBR layer, the second reflective layer is a P-DBR layer, the first type doped semiconductor layer is an N-type doped semiconductor layer, and the second type doped semiconductor layer is a P-type doped semiconductor layer.

[0022] In the VCSEL integrated wafer according to the present application, the first reflective layer is a P-DBR layer, the second reflective layer is an N-DBR layer, the first type doped semiconductor layer is a P type doped semiconductor layer, and the second type doped semiconductor layer is an N type doped semiconductor layer.

[0023] In the VCSEL integrated wafer according to the present application, the thermoelectric cooling structure also includes a thermoelectric positive electrode electrically connected to one of the thermocouple pairs and a thermoelectric negative electrode electrically connected to the other thermocouple, and the thermoelectric positive electrode and the thermoelectric negative electrode are configured to control the hot end of the thermoelectric cooling structure to be formed on the top of the thermoelectric cooling structure.

[0024] According to another aspect of the present application, a method for manufacturing a VCSEL integrated wafer is provided, comprising: Forming at least one VCSEL body by an epitaxial growth process, wherein the VCSEL body comprises: a substrate layer, a first reflective layer, an active region, a restriction layer having a restriction hole, and a second reflective layer; growing a first-type doped semiconductor layer, an inner depletion layer, a second-type doped semiconductor layer and an anti-reflection layer on the substrate layer to form a diode body; forming a VCSEL positive electrode and a VCSEL negative electrode connected to the VCSEL body, and forming a diode positive electrode and a diode negative electrode connected to the diode body; and A thermoelectric cooling structure is formed below the substrate layer.

[0025] According to another aspect of the present application, a method for manufacturing a VCSEL integrated wafer is provided, comprising: providing a substrate layer; forming a thermoelectric cooling structure above the substrate layer; forming a first reflective layer, an active area, a confinement layer having confinement holes, and a second reflective layer above the thermoelectric cooling structure to form an integrated unit of the thermoelectric cooling structure and the VCSEL body; growing a first-type doped semiconductor layer, an inner depletion layer, a second-type doped semiconductor layer, and an anti-reflection layer over the thermoelectric cooling structure to form a diode body; and A VCSEL positive electrode and a VCSEL negative electrode connected to the VCSEL body are formed, and a diode positive electrode and a diode negative electrode connected to the diode body are formed.

[0026] According to another aspect of the present application, a method for manufacturing a VCSEL integrated wafer is provided, comprising: Forming at least one VCSEL body by an epitaxial growth process, wherein the VCSEL body comprises: a substrate layer, a first reflective layer, an active region, a restriction layer having a restriction hole, and a second reflective layer; growing a first-type doped semiconductor layer, an inner depletion layer, a second-type doped semiconductor layer and an anti-reflection layer on the substrate layer to form a diode body; forming a VCSEL positive electrode and a VCSEL negative electrode electrically connected to the VCSEL body, and forming a diode positive electrode and a diode negative electrode electrically connected to the diode body; and A thermoelectric cooling structure is formed above the VCSEL body and / or above the diode body.

[0027] Further objectives and advantages of the present application will be fully reflected through understanding of the following description and drawings.

[0028] These and other objects, features and advantages of the present application are fully reflected in the following detailed description, drawings and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] These and / or other aspects and advantages of the present application will become clearer and easier to understand from the following detailed description of the embodiments of the present application in conjunction with the accompanying drawings, in which: Figure 1The figure shows a schematic diagram of the relationship between the operating temperature of a VCSEL chip and its optical power.

[0030] Figure 2 FIG. 4 is a schematic diagram of a VCSEL integrated wafer according to an embodiment of the present application.

[0031] Figure 3 FIG. 1 is a partial cross-sectional schematic diagram of a VCSEL integrated wafer according to an embodiment of the present application.

[0032] Figure 4 FIG. 4 is another partial cross-sectional schematic diagram of a VCSEL integrated wafer according to an embodiment of the present application.

[0033] Figure 5 FIG. 4 is another partial cross-sectional schematic diagram of a VCSEL integrated wafer according to an embodiment of the present application.

[0034] Figure 6 FIG. 4 is another partial cross-sectional schematic diagram of a VCSEL integrated wafer according to an embodiment of the present application.

[0035] Figure 7 FIG. 4 is another partial cross-sectional schematic diagram of a VCSEL integrated wafer according to an embodiment of the present application.

[0036] Figure 8 FIG. 4 is another partial cross-sectional schematic diagram of a VCSEL integrated wafer according to an embodiment of the present application.

[0037] Fig. 9 The figure shows a schematic flow chart of a method for manufacturing a VCSEL integrated wafer according to an embodiment of the present application.

[0038] Fig.10 FIG. 1 is a schematic diagram of a manufacturing process of a VCSEL integrated wafer according to an embodiment of the present application.

[0039] Fig.11 FIG2 is a second schematic diagram of a manufacturing process of a VCSEL integrated wafer according to an embodiment of the present application.

[0040] Fig.12 Another schematic diagram of the process of manufacturing a VCSEL integrated wafer according to an embodiment of the present application is illustrated.

[0041] Fig.13 FIG. 1 is a schematic diagram of another manufacturing process of a VCSEL integrated wafer according to an embodiment of the present application.

[0042] Fig.14 FIG2 is a second schematic diagram illustrating another manufacturing process of a VCSEL integrated wafer according to an embodiment of the present application.

[0043] Fig.15FIG. 4 is another schematic diagram of a method for manufacturing a VCSEL integrated wafer according to an embodiment of the present application.

[0044] Fig.16 FIG. 1 is a schematic diagram of another manufacturing process of a VCSEL integrated wafer according to an embodiment of the present application.

[0045] Fig.17 FIG2 is a second schematic diagram of another manufacturing process of a VCSEL integrated wafer according to an embodiment of the present application. DETAILED DESCRIPTION

[0046] The terms and words used in the following specification and claims are not limited to the literal meanings, but are merely used by the inventor to enable a clear and consistent understanding of the present application. Therefore, it will be apparent to those skilled in the art that the following description of various embodiments of the present application is provided for illustration purposes only and not for the purpose of limiting the present application as defined by the appended claims and their equivalents.

[0047] It is to be understood that the term "one" should be understood as "at least one" or "one or more", that is, in one embodiment, the number of an element may be one, while in another embodiment, the number of the element may be multiple, and the term "one" should not be understood as a limitation on the quantity.

[0048] Although ordinals such as "first," "second," and the like will be used to describe various components, those components are not limited herein. The term is used only to distinguish one component from another. For example, a first component may be referred to as a second component, and likewise, a second component may be referred to as a first component without departing from the teachings of the present application. The term "and / or" as used herein includes any and all combinations of one or more associated listed items.

[0049] The terms used herein are only used for the purpose of describing various embodiments and are not intended to be limiting. As used herein, singular forms are intended to also include plural forms, unless the context clearly indicates an exception. In addition, it will be understood that the terms "including" and / or "having" when used in this specification specify the presence of the described features, numbers, steps, operations, components, elements or combinations thereof, without excluding the presence or addition of one or more other features, numbers, steps, operations, components, elements or groups thereof.

[0050] Application Summary: As mentioned above, there are problems with assembly stability and installation accuracy in the process of assembling the VCSEL laser and other devices. For example, as VCSEL technology matures, more high-power and high-power density applications are gradually developed. In recent years, the gradually mature multi-junction technology can meet the application of automotive laser radar. However, the working environment of VCSEL used in automotive laser radar is relatively harsh. When the working environment temperature of VCSEL is 85℃ to 105℃, the optical power will drop rapidly. Figure 1 As shown in FIG. 1 , based on the thermal sensitivity, the performance of VCSEL deteriorates as the temperature increases. In order to reduce the operating temperature of the VCSEL laser, a semiconductor cooler can be assembled on the VCSEL laser. Currently, the semiconductor cooler is mainly assembled on the packaged VCSEL laser by mounting.

[0051] However, when the semiconductor cooler is mounted on the packaged VCSEL laser by mounting, the bonding stability between the semiconductor cooler and the VCSEL laser is poor and the semiconductor cooler is easy to fall off.

[0052] In the actual industry, VCSEL lasers are usually provided by chip manufacturers, while the assembly of VCSEL packaged products is completed by packaging plants. That is, from VCSEL lasers to VCSEL packaged products, there are two nodes in the industrial chain. Moreover, in the actual industry, packaging plants may purchase VCSEL lasers provided by different manufacturers. At the same time, there may be problems such as uneven assembly accuracy during the assembly process, which makes it difficult to ensure the consistency of the final VCSEL packaged products.

[0053] Based on this, the inventor of this application proposes to integrate the VCSEL laser structure, the thermoelectric cooling structure and the photodiode chip structure at the wafer level based on the semiconductor product design and manufacturing process. In this way, a relatively stable combination between the thermoelectric cooling structure and the VCSEL laser structure and / or the photodiode chip structure is achieved.

[0054] Accordingly, according to one aspect of the present application, the present application proposes a VCSEL integrated wafer, which includes: at least one VCSEL chip, at least one photodiode chip spaced apart from the VCSEL chip, and a thermoelectric cooling structure integrated with the VCSEL chip at the wafer level, each VCSEL chip includes at least one VCSEL light-emitting point; the VCSEL chip and the photodiode chip share a substrate layer; the thermoelectric cooling structure includes a plurality of thermocouple pairs, each thermocouple pair includes a P-type structure and an N-type structure electrically connected to each other.

[0055] After introducing the basic principles of the present application, various non-limiting embodiments of the present application will be described in detail with reference to the accompanying drawings.

[0056] Schematic VCSEL integrated wafer: Figures 1 to 8 As shown, a VCSEL integrated wafer according to an embodiment of the present application is illustrated, wherein, as Figure 1 As shown, the VCSEL integrated wafer includes at least one VCSEL chip 10 and at least one photodiode chip 20 integrated at the wafer level, and a thermoelectric cooling structure 30 integrated in the VCSEL chip 10 and / or the photodiode chip 20 at the wafer level. The VCSEL chip 10 can be used as a light source for a laser projection unit in a depth camera module, and the photodiode chip 20 can be used as a photoelectric sensor for a camera unit in the depth camera module. That is, the VCSEL integrated wafer can form part of the laser projection unit of the depth camera module and part of the camera unit of the depth camera module on the same wafer. The depth camera module can be a structured light camera module or a TOF camera module.

[0057] Specifically, Figures 2 to 8 As shown, in the embodiment of the present application, the VCSEL chip 10 includes at least one VCSEL light-emitting point 60, that is, a single VCSEL laser structure. Each VCSEL light-emitting point 60 includes a VCSEL body 61, and a VCSEL positive electrode 62 and a VCSEL negative electrode 63 electrically connected to the VCSEL body 61. Each VCSEL body 61 includes a substrate layer 611, a first reflective layer 612, an active area 613, a restriction layer 614 having a restriction hole 601, and a second reflective layer 615 stacked on each other. The substrate layer 611, the first reflective layer 612, the active area 613, and the second reflective layer 615 of the VCSEL light-emitting point 60 are arranged in sequence from bottom to top. The restriction layer 614 is located on the upper side of the active area 613 and / or the lower side of the active area 613. Optionally, the first reflective layer 612 is an N-DBR layer, and the second reflective layer 615 is a P-DBR layer, that is, the substrate layer 611, the N-DBR layer, the active area 613 and the P-DBR layer of the VCSEL light-emitting point 60 are arranged in sequence from bottom to top; or, the first reflective layer 612 is a P-DBR layer, and the second reflective layer 615 is an N-DBR layer, that is, the substrate layer 611, the P-DBR layer, the active area 613 and the N-DBR layer of the VCSEL light-emitting point 60 are arranged in sequence from bottom to top.

[0058] In the embodiment of the present application, the substrate layer 611 may be made of a doped material such as InP, GaN, or GaAs. When the first reflective layer 612 is an N-DBR layer, the substrate layer 611 is made of an N-type doped material; and when the first reflective layer 612 is a P-DBR layer, the substrate layer 611 is made of a P-type doped material.

[0059] The N-DBR layer is composed of N-type doped high aluminum content Al x Ga 1-x As (x=1~0) and N-type doped low aluminum content Al x Ga 1-x The P-DBR layer is composed of P-type doped Al with high aluminum content. x Ga 1-x As (x=1~0) and P-type doped low aluminum content Al x Ga 1-x As (x=1~0) is formed. In some examples of the present application, the materials of the N-DBR layer and the P-DBR layer may not even contain aluminum, that is, they do not contain aluminum. It is worth mentioning that the material selection of the alternating layer depends on the operating wavelength of the laser emitted by the VCSEL light emitting point 60, and the optical thickness of each alternating layer is equal to or approximately equal to 1 / 4 of the operating wavelength of the laser.

[0060] The active region 613 is sandwiched between the first reflective layer 612 and the second reflective layer 615 to form a resonant cavity, wherein after being excited, photons are reflected back and forth in the resonant cavity and repeatedly amplified to form laser oscillation, thereby forming a laser. A person skilled in the art should know that by configuring and designing the first reflective layer 612 and the second reflective layer 615, the emission direction of the laser can be selectively controlled, for example, to be emitted from the first reflective layer 612, or, to be emitted from the second reflective layer 615. Accordingly, the first reflective layer 612 and the second reflective layer 615 are configured so that after the VCSEL light-emitting point 60 is turned on, the laser generated by the active region 613 is reflected multiple times in the resonant cavity formed between the first reflective layer 612 and the second reflective layer 615, and then emitted from the second reflective layer 615, or, the first reflective layer 612.

[0061] After the VCSEL light-emitting point 60 is turned on, the current is restricted by the restriction layer 614 and is finally introduced into the middle area of ​​the VCSEL light-emitting point 60, so that the middle area of ​​the active area 613 generates laser. More specifically, in the embodiment of the present application, the restriction layer 614 has a restriction area surrounding the restriction hole 601, the restriction area has a higher resistivity to restrict the flow of carriers into the middle area of ​​the VCSEL light-emitting point 60, and the refractive index of the restriction area is lower to laterally restrict photons. The carrier and optical lateral restriction increases the density of carriers and photons in the active area 613, and improves the efficiency of generating light in the active area 613.

[0062] In the embodiment of the present application, the confinement layer 614 may be implemented as an oxidized confinement layer 614, which is formed on the upper side and / or lower side of the active region 613 through an oxidation process. The confinement layer 614 may also be implemented as other types, for example, as an ion confinement layer 614, which is formed on the upper side or lower side of the active region 613 through an ion implantation process, which is not limited by the present application.

[0063] The formation positions of the VCSEL positive electrode 62 and the VCSEL negative electrode 63 are not limited by the present application. In some embodiments of the present application, Figure 3 to Figure 4 As shown, the first reflective layer 612 is an N-DBR layer, the second reflective layer 615 is a P-DBR layer, the P-DBR layer is located above the active region 613, the N-DBR layer is located below the active region 613, the VCSEL positive electrode 62 is formed on the upper surface of the VCSEL body 61, that is, the upper surface 602 of the body, the upper surface of the substrate layer 611 is partially exposed, and the VCSEL negative electrode 63 is formed on the exposed portion of the upper surface of the substrate layer 611. Optionally, the VCSEL negative electrode 63 may also be formed at other locations, for example, the upper surface of the first reflective layer 612 (that is, the N-DBR layer) is partially exposed, and the VCSEL negative electrode 63 is formed on the exposed portion of the upper surface of the first reflective layer 612 (that is, the N-DBR layer); for another example, the lower surface of the substrate layer 611 (such as Figure 5As shown). When the second reflective layer 615 (i.e., P-DBR layer) is located above the active region 613 and the VCSEL light emitting point 60 is turned on, the laser generated by the active region 613 is emitted from the second reflective layer 615 (i.e., P-DBR layer), and the VCSEL positive electrode 62 can be implemented as a ring-shaped positive electrode, and a light exit hole 604 corresponding to the limiting hole 601 is formed in the middle thereof to allow the light to pass through. When the second reflective layer 615 (i.e., P-DBR layer) is located above the active region 613 and the VCSEL light emitting point 60 is turned on, the laser generated by the active region 613 is emitted from the first reflective layer 612 (i.e., N-DBR layer), the VCSEL negative electrode 63 can be implemented as a ring-shaped negative electrode, and a light exit hole 604 corresponding to the limiting hole 601 is formed in the middle thereof to allow the light to pass through.

[0064] In other embodiments of the present application, Figure 6 to Figure 7 As shown, the first reflective layer 612 is a P-DBR layer, the second reflective layer 615 is an N-DBR layer, the N-DBR layer is located above the active region 613, the P-DBR layer is located below the active region 613, the VCSEL negative electrode 63 is formed on the upper surface of the VCSEL body 61, that is, the upper surface 602 of the body, the upper surface of the substrate layer 611 is partially exposed, and the VCSEL positive electrode 62 is formed on the exposed portion of the upper surface of the substrate layer 611. Optionally, the VCSEL positive electrode 62 may also be formed at other locations, for example, the upper surface of the first reflective layer 612 (that is, the P-DBR layer) is partially exposed, and the VCSEL positive electrode 62 is formed on the exposed portion of the upper surface of the first reflective layer 612 (that is, the P-DBR layer); for another example, the lower surface of the substrate layer 611 (such as Figure 8As shown). When the second reflective layer 615 (i.e., N-DBR layer) is located above the active region 613 and the VCSEL light emitting point 60 is turned on, when the laser light generated by the active region 613 is emitted from the second reflective layer 615 (i.e., N-DBR layer), the VCSEL negative electrode 63 may be implemented as a ring-shaped negative electrode, in which a light exit hole 604 corresponding to the limiting hole 601 is formed in the middle to allow the light to pass through. When the second reflective layer 615 (i.e., N-DBR layer) is located above the active region 613 and the VCSEL light emitting point 60 is turned on, when the laser light generated by the active region 613 is emitted from the first reflective layer 6122 (i.e., P-DBR layer), the VCSEL positive electrode 62 may be implemented as a ring-shaped negative electrode, in which a light exit hole 604 corresponding to the limiting hole 601 is formed in the middle to allow the light to pass through.

[0065] In the embodiment of the present application, the VCSEL chip 10 and the photodiode chip 20 are formed on the same wafer and completed in the same chip manufacturing plant, and can also be assembled in the chip manufacturing plant to improve industrial efficiency. The VCSEL chip 10 and the photodiode chip 20 are completed in the same chip manufacturing plant, which can improve the structural uniformity between each photodiode chip 20, and the assembly uniformity between the VCSEL chip 10 and the photodiode chip 20.

[0066] The photodiode chip 20 is spaced apart from the VCSEL chip 10. Each of the photodiode chips 20 includes at least one photodiode 90, each of the photodiodes 90 includes a diode body 91, a diode positive electrode 92 and a diode negative electrode 93 electrically connected to the diode body 91, each of the diode bodies 91 includes the substrate layer 611, a first-type doped semiconductor layer 911, an inner depletion layer 912, a second-type doped semiconductor layer 913 and an anti-reflection layer 914, and the VCSEL body 61 and the diode body 91 share the substrate layer 611. That is, the substrate layer 611 of the VCSEL body 61 of the VCSEL chip 10 and the substrate layer 611 of the diode body 91 are a common substrate layer.

[0067] In one embodiment of the present application, the first-type doped semiconductor layer 911 is an N-type doped semiconductor layer, and the second-type doped semiconductor layer 913 is a P-type doped semiconductor layer. In other embodiments of the present application, the first-type doped semiconductor layer 911 is a P-type doped semiconductor layer, and the second-type doped semiconductor layer 913 is an N-type doped semiconductor layer.

[0068] The N-type doped semiconductor layer may be made of N-type doped GaAs, and the N-type doped semiconductor layer may be made of P-type doped GaAs. It should be understood that the N-type doped semiconductor layer may be made of other N-type doped semiconductor materials, and the P-type doped semiconductor layer may be made of other P-type doped semiconductor materials.

[0069] The inner depletion layer 912 can be made of non-doped GaAs or low-concentration N-type doped GaAs, or other non-doped semiconductor materials or other low-concentration N-type doped materials. The anti-reflection layer 914 can be made of silicon dioxide material, located on the light-receiving surface of the photodiode 90, or other anti-reflection materials.

[0070] In the embodiment of the present application, the substrate layer 611, the first-type doped semiconductor layer 911, the inner depletion layer 912, the second-type doped semiconductor layer 913 and the anti-reflection layer 914 are arranged in sequence from bottom to top. When the first-type doped semiconductor layer 911 is an N-type doped semiconductor layer and the second-type doped semiconductor layer 913 is a P-type doped semiconductor layer, the substrate layer 611, the N-type doped semiconductor layer, the inner depletion layer 912, the P-type doped semiconductor layer and the anti-reflection layer 914 are arranged in sequence from bottom to top. The diode positive electrode 92 is formed above the second-type doped semiconductor layer 913 (i.e., the P-type doped semiconductor layer), the upper surface of the substrate layer 611 is partially exposed, and the diode negative electrode 93 is formed on the exposed portion of the upper surface of the substrate layer 611. The diode negative electrode 93 may also be formed at other locations, for example, the upper surface of the first-type doped semiconductor layer 911 (i.e., the N-type doped semiconductor layer) is partially exposed, and the diode negative electrode 93 is formed on the exposed portion of the upper surface of the first-type doped semiconductor layer 911 (i.e., the N-type doped semiconductor layer).

[0071] When the first-type doped semiconductor layer 911 is a P-type doped semiconductor layer and the second-type doped semiconductor layer 913 is an N-type doped semiconductor layer, the substrate layer 611, the P-type doped semiconductor layer, the internal depletion layer 912, the N-type doped semiconductor layer and the anti-reflection layer 914 are arranged in sequence from bottom to top. The diode negative electrode 93 is formed above the second-type doped semiconductor (i.e., the N-type doped semiconductor layer), the upper surface of the substrate layer 611 is partially exposed, and the diode positive electrode 92 is formed on the exposed portion of the upper surface of the substrate layer 611. The diode positive electrode 92 may also be formed at other locations, for example, the upper surface of the first-type doped semiconductor layer 911 (i.e., the P-type doped semiconductor layer) is partially exposed, and the diode positive electrode 92 is formed on the exposed portion of the upper surface of the first-type doped semiconductor layer 911 (i.e., the P-type doped semiconductor layer).

[0072] When the substrate layer 611 of the photodiode chip 20, the N-type doped semiconductor layer, the internal depletion layer 912, the P-type doped semiconductor layer and the anti-reflection layer 914 are arranged in sequence from bottom to top, the photodiode chip 20 also includes a guard ring (not shown in the figure) surrounding the N-doped semiconductor layer.

[0073] In the present application, the arrangement of the VCSEL chips 10 and the photodiode chips 20 is not limited by the present application. In one embodiment of the present application, the VCSEL integrated wafer includes at least one row of the VCSEL chips 10 and at least one row of the photodiode chips 20 arranged along a first preset direction, and at least one row of the VCSEL chips 10 and at least one row of the photodiode chips 20 are arranged adjacent to each other. When the VCSEL integrated wafer includes multiple rows of the VCSEL chips 10 and multiple rows of the photodiode chips 20 arranged along a first preset direction, each row of the VCSEL chips 10 and each row of the photodiode chips 20 are arranged alternately, and a row of the photodiode chips 20 is arranged every other row or rows of the VCSEL chips 10, or a row of the VCSEL chips 10 is arranged every other row or rows of the photodiode chips 20, such as Figure 1 shown.

[0074] In an embodiment of the present application, the VCSEL integrated wafer further includes a thermoelectric cooling structure 30 to reduce the operating temperature of the VCSEL chip 10 and / or the photodiode chip 20, and the thermoelectric cooling structure 30 is integrated into the VCSEL chip 10 and / or the photodiode chip 20 at the wafer level, which can improve the bonding strength between the thermoelectric cooling structure 30 and the VCSEL chip 10 and / or the photodiode chip 20.

[0075] The thermoelectric cooling structure 30 uses the Peltier effect to reduce the operating temperature of the VCSEL chip 10 and / or the photodiode chip 20. The Peltier effect refers to the fact that when a current passes through a loop composed of different conductors, in addition to generating irreversible Joule heat, heat absorption and heat release phenomena will occur at the joints of different conductors depending on the direction of the current. Accordingly, the thermoelectric cooling structure 30 includes a plurality of thermocouple pairs 31, each of which includes two different types of conductor structures, namely, a P-type structure 311 and an N-type structure 312, to form a hot end and a cold end. The P-type structure 311 can be implemented as a P-type material doped with Bi or Te alloy (for example, Bi 2 Te 3 Or BiSb), PbTe, SiGe, MgSi, P-type doping elements include Sb, B, etc.; the N-type structure 312 can be implemented as an N-type material doped with Bi or Te alloy (for example, Bi2Te3 or BiSb), PbTe, SiGe, MgSi, and N-type doping elements include Se, P, etc.

[0076] The thermoelectric cooling structure 30 also includes a thermoelectric positive electrode 32 electrically connected to one of the thermocouple pairs 31 and a thermoelectric negative electrode 33 electrically connected to another of the thermocouple pairs 31. The thermoelectric positive electrode 32 is formed at the N-type structure 312 of one of the thermocouple pairs, and the thermoelectric negative electrode 33 is formed at the P-type structure 311 of one of the thermocouple pairs. The hot end of the thermoelectric cooling structure 30, i.e., the heat release end, and the cold end of the thermoelectric cooling structure 30, i.e., the heat absorption end, can be controlled by controlling the electrical connection mode of the thermoelectric cooling structure 30. Optionally, the thermoelectric positive electrode 32 and the thermoelectric negative electrode 33 are configured to control the hot end of the thermoelectric cooling structure 30 to be formed at the bottom of the thermoelectric cooling structure 30; or, the thermoelectric positive electrode 32 and the thermoelectric negative electrode 33 are configured to control the hot end of the thermoelectric cooling structure 30 to be formed at the top of the thermoelectric cooling structure 30.

[0077] Optionally, a plurality of the thermocouple pairs 31 are connected in electrical series and thermal parallel. Accordingly, the thermoelectric cooling structure 31 includes a plurality of first electrical connection lines 341 and a plurality of second electrical connection lines 351, wherein a first electrical connection line 341 is formed between a P-type structure 311 and an N-type structure 312 of each thermocouple pair 31, and a second electrical connection line 351 is formed between the P-type structure 311 of each thermocouple pair 31 and the N-type structure 312 of another thermocouple pair 31 in each two adjacent thermocouple pairs 31. Accordingly, each of the first electrical connection lines 341 is formed between the P-type structure 311 and the N-type structure 312 of each thermocouple pair 31, and each of the second electrical connection lines 432 is formed between the P-type structure 311 of one thermocouple pair 31 and the N-type structure 312 of the adjacent thermocouple pair 31. The plurality of first electrical connection lines 341 form a first electrical connection layer 34 , and the plurality of second electrical connection lines 351 form a second electrical connection layer 35 .

[0078] The thermoelectric cooling structure 30 further includes an insulating filler 36. At least part of the insulating filler 36 is filled between the P-type structure 311 and the N-type structure 312 of two adjacent thermocouple pairs 31; at least part of the insulating filler 36 is filled between the P-type structure 311 and the N-type structure 312 of each thermocouple end 31.

[0079] The thermoelectric cooling structure 30 further includes an insulating layer 37 formed between the VCSEL body 61 and / or the diode body 91 to electrically isolate the VCSEL light emitting point 60 and / or the photodiode 90 from the thermoelectric cooling structure 30 .

[0080] Optionally, the thermoelectric cooling structure 30 may be formed on the surface of the VCSEL body 61 and / or the photodiode body 91 (eg, Figure 3 and Figure 5 , Figures 6 to 8 ), may also be formed in the VCSEL body 61 and / or the photodiode body 91 (as shown in Figure 4 and Figure 7 When the thermoelectric cooling structure 30 is formed on the surface of the VCSEL body 61, it is convenient for the thermoelectric cooling structure 30 to fit with the heat sink structure during packaging, thereby accelerating heat dissipation. The heat sink structure refers to a structure whose temperature does not substantially change with the change of the amount of heat transferred thereto.

[0081] Preferably, the thermoelectric cooling structure 30 is formed on the backlight side of the VCSEL light emitting point 60 to avoid affecting the light emitting performance of the VCSEL light emitting point 60 . The backlight side of the VCSEL light-emitting point 30 refers to the side of the active area 613 thereof that emits light away from the light emission direction. For example, when the substrate layer 611, the first reflective layer 612, the active area 613 and the second reflective layer 615 are arranged in sequence from bottom to top, and the light emission direction is from the active area 613 to the second reflective layer 615, the lower side of the active area 613 is the backlight side of the VCSEL light-emitting point 60, and the first reflective layer 612 and the substrate layer are located on the backlight side of the VCSEL light-emitting point; when the substrate layer 611, the first reflective layer 612, the active area 613 and the second reflective layer 615 are arranged in sequence from bottom to top, and the light emission direction is from the active area 613 to the first reflective layer 612, the side of the active area 613 is the backlight side of the VCSEL light-emitting point 60, and the second reflective layer 615 is located on the backlight side of the VCSEL light-emitting point 60.

[0082] Accordingly, in some embodiments of the present application, Figure 3 As shown, the first reflective layer 612 is an N-DBR layer, the second reflective layer 615 is a P-DBR layer, the substrate layer 611, the P-DBR layer, the active area 613 and the N-DBR layer of the VCSEL light-emitting point 60 are arranged in sequence from bottom to top, and the light emitting direction of the VCSEL light-emitting point 60 is from the active area 613 to the second reflective layer 615 (i.e., the P-DBR layer). The thermoelectric cooling structure 30 is formed below the substrate layer 611. In a specific example of the present application, the lower surface of the substrate layer 611 forms the lower surface of the VCSEL light-emitting body 61, that is, the thermoelectric cooling structure 30 is formed on the lower surface of the VCSEL light-emitting body 61.

[0083] When the thermoelectric cooling structure 30 is formed on the substrate layer 611, the thermoelectric positive electrode 32 and the thermoelectric negative electrode 33 are configured to control the hot end of the thermoelectric cooling structure 30 to be formed at the bottom of the thermoelectric cooling structure 30. The top of the thermoelectric cooling structure 30 absorbs the heat of the VCSEL light emitting point 60 and / or the photodiode 90, and the thermoelectric cooling structure 30 dissipates heat through the heat sink structure, so that the VCSEL body 10 works under a lower temperature condition to ensure its performance, for example, its optical power. The thermoelectric cooling structure 30 includes an insulating layer 37 formed between the substrate layer 611 and the thermocouple pair 31.

[0084] In other embodiments of the present application, Figure 4 As shown, the first reflective layer 612 is an N-DBR layer, the second reflective layer 615 is a P-DBR layer, the substrate layer 611, the P-DBR layer, the active area 613 and the N-DBR layer of the VCSEL light-emitting point 60 are arranged in sequence from bottom to top, and the light emitting direction of the VCSEL light-emitting point 60 is from the active area 613 to the second reflective layer 615 (i.e., the P-DBR layer). The thermoelectric cooling structure 30 is formed between the substrate layer 611 and the first reflective layer 612 (i.e., the N-DBR layer).

[0085] When the thermoelectric cooling structure 30 is formed between the substrate layer 611 and the first reflective layer 612, the thermoelectric positive electrode 32 and the thermoelectric negative electrode 33 are configured to control the hot end of the thermoelectric cooling structure 30 to be formed at the bottom of the thermoelectric cooling structure 30. The top of the thermoelectric cooling structure 30 absorbs the heat of the VCSEL light-emitting point 60 and / or the photodiode 90, and the bottom of the thermoelectric cooling structure 30 dissipates heat through the substrate layer 611. Optionally, a heat sink structure can be provided at the substrate layer 611 to further dissipate heat through the heat sink structure. The thermoelectric cooling structure 30 includes an insulating layer 37 formed between the substrate layer 611 and the thermocouple pair 31 and an insulating layer 37 formed between the substrate layer 611 and the first reflective layer 612.

[0086] In some other embodiments of the present application, Figure 5 As shown, the first reflective layer 612 is an N-DBR layer, the second reflective layer 615 is a P-DBR layer, the substrate layer 611, the P-DBR layer, the active area 613 and the N-DBR layer of the VCSEL light-emitting point 60 are arranged in sequence from bottom to top, and the light emitting direction of the VCSEL light-emitting point 60 is from the active area 613 to the first reflective layer 612 (i.e., N-DBR layer). The thermoelectric cooling structure 30 is formed above the second reflective layer 615 (i.e., P-DBR layer).

[0087] When the thermoelectric cooling structure 30 is formed above the second reflective layer 615, the thermoelectric positive electrode 32 and the thermoelectric negative electrode 33 are configured to control the hot end of the thermoelectric cooling structure 30 to be formed at the bottom and top of the thermoelectric cooling structure 30. The bottom of the thermoelectric cooling structure 30 absorbs the heat of the VCSEL light emitting point 60 and / or the photodiode 90, and the top of the thermoelectric cooling structure 30 dissipates heat through the substrate layer 611. The thermoelectric cooling structure 30 includes an insulating layer 37 formed between the second reflective layer 615 and the thermocouple pair 31.

[0088] In some other embodiments of the present application, Figure 6 As shown, the first reflective layer 612 is a P-DBR layer, the second reflective layer 615 is an N-DBR layer, the substrate layer 611, the P-DBR layer, the active area 613 and the N-DBR layer of the VCSEL light-emitting point 60 are arranged in sequence from bottom to top, and the light emitting direction of the VCSEL light-emitting point 60 is from the active area 613 to the second reflective layer 615 (i.e., the N-DBR layer). The thermoelectric cooling structure 30 is formed below the substrate layer 611. In a specific example of the present application, the lower surface of the substrate layer 611 forms the lower surface of the VCSEL light-emitting body 61, that is, the thermoelectric cooling structure 30 is formed on the lower surface of the VCSEL light-emitting body 61.

[0089] In some other embodiments of the present application, Figure 7 As shown, the first reflective layer 612 is a P-DBR layer, the second reflective layer 615 is an N-DBR layer, the substrate layer 611, the P-DBR layer, the active area 613 and the N-DBR layer of the VCSEL light-emitting point 60 are arranged in sequence from bottom to top, and the light emitting direction of the VCSEL light-emitting point 60 is from the active area 613 to the second reflective layer 615 (i.e., the N-DBR layer). The thermoelectric cooling structure 30 is formed between the substrate layer 611 and the first reflective layer 612 (i.e., the P-DBR layer).

[0090] In some other embodiments of the present application, Figure 8As shown, the first reflective layer 612 is a P-DBR layer, the second reflective layer 615 is an N-DBR layer, the substrate layer 611, the P-DBR layer, the active area 613 and the N-DBR layer of the VCSEL light-emitting point 60 are arranged in sequence from bottom to top, and the light emitting direction of the VCSEL light-emitting point 60 is from the active area 613 to the first reflective layer 612 (i.e., the P-DBR layer). The thermoelectric cooling structure 30 is formed above the second reflective layer 615 (i.e., the N-DBR layer).

[0091] Schematic method for manufacturing a VCSEL integrated wafer: Accordingly, in an embodiment of the present application, a method for manufacturing a VCSEL integrated wafer is proposed, such as Figures 9 to 11 As shown, it includes: S110, forming at least one VCSEL body 61 by an epitaxial growth process, wherein the VCSEL body 61 includes: a substrate layer 611, a first reflective layer 612, an active region 613, a limiting layer 614 having a limiting hole 601, and a second reflective layer 615; S120, growing a first type doped semiconductor layer 911, an inner depletion layer 912, a second type doped semiconductor layer 913, and an anti-reflection layer 914 above the substrate layer 611 to form a diode body 91; S130, forming a VCSEL positive electrode 62 and a VCSEL negative electrode 63 connected to the VCSEL body 61, and forming a diode positive electrode 92 and a diode negative electrode 93 connected to the diode body 91; and, S140, forming a thermoelectric cooling structure 30 below the substrate layer 611.

[0092] In step S110, at least one VCSEL body 61 is formed by an epitaxial growth process. Specifically, the specific implementation method of forming the VCSEL body 61 is not limited by the present application. In a specific example of the present application, first, a substrate layer 611 is provided, and then, a first doped semiconductor alternating layer, an active region forming layer, and a second doped semiconductor alternating layer stacked on the substrate layer 611 are grown on the substrate layer 611 by an epitaxial growth process to form an epitaxial body structure, wherein the epitaxial body structure includes a first doped semiconductor alternating layer, an active region forming layer, and a second doped semiconductor alternating layer stacked on the substrate layer 611. The first doped semiconductor alternating layer, the active region forming layer, and the second doped semiconductor alternating layer are arranged from bottom to top. The first doped semiconductor alternating layer is implemented as an N-type semiconductor alternating layer, and the second doped semiconductor alternating layer is implemented as a P-type semiconductor alternating layer, or the first doped semiconductor alternating layer is implemented as a P-type semiconductor alternating layer, and the second doped semiconductor alternating layer is implemented as an N-type semiconductor alternating layer. Next, a VCSEL chip formation region is defined, and the portion of the epitaxial body outside the VCSEL chip formation region is removed by an etching process, so that the epitaxial body structure is divided into a plurality of unit structures for forming the VCSEL chip 10. Specifically, each layer structure of the epitaxial body structure (i.e., the N-type semiconductor alternating layer, the active region forming layer, and the P-type semiconductor alternating layer) is respectively divided into a plurality of sub-unit regions. Each unit structure includes: at least one first doped semiconductor alternating layer sub-unit region, at least one active region forming layer sub-unit region, and at least one second doped semiconductor alternating layer sub-unit region. The unit structure is oxidized so that the part of the alternating layers of each first doped semiconductor alternating layer sub-unit area and / or the part of the alternating layers of the second doped semiconductor alternating layer sub-unit area in the unit structure near the outer edge of the unit structure is oxidized to form a confining area, and the part near the center of the unit structure is not oxidized to form a confining hole 601 in the confining area, so that the part of the alternating layers of the first doped semiconductor alternating layer sub-unit area and / or the part of the alternating layers of the second doped semiconductor alternating layer sub-unit area in the unit structure forms a confining layer 614 with a confining hole 601. The confining layer 614 can also be formed by other methods, for example, by an ion implantation process. In this way, each oxidized unit structure and the substrate layer 611 form a VCSEL body 61, wherein the part of the first doped semiconductor alternating layer sub-unit area where the confining layer is not formed forms the first reflective layer 612, the part of the second doped semiconductor alternating layer sub-unit area where the confining layer is not formed forms the second reflective layer 615, and the active region forming layer sub-unit area forms the active region of the VCSEL body 61.In the embodiment of the present application, the substrate layer 611 may be thinned.

[0093] In step S120, a first-type doped semiconductor layer 911, an inner depletion layer 912, a second-type doped semiconductor layer 913 and an anti-reflection layer 914 are grown on the substrate layer 611 to form a diode body 91. Specifically, a photodiode formation region is defined, and the photodiode formation region is spaced apart from the VCSEL chip formation region. A first-type doped semiconductor layer 911, an inner depletion layer 912, a second-type doped semiconductor layer 913 and an anti-reflection layer 914 are formed in the photodiode formation region on the substrate layer 611 by an epitaxial growth process and are stacked on the substrate layer 611 to form a diode body 91. When the first doped-type semiconductor alternating layer is implemented as an N-type semiconductor alternating layer and the second doped-type semiconductor alternating layer is implemented as a P-type semiconductor alternating layer, the first-type doped semiconductor layer 911 is an N-type doped semiconductor layer and the second-type doped semiconductor layer 913 is a P-type doped semiconductor layer. When the first doped semiconductor alternating layer is implemented as a P-type semiconductor alternating layer and the second doped semiconductor alternating layer is implemented as an N-type semiconductor alternating layer, the first doped semiconductor layer 911 is a P-type doped semiconductor layer and the second doped semiconductor layer 913 is an N-type doped semiconductor layer.

[0094] In step S130, a VCSEL positive electrode 62 and a VCSEL negative electrode 63 connected to the VCSEL body 61 are formed, and a diode positive electrode 92 and a diode negative electrode 93 connected to the diode body 91 are formed. Specifically, the formation method and formation position of the VCSEL positive electrode 62 and the VCSEL negative electrode 63, and the diode positive electrode 92 and the diode negative electrode 93 are not limited to the present application. In one embodiment of the present application, when the N-type semiconductor alternating layers, the active region forming layer and the P-type semiconductor alternating layers are arranged from bottom to top, the VCSEL positive electrode 62 is formed on the upper surface of the VCSEL body 61, that is, on the upper surface 602 of the body, by electroplating, and the VCSEL negative electrode 63 is formed on the upper surface of the VCSEL substrate layer 611 by electroplating; the diode positive electrode 92 is formed on the upper surface of the diode body 91 by electroplating; and the diode negative electrode 93 is formed on the upper surface of the VCSEL substrate layer 611 by electroplating.

[0095] When the P-type semiconductor alternating layer, the active area forming layer and the N-type semiconductor alternating layer are arranged from bottom to top, the VCSEL positive electrode 62 is formed on the upper surface of the VCSEL substrate layer 611 by electroplating; the VCSEL negative electrode 63 is formed on the upper surface of the VCSEL body 61, that is, the body upper surface 602 by electroplating; the diode positive electrode 92 is formed on the upper surface of the VCSEL substrate layer 611 by electroplating; and the diode negative electrode 93 is formed on the upper surface of the diode body 91 by electroplating.

[0096] In step S140, a thermoelectric cooling structure 30 is formed under the substrate layer 611. Specifically, first, an insulating layer 37 is formed on the lower surface of the substrate layer 611. Then, a first electrical connection layer 34 is formed on the lower surface of the insulating layer 37, and the first electrical connection layer 34 includes a plurality of first electrical connection lines 341 spaced apart from each other. Next, a plurality of thermocouple pairs 31 can be grown on the lower surface of the first electrical connection lines 341 by a semiconductor growth process, and each of the thermocouple pairs 31 includes a P-type structure 311 and an N-type structure 312, and the P-type structure 311 and the N-type structure 312 of a thermocouple pair 31 are formed on one of the first electrical connection lines 341. Subsequently, a second electrical connection layer 35, a thermoelectric positive electrode 32 and a thermoelectric negative electrode 33 can be formed on the lower surface of the thermocouple pair 31, wherein the second electrical connection layer 35 includes a plurality of second electrical connection lines 351 spaced apart from each other, and one of the second electrical connection lines 351 is formed between a P-type structure 311 of a thermocouple pair 31 and an N-type structure 312 of the thermocouple pair 31 adjacent thereto; the thermoelectric positive electrode 32 is formed on the N-type structure 312 of a thermocouple pair 31, and the thermoelectric negative electrode 33 is formed on the P-type structure 311 of a thermocouple pair 31.

[0097] In the embodiment of the present application, another method for manufacturing a VCSEL integrated wafer is proposed, such as Figure 12 to Figure 14As shown, it includes: S210, providing a substrate layer 611; S220, forming a thermoelectric cooling structure 30 above the substrate layer; S230, forming a first reflection layer 612, an active area 613, a restriction layer 614 with a restriction hole 601 and a second reflection layer 615 above the thermoelectric cooling structure 30 to form an integrated unit of the thermoelectric cooling structure 30 and the VCSEL body 61; S240, growing a first type doped semiconductor layer 911, an inner depletion layer 912, a second type doped semiconductor layer 913 and an anti-reflection layer 914 on the thermoelectric cooling structure 30 to form a diode body 91; S250, forming a VCSEL positive electrode 62 and a VCSEL negative electrode 63 connected to the VCSEL body 61, and forming a diode positive electrode 92 and a diode negative electrode 93 connected to the diode body 91.

[0098] In step S210, a substrate layer 611 is provided. Specifically, the substrate layer 611 may be made of a doped material such as InP, GaN, or GaAs.

[0099] In step S220, a thermoelectric cooling structure 30 is formed on the substrate layer to form an integrated unit of the thermoelectric cooling structure 30 and the VCSEL body 61. Specifically, first, an insulating layer 37 is formed on the substrate layer 611. Then, an electrical connection layer, a thermoelectric positive electrode 32 and a thermoelectric negative electrode 33 are formed on the insulating layer 37, and the electrical connection layer includes a plurality of electrical connection lines spaced from each other. Next, a plurality of thermocouple pairs 31 can be grown above the electrical connection lines by a semiconductor growth process, each of the thermocouple pairs 31 includes a P-type structure 311 and an N-type structure 312, and the P-type structure 311 and the N-type structure 312 of a thermocouple pair 31 are formed on one of the electrical connection lines; an N-type structure 312 is formed on the thermoelectric positive electrode 32, and a P-type structure 311 is formed on the thermoelectric negative electrode 33. Subsequently, another electrical connection layer including a plurality of electrical connection lines spaced apart from each other may be formed above the thermocouple pairs 31, wherein each electrical connection line above the thermocouple pairs 31 is formed between a P-type structure 311 of one thermocouple pair 31 and an N-type structure 312 of an adjacent thermocouple pair 31. Then, another insulating layer 37 is formed on the second electrical connection line 351.

[0100] In step S230, a first reflective layer 612, an active area 613, a limiting layer 614 having a limiting hole 601, and a second reflective layer 615 are formed on the insulating layer 37 of the thermoelectric cooling structure 30 located on the second electrical connection line 351 to form an integrated unit of the thermoelectric cooling structure 30 and the VCSEL body 61. Specifically, a first doped semiconductor alternating layer, an active area forming layer, and a second doped semiconductor alternating layer are grown on the thermoelectric cooling structure 30 by an epitaxial growth process to form an epitaxial main body structure, the epitaxial main body structure comprising the first doped semiconductor alternating layer, the active area forming layer, and the second doped semiconductor alternating layer. The first doped semiconductor alternating layer, the active area forming layer, and the second doped semiconductor alternating layer are arranged from bottom to top. The first doped semiconductor alternating layer is implemented as an N-type semiconductor alternating layer, and the second doped semiconductor alternating layer is implemented as a P-type semiconductor alternating layer, or the first doped semiconductor alternating layer is implemented as a P-type semiconductor alternating layer, and the second doped semiconductor alternating layer is implemented as an N-type semiconductor alternating layer. Next, a VCSEL chip formation region is defined, and the portion of the epitaxial body outside the VCSEL chip formation region is removed by an etching process, so that the epitaxial body structure is divided into a plurality of unit structures for forming the VCSEL chip 10. Specifically, each layer structure of the epitaxial body structure (i.e., the N-type semiconductor alternating layer, the active region forming layer, and the P-type semiconductor alternating layer) is respectively divided into a plurality of sub-unit regions. Each unit structure includes: at least one first doped semiconductor alternating layer sub-unit region, at least one active region forming layer sub-unit region, and at least one second doped semiconductor alternating layer sub-unit region. The unit structure is subjected to oxidation treatment, so that the portion of the alternating layers of each first doped semiconductor alternating layer sub-unit area and / or the portion of the alternating layers of the second doped semiconductor alternating layer sub-unit area in the unit structure near the outer edge of the unit structure is oxidized to form a restriction area, and the portion near the center of the unit structure is not oxidized to form a restriction hole 601 in the restriction area, so that the portion of the alternating layers of the first doped semiconductor alternating layer sub-unit area and / or the portion of the alternating layers of the second doped semiconductor alternating layer sub-unit area in the unit structure forms a restriction layer 614 having a restriction hole 601. The restriction layer 614 can also be formed by other methods, for example, by an ion implantation process.In this way, each oxidized unit structure and the substrate layer 611 form a VCSEL body 61, wherein the portion of the first doped semiconductor alternating layer sub-unit region where the confinement layer is not formed forms the first reflective layer 612, the portion of the second doped semiconductor alternating layer sub-unit region where the confinement layer is not formed forms the second reflective layer 615, and the active region forming layer sub-unit region forms the active region of the VCSEL body 61. In the embodiment of the present application, the substrate layer 611 can be thinned.

[0101] In step S240, a first-type doped semiconductor layer 911, an inner depletion layer 912, a second-type doped semiconductor layer 913 and an anti-reflection layer 914 are grown on the thermoelectric cooling structure 30 to form a diode body 91. Specifically, a photodiode formation region is defined, and the photodiode formation region is spaced apart from the VCSEL light-emitting point formation region. A first-type doped semiconductor layer 911, an inner depletion layer 912, an anti-reflection layer 914, and a second-type doped semiconductor layer 913 are formed on the thermoelectric cooling structure 30 by an epitaxial growth process to form a diode body 91. When the first doped semiconductor alternating layer is implemented as an N-type semiconductor alternating layer and the second doped semiconductor alternating layer is implemented as a P-type semiconductor alternating layer, the first-type doped semiconductor layer 911 is an N-type doped semiconductor layer and the second-type doped semiconductor layer 913 is a P-type doped semiconductor layer. When the first doped semiconductor alternating layer is implemented as a P-type semiconductor alternating layer and the second doped semiconductor alternating layer is implemented as an N-type semiconductor alternating layer, the first doped semiconductor layer 911 is a P-type doped semiconductor layer and the second doped semiconductor layer 913 is an N-type doped semiconductor layer.

[0102] In step S250, a VCSEL positive electrode 62 and a VCSEL negative electrode 63 connected to the VCSEL body 61 are formed, and a diode positive electrode 92 and a diode negative electrode 93 connected to the diode body 91 are formed. Specifically, the VCSEL positive electrode 62 and the VCSEL negative electrode 63, and the formation method and formation position of the diode positive electrode 92 and the diode negative electrode 93 are not limited by the present application. In one embodiment of the present application, when the N-type semiconductor alternating layer, the active region forming layer and the P-type semiconductor alternating layer are arranged from bottom to top, the VCSEL positive electrode 62 is formed on the upper surface of the VCSEL body 61, that is, the upper surface 602 of the body by electroplating, and the VCSEL negative electrode 63 is formed on the N-type semiconductor alternating layer by electroplating; the diode positive electrode 92 is formed on the upper surface of the diode body 91 by electroplating; and the diode negative electrode 93 is formed on the N-type doped semiconductor layer by electroplating.

[0103] When the P-type semiconductor alternating layer, the active area forming layer and the N-type semiconductor alternating layer are arranged from bottom to top, the VCSEL positive electrode 62 is formed on the P-type semiconductor alternating layer by electroplating; the VCSEL negative electrode 63 is formed on the upper surface of the VCSEL body 61, that is, on the upper surface 602 of the body by electroplating; the diode positive electrode 92 is formed on the P-type doped semiconductor layer by electroplating; and the diode negative electrode 93 is formed on the upper surface of the diode body 91 by electroplating.

[0104] In the embodiment of the present application, another method for manufacturing a VCSEL integrated wafer is proposed, such as Figures 15 to 17 As shown, it includes: S310, forming at least one VCSEL body 61 by an epitaxial growth process, wherein the VCSEL body 61 includes: a substrate layer 611, a first reflective layer 612, an active region 613, a limiting layer 614 having a limiting hole 601, and a second reflective layer 615; S320, growing a first type doped semiconductor layer 911, an inner depletion layer 912, a second type doped semiconductor layer 913, and an anti-reflection layer 914 on the substrate layer 611 to form a diode body 91; S330, forming a VCSEL positive electrode 62 and a VCSEL negative electrode 63 connected to the VCSEL body 61, and forming a diode positive electrode 92 and a diode negative electrode 93 connected to the diode body 91; and, S340, forming a thermoelectric cooling structure 30 on the VCSEL body 61 and / or on the diode body 91.

[0105] In step S310, at least one VCSEL body 61 is formed by an epitaxial growth process. Specifically, the specific implementation of forming the VCSEL body 61 is not limited by the present application. In a specific example of the present application, first, a substrate layer 611 is provided, and then, a first doped semiconductor alternating layer, an active region forming layer, and a second doped semiconductor alternating layer stacked on the substrate layer 611 are grown on the substrate layer 611 by an epitaxial growth process to form an epitaxial body structure, wherein the epitaxial body structure includes a first doped semiconductor alternating layer, an active region forming layer, and a second doped semiconductor alternating layer stacked on the substrate layer 611. The first doped semiconductor alternating layer, the active region forming layer, and the second doped semiconductor alternating layer are arranged from bottom to top. The first doped semiconductor alternating layer is implemented as an N-type semiconductor alternating layer, and the second doped semiconductor alternating layer is implemented as a P-type semiconductor alternating layer, or the first doped semiconductor alternating layer is implemented as a P-type semiconductor alternating layer, and the second doped semiconductor alternating layer is implemented as an N-type semiconductor alternating layer. Next, a VCSEL chip formation region is defined, and the portion of the epitaxial body outside the VCSEL chip formation region is removed by an etching process, so that the epitaxial body structure is divided into a plurality of unit structures for forming the VCSEL chip 10. Specifically, each layer structure of the epitaxial body structure (i.e., the N-type semiconductor alternating layer, the active region forming layer, and the P-type semiconductor alternating layer) is respectively divided into a plurality of sub-unit regions. Each unit structure includes: at least one first doped semiconductor alternating layer sub-unit region, at least one active region forming layer sub-unit region, and at least one second doped semiconductor alternating layer sub-unit region. The unit structure is oxidized so that the part of the alternating layers of each first doped semiconductor alternating layer sub-unit area and / or the part of the alternating layers of the second doped semiconductor alternating layer sub-unit area in the unit structure near the outer edge of the unit structure is oxidized to form a confining area, and the part near the center of the unit structure is not oxidized to form a confining hole 601 in the confining area, so that the part of the alternating layers of the first doped semiconductor alternating layer sub-unit area and / or the part of the alternating layers of the second doped semiconductor alternating layer sub-unit area in the unit structure forms a confining layer 614 with a confining hole 601. The confining layer 614 can also be formed by other methods, for example, by an ion implantation process. In this way, each oxidized unit structure and the substrate layer 611 form a VCSEL body 61, wherein the part of the first doped semiconductor alternating layer sub-unit area where the confining layer is not formed forms the first reflective layer 612, the part of the second doped semiconductor alternating layer sub-unit area where the confining layer is not formed forms the second reflective layer 615, and the active region forming layer sub-unit area forms the active region of the VCSEL body 61.In the embodiment of the present application, the substrate layer 611 may be thinned.

[0106] In step S320, a first-type doped semiconductor layer 911, an inner depletion layer 912, a second-type doped semiconductor layer 913 and an anti-reflection layer 914 are grown on the substrate layer 611 to form a diode body 91. Specifically, a photodiode formation region is defined, and the photodiode formation region is spaced apart from the VCSEL chip formation region. A first-type doped semiconductor layer 911, an inner depletion layer 912, a second-type doped semiconductor layer 913 and an anti-reflection layer 914 are formed in the photodiode formation region on the substrate layer 611 by an epitaxial growth process and are stacked on the substrate layer 611 to form a diode body 91. When the first doped-type semiconductor alternating layer is implemented as an N-type semiconductor alternating layer and the second doped-type semiconductor alternating layer is implemented as a P-type semiconductor alternating layer, the first-type doped semiconductor layer 911 is an N-type doped semiconductor layer and the second-type doped semiconductor layer 913 is a P-type doped semiconductor layer. When the first doped semiconductor alternating layer is implemented as a P-type semiconductor alternating layer and the second doped semiconductor alternating layer is implemented as an N-type semiconductor alternating layer, the first doped semiconductor layer 911 is a P-type doped semiconductor layer and the second doped semiconductor layer 913 is an N-type doped semiconductor layer.

[0107] In step S330, a VCSEL positive electrode 62 and a VCSEL negative electrode 63 connected to the VCSEL body 61 are formed, and a diode positive electrode 92 and a diode negative electrode 93 connected to the diode body 91 are formed. Specifically, the formation method and formation position of the VCSEL positive electrode 62 and the VCSEL negative electrode 63, and the diode positive electrode 92 and the diode negative electrode 93 are not limited by the present application. In one embodiment of the present application, when the N-type semiconductor alternating layers, the active region forming layer and the P-type semiconductor alternating layers are arranged from bottom to top, the VCSEL positive electrode 62 is formed on the upper surface of the VCSEL body 61, that is, on the upper surface 602 of the body, by electroplating, and the VCSEL negative electrode 63 is formed on the upper surface of the VCSEL substrate layer 611 by electroplating; the diode positive electrode 92 is formed on the upper surface of the diode body 91 by electroplating; and the diode negative electrode 93 is formed on the upper surface of the VCSEL substrate layer 611 by electroplating.

[0108] When the P-type semiconductor alternating layer, the active area forming layer and the N-type semiconductor alternating layer are arranged from bottom to top, the VCSEL positive electrode 62 is formed on the upper surface of the VCSEL substrate layer 611 by electroplating; the VCSEL negative electrode 63 is formed on the upper surface of the VCSEL body 61, that is, the body upper surface 602 by electroplating; the diode positive electrode 92 is formed on the upper surface of the VCSEL substrate layer 611 by electroplating; and the diode negative electrode 93 is formed on the upper surface of the diode body 91 by electroplating.

[0109] In step S340, a thermoelectric cooling structure 30 is formed on the VCSEL body 61 and / or on the diode body 91. Specifically, when the N-type semiconductor alternating layer, the active region forming layer and the P-type semiconductor alternating layer are arranged from bottom to top, the VCSEL positive electrode 62 is formed on the upper surface of the VCSEL body 61, and the diode positive electrode 92 is formed on the upper surface of the diode body 91, first, an insulating layer 37 is formed on the upper surface of the VCSEL positive electrode 62 and / or the diode positive electrode 92. Then, an electrical connection layer, a thermoelectric positive electrode 32 and a thermoelectric negative electrode 33 are formed on the insulating layer 37, and the electrical connection layer includes a plurality of electrical connection lines spaced apart from each other. Next, a plurality of thermocouple pairs 31 may be grown above the electrical connection line by a semiconductor growth process, each of the thermocouple pairs 31 including a P-type structure 311 and an N-type structure 312, the P-type structure 311 and the N-type structure 312 of a thermocouple pair 31 are formed on one of the electrical connection lines; an N-type structure 312 is formed on the thermoelectric positive electrode 32, and a P-type structure 311 is formed on the thermoelectric negative electrode 33. Subsequently, another electrical connection layer including a plurality of electrical connection lines spaced apart from each other may be formed above the thermocouple pairs 31, each of the electrical connection lines above the thermocouple pairs 31 is formed between a P-type structure 311 of a thermocouple pair 31 and an N-type structure 312 of the thermocouple pair 31 adjacent thereto.

[0110] In summary, the VCSEL integrated wafer and its manufacturing method based on the embodiments of the present application are explained. In the VCSEL integrated wafer, the thermoelectric cooling structure is integrated into the VCSEL chip and / or the photodiode chip at the wafer level, which can improve the combination stability of the thermoelectric cooling structure and the VCSEL chip and / or the photodiode chip.

[0111] The basic principles of the present application are described above in conjunction with specific embodiments. However, it should be noted that the advantages, strengths, effects, etc. mentioned in the present application are only examples and not limitations, and it cannot be considered that these advantages, strengths, effects, etc. are required by each embodiment of the present application. In addition, the specific details disclosed above are only for the purpose of illustration and ease of understanding, not for limitation, and the above details do not limit the present application to being implemented by adopting the above specific details.

Claims

1. A VCSEL integrated wafer, It is characterized in that include: At least one VCSEL chip, each VCSEL chip comprising at least one VCSEL light emitting point; at least one photodiode chip spaced apart from the VCSEL chip, the VCSEL chip and the photodiode chip sharing a substrate layer; and A thermoelectric cooling structure is integrated into the VCSEL chip at the wafer level, wherein the thermoelectric cooling structure includes a plurality of thermocouple pairs, and each thermocouple pair includes a P-type structure and an N-type structure electrically connected to each other.

2. The VCSEL integrated wafer according to claim 1, in, Each of the VCSEL light-emitting points includes a VCSEL body, and a VCSEL positive electrode and a VCSEL negative electrode electrically connected to the VCSEL body. Each of the VCSEL bodies includes the substrate layer, a first reflective layer, an active region, a limiting layer with limiting holes, and a second reflective layer. Each of the photodiode chips includes at least one photodiode. Each of the photodiodes includes a diode body, a diode positive electrode and a diode negative electrode electrically connected to the diode body. Each of the diode bodies includes the substrate layer, a first type doped semiconductor layer, an internal depletion layer, a second type doped semiconductor layer, and an anti-reflection layer.

3. The VCSEL integrated wafer according to claim 2, in, The thermoelectric cooling structure is arranged on the backlight side of the active area of ​​the VCSEL chip.

4. The VCSEL integrated wafer according to claim 3, in, The substrate layer, the first reflective layer, the active area and the second reflective layer of the VCSEL light-emitting point are arranged in sequence from bottom to top, the limiting layer is located on the upper side of the active area and / or the lower side of the active area, the substrate layer, the first type doped semiconductor layer, the internal depletion layer, the second type doped semiconductor layer and the anti-reflective layer of the photodiode chip are arranged in sequence from bottom to top, the light emitting direction of the VCSEL light-emitting point is from the active area to the second reflective layer, and the thermoelectric cooling structure is located below the first reflective layer.

5. The VCSEL integrated wafer according to claim 4, in, The thermoelectric cooling structure is formed below the substrate layer.

6. The VCSEL integrated wafer according to claim 4, in, The thermoelectric cooling structure is formed between the first reflective layer and the substrate layer.

7. The VCSEL integrated wafer according to claim 3, in, The first reflective layer is an N-DBR layer, the second reflective layer is a P-DBR layer, the first type doped semiconductor layer is an N type doped semiconductor layer, and the second type doped semiconductor layer is a P type doped semiconductor layer.

8. The VCSEL integrated wafer according to claim 3, in, The first reflective layer is a P-DBR layer, the second reflective layer is an N-DBR layer, the first type doped semiconductor layer is a P type doped semiconductor layer, and the second type doped semiconductor layer is an N type doped semiconductor layer.

9. The VCSEL integrated wafer according to claim 3, in, The thermoelectric cooling structure also includes a thermoelectric positive electrode electrically connected to one of the thermocouple pairs and a thermoelectric negative electrode electrically connected to the other thermocouple, and the thermoelectric positive electrode and the thermoelectric negative electrode are configured to control the hot end of the thermoelectric cooling structure to be formed at the bottom of the thermoelectric cooling structure.

10. The VCSEL integrated wafer according to claim 3, in, The substrate layer, the first reflective layer, the active area and the second reflective layer of the VCSEL light-emitting point are arranged in sequence from bottom to top, the limiting layer is located on the upper side of the active area and / or the lower side of the active area, the substrate layer, the first type doped semiconductor layer, the internal depletion layer, the second type doped semiconductor layer and the anti-reflective layer of the photodiode chip are arranged in sequence from bottom to top, the light emitting direction of the VCSEL light-emitting point is from the active area to the first reflective layer, and the thermoelectric cooling structure is located above the second reflective layer.

11. The VCSEL integrated wafer according to claim 10, in, The first reflective layer is an N-DBR layer, the second reflective layer is a P-DBR layer, the first type doped semiconductor layer is an N type doped semiconductor layer, and the second type doped semiconductor layer is a P type doped semiconductor layer.

12. The VCSEL integrated wafer according to claim 10, in, The first reflective layer is a P-DBR layer, the second reflective layer is an N-DBR layer, the first type doped semiconductor layer is a P type doped semiconductor layer, and the second type doped semiconductor layer is an N type doped semiconductor layer.

13. The VCSEL integrated wafer according to claim 10, in, The thermoelectric cooling structure also includes a thermoelectric positive electrode electrically connected to one of the thermocouple pairs and a thermoelectric negative electrode electrically connected to the other thermocouple, and the thermoelectric positive electrode and the thermoelectric negative electrode are configured to control the hot end of the thermoelectric cooling structure to be formed on the top of the thermoelectric cooling structure.

14. A method for manufacturing a VCSEL integrated wafer, It is characterized in that include: Forming at least one VCSEL body by an epitaxial growth process, wherein the VCSEL body comprises: a substrate layer, a first reflective layer, an active region, a restriction layer having a restriction hole, and a second reflective layer; growing a first-type doped semiconductor layer, an inner depletion layer, a second-type doped semiconductor layer and an anti-reflection layer on the substrate layer to form a diode body; forming a VCSEL positive electrode and a VCSEL negative electrode connected to the VCSEL body, and forming a diode positive electrode and a diode negative electrode connected to the diode body; and A thermoelectric cooling structure is formed below the substrate layer.

15. A method for manufacturing a VCSEL integrated wafer, It is characterized in that include: providing a substrate layer; forming a thermoelectric cooling structure above the substrate layer; forming a first reflective layer, an active area, a confinement layer having confinement holes, and a second reflective layer above the thermoelectric cooling structure to form an integrated unit of the thermoelectric cooling structure and the VCSEL body; Growing a first-type doped semiconductor layer, an inner depletion layer, a second-type doped semiconductor layer and an anti-reflection layer above the thermoelectric cooling structure to form a diode body; as well as A VCSEL positive electrode and a VCSEL negative electrode connected to the VCSEL body are formed, and a diode positive electrode and a diode negative electrode connected to the diode body are formed.

16. A method for manufacturing a VCSEL integrated wafer, It is characterized in that include: Forming at least one VCSEL body by an epitaxial growth process, wherein the VCSEL body comprises: a substrate layer, a first reflective layer, an active region, a restriction layer having a restriction hole, and a second reflective layer; growing a first-type doped semiconductor layer, an inner depletion layer, a second-type doped semiconductor layer and an anti-reflection layer on the substrate layer to form a diode body; forming a VCSEL positive electrode and a VCSEL negative electrode electrically connected to the VCSEL body, and forming a diode positive electrode and a diode negative electrode electrically connected to the diode body; and A thermoelectric cooling structure is formed above the VCSEL body and / or above the diode body.

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