Circuit and method for electrostatic discharge protection

Abstract

The invention provides an electrostatic discharge protection circuit and method. A circuit includes a substrate, a target device on the substrate, and an electrostatic discharge (ESD) device electrically coupled to the target device. An ESD device includes an ESD detection circuit electrically coupled to a first reference voltage supply and a second reference voltage supply, an inverter circuit electrically coupled to the ESD detection circuit and configured to be triggered in response to an ESD event on the first or second reference voltage supply, a rectifier circuit electrically coupled to the inverter circuit and configured to rectify a current discharged from the inverter circuit, and a transistor electrically coupled to the rectifier circuit and configured to discharge a residual current passed through the rectifier circuit.

Description

Technical Field

[0001] An embodiment of the present disclosure relates to an electrostatic discharge protection circuit and method, and more particularly to an electrostatic discharge protection circuit and method using a rectifier circuit. Background Art

[0002] Gallium nitride (GaN) is becoming a favorable material for integrated circuit (IC) manufacturing. However, GaN substrates can limit the fabrication of n-type semiconductor devices thereon. As a result, electrostatic discharge (ESD) events in GaN structures can be difficult to mitigate. Summary of the invention

[0003] In some embodiments, a circuit for electrostatic discharge protection is provided. The circuit includes a substrate, a target device on the substrate, and an electrostatic discharge device electrically coupled to the target device. The electrostatic discharge device includes an electrostatic discharge detection circuit electrically coupled to a first reference voltage supply and a second reference voltage supply, an inverter circuit electrically coupled to the electrostatic discharge detection circuit and triggered in response to an electrostatic discharge event on the first reference voltage supply or the second reference voltage supply, a rectifier circuit electrically coupled to the inverter circuit and used to rectify a current discharged from the inverter circuit, and a transistor electrically coupled to the rectifier circuit and used to discharge a residual current transmitted through the rectifier circuit.

[0004] In some embodiments, a circuit for electrostatic discharge protection is provided. The circuit includes a gallium nitride substrate, a target device, and an electrostatic discharge device electrically coupled to the target device. The electrostatic discharge device includes: an electrostatic discharge detection circuit electrically coupled to a first reference voltage supply and a second reference voltage supply; a gallium nitride inverter circuit including an enhancement mode transistor device and a resistor element, wherein the gallium nitride inverter circuit is electrically coupled to the electrostatic discharge detection circuit, and wherein the gallium nitride inverter circuit is used to be triggered in response to an electrostatic discharge event on the first reference voltage supply or the second reference voltage supply; a rectifier circuit electrically coupled to the gallium nitride inverter circuit and used to rectify a current discharged from the gallium nitride inverter circuit; and a field effect transistor electrically coupled to the rectifier circuit and used to discharge a residual current transmitted through the rectifier circuit.

[0005] In some embodiments, a method for electrostatic discharge protection is provided, comprising the following steps: detecting an electrostatic discharge current on a reference voltage supply; transmitting the electrostatic discharge current to a rectifier circuit; enabling a transistor based on the electrostatic discharge current flowing through the rectifier circuit; and discharging the electrostatic discharge current from a first reference voltage supply to a second reference voltage supply through the transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The embodiments of the present disclosure are described in detail in conjunction with the accompanying Figure 1 It is best understood from the following detailed description when read together.

[0007] Figure 1 , Figure 2 , Figure 3A ,and Figure 3B is a circuit diagram of an electrostatic discharge clamp according to some embodiments;

[0008] Figure 4 is a flow chart of a method for mitigating ESD events in a GaN structure according to some embodiments;

[0009] Figure 5 is a group of voltage curves associated with ESD events over time according to some embodiments.

[0010] Illustrative embodiments will now be described with reference to the accompanying drawings.In the drawings, like reference numbers generally indicate identical, functionally similar, and / or structurally similar elements.

[0011]

Explanation of symbols

[0012] 100:ESD device

[0013] 110:ESD detection circuit

[0014] 115: Inverter circuit

[0015] 120: Resistor

[0016] 130: Capacitor

[0017] 140:Resistor

[0018] 150: Enhancement mode transistor device

[0019] 160: Field Effect Transistor

[0020] 170: Rectifier circuit

[0021] 171: First series rectifier circuit

[0022] 172: Second series rectifier circuit

[0023] 180: Target device

[0024] 200:ESD device

[0025] 300:ESD current spike

[0026] 310: Current path

[0027] 320:Diode

[0028] 330: Current path

[0029] 350:ESD current spike

[0030] 360: Current Path

[0031] 370: Current path

[0032] 400:Method

[0033] 410~440: Operation DETAILED DESCRIPTION

[0034] The following disclosure provides many different embodiments, or examples, for implementing the different features of the provided subject matter. Specific examples of components and configurations are described below to simplify an embodiment of the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first feature is formed in direct contact with the second feature, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition itself does not specify the relationship between the various embodiments and / or configurations discussed.

[0035] The terms used in this specification generally have their ordinary meaning in the art and in the specific context in which each term is used. The use of examples in this specification, including the use of examples of any term discussed herein, is illustrative only and in no way limits the scope and meaning of the disclosure or any exemplified term. Likewise, the disclosure is not limited to the various embodiments given in this specification.

[0036] In some embodiments, the terms "about" and "substantially" may indicate a value of a given amount that varies within 5% of that value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of that value). These values ​​are examples only and are not intended to be limiting. The terms "about" and "substantially" may refer to percentages of values ​​as interpreted by one skilled in the art based on the teachings herein.

[0037] Embodiments described herein relate to an electrostatic discharge (ESD) clamp for an integrated circuit (IC) disposed on a gallium nitride (GaN) substrate. In some embodiments, the IC includes a substrate, a target device on the substrate, and an ESD device electrically coupled to the target device. According to some embodiments, the ESD device is used to mitigate ESD events that may damage the target device that occur in the structure.

[0038] The ESD device may be incorporated into the IC or may be externally connected to the IC. For example, the ESD device may be included in the IC chip design. In some embodiments, the ESD device is an independent circuit. The independent ESD device may be interchangeable so that the ESD device can be changed after any ESD event that may damage the ESD device. For example, the ESD device may be packaged as an external plug-in device similar to a fuse. The ESD device may be used to attach to an external port of a device and / or system that is susceptible to damage by an ESD event. Similarly, the ESD device may be used to attach to a circuit board (e.g., a breadboard, a printed circuit board (PCB), a motherboard, or the like).

[0039] In some embodiments, components of an ESD device (e.g., transistors, diodes, resistors, capacitors, and the like) may be replaced when damaged by an ESD event. The ESD device may be a modular device with removably attached components that may be replaced if damaged by an ESD event. For example, if a resistor is damaged during an ESD event, the resistor may be replaced by simply removing the damaged resistor and installing a working resistor.

[0040] In some embodiments, the ESD device may include an ESD detection circuit. According to some embodiments, the ESD detection circuit may be electrically coupled to a first reference voltage supply and a second reference voltage supply. The ESD detection circuit may include at least one resistive element and at least one capacitive element. In some embodiments, the resistive element (e.g., a resistor) is electrically coupled to a first reference voltage supply (e.g., a power supply rail, also referred to herein as "VDD"). The capacitive element (e.g., a capacitor) may be coupled to a second reference voltage supply (e.g., ground, also referred to herein as "VSS"). The resistor and the capacitor may be electrically coupled to each other. An ESD event occurring on the first reference voltage supply (e.g., VDD) may cause excess current to flow into the circuit. For example, a spike occurring on the first reference voltage supply (e.g., VDD) will enter the circuit as a voltage increase, which may raise the gate voltage of an enhancement transistor device (including a portion of an inverter in the circuit) and turn on the enhancement transistor device. Similarly, an event of ESD occurring on the second reference voltage supply (e.g., VSS) may send a voltage spike into the capacitor, thereby inducing dielectric breakdown.

[0041] In some embodiments, an ESD detection circuit (e.g., a resistor electrically coupled to a first reference voltage supply, a capacitor electrically coupled to a second reference voltage supply, wherein the resistor and the capacitor are also electrically coupled to each other) is connected to an inverter circuit. In some embodiments, the inverter circuit includes a resistive element and a transistor device electrically coupled to each other. The resistive element may be a depletion-mode transistor device or a resistor. The resistive element is electrically coupled to a first reference voltage supply (e.g., VDD). The transistor device may be an enhancement-mode transistor device and is electrically coupled to a second reference voltage supply (e.g., VSS).

[0042] During an ESD event, the inverter circuit is electrically triggered. For example, an enhancement mode transistor device may be disabled during an ESD event. On the other hand, a resistor element may be enabled during an ESD event (e.g., to allow a portion of excess current from the ESD event to pass through the resistor element). In some embodiments, the resistor element may be enabled in response to an ESD event on a first reference voltage supply (e.g., VDD). Conversely, an enhancement mode transistor device may be disabled in response to an ESD event on a second reference voltage supply (e.g., VSS).

[0043] In some embodiments, the rectifier circuit may be electrically coupled to the inverter circuit. The rectifier circuit may include at least one diode or multiple diodes connected in series to form a series rectifier circuit. The rectifier circuit may also include multiple series rectifier circuits. The first series rectifier circuit (from the multiple series rectifier circuits) can be electrically coupled to a first reference voltage supply (e.g., VDD) in a reverse bias configuration. For example, as shown below, when excess current passes through each reverse biased diode in the series diode, the reverse bias configuration relative to the first reference voltage supply (e.g., VDD) can provide a step-by-step rectification of at least a portion of the excess current from the ESD event. Similarly, the second series rectifier circuit (from the multiple series rectifier circuits) can be electrically coupled to a second reference voltage supply (e.g., VSS) in a reverse bias configuration. The second series rectifier circuit can rectify at least a portion of the excess current from the ESD event occurring on the second reference voltage supply (e.g., VSS). The first series rectifier circuit and the second series rectifier circuit can be electrically coupled to each other. In some embodiments, the inverter circuit is electrically coupled to the first series rectifier and the second series rectifier in a forward biased configuration.

[0044] In some embodiments, the field effect transistor may be electrically coupled to the rectifier circuit. The field effect transistor may also be electrically coupled to the target device. The field effect transistor may be further electrically coupled to a first reference voltage supply (e.g., VDD) and a second reference voltage supply (e.g., VSS). The field effect transistor may be used to discharge residual current from an ESD event occurring on the first reference voltage supply (e.g., VDD) or the second reference voltage supply (e.g., VSS) when passing through the rectifier circuit.

[0045] In some embodiments, the rectifier circuit protects the field effect transistor from being exposed to higher currents. As a result, the ESD device with the rectifier circuit provides a higher level of protection for the target device than an ESD device lacking the rectifier circuit.

[0046] Figure 1 is a diagram of an ESD device 100 disposed on a GaN substrate (not shown) according to some embodiments. Figure 1 As shown in , the ESD device 100 includes an ESD detection circuit 110, which includes a resistor 120 and a capacitor 130. The resistor 120 and the capacitor 130 are electrically coupled to each other, wherein the resistor 120 is electrically coupled to a first reference voltage supply (e.g., VDD) and the capacitor is electrically coupled to a second reference voltage supply (e.g., VSS). The ESD device 100 includes an inverter circuit 115, which includes a resistor element 140 (e.g., a depletion mode device 140) electrically coupled to a transistor device 150 (e.g., an enhancement mode transistor device 150). According to some embodiments, the inverter circuit 115 may be a GaN inverter circuit. The ESD device 100 includes a field effect transistor 160. In some embodiments, the ESD device 100 includes a rectifier circuit 170. In some embodiments, the ESD detection circuit 110, the inverter circuit 115, the field effect transistor 160, and the rectifier circuit 170 are used to protect a target device 180.

[0047] In some embodiments, the substrate may be a bulk semiconductor wafer or a semiconductor on insulator (SOI) wafer, such as, for example, GaN on insulator. In addition, the substrate may be made of an n-type semiconductor such as GaN. In other embodiments, any n-type semiconductor substrate may be used, including (i) germanium (Ge); (ii) a compound semiconductor including gallium arsenide (GaAs), gallium phosphide (GaP); (iii) an alloy semiconductor including gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP); or (iv) or a combination thereof. In some embodiments, the ESD device 100 described herein may be disposed on other types of semiconductor substrates, such as a p-type semiconductor substrate.

[0048] In some embodiments, the ESD device 100 can be incorporated into complementary metal-oxide-silicon (CMOS) architectures and processing lines. Additionally, the GaN substrate can be integrated into a CMOS production environment. Although the present description refers to n-type devices, the materials and systems described herein can be subjected to process steps and equipment used in other types of manufacturing processes, such as silicon (Si)-based manufacturing processes.

[0049] The target device 180 may be any device or system susceptible to damage from an ESD event. The target device 180 may include any semiconductor device, such as discrete components (e.g., resistors) and electronic systems. For example, the target device 180 may be a fin-FET circuit, a gate-all-around (GAA) FET circuit, or any other type of circuit. The target device 180 may be any type of electronic system, such as a transmitter, a receiver, a transceiver, a graphics board, a motherboard, a processor, a memory device, a signal processor, an amplifier, or a sensor.

[0050] refer to Figure 1, the ESD detection circuit 110 is configured to be triggered at the beginning of an ESD event. For example, during an ESD event on a second reference voltage supply (e.g., VSS), the capacitor 130 in the ESD detection circuit 110 may be discharged (e.g., a short circuit caused by an input current that raises the potential on the capacitor plate (e.g., the bottom plate of the capacitor) closest to the second reference voltage (e.g., VSS)). According to some embodiments, the capacitor 130 may have a capacitance ranging from about 1 pF to about 1 nF (e.g., 1 pF, 10 pF, 100 pF, or 1 nF). Other capacitance ranges / values ​​are within the scope of an embodiment of the present disclosure. In addition, the resistor 140 in the ESD detection circuit 110 may have a resistance ranging from about 1 kΩ to about 10 kΩ (e.g., about 1 kΩ to about 9 kΩ, about 2 kΩ to about 10 kΩ, about 3 kΩ to about 7 kΩ, or about 1 kΩ to about 5 kΩ). For example, according to some embodiments, the ESD detection circuit 110 may have a resistance of about 1 kΩ, about 2 kΩ, about 3 kΩ, about 4 kΩ, about 5 kΩ, about 6 kΩ, about 7 kΩ, about 8 kΩ, about 9 kΩ, or about 10 kΩ.

[0051] During an ESD event on a first reference voltage supply (e.g., VDD), resistor 120 will pass current from the ESD event on the first reference voltage supply (e.g., VDD). For example, resistor 120 may exhibit a voltage increase or a voltage decrease depending on the source of the ESD event. For example, resistor 120 may exhibit a voltage increase thereon when an ESD event occurs on the first reference voltage supply (e.g., VDD), and may exhibit a voltage decrease thereon when an ESD event occurs on the second reference voltage supply (e.g., VSS). In some embodiments, resistor 120 is electrically coupled to capacitor 130 to cooperate in detecting an ESD event.

[0052] According to some embodiments, the response time of the ESD detection circuit 110 may be up to about 10 nanoseconds (ns). As clock rates in microchip technology increase, reduced response times are necessary to protect the target device 180. Therefore, response times up to about 10 ns or less are important. In some embodiments, the response time may be about 1 ns, 2 ns, 3 ns, 4 ns, 5 ns, 6 ns, 7 ns, 8 ns, 9 ns, or 10 ns. Other response times are within the scope of an embodiment of the present disclosure. The response time may be based on an RC delay set by the resistor 120 and the capacitor 130.

[0053] The inverter circuit 115 can be electrically coupled to the ESD detection circuit 110. For example, the resistor element 140 (e.g., the depletion mode device 140) and the transistor device 150 (e.g., the enhancement mode transistor device 150) can both be electrically coupled to the ESD detection circuit 110 at a common circuit node, such as Figure 1 In addition, the resistor element 140 (eg, depletion mode device 140) can be electrically coupled to a first reference voltage supply (eg, VDD). The transistor device 150 (eg, enhancement mode transistor device 150) can be electrically coupled to a second reference voltage supply (eg, VSS).

[0054] According to some embodiments, the resistive element 140 (e.g., depletion-mode device 140) is triggered during an ESD event on a first reference voltage supply (e.g., VDD). The depletion-mode device 140 remains in an on state until an ESD event occurs. In some embodiments, when an excess current flows through the resistor 120 (e.g., an ESD event), the depletion-mode device 140 may be disabled (e.g., turned off). The excess current may be manifested as a voltage rise across the resistor. A voltage rise ranging in magnitude from about 0.5V to about 3V (e.g., about 1V to about 3V, about 0.5V to about 2.5V, or about 1V to about 2.5V) may trigger the deactivation of the depletion-mode device. Other voltage ranges / values ​​are within the scope of an embodiment of the present disclosure. For example, the depletion-mode device 140 may be triggered at a voltage of 0.5V, 1V, 1.5V, 2V, 2.5V, or 3V.

[0055] According to some embodiments, transistor device 150 (e.g., enhancement mode transistor device 150) may be triggered during an ESD event on a second reference voltage supply (e.g., VSS). According to some embodiments, enhancement mode transistor device 150 is enabled (e.g., turned on) when the voltage discharged from capacitor 130 is in a range of about 1V to about 3V (e.g., about 1V to about 2V, or about 2V to about 3V). Other enabling voltage ranges / values ​​are within the scope of an embodiment of the present disclosure. Enhancement mode transistor device 150 may be enabled when the voltage on resistor 120 is 1V, 1.1V, 1.2V, 1.3V, 1.4V, 1.5V, 1.6V, 1.7V, 1.8V, 1.9V, 2V, 2.1V, 2.2V, 2.3V, 2.4V, 2.5V, 2.6V, 2.7V, 2.8V, 2.9V, or 3V. When the voltage across the resistor (eg, the source voltage resulting from an ESD event) is greater than the threshold voltage of the transistor gate, the gate voltage across the enhancement mode transistor device 150 may increase.

[0056] In some embodiments, the resistor element 140 (e.g., depletion mode device 140) and the transistor device 150 (e.g., enhancement mode transistor device 150) are n-type devices and are therefore suitable for use in GaN technology. In addition, the inclusion of both the resistor element 140 (e.g., depletion mode device 140) and the transistor device 150 (e.g., enhancement mode transistor device 150) prevents ESD events from occurring on the first reference voltage supply (e.g., VDD) or the second reference voltage supply (e.g., VSS).

[0057] In some embodiments, the rectifier circuit 170 is electrically coupled to the ESD detection circuit 110 and the inverter circuit 115. The rectifier circuit 170 is also connected to a first reference voltage supply (e.g., VDD) and a second reference voltage supply (e.g., VSS). The rectifier circuit 170 may include a first series rectifier circuit 171 electrically coupled to the first reference voltage supply (e.g., VDD) and a second series rectifier circuit 172 electrically coupled to the second reference voltage supply (e.g., VSS). The first series rectifier circuit 171 is configured in a reverse bias configuration relative to the first reference voltage supply (e.g., VDD). The second series rectifier circuit 172 is configured in a reverse bias configuration relative to the second reference voltage supply (e.g., VSS). The rectifier circuit 170 is enabled when the resistor element 140 (e.g., the depletion mode device 140) is disabled or the transistor device 150 (e.g., the enhancement mode transistor device 150) is enabled. The rectifier circuit 170 includes at least one diode and may include any number of diodes depending on the magnitude of the expected ESD event. Therefore, the number of diodes in the series diodes is proportional to the magnitude of the rectification of the ESD event. For example, when each diode in the first series rectifier circuit 171 or the second series rectifier circuit 172 is rated at approximately 1.5V, four diodes in the series rectifier circuit may suppress an ESD event of approximately 6V.

[0058] In some embodiments, the field effect transistor 160 can be used to have a maximum gate breakdown voltage ranging from about 10V to about 15V (e.g., about 10V to about 14V, about 11V to about 15V, or about 11V to about 14V). Other voltage ranges / values ​​are within the scope of an embodiment of the present disclosure. For example, the maximum gate breakdown voltage can be about 10V, about 11V, about 12V, about 13V, about 14V, or about 15V. In some embodiments, the field effect transistor 160 can be turned on with a gate voltage of about 6V. The field effect transistor 160 can be turned on at a voltage less than the gate breakdown voltage (e.g., from about 6V to about 10V), thereby allowing the rise time on the gate of the field effect transistor 160 to be reduced. The 6V breakdown enables the ESD device 100 to have a shorter response time, thereby having a faster ESD protection time. For example, the response time depends on the rise time of the gate of the field effect transistor 160, which can be less than or equal to 10 nanoseconds (ns). For example, the rise time of the gate of field effect transistor 160 may be up to about 10ns, up to about 9ns, up to about 8ns, up to about 7ns, up to about 6ns, up to about 5ns, up to about 4ns, up to about 3ns, up to about 2ns, or up to about 1ns. ESD device 100 may be less than or equal to 10ns to mitigate ESD events.

[0059] In addition, the ESD device 100 described herein provides a more robust circuit over different operating voltages in GaN substrate technology. To increase the breakdown voltage, in the inverter circuit 115, the resistor element 140 (e.g., depletion mode device 140) and / or the transistor device (e.g., enhancement mode transistor device 150) can be adjusted by modifying the drift region across the source and drain of these devices. Modifications to the mobility of holes and / or electrons in the drift region across the source and drain of the transistor device include doping the drift region and / or changing the length scale of the drift region during manufacturing. For example, a 650V GaN high electron mobility transistor (HEMT) power switch with modified gate and source connections for a high voltage rectifier can sustain up to 900V. Modifications to the drift region across the source and drain of the depletion mode device 140 and / or the enhancement mode device 150 can reduce the risk of device and diode damage and provide operation at a variety of voltages. Thus, by incorporating an ultra-high voltage enhancement mode transistor device, an ultra-high voltage depletion mode device, and an ultra-high voltage series rectifier, the ESD device 100 may be configured to withstand ultra-high voltage applications.

[0060] Figure 2 is a diagram of an ESD device 200 according to some embodiments. Figure 1The resistive element 140 (e.g., depletion mode device 140) is replaced with resistor 210, which can reduce the overall size of ESD device 200 without affecting ESD protection. In some embodiments, resistor 210 can have a resistance of at least about 10 mΩ (e.g., from about 10 mΩ to about 100 mΩ, from about 20 mΩ to about 100 mΩ, from about 10 mΩ to about 90 mΩ, from about 20 mΩ to about 80 mΩ, or from about 10 mΩ to about 70 mΩ). Other resistance ranges / values ​​are within the scope of an embodiment of the present disclosure. The resistance of resistor 210 may be at least 10 mΩ, at least 15 mΩ, at least 20 mΩ, at least 25 mΩ, at least 30 mΩ, at least 35 mΩ, at least 40 mΩ, at least 45 mΩ, at least 50 mΩ, at least 55 mΩ, at least 60 mΩ, at least 65 mΩ, at least 70 mΩ, at least 75 mΩ, at least 80 mΩ, at least 85 mΩ, at least 90 mΩ, at least 95 mΩ, or at least 100 mΩ.

[0061] refer to Figure 3A , Figure 3B and Figure 4 , according to some embodiments, a circuit diagram illustrating a method 400 of protecting a target device 180 and annotations for explaining the method ( Figure 3A and Figure 3B During an ESD event on a first reference voltage supply (eg, VDD), detection circuit 110 detects an increase in voltage across resistor 120. Detection circuit 110 directs excess circuit current to resistive element 140 (eg, depletion mode device 140). Figure 3A In one example shown in , the ESD event may be a static discharge of about 10V from a first reference voltage supply (e.g., VDD), represented by an ESD current spike 300. Resistor 120 exhibits a voltage increase across it. Resistive element 140 (e.g., depletion-mode device 140) is disabled, and excess current from an ESD event occurring on a first reference voltage supply (e.g., VDD) is directed to a first series rectifier circuit 171 along a current path 310. In some embodiments, the first series rectifier circuit 171 includes four diodes 320. In some embodiments, each diode 320 is rated at about 1.5V, so a group of four diodes 320 reduces an ESD event occurring on a first reference voltage supply (e.g., VDD) by about 6V. The remaining excess current is directed to field effect transistor 160 and eliminated via field effect transistor 160 along a current path 330. In this example, the remaining approximately 4V from an ESD event occurring on a first reference voltage supply (e.g., VDD) is directed to the gate of field effect transistor 160. The target device 180 is not exposed to current from an ESD event occurring on the first reference voltage supply (eg, VDD) or any current discharging from the capacitor 130 in the detection circuit 110 .

[0062] During an ESD event on the second reference voltage supply (eg, VSS), the detection circuit 110 exhibits a discharge from the capacitor 130. The detection circuit 110 directs the discharge current to the transistor device 150 (eg, enhancement mode transistor device 150). Figure 3B In one example shown in , the ESD event may be a static discharge of about 10V from a second reference voltage supply (e.g., VSS). When sufficient charge accumulates on the bottom plate of capacitor 130, capacitor 130 exhibits a current discharge. The discharge from capacitor 130 may flow to the gate of enhancement mode transistor device 150. Enhancement mode transistor device 150 is enabled, and excess current from an ESD event occurring on a second reference voltage supply (e.g., VSS) is directed to second series rectifier circuit 172 along current path 360. In some embodiments, second series rectifier circuit 172 includes four diodes 320. In some embodiments, each diode 320 is rated at about 1.5V, so a group of four diodes 320 reduces an ESD event occurring on a second reference voltage supply (e.g., VSS) by about 6V. The remaining excess current is directed to field effect transistor 160 and eliminated via field effect transistor 160 along current path 370. In this example, the remaining approximately 4V from the ESD event on the second reference voltage supply (eg, VSS) is directed to the gate of FET 160. Target device 180 is not exposed to current from the ESD event on the second reference voltage supply (eg, VSS).

[0063] Figure 4 is a flow chart illustrating a method 400 of operating an ESD device after an ESD event according to some embodiments. For ease of description, reference will be made to Figure 1 , Figure 2 , Figure 3A ,and Figure 3B The operations of method 400 are described. The operations of method 400 may be performed in different orders or not performed according to the specific application. In addition, it should be understood that additional operations may be provided before, during, and after method 400, and other operations may only be briefly described herein.

[0064] In operation 410, ESD is detected. For example, an ESD event may enter the ESD device 100 via a first reference voltage supply (e.g., VDD) or a second reference voltage supply (e.g., VSS). According to some embodiments, detecting the ESD event is performed by the detection circuit 110. Detecting the ESD event may be performed by monitoring a voltage drop across the resistor 120, a voltage increase across the resistor 120, or a discharge from the capacitor 130. The detection circuit 110 is used to sense an ESD event from the first reference voltage supply (e.g., VDD) or the second reference voltage supply (e.g., VSS). In some embodiments, an ESD event occurring on the first reference voltage supply (e.g., VDD) may be detected by the detection circuit 110 and transmitted to the inverter circuit 115, in particular the resistor element 140 (e.g., Figure 1 A depletion mode device 140 or Figure 2 In contrast, an ESD event occurring on the second reference voltage supply (eg, VSS) may be detected as a discharge from capacitor 130.

[0065] In operation 420, the ESD current is passed to the rectifier circuit. Regardless of whether the ESD event occurs on a first reference voltage supply (e.g., VDD) or on a second reference voltage supply (e.g., VSS), the current passed through the detection circuit 110 and the inverter circuit 115 will be passed to the rectifier circuit 170. In the event that an ESD event occurs on the first reference voltage supply (e.g., VDD), the excess current from the ESD event passed through the detection circuit 110 and the inverter circuit 115 can be rectified by the rectifier circuit 170. In some embodiments, an ESD event occurring on the first reference voltage supply (e.g., VDD) can be rectified by the first series rectifier circuit 171. Similarly, an ESD event occurring on the second reference voltage supply (e.g., VSS) can be rectified by the second series rectifier circuit 172. Rectification of the ESD event is performed by passing the excess current from the ESD event through at least one diode configured in a reverse bias configuration relative to the source of the excess current within the ESD device 100. In other words, an ESD event occurring on a first reference voltage supply (e.g., VDD) will be rectified by at least one diode in the rectifier circuit 170 configured in a reverse bias configuration relative to the first reference voltage supply (e.g., VDD). Similarly, an ESD event occurring on a second reference voltage supply (e.g., VSS) will be rectified by at least one diode in the rectifier circuit 170 configured in a reverse bias configuration relative to the second reference voltage supply (e.g., VSS). In particular, an ESD event occurring on the first reference voltage supply (e.g., VDD) may be rectified by the first series rectifier circuit 171, and an ESD event occurring on the second reference voltage supply VSS may be rectified by the second series rectifier circuit 172.

[0066] In operation 430 , a transistor (eg, FET 160 ) is enabled based on the ESD current flowing through the rectifier circuit. Rectified current from an ESD event on a first reference voltage supply (eg, VDD) or a second reference voltage supply (eg, VSS) may be passed to FET 160 .

[0067] In operation 440, ESD current flows from one reference voltage supply to another reference voltage supply via a transistor (e.g., field effect transistor 160). Passing a rectified current (e.g., residual current from an ESD event) corresponds to enabling field effect transistor 160. Enabling field effect transistor 160 includes causing ESD current to flow from a first reference voltage supply (e.g., VDD) to a second reference voltage supply (e.g., VSS) via field effect transistor 160 in the event of an ESD event on the first reference voltage supply. Similarly, enabling field effect transistor 160 includes causing ESD current to flow from a second reference voltage supply (e.g., VSS) to a first reference voltage supply (e.g., VDD) via field effect transistor 160 in the event of an ESD event on the second reference voltage supply.

[0068] Figure 5 1 illustrates voltage profiles during an ESD event according to some embodiments. Curve A illustrates a voltage spike (e.g., approximately 2 kV) on a first reference voltage supply (e.g., VDD) where transistor device 150 (e.g., enhancement mode transistor device 150) is enabled and resistor element 140 (e.g., depletion mode device 140) is disabled. ESD detection circuit 110 ( Figure 5 Curve B in FIG. 1 shows that the resistor 120 or the capacitor 130 and the rectifier circuit 170 ( Figure 5 The voltage on the curve C in FIG. 1 increases (eg, about 0.5 V). The rectifier circuit 170 generates a spike voltage, and the voltage of the field effect transistor 160 decreases ( Figure 4 Curve D in FIG. 1 shows the current flowing through the field effect transistor 160.

[0069] The ESD device 100 may be incorporated into the IC, or may be externally connected to the IC. For example, the ESD device 100 may be included in the IC chip design. In some embodiments, the ESD device 100 is an independent circuit. The independent ESD device 100 may be interchangeable, so that the ESD device 100 can be changed after any ESD event that may damage the ESD device 100. For example, the ESD device 100 may be packaged as an external plug-in device similar to a fuse. The ESD device 100 may be used to attach to an external port of a device and / or system that is susceptible to damage by an ESD event. Similarly, the ESD device 100 may be used to attach to a circuit board (e.g., a breadboard, a printed circuit board (PCB), a motherboard, or the like).

[0070] In some embodiments, components of the ESD device 100 (e.g., transistors, diodes, resistors, capacitors, and the like) can be replaced when damaged by an ESD event. The ESD device 100 can be a modular device with removably attached components that can be replaced if damaged by an ESD event. For example, if a resistor is damaged during an ESD event, the resistor can be immediately replaced by simply removing the damaged resistor and installing a working resistor.

[0071] In some embodiments, a circuit is provided. The circuit includes a substrate, a target device on the substrate, and an electrostatic discharge (ESD) device electrically coupled to the target device. The ESD device 100 includes an ESD detection circuit electrically coupled to a first reference voltage supply and a second reference voltage supply, an inverter circuit electrically coupled to the ESD detection circuit and triggered in response to an ESD event on the first or second reference voltage supply, a rectifier circuit electrically coupled to the inverter circuit and used to rectify a current discharged from the inverter circuit, and a transistor electrically coupled to the rectifier circuit and used to discharge a residual current transmitted through the rectifier circuit.

[0072] In some embodiments, the substrate comprises an n-type substrate.

[0073] In some embodiments, the electrostatic discharge detection circuit includes a resistor electrically coupled to a capacitor.

[0074] In some embodiments, the ESD detection circuit is electrically coupled to the inverter circuit.

[0075] In some embodiments, an inverter circuit includes an enhancement mode transistor device electrically coupled to a resistive element.

[0076] In some embodiments, the inverter circuit is electrically coupled to the rectifier circuit.

[0077] In some embodiments, the rectifier circuit includes a diode to rectify current from an electrostatic discharge event.

[0078] In some embodiments, the rectifier circuit includes a plurality of diodes configured in a reverse biased configuration.

[0079] In some embodiments, the transistor is electrically coupled to a target device.

[0080] In some embodiments, a circuit is provided. The circuit includes a gallium nitride (GaN) substrate, a target device, and an electrostatic discharge (ESD) device electrically coupled to the target device. The ESD device 100 includes an ESD detection circuit electrically coupled to a first reference voltage electrode and a second voltage electrode, and a GaN inverter circuit including an enhancement mode transistor device and a resistor element. The GaN inverter circuit is electrically coupled to the ESD detection circuit, and the GaN inverter circuit is used to be triggered in response to an ESD event on a first or second reference voltage supply. The ESD device 100 also includes a rectifier circuit electrically coupled to the GaN inverter circuit and used to rectify a current discharged from the GaN inverter circuit, and a field effect transistor (FET) electrically coupled to the rectifier circuit and used to discharge a residual current transmitted through the rectifier circuit.

[0081] In some embodiments, the electrostatic discharge detection circuit includes a resistor electrically coupled to a capacitor.

[0082] In some embodiments, the enhancement mode transistor device is electrically coupled to the resistive element.

[0083] In some embodiments, the rectifier circuit includes a plurality of diodes configured in a reverse biased configuration.

[0084] In some embodiments, the field effect transistor is electrically coupled to the target device.

[0085] In some embodiments, a method is provided that includes detecting electrostatic discharge (ESD) current on a reference voltage supply, passing the ESD current to a rectifier circuit, enabling a transistor based on the ESD current flowing through the rectifier circuit, and discharging the ESD current from a first reference voltage supply to a second reference voltage supply through the transistor.

[0086] In some embodiments, the method further comprises the step of triggering the inverter circuit by causing current to flow through the resistive element or enabling an enhancement mode transistor device.

[0087] In some embodiments, enabling the transistor includes causing current to flow through at least one diode.

[0088] In some embodiments, the step of causing the current to flow through at least one diode includes the step of causing the current to flow through a plurality of diodes configured in a reverse biased configuration.

[0089] In some embodiments, causing current to flow through the diodes configured in a reverse bias configuration includes rectifying the electrostatic discharge current.

[0090] In some embodiments, the number of the diodes is proportional to the rectification amplitude of the ESD current.

[0091] It should be understood that the detailed description section, rather than the abstract section, is intended to be used to interpret the scope of the claims. The abstract section may describe one or more but not all possible embodiments of the present disclosure contemplated by the inventor, and therefore is not intended to limit the scope of the claims in any way.

[0092] The foregoing summarizes the features of several embodiments so that those skilled in the art may better understand the aspects of an embodiment of the present disclosure. Those skilled in the art will appreciate that they may readily use an embodiment of the present disclosure as a basis for designing or modifying other processes and structures for implementing the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of an embodiment of the present disclosure, and such equivalent constructions may be variously modified, substituted, and replaced herein without departing from the spirit and scope of an embodiment of the present disclosure.

Claims

1. A circuit for electrostatic discharge protection, characterized in that: Include: a substrate; a target device on the substrate; and an electrostatic discharge device electrically coupled to the target device, the electrostatic discharge device comprising: an electrostatic discharge detection circuit electrically coupled to a first reference voltage supply and a second reference voltage supply; an inverter circuit electrically coupled to the ESD detection circuit and configured to be triggered in response to an ESD event on the first reference voltage supply or the second reference voltage supply; a rectifier circuit electrically coupled to the inverter circuit and configured to rectify a current discharged from the inverter circuit; and A transistor is electrically coupled to the rectifier circuit and is used to discharge a residual current transmitted through the rectifier circuit.

2. The circuit according to claim 1, characterized in that The rectifier circuit includes a diode, which is used to rectify a current from the electrostatic discharge event.

3. The circuit according to claim 1, characterized in that The transistor is electrically coupled to the target device.

4. An electrostatic discharge protection circuit, characterized in that: Include: A gallium nitride substrate; a target device; and an electrostatic discharge device electrically coupled to the target device, the electrostatic discharge device comprising: an electrostatic discharge detection circuit electrically coupled to a first reference voltage supply and a second reference voltage supply; a GaN inverter circuit comprising an enhancement mode transistor device and a resistor element, wherein the GaN inverter circuit is electrically coupled to the ESD detection circuit, and wherein the GaN inverter circuit is configured to be triggered in response to an ESD event on the first reference voltage supply or the second reference voltage supply; a rectifier circuit electrically coupled to the GaN inverter circuit and configured to rectify current discharged from the GaN inverter circuit; and A field effect transistor is electrically coupled to the rectifier circuit and is used to discharge a residual current transmitted through the rectifier circuit.

5. The circuit according to claim 4, characterized in that The electrostatic discharge detection circuit includes a resistor electrically coupled to a capacitor.

6. The circuit according to claim 4, characterized in that The gallium nitride inverter circuit wherein the enhancement mode transistor device is electrically coupled to the resistor element.

7. The circuit according to claim 4, characterized in that The rectifier circuit includes a plurality of diodes configured in a reverse bias configuration.

8. A method for electrostatic discharge protection, characterized in that: The following steps are involved: detecting an electrostatic discharge current on a reference voltage supply; passing the electrostatic discharge current to a rectifier circuit; enabling a transistor based on the electrostatic discharge current flowing through the rectifier circuit; and The electrostatic discharge current is discharged from a first reference voltage supply to a second reference voltage supply via the transistor.

9. The method according to claim 8, characterized in that The method further includes the step of triggering an inverter circuit by causing current to flow through a resistor element or enabling an enhancement mode transistor device.

10. The method according to claim 8, characterized in that The step of enabling the transistor comprises the steps of: allowing current to flow through at least one diode, wherein the step of causing the current to flow through the at least one diode comprises the steps of causing the current to flow through a plurality of diodes arranged in a reverse bias configuration, The step of causing the current to flow through the plurality of diodes configured in the reverse bias configuration comprises the following steps: rectifying the electrostatic discharge current, A number of the plurality of diodes is proportional to a rectification amplitude of the electrostatic discharge current.

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