A high linearity low noise amplifier based on post-distortion technique

Abstract

The application discloses a high linearity low noise amplifier based on a post-distortion technology, which comprises a common source and common gate structure circuit, an input matching circuit, an output matching circuit, an auxiliary amplification circuit and a neutralizing inductor; the common source and common gate structure circuit comprises a first common source tube and a second common gate tube; the auxiliary amplification circuit comprises a first common gate tube; the gate and the source of the first common source tube are connected with the input matching circuit; the drain of the first common source tube is connected with the output end of the neutralizing inductor and the source of the first common gate tube; the source of the second common gate tube is connected with the input end of the neutralizing inductor; the drain and the gate of the second common gate tube are connected with the output matching circuit; the source and the gate of the first common gate tube are connected with the auxiliary amplification circuit. The application can realize the balance of multiple indexes such as linearity, power consumption, gain and matching. The application can be widely applied in the field of radio frequency integrated circuit technology.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of radio frequency integrated circuits, and particularly relates to a high-linearity low-noise amplifier based on post-distortion technology. BACKGROUND

[0002] A low noise amplifier (LNA) is one of the key units in a wireless communication system, and is an amplifier with an extremely low noise coefficient, mainly used for amplifying weak signals. The noise coefficient, gain, power consumption and linearity of the low noise amplifier have an important influence on the wireless communication system.

[0003] In the spectrum allocation of a 5G communication network, the Sub-6GHz frequency band and the millimeter wave frequency band are two major frequency bands. Although the millimeter wave frequency band has been rapidly developed and widely applied in recent years due to its high speed, low latency and other characteristics, the Sub-6GHz frequency band still exhibits significant advantages in terms of coverage range, penetration ability, power consumption control, cost-effectiveness and compatibility with other communication technologies. Therefore, the Sub-6GHz frequency band is still the dominant frequency band in the current 5G network layout.

[0004] With the continuous development of semiconductor technology, the process materials of radio frequency chips are also constantly upgrading. From the first generation of RFCMOS to the third generation of GaN, each material has its unique advantages and application scenarios. However, considering the production cost, integration level and process breakthrough, silicon-based technology is still the most cost-effective solution in modern radio frequency chip design.

[0005] A low noise amplifier not only needs a low noise coefficient and a high power gain, but also needs a high linearity to maintain the shape and amplitude of the input signal and avoid distortion. However, for CMOS technology, the low electron mobility limits the linearity. Therefore, when using CMOS devices to implement a radio frequency front end, methods for improving linearity must be considered.

[0006] Compared to common-source and common-gate designs, the cascode structure offers better linearity. Therefore, low-noise amplifiers in Sub-6G are typically designed based on this structure. Traditional cascode structures improve linearity by selecting appropriate bias voltages and CMOS transistor sizes. Adjusting the bias voltage can reduce the third-order nonlinearity coefficient, thus improving linearity. However, lower third-order nonlinearity coefficients are usually achieved only when the bias voltage is in the weak inversion and linear regions. In the weak inversion region, CMOS transistors are susceptible to process variations, leading to transistor turn-off. In the linear region, the higher bias voltage results in higher drain-source current, increasing power consumption. While smaller CMOS transistor sizes can also reduce the third-order nonlinearity coefficient, smaller transistor sizes cannot achieve higher gain. Therefore, existing cascode low-noise amplifiers cannot achieve a balance between linearity, power consumption, gain, and matching performance. Summary of the Invention

[0007] To address the aforementioned technical problems, the objective of this invention is to provide a high-linearity, low-noise amplifier based on post-distortion technology, capable of achieving a balance among multiple metrics including linearity, power consumption, gain, and matching.

[0008] The technical solution adopted in this invention is: a high linearity, low noise amplifier based on post-distortion technology, comprising a common-source cascode structure circuit, an input matching circuit, an output matching circuit, an auxiliary amplification circuit, and a neutralizing inductor, wherein:

[0009] The common-source, common-gate structure circuit includes a first common-source transistor and a second common-gate transistor;

[0010] The auxiliary amplifier circuit includes a first common-gate transistor, a third resistor, a fourth resistor, a fifth capacitor, and a sixth capacitor;

[0011] The neutralizing inductor is used to neutralize the parasitic capacitance between the first common-source transistor and the second common-gate transistor, thereby improving reverse isolation.

[0012] The gate and source of the first common-source transistor are connected to the input matching circuit; the drain of the first common-source transistor is connected to the output terminal of the neutralizing inductor and the source of the first common-gate transistor; the source of the second common-gate transistor is connected to the input terminal of the neutralizing inductor; the drain and gate of the second common-gate transistor are connected to the output matching circuit; the drain of the first common-gate transistor is connected to the output terminal of the fourth resistor and the output terminal of the sixth capacitor; the input terminal of the fourth resistor is connected to the input terminal of the sixth capacitor, the output matching circuit, and the input terminal of the third resistor; the output terminal of the third resistor is connected to the gate of the first common-gate transistor and the input terminal of the fifth capacitor; the output terminal of the fifth capacitor is grounded.

[0013] Further, the fourth resistor and the sixth capacitor constitute an RC parallel resonance network, wherein:

[0014] The fourth resistor provides a direct current path for the first common-gate tube, and the first common-gate tube is biased in a deep linear region through series voltage division;

[0015] The sixth capacitor is used for adjusting the impedance of the auxiliary amplification circuit, providing an alternating current path, keeping the signal unblocked, and further eliminating the nonlinearity of the first common-source tube.

[0016] Further, the first resistor of the input matching circuit, the second resistor of the output matching circuit, and the third resistor are used for acting as a choke inductance to prevent the input radio frequency signal from interfering with the bias voltage of the gate of the common-source common-gate structure.

[0017] The beneficial effects of the present application are as follows: the present application introduces an auxiliary amplification tube working in a strong inverse type region to generate a nonlinear characteristic opposite to that of the main amplification tube, thereby offsetting the coefficient of the third-order nonlinearity, improving the linearity without adjusting the bias voltage and size of the main amplification tube; the auxiliary amplification tube is connected to the output end of the main amplification tube, and does not directly affect the design of the input matching and the output matching and the gain flatness, which makes the design of the matching network simpler, reduces the design complexity, and helps the designer to optimize the performance of the input and output ends respectively, thereby improving the overall design efficiency; in addition, in the RC parallel resonance network, the static working point of the auxiliary amplification tube is adjusted by selecting appropriate resistance values, the drain-source voltage is reduced, the auxiliary amplification tube is biased in a deep linear region, thereby minimizing the current introduced by the auxiliary branch, reducing the influence of the auxiliary amplification tube on the overall power consumption and gain to the minimum, and selecting appropriate capacitance values to adjust the impedance of the auxiliary branch to achieve better nonlinear elimination effect, and to balance the linearity, power consumption, gain, and matching multiple indicators. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1 is a circuit structure diagram of a high linearity low noise amplifier based on post-distortion technology according to the present application;

[0019] Figure 2 is an equivalent schematic diagram of a high linearity low noise amplifier based on post-distortion technology according to the present application;

[0020] Figure 3 is a diagram showing the influence of the capacitance value of the sixth capacitor on the linearity of a high linearity low noise amplifier based on post-distortion technology according to the present application;

[0021] Figure 4 is a diagram showing the influence of the capacitance value of the sixth capacitor on the gain of a high linearity low noise amplifier based on post-distortion technology according to the present application;

[0022] Figure 5It is a fourth resistance value of a high linearity low noise amplifier based on post-distortion technology of the application and the influence diagram of the linearity;

[0023] Figure 6 It is a fourth resistance value of a high linearity low noise amplifier based on post-distortion technology of the application and the influence diagram of the power consumption;

[0024] Figure 7 It is a fourth resistance value of a high linearity low noise amplifier based on post-distortion technology of the application and the influence diagram of the gain;

[0025] Figure 8 It is a return loss and structure gain diagram of a high linearity low noise amplifier based on post-distortion technology of the application;

[0026] Figure 9 It is a comparison diagram of the linearity of the low noise amplifier of the structure of the application and the low noise amplifier of the traditional structure under the frequency of 1.9-2.1GHz;

[0027] Figure 10 It is a comparison diagram of the gain of the low noise amplifier of the structure of the application and the low noise amplifier of the traditional structure under the frequency of 1.9-2.1GHz;

[0028] BRIEF DESCRIPTION OF DRAWINGS: RF in , RF signal input end; C1, first capacitor; C2, second capacitor; C3, third capacitor; C4, fourth capacitor; C5, fifth capacitor; C6, sixth capacitor; R1, first resistor; R2, second resistor; R3, third resistor; R4, fourth resistor; L1, first inductor; L2, second inductor; L3, neutralizing inductor; L4, fourth inductor; L5, fifth inductor; RF out , RF signal output end; VG1, first power supply voltage; VDD, gate power supply voltage; M A , first common source transistor; M B , first common gate transistor; M C , second common gate transistor. DETAILED DESCRIPTION

[0029] The application will be further described in detail below with reference to the drawings and specific embodiments. For the step numbers in the following embodiments, only the setting is for the convenience of description, and the order between the steps is not limited in any way, and the execution order of each step in the embodiments can be adaptively adjusted according to the understanding of those skilled in the art.

[0030] Referring to Figure 1 , a high linearity low noise amplifier based on post-distortion technology, comprising a common source common gate structure circuit, an input matching circuit, an output matching circuit, an auxiliary amplification circuit and a neutralizing inductor L3, wherein:

[0031] The common-source common-gate structure circuit comprises a first common-source tube M A and a second common-gate tube M C ;

[0032] The auxiliary amplification circuit comprises a first common-gate tube M B , a third resistor R3, a fourth resistor R4, a fifth capacitor C5 and a sixth capacitor C6;

[0033] The neutralizing inductor L3 is used for neutralizing the parasitic capacitance between the first common-source tube M A and the second common-gate tube M C , and improving the reverse isolation degree;

[0034] The gate and the source of the first common-source tube are connected with the input matching circuit; the drain of the first common-source tube is connected with the output end of the neutralizing inductor L3, the source of the first common-gate tube M B ; the source of the second common-gate tube M C is connected with the input end of the neutralizing inductor L3; the drain and the gate of the second common-gate tube M C are connected with the output matching circuit; the drain of the first common-gate tube M B is connected with the output end of the fourth resistor R4 and the output end of the sixth capacitor C6; the input end of the fourth resistor R4 is connected with the input end of the sixth capacitor C6, the output matching circuit and the input end of the third resistor R3; the output end of the third resistor R3 is connected with the gate of the first common-gate tube M B and the input end of the fifth capacitor C5; and the output end of the fifth capacitor C5 is grounded.

[0035] Preferably, the first common-source tube M A is a main amplification tube; the first common-gate tube M B is an auxiliary amplification tube, and the first common-gate tube M B is used for compensating the third-order nonlinearity of the first common-source tube M A , is connected with the output end of the first common-source tube M A , reduces the influence on the input matching, and is conducive to the unidirectional design.

[0036] Preferably, the fourth resistor R4 and the sixth capacitor C6 constitute an RC parallel resonance network, wherein:

[0037] The fourth resistor R4 provides a direct current path for the first common-gate tube M B , and biases the first common-gate tube M A in a deep linear region through series voltage division;

[0038] The sixth capacitor C6 is used for providing an alternating current path and keeping the signal unblocked.

[0039] The input matching circuit includes a first capacitor, a first resistor, a first inductor, a second capacitor, and a second inductor, wherein:

[0040] The first common source transistor M A The source of the transistor is connected to the output terminal of the second capacitor C2 and the input terminal of the second inductor L2; the output terminal of the second inductor L2 is grounded; the first common-source transistor M... A The gate of the capacitor is connected to the input terminal of the second capacitor C2 and the output terminal of the first inductor L1; the input terminal of the first inductor L1 is connected to the output terminal of the first capacitor C1 and the output terminal of the first resistor R1; the input terminal of the first capacitor C1 is connected to the RF signal input terminal. in Connection; the input terminal of the first resistor R1 is connected to the first power supply voltage VG1.

[0041] Preferably, the first capacitor C1 is a DC blocking capacitor, and because its capacitance is large, it does not participate in the impedance matching of the input terminal.

[0042] Preferably, the second inductor L2 is a source degradation inductor, used to improve circuit stability and reduce the noise figure of the circuit.

[0043] Preferably, the first inductor, the second inductor, and the second capacitor work together to adjust the input matching, matching the input capacitive impedance of the cascode circuit to 50 ohms.

[0044] Preferably, the output matching circuit includes a second resistor R2, a third capacitor C3, a fourth capacitor C4, a fourth inductor L4, and a fifth inductor L5, wherein:

[0045] The second common gate transistor M C The drain of the capacitor is connected to the output terminal of the fourth inductor L4; the input terminal of the fourth inductor L4 is connected to the input terminal of the fourth capacitor C4 and the output terminal of the fifth inductor L5; the output terminal of the fourth capacitor C4 is connected to the RF signal output terminal. out Connections: The input terminal of the fifth inductor L5 is connected to the input terminal of the fourth resistor R4, the gate power supply voltage VDD, and the input terminal of the second resistor R2; the output terminal of the second resistor R2 is connected to the second common-gate transistor M. C The gate of the capacitor is connected to the input terminal of the third capacitor C3; the output terminal of the third capacitor C3 is grounded.

[0046] Preferably, the fifth inductor L5 is a high-inductance radio frequency choke coil used to block AC signals and provide a DC path to provide a stable gate power supply voltage for the output path.

[0047] The fourth capacitor C4 and the fifth inductor L5 jointly regulate the output matching, matching the output capacitive impedance of the common-source and common-gate structure circuit to 50 ohms.

[0048] The third capacitor C3 and the fifth capacitor C5 are both bypass capacitors, used to short the radio frequency signal to the ground, preventing the radio frequency signal from interfering with the direct current bias.

[0049] The first resistor R1, the second resistor R2 and the third resistor R3 are used to act as a choke inductor, preventing the input radio frequency signal from interfering with the bias voltage of the gate of the common-source and common-gate structure.

[0050] The fourth inductor L4 is a series peaking inductor, inserted between the second common-gate tube M C and the output matching network, used to expand the bandwidth.

[0051] The equivalent schematic diagram of the circuit of the present application is simplified as shown in Figure 2 , Figure 2 The expression of the current i A in

[0052] i A = g 1A v1+ g 2A v1 2 + g 3A v1 3 (1)

[0053] wherein i A represents the current of the first common-source tube M g ; g 1A represents the first-order derivative of the direct current transmission characteristic of the first common-source tube; g 2A represents the second-order derivative of the direct current transmission characteristic of the first common-source tube; g 3A represents the third-order derivative of the direct current transmission characteristic of the first common-source tube; and v1 represents the gate-source voltage of the first common-source tube.

[0054] The expression of the current i B is as follows:

[0055] i B = g 1B v2+ g 2B v2 2 + g 3B v2 3 (2)

[0056] wherein i B represents the current of the first common-source tube M B ; g 1B represents the first-order derivative of the direct current transmission characteristic of the first common-gate tube; g 2Bthe second derivative of the DC transfer characteristic of the first common-gate transistor; g 3B the third derivative of the DC transfer characteristic of the first common-gate transistor; v2 represents the voltage at the drain of the first common-source transistor M a .

[0057] the current i out is expressed as follows:

[0058] i out = i A + i B (3)

[0059] where i out represents the drain-source current of the second common-gate transistor.

[0060] Since the first common-source transistor M A amplifies the RF input signal in the reverse direction, the first common-source transistor M A needs to be biased in the saturation region.

[0061] v2 = -b1v1, b1 > 0 (4)

[0062] where v2 represents the voltage at the drain of the first common-source transistor M A ; and b1 represents the linear gain of the first common-source transistor.

[0063] From equations 1, 2, 3 and 4, we have:

[0064] i out = (g 1A -b1g 1B )v1+ (g 2A -b1 2 g 2B )v1 2 + (g 3A -b1 3 g 3B )v1 2 (5)

[0065] From equation 5, we can see that the linearity (OIP3) can be improved by making the third derivative g 3A -b1 3 g 3B equal to 0. The first common-source transistor M A needs to be biased in the saturation region as the main amplification transistor, so g 3A is less than 0. When g 3B is negative, the auxiliary amplification transistor can only eliminate the nonlinearity of the main amplification transistor, at which time the auxiliary amplification transistor M B needs to be biased in the strong inverse region. In addition, the size of the auxiliary amplification transistor needs to be reasonably selected so that g 3A = b1 3 g3B , to eliminate the third-order nonlinearity, and obtain good linearity. In the RC parallel resonant network, by selecting a proper fourth resistance value R4, adjusting the fourth resistance R4 and the auxiliary amplification tube M B , the static operating point of the auxiliary amplification tube can be more flexibly adjusted, and the drain-source voltage is as small as possible, so as to be biased in the deep linear region. According to the current formula of the deep linear region , wherein I D represents the current of the branch where the auxiliary amplification tube is located; μ represents the electron mobility; C ox represents the gate oxide layer capacitance per unit area; V GS represents the gate-source voltage of the transistor; V TH represents the threshold voltage of the transistor; V DS represents the drain-source voltage of the transistor; W represents the gate width of the transistor; and L represents the channel length of the transistor. It can be known that reducing the drain-source voltage V DS can reduce the current I D of the branch where the auxiliary amplification tube is located, thereby reducing the power consumption introduced additionally, and the reduction of the consumed current can also reduce the gain attenuation.

[0066] The influence of the resistance value of the fourth resistance R4 on the linearity, power consumption, and gain can be referred to Figure 5 , Figure 6 and Figure 7 , respectively. It can be found that with the increase of the resistance value of R4, the linearity OIP3 first increases and then decreases, and when R4 = 3.5 kΩ, OIP3 reaches the peak value of 30.0 dBm; in the range of R4 = 0-5 kΩ, the power consumption introduced by the auxiliary branch is significantly reduced with the increase of the resistance value of R4, and when R4 is greater than 5 kΩ, the power consumption introduced by the auxiliary branch is less affected by the resistance value of R4; the gain gradually increases with the increase of the resistance value of R4, that is, a slightly larger resistance value can reduce the gain attenuation caused by the auxiliary amplification tube, so a proper resistance value should be selected by considering the compromise of the power consumption, gain, and linearity.

[0067] Although increasing the resistance value of the fourth resistance R4 can adjust the static operating point, it will increase the impedance of the branch where the auxiliary amplification tube is located, and affect the elimination of nonlinearity. Therefore, the sixth capacitor C6 is adopted to adjust the impedance of the branch, so that the impedance of the RC resonant network at the working frequency reaches the minimum, the signal can pass through the auxiliary amplification tube smoothly, and the nonlinearity of the main amplification tube is fully eliminated, thereby improving the linearity OIP3 of the low-noise amplifier. The influence of the capacitance value of the sixth capacitor on the linearity and gain can be referred to Figure 3 and Figure 4It can be found that the linearity OIP3 increases first and then decreases with the increase of the C6 capacitance value, and the OIP3 reaches a peak value of 23.6dBm when C6=3p; the gain gradually decreases with the increase of the C6 capacitance value, that is, a larger capacitance value will cause a certain degree of gain attenuation, so the appropriate capacitance value should be selected in combination with the trade-off between linearity and gain.

[0068] With reference to Figure 8 It can be found that the circuit of the application realizes good input matching and output matching in the range of 1.9-2.1GHz, the input return loss is better than 16.8dB, the output return loss is better than 13.6dB, and at the same time, the gain flatness is high, the gain in the frequency band is 14.7-14.8dB, and the in-band gain fluctuation is only 0.1dB.

[0069] The low-noise amplifier of the specific embodiment of the application is simulated and compared with the low-noise amplifier of the traditional structure at the frequency of 1.9-2.1GHz to verify that the low-noise amplifier of the structure of the application has superior performance.

[0070] With reference to Figure 9 In terms of linearity, the linearity OIP3 of the low-noise amplifier of the traditional structure is 15.8dBm, while the linearity OIP3 of the low-noise amplifier of the structure of the application is 23.6dBm, which is improved by 7dB; with reference to Figure 10 In terms of gain, the gain of the low-noise amplifier of the traditional structure is 15.6dB, while the gain of the low-noise amplifier of the structure of the application is 14.7dB, which only decreases by 0.9dB; in addition, in terms of power consumption, the current of the common-source and common-gate structure of the low-noise amplifier of the traditional structure is 9.943mA, and the overall power consumption is 17.897mW; while the current of the common-source and common-gate structure of the low-noise amplifier of the structure of the application is 9.945mA, and the overall power consumption is 17.901mW, which is similar.

[0071] In summary, the high-linearity low-noise amplifier based on the post-distortion technology can maintain good linearity, low power consumption and high gain at the same time.

[0072] The above is a specific description of the preferred embodiment of the application, but the application is not limited to the described embodiments, and those skilled in the art can make various equivalent modifications or replacements without departing from the spirit of the application, and these equivalent modifications or replacements are all included in the scope defined by the claims of the application.

Claims

1. A high-linearity, low-noise amplifier based on post-distortion technology, characterized in that, It includes a common-source cascode structure circuit, an input matching circuit, an output matching circuit, an auxiliary amplifier circuit, and a neutralizing inductor, wherein: The common-source, common-gate structure circuit includes a first common-source transistor and a second common-gate transistor; The auxiliary amplifier circuit includes a first common-gate transistor, a third resistor, a fourth resistor, a fifth capacitor, and a sixth capacitor; The neutralizing inductor is used to neutralize the parasitic capacitance between the first common-source transistor and the second common-gate transistor, thereby improving reverse isolation. The gate and source of the first common-source transistor are connected to the input matching circuit; the drain of the first common-source transistor is connected to the output terminal of the neutralizing inductor and the source of the first common-gate transistor; the source of the second common-gate transistor is connected to the input terminal of the neutralizing inductor; the drain and gate of the second common-gate transistor are connected to the output matching circuit; the drain of the first common-gate transistor is connected to the output terminal of the fourth resistor and the output terminal of the sixth capacitor; the input terminal of the fourth resistor is connected to the input terminal of the sixth capacitor, the output matching circuit, and the input terminal of the third resistor; the output terminal of the third resistor is connected to the gate of the first common-gate transistor and the input terminal of the fifth capacitor; the output terminal of the fifth capacitor is grounded.

2. The high linearity, low noise amplifier based on post-distortion technology according to claim 1, characterized in that, The fourth resistor and the sixth capacitor form an RC parallel resonant network, wherein: The fourth resistor provides a DC path for the first common gate transistor, and biases the first common gate transistor in the deep linear region through series voltage division. The sixth capacitor is used to adjust the impedance of the auxiliary amplifier circuit, provide an AC path, keep the signal unobstructed, and thus eliminate the nonlinearity of the first common-source transistor.

3. The high linearity, low noise amplifier based on post-distortion technology according to claim 2, characterized in that, The first resistor in the input matching circuit, the second resistor in the output matching circuit, and the third resistor are used as choke inductors to prevent the input radio frequency signal from interfering with the bias voltage of the gate of the cascode structure.

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