System, method and device for realizing high-precision and dynamic multipath delay in channel simulation, processor and computer readable storage medium

Abstract

The invention relates to a system for realizing high-precision and dynamic multipath delay in channel simulation. The invention also relates to a method for realizing high-precision dynamic multipath delay in channel simulation. By adopting the system, the method, the device, the processor and the computer readable storage medium for realizing high-precision and dynamic multipath time delay in channel simulation, provided by the invention, the multipath time delay with higher precision is realized for wireless channel simulation with larger bandwidth, the time delay resolution and accuracy are ensured, and the multipath simulation performance in the channel simulation process is improved. In the radial delay processing module, multiple RAMs are connected in series to improve the depth of the RAMs, so that the maximum delay number is effectively improved, and the time delay resolution can be improved by using reg delay. The FPGA can obtain a higher data sampling rate by using a high-speed clock, so that the channel simulation bandwidth is increased.

Description

Technical Field

[0001] The present invention relates to the field of digital signal processing, and in particular to the field of channel simulators and channel multipath delays, and specifically refers to a system, method, device, processor and computer-readable storage medium thereof for realizing high-precision and dynamic multipath delay in channel simulation. Background Art

[0002] When electromagnetic wave signals propagate in wireless communication, different obstacles may absorb or reflect the signals, which will have a significant impact on their amplitude and phase. Due to the effects of reflection, scattering and refraction, the signals do not propagate directly in a straight line, but along different paths. These different paths may cause the signal to arrive at the receiver at different times, thus producing a multipath effect. The propagation distance and incident angle of each propagation path are different, resulting in different delays, amplitudes and phases when each path reaches the receiver.

[0003] In order to simulate these multipath effects in the laboratory, the channel simulator needs to simulate multiple different propagation paths for each input signal and impose different delays on these paths. However, as the bandwidth of wireless communications becomes higher and higher, the simulation accuracy becomes higher and higher, and the time extension requirements for multipath delays become larger and larger, requiring high-speed data processing and high-precision, dynamic and large multipath delay range. This requires more complex and higher-rate clock data processing in FPGA. Summary of the invention

[0004] The purpose of the present invention is to overcome the shortcomings of the above-mentioned prior art and to provide a system, method, device, processor and computer-readable storage medium thereof that can realize high-precision and dynamic multipath delay in channel simulation, which are high-precision, easy to operate and have a wide range of applications.

[0005] In order to achieve the above-mentioned object, the system, method, device, processor and computer-readable storage medium for realizing high-precision and dynamic multipath delay in channel simulation of the present invention are as follows:

[0006] The system for realizing high-precision and dynamic multipath delay in channel simulation has the following main features:

[0007] The coefficient sending and processing module is used to send dynamic coefficients and update signals through the host computer, and allocate coefficients to each serial part RAM;

[0008] The path delay processing module is used to write input data to multiple Ultra-RAMs connected in series, introduce a new 1-bit extended address, and obtain the RAM read address;

[0009] The output data Reg-Delay module is used to rearrange the output data according to the 1-bit extended address so that the output data Reg-Delay module runs at twice the sampling rate of the FPGA clock;

[0010] The output synchronization module is used to analyze the internal timing and perform final output synchronization.

[0011] Preferably, the path delay processing module includes a plurality of Ultra-RAMs connected in series, and input data is written into each Ultra-RAM by a self-incrementing write address, and a new 1-bit extended address is introduced, so that two 32-bit data of a dual pipeline mode corresponding to each UltraRAM address are obtained to obtain the read address of the UltraRAM.

[0012] Preferably, the self-incremented write address of the path delay processing module is specifically:

[0013] Increment from the first address of RAM to the last address and automatically return to the first address to set the upper limit of the delay coefficient.

[0014] Preferably, the path delay processing module obtains the read address of the RAM, specifically:

[0015] The UltraRAM read address is obtained by subtracting each calculated UltraRAM delay coefficient from the extended write address.

[0016] Preferably, the coefficient sending and processing module stores static delay coefficients in advance before the simulation starts, and periodically sends a small portion of dynamic delay coefficients and update signals through an external module after the simulation starts.

[0017] Preferably, the write address of the 1-bit extended address in the output data Reg-Delay module corresponds to the read address.

[0018] The method for realizing high-precision dynamic multipath delay in channel simulation has the following main features:

[0019] (1) The delay coefficient and dynamic range are sent down through the host computer;

[0020] (2) Perform path delay processing on input data;

[0021] (3) register delay for dual data pipelines;

[0022] (4) Synchronize the multipath data and output the final multipath data.

[0023] Preferably, the step (1) specifically comprises the following steps:

[0024] (1.1) The PC host sends the static delay coefficient to the FPGA through PCIe and stores it in BRAM;

[0025] (1.2) Store the dynamic range MUSK during the simulation into BRAM;

[0026] (1.3) The external module sends the dynamic delay coefficient through AURORA;

[0027] (1.4) Select the static delay coefficient according to the dynamic range MUSK and the dynamic delay coefficient to obtain the final delay coefficient list;

[0028] (1.5) Send update signals through external modules and continuously update coefficients to the path delay processing module.

[0029] Preferably, the step (2) specifically comprises the following steps:

[0030] (2.1) Generate RAM write address and increment it;

[0031] (2.2) Write the input data into the deep RAM connected in series by Ultra-RAM;

[0032] (2.3) The input address is divided into two 32-bit data in the low-order extension area, input into the subtractor, obtains the output address, and reads the output data through the RAM according to the output address.

[0033] Preferably, the step (3) specifically comprises the following steps:

[0034] The output data is delayed in registers according to the input address, and data with a sampling rate higher than one times the FPGA clock is delayed.

[0035] The main feature of the device for realizing high-precision and dynamic multipath delay in channel simulation is that the device comprises:

[0036] a processor configured to execute computer-executable instructions;

[0037] The memory stores one or more computer executable instructions. When the computer executable instructions are executed by the processor, the various steps of the above-mentioned method for realizing high-precision dynamic multipath delay in channel simulation are implemented.

[0038] The processor for realizing high-precision, dynamic multipath delay in channel simulation has the main feature that the processor is configured to execute computer executable instructions, and when the computer executable instructions are executed by the processor, the various steps of the above-mentioned method for realizing high-precision dynamic multipath delay in channel simulation are realized.

[0039] The main feature of the computer-readable storage medium is that a computer program is stored thereon, and the computer program can be executed by a processor to implement the various steps of the above-mentioned method for realizing high-precision dynamic multipath delay in channel simulation.

[0040] The system, method, device, processor and computer-readable storage medium for realizing high-precision and dynamic multipath delay in channel simulation of the present invention are adopted to realize multipath delay with higher precision for simulation of wireless channels with larger bandwidth, ensure the delay resolution and accuracy, and improve the multipath simulation performance of the channel simulation process. In the path delay processing module, the use of multiple RAMs in series can increase the RAM depth, thereby effectively increasing the maximum delay number, and the use of reg delay can improve the delay resolution. The use of high-speed clocks by FPGA can obtain a higher data sampling rate, thereby increasing the channel simulation bandwidth. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 It is an overall schematic diagram of a system for realizing high-precision and dynamic multipath delay in channel simulation of the present invention.

[0042] Figure 2 The present invention is a schematic diagram of coefficient distribution for a system that realizes high-precision and dynamic multipath delay in channel simulation.

[0043] Figure 3 It is a schematic diagram of path delay processing of a system for realizing high-precision and dynamic multipath delay in channel simulation of the present invention. DETAILED DESCRIPTION

[0044] In order to more clearly describe the technical content of the present invention, further description is given below in conjunction with specific embodiments.

[0045] The system for realizing high-precision and dynamic multipath delay in the channel simulation of the present invention comprises:

[0046] The coefficient sending and processing module is used to send dynamic coefficients and update signals through the host computer, and allocate coefficients to each serial part RAM;

[0047] The path delay processing module is used to write input data to multiple Ultra-RAMs connected in series, introduce a new 1-bit extended address, and obtain the RAM read address;

[0048] The output data Reg-Delay module is used to rearrange the output data according to the 1-bit extended address so that the output data Reg-Delay module runs at twice the sampling rate of the FPGA clock;

[0049] The output synchronization module is used to analyze the internal timing and perform final output synchronization.

[0050] As a preferred embodiment of the present invention, the path delay processing module includes multiple Ultra-RAMs connected in series, and input data is written to each Ultra-RAM by a self-incrementing write address, and a new 1-bit extended address is introduced, so that the two 32-bit data of the dual pipeline mode corresponding to each UltraRAM address are obtained to obtain the read address of the UltraRAM.

[0051] As a preferred embodiment of the present invention, the self-incremented write address of the path delay processing module is specifically:

[0052] Increment from the first address of RAM to the last address and automatically return to the first address to set the upper limit of the delay coefficient.

[0053] As a preferred embodiment of the present invention, the path delay processing module obtains the read address of the RAM, specifically:

[0054] The UltraRAM read address is obtained by subtracting each calculated UltraRAM delay coefficient from the extended write address.

[0055] As a preferred embodiment of the present invention, the coefficient sending and processing module stores static delay coefficients in advance before the simulation starts, and sends a small portion of dynamic delay coefficients and update signals regularly through an external module after the simulation starts.

[0056] As a preferred implementation of the present invention, the write address of the 1-bit extended address in the output data Reg-Delay module corresponds to the read address.

[0057] The method for realizing high-precision dynamic multipath delay in channel simulation of the present invention comprises the following steps:

[0058] (1) The delay coefficient and dynamic range are sent down through the host computer;

[0059] (2) Perform path delay processing on input data;

[0060] (3) register delay for dual data pipelines;

[0061] (4) Synchronize the multipath data and output the final multipath data.

[0062] As a preferred embodiment of the present invention, the step (1) specifically comprises the following steps:

[0063] (1.1) The PC host sends the static delay coefficient to the FPGA through PCIe and stores it in BRAM;

[0064] (1.2) Store the dynamic range MUSK during the simulation into BRAM;

[0065] (1.3) The external module sends the dynamic delay coefficient through AURORA;

[0066] (1.4) Select the static delay coefficient according to the dynamic range MUSK and the dynamic delay coefficient to obtain the final delay coefficient list;

[0067] (1.5) The update signal is sent through the external module, and the coefficients are continuously updated to the path delay processing module.

[0068] As a preferred embodiment of the present invention, the step (2) specifically comprises the following steps:

[0069] (2.1) Generate RAM write address and increment it;

[0070] (2.2) Write the input data into the deep RAM connected in series by Ultra-RAM;

[0071] (2.3) The input address is divided into two 32-bit data in the low-order extension area, input into the subtractor, obtains the output address, and reads the output data through the RAM according to the output address.

[0072] As a preferred embodiment of the present invention, the step (3) specifically comprises the following steps:

[0073] The output data is delayed in registers according to the input address, and data with a sampling rate higher than one times the FPGA clock is delayed.

[0074] The device for realizing high-precision and dynamic multipath delay in channel simulation of the present invention comprises:

[0075] a processor configured to execute computer executable instructions;

[0076] The memory stores one or more computer executable instructions. When the computer executable instructions are executed by the processor, the various steps of the above-mentioned method for realizing high-precision dynamic multipath delay in channel simulation are implemented.

[0077] The processor of the present invention is used to implement high-precision, dynamic multipath delay in channel simulation, wherein the processor is configured to execute computer-executable instructions. When the computer-executable instructions are executed by the processor, the various steps of the above-mentioned method for implementing high-precision dynamic multipath delay in channel simulation are implemented.

[0078] The computer-readable storage medium of the present invention stores a computer program thereon, and the computer program can be executed by a processor to implement the various steps of the above-mentioned method for realizing high-precision dynamic multipath delay in channel simulation.

[0079] In the specific implementation of the present invention, the purpose is to overcome the shortcomings of the above-mentioned prior art, improve the accuracy of delay processing, improve the range of multipath delay, and increase the FPGA data clock rate, so that it can achieve more accurate multipath delay processing for larger bandwidth wireless channel simulation. The present invention redesigns the data structure based on the small step integer delay module to obtain more accurate delay processing.

[0080] In order to achieve the above object, the present invention implements the following steps for multipath delay processing with higher accuracy for larger bandwidth wireless channel simulation:

[0081] (1) The delay coefficient and dynamic range are sent down through the host computer.

[0082] (2) Perform path delay processing on the input data.

[0083] (3) Perform register delay on the dual data pipeline to improve the delay resolution.

[0084] (4) Synchronize the multipath data and then output it.

[0085] In the claims and the specification, reg delay means register delay, which can be combined with integer delay module to obtain higher precision delay processing. Reg delay means to perform different delay combinations on two sets of data according to the delay conditions to obtain the final high precision result.

[0086] The step (1) specifically comprises the following steps:

[0087] 1. Before the simulation starts, the static delay coefficient is sent to the FPGA through PCIe and stored in BRAM.

[0088] 2. The dynamic range MUSK during the simulation process is stored in BRAM to facilitate the subsequent dynamic update of the delay coefficient.

[0089] 3. The external module sends the dynamic delay coefficient through AURORA.

[0090] 4. The static delay coefficient is selected according to the dynamic range MUSK and the dynamic delay coefficient to obtain the final delay coefficient list.

[0091] 5. Send update signals through external modules to continuously update the coefficients to the path delay processing module.

[0092] The step (2) specifically comprises the following steps:

[0093] 1. Generate RAM write address and increment it.

[0094] 2. Input data is written into a deep RAM connected in series by Ultra-RAM, with two 32-bit input data concatenated into 64 bits each time.

[0095] 3. The input address is extended at the low bit to distinguish two 32-bit data, and then enters the subtractor to obtain the output address, and the output data is read out through RAM according to the output address.

[0096] In the step (3), the output data is delayed in the register according to the lowest extended bit of the input address, and the data with a sampling rate higher than one times of the FPGA clock can be delayed.

[0097] In the step (4), the internal inherent register delay of the final output for different numbers of RAMs connected in series may be different. In step (4), synchronization processing is performed to output the final multipath data.

[0098] The present invention realizes a high-precision, large-range dynamic multipath delay method based on multiple Ultra-RAMs connected in series and dual pipelines processing data in parallel, which includes:

[0099] The coefficient sending and processing module is used to send dynamic coefficients and update signals through the host computer, and to allocate coefficients to each serial part RAM.

[0100] The path delay processing module includes multiple Ultra-RAMs connected in series. Each RAM writes input data by the write address generated by self-increment, and then introduces a new 1-bit extended address, so that each RAM address corresponds to two 32-bit data in the dual pipeline mode, and the output can be accurate to each data, thereby improving the data sampling rate and delay resolution. After that, the RAM read address can be obtained by subtracting the calculated delay coefficient of each RAM from the extended write address.

[0101] The output data Reg-Delay module can know how to arrange the two 32-bit data taken out according to the 1-bit extended address. The rearrangement of the output data can improve the delay resolution, so that this module can run at twice the sampling rate of the FPGA clock.

[0102] Output synchronization module: When processing multiple paths, the number of serially connected RAMs may be different, which may cause different internal delays for each path. In this case, it is necessary to analyze the internal timing for final output synchronization.

[0103] The coefficient sending and processing module is composed of a static delay coefficient and a dynamic delay coefficient. The static delay coefficient is stored in advance before the simulation starts. After the simulation starts, only a small part of the dynamic delay coefficient and the update signal need to be sent periodically through the external module to improve the system stability.

[0104] The input data in the path delay processing module will traverse each RAM, and the self-incrementing write address will increase from the first address of the RAM to the last address and automatically return to the first address. As long as the upper limit of the delay coefficient is specified, it can be ensured that each output data is a valid value.

[0105] The 1-bit extended address write address and the read address in the output data Reg-Delay module correspond to each other, thus ensuring the correspondence between output and input.

[0106] like Figure 1 As shown in the figure, after the data is input, it enters multiple delay modules. Each module increases the maximum delay length by connecting multiple RAMs in series. Then the data increases the delay resolution by using the Reg-Delay method. Figure 2 As shown, the external module updates the dynamic coefficient to the internal coefficient module through aurora, selects and merges with the internal static coefficient, and transmits it to the path delay module according to the update signal. Figure 3 As shown, after receiving the coefficients, the path delay module cuts and distributes the coefficients according to the number and arrangement of RAMs, effectively ensuring that the data is continuous and valid after passing through each RAM. After each two consecutive 32-bit input data are spliced ​​in order, they are written into the RAM according to the write address generated by self-increment. The lowest bit of the write address is increased by one address extension bit to expand to each corresponding 32-bit input data. The output address is obtained by subtracting the extended address from the delay coefficient. We take the output address and remove the last bit to get the read address of the RAM. At this time, the data read from the RAM is the front and back 32-bit data. According to the last bit of the output address, we can judge whether the data we need at this time is the high 32-bit data or the low 32-bit data. Then perform the Reg-Delay operation to rearrange the two data to get the final output result.

[0107] For example, we set the delay coefficient of the first path to be 10 through the external module, and the delay coefficient of the second update to be 11 after 20μm. After the delay coefficient is sent, the update signal is sent. The input data is converted from the external ADC sampling data and sent to this module as a group of two 32-bit data. At this time, our output data is the data written before 10+module fixed delay clock cycles at this sampling rate at the first update delay, and at this time, after the second coefficient update, the output data will output the data written before 11+fixed delay clock cycles at this sampling rate. If we set the number of Ultra-RAMs to be 2 in series, when the delay coefficient is greater than the maximum depth set by the Ultra-RAM after removing the last digit, the input coefficient of the first Ultra-RAM is fixed to its maximum depth value. We use the delay coefficient to remove the last digit minus the maximum depth value and then add the last digit back to get the delay coefficient input to the second Ultra-RAM. At this time, after the two RAMs are connected in series, a delay module with a larger delay range is obtained.

[0108] The specific implementation scheme of this embodiment can refer to the relevant description in the above embodiment, which will not be repeated here.

[0109] It can be understood that the same or similar parts of the above embodiments can be referenced to each other, and the contents not described in detail in some embodiments can refer to the same or similar contents in other embodiments.

[0110] It should be noted that, in the description of the present invention, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of the present invention, unless otherwise specified, the meaning of "plurality" refers to at least two.

[0111] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code that includes one or more executable instructions for implementing the steps of a specific logical function or process, and the scope of the preferred embodiments of the present invention includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by those skilled in the art to which the embodiments of the present invention belong.

[0112] It should be understood that the various parts of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, a plurality of steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution device. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0113] A person skilled in the art may understand that all or part of the steps in the method for implementing the above-mentioned embodiment may be completed by instructing related hardware through a program, and the corresponding program may be stored in a computer-readable storage medium, which, when executed, includes one of the steps of the method embodiment or a combination thereof.

[0114] In addition, each functional unit in each embodiment of the present invention may be integrated into a processing module, or each unit may exist physically separately, or two or more units may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0115] The storage medium mentioned above can be a read-only memory, a magnetic disk or an optical disk, etc.

[0116] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0117] The system, method, device, processor and computer-readable storage medium for realizing high-precision and dynamic multipath delay in channel simulation of the present invention are adopted to realize multipath delay with higher precision for simulation of wireless channels with larger bandwidth, ensure the delay resolution and accuracy, and improve the multipath simulation performance of the channel simulation process. In the path delay processing module, the use of multiple RAMs in series can increase the RAM depth, thereby effectively increasing the maximum delay number, and the use of reg delay can improve the delay resolution. The use of high-speed clocks by FPGA can obtain a higher data sampling rate, thereby increasing the channel simulation bandwidth.

[0118] In this specification, the present invention has been described with reference to specific embodiments thereof. However, it is apparent that various modifications and variations may be made without departing from the spirit and scope of the present invention. Therefore, the specification and drawings should be regarded as illustrative rather than restrictive.

Claims

1. A system for realizing high-precision and dynamic multipath delay in channel simulation, characterized in that: The system comprises: The coefficient sending and processing module is used to send dynamic coefficients and update signals through the host computer, and allocate coefficients to each serial part RAM; The path delay processing module is used to write input data to multiple Ultra-RAMs connected in series, introduce a new 1-bit extended address, and obtain the RAM read address; The output data Reg-Delay module is used to rearrange the output data according to the 1-bit extended address so that the output data Reg-Delay module runs at twice the sampling rate of the FPGA clock; The output synchronization module is used to analyze the internal timing and perform final output synchronization.

2. The system for realizing high-precision and dynamic multipath delay in channel simulation according to claim 1, characterized in that: The path delay processing module includes multiple Ultra-RAMs connected in series. Input data is written to each Ultra-RAM by a self-incrementing write address, and a new 1-bit extended address is introduced, so that two 32-bit data in a dual pipeline mode corresponding to each UltraRAM address are obtained to obtain the read address of the UltraRAM.

3. The system for realizing high-precision and dynamic multipath delay in channel simulation according to claim 2, characterized in that: The self-incremented write address of the path delay processing module is specifically: Increment from the first address of RAM to the last address and automatically return to the first address to set the upper limit of the delay coefficient.

4. The system for realizing high-precision and dynamic multipath delay in channel simulation according to claim 2, characterized in that: The path delay processing module obtains the read address of the RAM, specifically: The UltraRAM read address is obtained by subtracting each calculated UltraRAM delay coefficient from the extended write address.

5. The system for realizing high-precision and dynamic multipath delay in channel simulation according to claim 1, characterized in that: The coefficient sending and processing module stores the static delay coefficient in advance before the simulation starts, and sends a small part of the dynamic delay coefficient and the update signal regularly through the external module after the simulation starts.

6. The system for realizing high-precision and dynamic multipath delay in channel simulation according to claim 1, characterized in that: The write address of the 1-bit extended address in the output data Reg-Delay module corresponds to the read address.

7. A method for implementing high-precision, dynamic multipath delay in channel simulation based on the system of claim 1, characterized in that: The method comprises the following steps: (1) The delay coefficient and dynamic range are sent down through the host computer; (2) Perform path delay processing on input data; (3) register delay for dual data pipelines; (4) Synchronize the multipath data and output the final multipath data.

8. The method for realizing high-precision dynamic multipath delay in channel simulation according to claim 1, characterized in that: The step (1) specifically comprises the following steps: (1.1) The PC host sends the static delay coefficient to the FPGA through PCIe and stores it in BRAM; (1.2) Store the dynamic range MUSK during the simulation into BRAM; (1.3) The external module sends the dynamic delay coefficient through AURORA; (1.4) Select the static delay coefficient according to the dynamic range MUSK and the dynamic delay coefficient to obtain the final delay coefficient list; (1.5) The update signal is sent through the external module, and the coefficients are continuously updated to the path delay processing module.

9. The method for realizing high-precision dynamic multipath delay in channel simulation according to claim 1, characterized in that: The step (2) specifically comprises the following steps: (2.1) Generate RAM write address and increment it; (2.2) Write the input data into the deep RAM connected in series by Ultra-RAM; (2.3) The input address is divided into two 32-bit data in the low-order extension area, input into the subtractor, obtains the output address, and reads the output data through the RAM according to the output address.

10. The method for realizing high-precision dynamic multipath delay in channel simulation according to claim 1, characterized in that: The step (3) specifically comprises the following steps: The output data is delayed in registers according to the input address, and data with a sampling rate higher than one times the FPGA clock is delayed.

11. A device for realizing high-precision, dynamic multipath delay in channel simulation, characterized in that: The device comprises: a processor configured to execute computer-executable instructions; A memory storing one or more computer executable instructions, wherein when the computer executable instructions are executed by the processor, the steps of the method for realizing high-precision dynamic multipath delay in channel simulation as described in any one of claims 7 to 10 are implemented.

12. A processor for implementing high-precision, dynamic multipath delay in channel simulation, characterized in that: The processor is configured to execute computer executable instructions. When the computer executable instructions are executed by the processor, the various steps of the method for realizing high-precision dynamic multipath delay in channel simulation described in any one of claims 7 to 10 are implemented.

13. A computer-readable storage medium, characterized in that: A computer program is stored thereon, and the computer program can be executed by a processor to implement the various steps of the method for realizing high-precision dynamic multipath delay in channel simulation as described in any one of claims 7 to 10.

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