A semiconductor device and a method of fabricating the same

Abstract

The application provides a semiconductor device and a preparation method thereof, and is applied to the technical field of semiconductor. In the application, a dielectric layer is arranged on a buried word line structure to isolate the buried word line structure and a corresponding bit line structure, so that the second part of a first work function material layer in the buried word line structure is prevented from being short-circuited with the corresponding bit line structure and from leaking, and other problems caused by the miniaturization of the semiconductor device are avoided, so that the reliability and performance of the semiconductor device are improved. In addition, the first dielectric layer can also be used as an internal component film layer of the bit line structure, such as a gate dielectric layer, so that no additional process is needed, the process flow is simplified, and the manufacturing cost is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and in particular, to a semiconductor device and a preparation method thereof. BACKGROUND

[0002] With the trend of miniaturization of various electronic products, the design of semiconductor devices must also meet the requirements of high integration and high density. For dynamic random access memory (DRAM) with a recessed gate structure, because it can obtain a longer carrier channel length in the same semiconductor substrate to reduce the leakage of the capacitor structure, it has gradually replaced dynamic random access memory with only a planar gate structure under the current mainstream development trend. Generally speaking, dynamic random access memory with a recessed gate structure is formed by a large number of memory cells gathered to form an array region for storing information, and each memory cell can be composed of a transistor component and a capacitor component in series to receive voltage information from a word line (WL) and a bit line (BL). In response to product demand, the density of memory cells in the array region must continue to be improved, which increases the risk of shorting of part of the bit line structure and the buried word line structure. Therefore, the prior art or structure still needs to be further improved to effectively improve the performance and reliability of the related memory device. SUMMARY

[0003] The purpose of the present application is to provide a semiconductor device and a preparation method thereof to avoid the shorting and leakage of the bit line structure and the buried word line structure derived from the miniaturization of the semiconductor device, thereby improving the reliability and performance of the semiconductor device.

[0004] In a first aspect, to solve the above technical problems, the present application provides a semiconductor device, comprising:

[0005] a substrate, the substrate comprising a first region and a second region;

[0006] a plurality of active structures defined by an insulating structure;

[0007] a buried word line structure disposed in the substrate across the plurality of active structures, the insulating structure and extending in a horizontal direction, and the buried word line structure comprising:

[0008] a first work function material layer comprising:

[0009] a first portion located on the first region;

[0010] A second portion is located on the second region and vertically, an upper surface of the second portion is higher than an upper surface of the active structure, and an upper surface of the first portion is lower than the upper surface of the active structure.

[0011] A plurality of word line conductive plugs is in direct contact with the second portion of the first work function material layer.

[0012] In some optional examples, the insulating structure can include:

[0013] A first insulating structure is located on a first region of the substrate.

[0014] A second insulating structure is located on a second region of the substrate, and a width of the second insulating structure in a horizontal direction is greater than a width of the first insulating structure in the horizontal direction.

[0015] In some optional examples, the active structure can include:

[0016] A first active structure is disposed between adjacent first insulating structures.

[0017] A second active structure is disposed between adjacent first and second insulating structures, and a width of the second active structure in a horizontal direction is greater than a width of the first active structure in the horizontal direction.

[0018] In some optional examples, an interface between the first and second portions of the first work function material layer can be located on the second active structure, and an upper surface of the first work function material layer at the interface can be in a gradually decreasing stepped shape in the horizontal direction from the second active structure to the first insulating structure.

[0019] In some optional examples, the buried word line structure can further include a second work function material layer located above the first portion of the first work function material layer.

[0020] In some optional examples, a sidewall of the second work function material layer can be located above the interface between the first and second portions of the first work function material layer, and an upper surface profile of the second work function material layer can be in an arc shape that is concave toward the first insulating structure bottom surface.

[0021] In some optional examples, an upper surface of the second work function material layer located above the interface between the first and second portions of the first work function material layer can be in a gradually decreasing slope shape in the horizontal direction from the second active structure to the first insulating structure.

[0022] In some examples, an upper surface of the second work function material layer at a junction of the first portion and the second portion of the first work function material layer can be gradually lowered in a horizontal direction from the second active structure to the first insulating structure.

[0023] In some examples, the semiconductor device can further include:

[0024] a cap layer over the second work function material layer;

[0025] a dielectric layer over the cap layer and the second portion of the first work function material layer across the plurality of active structures, the plurality of insulating structures, and in a horizontal direction.

[0026] In a second aspect, based on the same inventive concept, the present disclosure provides a semiconductor device, comprising:

[0027] a substrate including a plurality of active structures defined by a plurality of insulating structures;

[0028] a word line trench in the substrate;

[0029] a buried word line structure, comprising:

[0030] a buried portion in the word line trench and having an upper surface no higher than an upper surface of the active structures;

[0031] a protruding portion over the buried portion, wherein in a vertical direction, an upper surface of the protruding portion is higher than the upper surface of all the active structures;

[0032] a plurality of word line conductive plugs in direct contact with the upper surface of the protruding portion.

[0033] In a second aspect, based on the same inventive concept, a method of manufacturing a semiconductor device, comprising:

[0034] a substrate including a first region and a second region;

[0035] a plurality of active structures defined by insulating structures;

[0036] a buried word line structure extending across the plurality of active structures, the insulating structures, and in a horizontal direction in the substrate, and comprising:

[0037] a first work function material layer, comprising:

[0038] a first portion over the first region;

[0039] a second portion located on the second region and vertically higher than the upper surface of the active structure and the upper surface of the first portion;

[0040] a plurality of word line conductive plugs in direct contact with the second portion of the first work function material layer.

[0041] In some optional examples, the buried word line structure can further include:

[0042] a second work function material layer located above the first portion of the first work function material layer.

[0043] In some optional examples, the method of forming the buried word line structure can include:

[0044] forming a plurality of word line trenches extending horizontally in the first region and the second region of the substrate;

[0045] forming a first work function material layer in the word line trenches;

[0046] removing a portion of the first work function material layer in the first region of the substrate;

[0047] forming a second work function material layer on a first portion of the first work function material layer remaining in the first region of the substrate.

[0048] In some optional examples, the insulating structure can include:

[0049] a first insulating structure located on the first region of the substrate;

[0050] a second insulating structure located on the second region of the substrate, and the second insulating structure has a horizontal width greater than a horizontal width of the first insulating structure.

[0051] In some optional examples, a sidewall of the second work function material layer can be located above an interface between the first portion and the second portion of the first work function material layer, and an upper surface profile of the second work function material layer can be arc-shaped concave towards the first insulating structure bottom surface.

[0052] In some optional examples, an upper surface of the second work function material layer located at the interface between the first portion and the second portion of the first work function material layer can be gradually lowered in a horizontal direction from the second insulating structure to the first insulating structure.

[0053] In some optional examples, the method of manufacturing the semiconductor device can further include:

[0054] a cover layer is formed above the second work function material layer;

[0055] a dielectric layer is formed on the cover layer, and the dielectric layer also spans the plurality of active structures, the plurality of insulating structures, and is disposed above the second portion of the first work function material layer in the horizontal direction.

[0056] In the present application, the dielectric layer is disposed on the buried word line structure to isolate the buried word line structure and the corresponding bit line structure, thereby avoiding the short circuit and leakage between the second portion of the first work function material layer in the buried word line structure and the corresponding bit line structure due to the miniaturization of semiconductor devices, and achieving the purpose of improving the reliability and performance of semiconductor devices. Moreover, the newly added dielectric layer can also serve as an internal component film layer of the bit line structure, such as a gate dielectric layer, so that no additional process is needed, i.e., the process flow is simplified and the manufacturing cost is reduced. BRIEF DESCRIPTION OF DRAWINGS

[0057] The accompanying drawings are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and serve to explain the principles of the application, but do not limit the application. In the drawings:

[0058] Figure 1 A top view of a semiconductor device provided in an embodiment of the present application.

[0059] Figures 2 to 23 A structure schematic diagram in the preparation process of a preparation method provided in an embodiment of the present application.

[0060] In the drawings, the reference signs are as follows:

[0061] 100 - substrate, 1 - first region, 2 - second region, AA / BB / CC - tangent direction, STI1 - first insulating structure, STI2 - second insulating structure, ACT1 - first active structure, ACT2 - second active structure, R - word line trench, WL - buried word line structure, 110 - insulating layer, 111 - mask layer, 120 / 120' / 120'' - first work function material layer, 120''.1 - first portion of the first work function material layer, 120''.2 - second portion of the first work function material layer, INT1 - intersection of the first portion 120''.1 and the second portion 120''.1 of the first work function material layer, 130 - photoresist layer, 140 / 140' - second work function material layer, 150 / 150' - cover layer, 160 / 160' - dielectric layer, 170 - gate layer, BL - bit line structure, 180 - first isolation layer, 190 - second isolation layer, WCT - word line conductive plug, BCT - bit line conductive plug.

[0062] In the drawings, like reference numerals refer to same components, and the drawings are not drawn to scale. DETAILED DESCRIPTION

[0063] The semiconductor device and the method of manufacturing the same according to the present application will be described in further detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present application will be more clearly understood from the following description. It should be noted that the drawings are very simplified and are not drawn to scale, and are used only to facilitate, clarify and assist in the understanding of the embodiments of the present application. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. However, the present application can be practiced without the specific details.

[0064] Reference will now be made to Figure 1 and Figure 22 , Figure 1 are top views of a semiconductor device according to some embodiments, Figure 22 are partial cross-sectional views of a semiconductor device according to a first embodiment of the present application along the AA, BB, CC directions shown in Figure 1 As shown in Figure 1 and Figure 22 , the semiconductor device can include a substrate 100, a plurality of insulating structures, a plurality of active structures, a plurality of buried word line structures WL, and a plurality of word line conductive plugs WCT.

[0065] In an embodiment, the substrate 100 has a first region 1 and a second region 2 defined thereon. The first region 1 can also be referred to as an array region, in which memory cells such as dynamic random access memory cells are disposed; the second region 2 can also be referred to as a periphery region, in which buried word line structures WL and bit line structures electrically connected to peripheral circuits are disposed for controlling operation of the memory cells, and the second region 2 is disposed adjacent to the first region 1, but is not limited thereto. The substrate 100 can have a plurality of insulating structures disposed thereon, the insulating structures defining a plurality of active structures on the first region 1 of the substrate 100 and isolating adjacent active structures, i.e., the plurality of insulating structures and the plurality of active structures are disposed on the substrate 100 in an adjacent arrangement; and the plurality of insulating structures can be specifically divided into first insulating structures STI1 on the first region 1 and second insulating structures STI2 on the second region 2 according to differences in width of the insulating structures in a direction parallel to the surface of the substrate 100 (hereinafter referred to as a horizontal direction), and the second insulating structures STI2 have a greater width in the horizontal direction than the first insulating structures STI1, and different first insulating structures STI1 or different second insulating structures STI2 can also have different widths in the horizontal direction, but are not limited thereto. Similarly, the plurality of active structures can also be specifically divided into first active structures ACT1 on the first region 1 and second active structures ACT2 substantially at the boundary region between the first region 1 and the second region 2 according to differences in width of the active structures in the horizontal direction, and the second active structures ACT2 have a greater width in the horizontal direction than the first active structures ACT1, but are not limited thereto. Specifically, the first active structures ACT1 can be disposed between adjacent first insulating structures STI1, and the second active structures ACT2 can be disposed between adjacent first insulating structures STI1 and second insulating structures STI2, but are not limited thereto.

[0066] In an embodiment, the semiconductor device can further include an insulating layer 110 on the surface of the insulating structures and active structures; the buried word line structures WL can span the plurality of first active structures ACT1, the plurality of second active structures ACT2, the plurality of first insulating structures STI1, and the plurality of second insulating structures STI2 in the horizontal direction and be disposed in word line trenches in the substrate 100 to bury the plurality of active structures and the plurality of insulating structures. In detail, the buried word line structures WL are on the insulating layer 110 in the word line trenches and can include a first work function material layer 120”, a second work function material layer 140’, and a cap layer 150’ disposed in sequence in a direction perpendicular to the surface of the substrate 100 (hereinafter referred to as a vertical direction).

[0067] In detail, the first work function material layer 120" can be divided into a first portion 120".1 and a second portion 120".2 in a horizontal direction, the first portion 120".1 of the first work function material layer 120" is located on at least a portion of the surface of the second active structure ACT2 and on the first insulating structure STI1 and the first active structure ACT1, the second portion 120".2 of the first work function material layer 120" is located on a remaining portion of the surface of the second active structure ACT2 and on a portion of the surface of the second insulating structure STI2, and in a vertical direction, an upper surface of the second portion 120".2 of the first work function material layer 120" can be higher than upper surfaces of all the first active structure ACT1 and the second active structure ACT2, and an upper surface of the first portion 120".1 of the first work function material layer 120" can be lower than an upper surface of the first active structure ACT1. The second work function material layer 140' is located above the first portion 120".1 of the first work function material layer 120", and the cap layer 150' is located above the second work function material layer 140'.

[0068] In the present embodiment, the interface INT1 between the first portion 120".1 and the second portion 120".2 of the first work function material layer 120" can be located on the second active structure ACT2, and an upper surface of the first work function material layer 120" at the interface INT1 can be gradually lowered in a horizontal direction from the second active structure ACT2 to the first insulating structure STI1, a sidewall of the second work function material layer 140' can be located above the interface INT1 between the first portion 120".1 and the second portion 120".2 of the first work function material layer 120", and an upper surface profile of the second work function material layer 140' can be irregularly concave toward a bottom surface of the first insulating structure STI1, for example, gradually lowered in a horizontal direction from the second active structure ACT2 to the first insulating structure STI1, as shown in FIG. 1C. Figure 22The L-shaped profile is shown, but is not limited thereto. Under this arrangement, the highest end of the upper surface of the second work function material layer 140' is at the same height as the upper surface of the second portion 120".2 of the first work function material layer 120", and there is a height difference between the highest end of the upper surface and the lowest end of the upper surface, i.e. the height of the sidewall of the second work function material layer 140', and the top surface of the cover layer 150' is lower than the highest end of the upper surface of the second work function material layer 140', i.e. the cover layer 150' only covers part of the sidewall of the second work function material layer 140'. Under this arrangement, the buried word line structure WL as a whole can include a buried portion arranged in the word line trench and having an upper surface not higher than the upper surface of the first active structure ACT1, and a protruding portion arranged above the buried portion and having an upper surface higher than the upper surfaces of the first active structure ACT1 and the second active structure ACT2, as shown in Figure 22 The area enclosed by the middle black dashed line is the protruding portion of the buried word line structure WL of the present application, which is higher than the upper surface of the active structure. Compared with the buried portion, the surface of the protruding portion is closer to the top of the bit line structure BL in the vertical direction, i.e. the difference between the protruding portion and the top of the bit line structure in the vertical direction is reduced, which is beneficial to the subsequent formation of the word line conductive plug WCT / bit line conductive plug BCT.

[0069] In one embodiment, the semiconductor device further comprises a plurality of bit line structures BL, a first isolation layer 180, a second isolation layer 190 and a bit line conductive plug BCT disposed on the substrate 100, the bit line structures BL extend along a direction perpendicular to the extending direction of the buried word line structures WL and are arranged in the middle region of the first active structures ACT1 or the second active structures ACT2 to control the source of the transistor of the memory cell. The first isolation layer 180 is wrapped on the outer surface of the bit line structure BL and extends to cover the exposed cap layer 150', the second work function material layer 140', the second portion 120".2 of the first work function material layer 120" and the second isolation structure STI2. The second isolation layer 190 is fully covering on the substrate 100, the word line conductive plug WCT is located on the buried word line structure WL and directly contacts the second portion 120".2 (i.e. the protruding portion) of the first work function material layer 120" under the second isolation layer 190 and the first isolation layer 180; the bit line conductive plug BCT is located on the bit line structure BL. In detail, the bit line structure BL can generally comprise a gate layer 170 and a dielectric layer 160' stacked in sequence along the vertical direction. The material of the dielectric layer 160' can comprise a dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbon nitride (SiCN), or a combination thereof, but not limited thereto, and the material of the gate layer 170 can comprise tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or a compound, alloy and / or composite layer of the aforementioned metal materials, but not limited thereto. Moreover, the dielectric layer 160' can be a single layer structure, such as a silicon oxide layer or a silicon nitride layer, or a composite layer, such as an ONO composite layer composed of a silicon oxide layer, a silicon nitride layer and a silicon oxide layer, but not limited thereto.

[0070] In the embodiment of the present application, after forming the cap layer 150' of the buried word line structure WL, a dielectric material, such as silicon dioxide or silicon nitride, and a gate material, such as tungsten (W), are formed on the substrate 100 to fully cover the active structures and the isolation structures, and then a portion of the dielectric material and the gate material are removed by etching along the vertical direction to form a plurality of bit line structures BL arranged in a spaced-apart manner. The additional dielectric material serves as both the gate dielectric layer of the bit line structure BL and the isolation layer between the bit line structure BL and the second portion 120".2 of the first work function material layer 120" in the buried word line structure WL. Therefore, the preparation method provided by the embodiment of the present application can achieve the purpose of isolating the buried word line structure and the corresponding bit line structure without additional process, and can simplify the process flow and reduce the manufacturing cost.

[0071] In some embodiments, the substrate 100 can be any suitable substrate material known in the art, such as a silicon substrate, a silicon-containing substrate (e.g., SiC, SiGe), a silicon-on-insulator substrate, or a substrate composed of other suitable materials, without limitation. The materials of the first and second insulating structures STI1, STI2 can include a single layer or multiple layers of insulating materials, such as oxide insulating materials, nitride insulating materials, or other suitable insulating materials, without limitation. The material of the first work function material layer 120" in the buried word line structure WL can include a single layer or multiple layers of conductive materials, such as titanium nitride, titanium carbide, tantalum nitride, tantalum carbide, tungsten nitride, tungsten carbide, titanium aluminide, aluminum nitride, titanium, tungsten, aluminum, copper, titanium, tantalum, or other suitable metallic or non-metallic conductive materials, without limitation. The material of the second work function material layer 140' can include doped polysilicon, undoped polysilicon, or other materials different from the conductive layer, without limitation. The materials of the cap layer 150', the first and second isolation layers 180, 190 can include dielectric materials, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbon nitride (SiCN), nitrogen-doped silicon carbide (NDC), or combinations thereof, without limitation. The materials of the word line conductive plug WCT and the bit line conductive plug BCT can be tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or compounds, alloys, and / or composite layers of the foregoing, without limitation.

[0072] Those of ordinary skill in the art of the present disclosure will readily understand that the semiconductor device of the present disclosure can have other configurations without being limited to the foregoing, provided that the semiconductor device meets the requirements of actual products. Further embodiments or variations of the semiconductor device of the present disclosure will be described below. For simplicity of description, the following description mainly focuses on the differences between the embodiments, and the same parts will not be described repeatedly. In addition, the same components in the embodiments of the present disclosure are denoted by the same reference numerals, so as to facilitate mutual comparison between the embodiments.

[0073] Please refer to Figure 23 and combine with Figure 1 , wherein Figure 23Fig. 2 shows a sectional view of a semiconductor device according to a second embodiment of the present application. The semiconductor device according to the second embodiment has substantially the same structure as the semiconductor device according to the first embodiment, and includes a plurality of first active structures ACT1, a plurality of second active structures ACT2, a plurality of first isolation structures STI1, a plurality of second isolation structures STI2, a plurality of buried word line structures WL, and a plurality of word line conductive plugs WCT. The main difference between the semiconductor device according to the second embodiment and the semiconductor device according to the first embodiment is that the upper surface profile of the second work function material layer 140' in the buried word line structure WL is concave in the direction of the bottom surface of the first insulating structure STI1, for example, in the form of a gradually decreasing slope in the horizontal direction from the second active structure ACT2 to the first insulating structure STI1, but is not limited thereto. With this arrangement, the problem of short circuiting and leakage between the second portion 120".2 of the first work function material layer 120" in the buried word line structure WL and the corresponding bit line structure BL can be avoided as the size of the semiconductor device is reduced.

[0074] It should be particularly noted that, for the purpose of simplification, the upper surface profile of the second portion 120".2 of the first work function material layer 120" in the first and second embodiments can be in the form of a planar structure as shown in Figure 22 or Figure 23 However, for the purpose of conforming to the actual semiconductor manufacturing result, the upper surface profile of the second portion 120".2 of the first work function material layer 120" can also be in the form of a curved surface structure as shown in Figure 6 but is not limited thereto.

[0075] For the purpose of enabling those skilled in the art to easily understand the manufacturing method of the semiconductor device according to the embodiments of the present application, the manufacturing method of the semiconductor device according to the embodiments of the present application will be further described below with reference to the structural schematic views of the manufacturing method of the semiconductor device according to the embodiments of the present application in the preparation process.

[0076] Please refer to Figures 2 to 23 , which shows the structural schematic views of the manufacturing method of the semiconductor device according to the embodiments of the present application in the preparation process.

[0077] As shown in Figure 2 and Figure 3As shown, first, a substrate 100 is provided, and a plurality of trenches are formed in the substrate 100 by using an etching process, and then an insulating material (e.g., silicon oxide, silicon nitride, etc.) is filled in the plurality of trenches by using a deposition process (e.g., at least one of a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process) to form a plurality of first isolation structures STI1 on a first region 1 of the substrate 100 and a plurality of second isolation structures STI2 on a second region 2 of the substrate 100, and to define a first active structure ACT1 on the substrate 100 between adjacent first isolation structures STI1 and to define a second active structure ACT2 on the substrate 100 between adjacent first and second isolation structures STI1 and STI2. In an embodiment, the second isolation structures STI2 have a width in a horizontal direction that is greater than a width in the horizontal direction of the first isolation structures STI1, and the second active structure ACT2 has a width in the horizontal direction that is greater than a width in the horizontal direction of the first active structure ACT1, but the application is not limited thereto.

[0078] Next, a plurality of word line trenches R extending in a horizontal direction are formed in the substrate 100 corresponding to the first region 1 and the second region 2 by using an etching process (e.g., at least one of a dry etching process or a wet etching process), and then a mask layer 111 (e.g., silicon nitride) is formed on the active structures and the isolation structures by using at least one of the deposition processes, and an insulating layer 110 (e.g., oxide), a first work function material layer 120 (e.g., tungsten), and a patterned photoresist layer 130 are sequentially formed in the word line trenches R. In an embodiment, the insulating layer 110 and the first work function material layer 120 also extend on the top surface of the second isolation structures STI2 and the substrate 100 outside the word line trenches R, and the patterned photoresist layer 130 exposes the top surface of the first work function material layer 120 on the first active structure ACT1, the first isolation structures STI1, and part of the second active structure ACT2 to prepare for a subsequent etching process.

[0079] As shown in FIGS. 1C and 1D, a first etching process is performed on the first work function material layer 120 with the patterned photoresist layer 130 as a mask to remove part of the first work function material layer 120, and the top surface of the remaining first work function material layer 120 in the word line trenches R in the first region 1 is lower than the top surface of the active structure, and the top surface of the remaining first work function material layer 120 in the word line trenches R in the second region 2 is higher than the top surface of the active structure. In particular, the first work function material layer 120 is etched to form a first work function material layer 120a in the word line trenches R in the first region 1 and a first work function material layer 120b in the word line trenches R in the second region 2. Figure 4 and Figure 5 As shown in FIGS. 1C and 1D, a first etching process is performed on the first work function material layer 120 with the patterned photoresist layer 130 as a mask to remove part of the first work function material layer 120, and the top surface of the remaining first work function material layer 120 in the word line trenches R in the first region 1 is lower than the top surface of the active structure, and the top surface of the remaining first work function material layer 120 in the word line trenches R in the second region 2 is higher than the top surface of the active structure. In particular, the first work function material layer 120 is etched to form a first work function material layer 120a in the word line trenches R in the first region 1 and a first work function material layer 120b in the word line trenches R in the second region 2. Figure 4As shown in the structure, at this time, since the top surface of the first work function material layer 120 in the second region 2 is covered with the patterned photoresist layer 130, its height is not changed after this etching, while the first work function material layer 120 on the first region 1 is removed in the vertical direction, that is, after the first etching, the top surface of the remaining first work function material layer on the first region 1 can be at the same height as the top surface of the mask layer 111, while the top surface of the remaining first work function material layer on the second region 2 is higher than the top surface of the insulating layer 110 (that is, higher than the top surface of the remaining first work function material layer on the second region 2); for example, the first work function material layer remaining after the first etching is denoted by reference numeral 120' in the embodiment of the present application, wherein the portion of the first work function material layer 120' on the first region 1 is denoted by reference numeral 120'.1, and the portion of the first work function material layer 120' on the second region 2 is denoted by reference numeral 120'.2, and the interface between the two is denoted by reference numeral INT1; then, the patterned photoresist layer 130 is removed, and the first work function material layer 120' is further etched in the vertical direction to form a structure as shown in Figure 5 that is, after the second etching, the top surface of the remaining first work function material layer on the first region 1 is lower than the top surface of the substrate 100 (that is, the active structure), while the top surface of the remaining first work function material layer on the second region 2 is at the same height as the top surface of the mask layer 111; obviously, the second etching deepens the height difference of the remaining first work function material layer on the first region 1 and the second region 2 in the vertical direction; for example, the first work function material layer remaining after the second etching is denoted by reference numeral 120" in the embodiment of the present application, wherein the portion of the first work function material layer 120" on the first region 1 is denoted by reference numeral 120".1 (hereinafter referred to as the first portion 120".1), and the portion of the first work function material layer 120" on the second region 2 is denoted by reference numeral 120".2 (hereinafter referred to as the second portion 120".2), and the interface between the two is also denoted by reference numeral INT1.

[0080] It should be particularly noted that, for the sake of simplification of drawing, the upper surface profile of the second portion 120".2 of the first work function material layer 120" can be a planar structure as shown in Figure 5 for the sake of actual semiconductor process results, the upper surface profile of the second portion 120".2 of the first work function material layer 120" can also be a concave-convex curved arc surface structure as shown in Figure 6 Figure 6 the black dashed box in the middle), but is not limited thereto. Furthermore, for the sake of further simplification of drawing, the first portion 120".1 and the second portion 120".2 of the first work function material layer 120" in the embodiment of the present application are both in the same plane as the top surface of the mask layer 111. Figures 7 to 23 Figure 5 ​​The upper surface profile of the second part 120”.2 of the first work function material layer 120” shown is based on a planar structure, and subsequent related manufacturing processes are carried out accordingly.

[0081] like Figures 7 to 9 As shown, a deposition process can then be used to form a second work function material layer 140 (e.g., polysilicon) that completely covers the first portion 120”.1 and the second portion 120”.2 of the first work function material layer 120” on the substrate 100. Subsequently, a portion of the second work function material layer 140 is removed vertically using an etching process to form a layer as shown. Figure 8 The structure is shown, and the remaining second work function material layer 140 after etching is exemplarily identified by reference numeral 140'. In one embodiment, as... Figure 8 As shown, the sidewalls and bottom of the second work function material layer 140' may have an L-shaped profile, that is, the upper surface profile of the second work function material layer 140' may be a step that gradually decreases in the horizontal direction from the second active structure ACT2 to the first insulating structure STI1, and the sidewalls of the second work function material layer 140' are located above the junction INT1 of the first portion 120".1 and the second portion 120".2 of the first work function material layer 120"", but are not limited thereto. In another embodiment, as Figure 9 As shown, the sidewalls and bottom of the second work function material layer 140' have arc-shaped profiles. That is, the upper surface profile of the second work function material layer 140' can be a gradually decreasing slope in the horizontal direction from the second active structure ACT2 to the first insulating structure STI1. The sidewalls of the second work function material layer 140' can also be located above the junction of the first part 120".1 and the second part 120".2 of the first work function material layer 120", but are not limited thereto.

[0082] It should be understood that, as follows: Figures 10 to 23 They are based on Figure 8 or Figure 9 The structures shown are obtained by performing the same subsequent manufacturing processes. Therefore, for the sake of simplicity, the following embodiments of the present invention are all described using two accompanying drawings corresponding to the same manufacturing process.

[0083] like Figure 10 or Figure 11 As shown, a capping layer 150 (e.g., silicon oxynitride) is then formed on the substrate 100 using a deposition process to completely cover the first work function material layer 120” on the active structure and the insulating structure. The portion of the capping layer 150 located on the first region 1 vertically fills the first insulating structure STI1 and is in direct contact with the second work function material layer 140' located therein.

[0084] As shown in Figure 12 or Figure 13 , then a part of the height of the covering layer 150 is removed in the vertical direction by using an etching process, so that the remaining covering layer 150' is only located on the first region 1, and the top surface of the covering layer 150' is flush with the surface of the substrate 100 (i.e. the top surface of the first active structure ACT1).

[0085] As shown in Figure 14 or Figure 15 , then the insulating layer 110 and the mask layer 111 on the substrate 100 are removed by using an etching process, so that the surface of the substrate 100 on both sides of the adjacent word line trench R on the first region 1 is exposed, and the surface of the second insulating structure STI2 on both sides of the adjacent word line trench R on the second region 2 is exposed, at this time, the top surface of the second part 120”.2 of the first work function material layer of the word line trench R located in the second region 2 is higher than the surface of the substrate 100.

[0086] As shown in Figure 16 or Figure 17 , then a medium layer 160 is formed on the substrate 100 by using a deposition process, which fully covers the second part 120”.2 of the first work function material layer 120” and the covering layer 150’ on the active structure and the insulating structure, wherein the medium layer 160 can be a single layer structure, such as a silicon oxide layer or a silicon nitride layer, or a composite layer, such as an ONO composite layer composed of a silicon oxide layer, a silicon nitride layer and a silicon oxide layer, but is not limited to this; at this time, the medium layer 160 on the second region 1 wraps the top surface and the sidewall of the second part 120”.2 of the first work function material layer 120” exposed on the second region 2. Obviously, the medium layer 160 is formed after the covering layer 150’ of the buried word line structure WL is formed and before the bit line structure BL is formed in the embodiment of the present application, so that the second part 120”.2 of the first work function material layer 120” in the buried word line structure WL is isolated from the corresponding bit line structure BL by the medium layer 160, which avoids the short circuit and the leakage between the second part 120”.2 of the first work function material layer 120” in the buried word line structure WL and the corresponding bit line structure BL due to the miniaturization of the semiconductor device.

[0087] As shown in Figure 18 or Figure 19As shown, a gate material layer (not shown) can then be further formed on the dielectric layer 160, and a portion of the gate material layer and dielectric layer 160 can be removed using an etching process to form multiple bit line structures BL composed of the etched gate layer 170 and the remaining dielectric layer 160'. The bit line structures BL extend in a direction perpendicular to the extension direction of the buried word line structure WL and are arranged at intervals in the middle region of the first active structure ACT1 or the second active structure ACT2. In other embodiments, the top and side dielectric layers 160 of the second portion 120”.2 can be retained. In one embodiment, the gate material layer... Materials may include tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or compounds, alloys, and / or composite layers of the aforementioned metals, but are not limited thereto. Clearly, in this embodiment of the invention, the dielectric layer 160' serves not only as an isolation layer between the second portion 120" of the first work function material layer 120" in the bit line structure BL and the embedded word line structure WL, but also as the gate dielectric layer of the bit line structure BL. Therefore, the fabrication method provided in this embodiment of the invention can achieve the purpose of isolating the embedded word line structure and the corresponding bit line structure without adding additional processing steps, while simultaneously simplifying the process flow and reducing manufacturing costs.

[0088] like Figure 20 or Figure 21 As shown, a first isolation layer 180 (e.g., silicon nitride) is then formed on the substrate 100. The first isolation layer 180 covers the outer surface of the bit line structure BL and extends to cover the top surface of the second portion 120”.2 of the cover layer 150' and the first work function material layer 120”” in the embedded word line structure WL. At this time, the first isolation layer 180 wraps the top surface and sidewalls of the second portion 120”.2 of the first work function material layer 120”” exposed on the second region 2. In other embodiments, the first isolation layer 180 may cover the surface of the dielectric layer 160, which covers the top and side of the second portion 120”.2.

[0089] like Figure 22 or Figure 23As shown, then a second isolation layer 190 (e.g. silicon oxide or silicon nitride) is formed on the substrate 100, which buries both the first and second semiconductor components (e.g. bit line structure BL) in the first and second regions 1 and 2, respectively, and a plurality of word line conductive plugs WCT directly contacting the second portion 120”.2 of the second portion 120”.2 of the first work function material layer 120” through the second isolation layer 190 and the first isolation layer 180 thereunder, and a plurality of bit line conductive plugs BCT directly contacting the gate layer 170 in the bit line structure through the second isolation layer 190 and the first isolation layer 180. In an embodiment, the material of the word line conductive plugs WCT and the bit line conductive plugs BCT can be tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or a compound, alloy, and / or composite layer of the aforementioned metal materials, but not limited thereto.

[0090] In summary, in the present application, the medium layer is arranged on the buried word line structure to isolate the buried word line structure and the corresponding bit line structure, so as to avoid the short circuit and leakage between the second portion of the first work function material layer in the buried word line structure and the corresponding bit line structure, which is derived from the miniaturization of the semiconductor device, so as to achieve the purpose of improving the reliability and performance of the semiconductor device. Moreover, the newly added medium layer can also serve as an internal component film layer of the bit line structure, such as a gate dielectric layer, so that no additional process is needed, that is, the process flow is simplified and the manufacturing cost is reduced.

[0091] It should be noted that the relational terms herein such as first and second, and the like, are used solely to distinguish one from another entity or action, without necessarily requiring or implying any such actual relationship or order between such entities or actions. Moreover, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element preceded by "comprises... a" does not, without more constraints, foreclose the existence of additional identical elements in the process, method, article, or apparatus that comprises the recited element.

[0092] Each of the embodiments in the present specification is described in a related manner, and the same or similar parts between the embodiments can be referred to each other. Each embodiment focuses on the difference from other embodiments. In particular, for the device, electronic device, and computer readable storage medium embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the part of the method embodiment.

[0093] The above merely provides the preferred embodiments of the application, and not intended to limit the protection scope of the application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the application shall fall within the protection scope of the application.

Claims

1. A semiconductor device, characterized by, Comprising: a substrate comprising a first region and a second region; a plurality of active structures defined by insulating structures; a buried word line structure disposed in the substrate across the plurality of active structures, the insulating structures and extending in a horizontal direction, and the buried word line structure comprising: a first work function material layer comprising: a first portion on the first region; a second portion on the second region, and in a vertical direction, a top surface of the second portion is higher than a top surface of the active structure, and a top surface of the first portion is lower than the top surface of the active structure; a dielectric layer on the first work function material layer; and a plurality of word line conductive plugs in direct contact with the second portion of the first work function material layer.

2. The semiconductor device of claim 1, wherein, the insulating structures comprising: a first insulating structure on the first region of the substrate; a second insulating structure on the second region of the substrate, and a width of the second insulating structure in the horizontal direction is greater than a width of the first insulating structure in the horizontal direction.

3. The semiconductor device of claim 2, wherein, the active structures comprising: a first active structure disposed between adjacent first insulating structures; a second active structure disposed between adjacent first and second insulating structures, and a width of the second active structure in the horizontal direction is greater than a width of the first active structure in the horizontal direction.

4. The semiconductor device of claim 3, wherein, an interface of the first and second portions of the first work function material layer is on the second active structure, and a top surface of the first work function material layer at the interface is in a gradually decreasing stepped shape in the horizontal direction from the second active structure to the first insulating structure.

5. The semiconductor device of claim 3, wherein, the buried word line structure further comprising:

6. The semiconductor device of claim 5, wherein, a second work function material layer on the first portion of the first work function material layer.

7. The semiconductor device of claim 6, wherein the first and second semiconductor layers are formed of a same material. a sidewall of the second work function material layer is on the interface of the first and second portions of the first work function material layer, and a top surface of the second work function material layer is in a gradually decreasing arc shape in the horizontal direction from the second active structure to the first insulating structure.

8. The semiconductor device of claim 5, wherein, a top surface of the second work function material layer on the interface of the first and second portions of the first work function material layer is in a gradually decreasing slope shape in the horizontal direction from the second active structure to the first insulating structure.

9. The semiconductor device of claim 5, wherein, a top surface of the second work function material layer on the interface of the first and second portions of the first work function material layer is in a gradually decreasing stepped shape in the horizontal direction from the second active structure to the first insulating structure. further comprising: a cap layer on the second work function material layer; 10. A semiconductor device, characterized by comprising: a dielectric layer disposed on the cap layer and the second portion of the first work function material layer across the plurality of active structures, the insulating structures and in the horizontal direction. Comprising: a substrate comprising a plurality of active structures defined by a plurality of insulating structures; a word line trench in the substrate; a buried word line structure comprising: a buried portion in the word line trench, and a top surface thereof is not higher than a top surface of the active structures; a protruding portion on the buried portion, wherein in a vertical direction, a top surface of the protruding portion is higher than the top surface of all the active structures; a dielectric layer on the buried word line structure; a plurality of word line conductive plugs in direct contact with the upper surface of the protruding portion.

11. A semiconductor device, characterized by comprising: comprising: a substrate comprising a first region and a second region; a plurality of active structures defined by insulating structures; a buried word line structure disposed in the substrate across the plurality of active structures, the insulating structures and extending in a horizontal direction, and the buried word line structure comprising: a first work function material layer comprising: a first portion on the first region; a second portion on the second region, and in a vertical direction, an upper surface of the second portion is higher than an upper surface of the active structure, and an upper surface of the first portion is lower than the upper surface of the active structure; a dielectric layer on the first work function material layer; a bit line structure on the dielectric layer; a first isolation layer on a sidewall of the bit line and laterally extending on the second portion of the first work function material layer; and a plurality of word line conductive plugs through the first isolation layer and in direct contact with the second portion of the first work function material layer.

12. A method of manufacturing a semiconductor device, characterized by, comprising: providing a substrate comprising a first region and a second region; forming a plurality of active structures defined by insulating structures; forming a buried word line structure disposed in the substrate across the plurality of active structures, the insulating structures and extending in a horizontal direction, and the buried word line structure comprising: forming a first work function material layer comprising: a first portion on the first region; a second portion on the second region, and in a vertical direction, an upper surface of the second portion is higher than an upper surface of the active structure, and an upper surface of the first portion is lower than the upper surface of the active structure; forming a dielectric layer on the first work function material layer; and forming a plurality of word line conductive plugs in direct contact with the second portion of the first work function material layer.

13. The method of producing a semiconductor device according to Claim 12, wherein the buried word line structure further comprises: a second work function material layer on the first portion of the first work function material layer.

14. The method of producing a semiconductor device according to Claim 13, wherein the step of forming the buried word line structure comprises: forming a plurality of word line trenches disposed in a horizontal direction in the first region and the second region of the substrate, respectively; forming a first work function material layer in the word line trenches; removing the first work function material layer in a portion of height of the first region of the substrate; forming a second work function material layer on the first portion of the first work function material layer remaining in the first region of the substrate.

15. The method of producing a semiconductor device according to Claim 14, wherein the insulating structures comprise: a first insulating structure on the first region of the substrate; a second insulating structure on the second region of the substrate, and a width of the second insulating structure in the horizontal direction is greater than a width of the first insulating structure in the horizontal direction.

16. The method of producing a semiconductor device according to Claim 15, wherein a sidewall of the second work function material layer is on the interface between the first portion and the second portion of the first work function material layer, and an upper surface profile of the second work function material layer is in an arc shape concave towards the bottom surface of the first insulating structure.

17. The method of producing a semiconductor device according to Claim 15, wherein An upper surface of the second work function material layer at a junction of the first portion and the second portion of the first work function material layer is gradually lowered in a horizontal direction from the second insulating structure to the first insulating structure.

18. The method of producing a semiconductor device according to Claim 14, wherein Also comprising: a cover layer formed over the second work function material layer; a dielectric layer formed over the cover layer, and further across the plurality of active structures, the plurality of insulating structures, and over the second portion of the first work function material layer in a horizontal direction.

19. A semiconductor device, characterized by comprising: Comprising: a substrate comprising a plurality of active structures defined by a plurality of insulating structures; a word line trench within the substrate; a buried word line structure comprising: a buried portion within the word line trench, and an upper surface of the buried portion not higher than an upper surface of the active structures; a protruding portion over the buried portion, wherein in a vertical direction, an upper surface of the protruding portion is higher than the upper surface of all the active structures; a dielectric layer over the buried word line structure; a bit line structure over the dielectric layer; a first isolation layer on a sidewall of the bit line structure and laterally extending onto the protruding portion of the buried word line structure; and a plurality of word line conductive plugs through the first isolation layer and directly contacting the upper surface of the protruding portion.

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