Three-dimensional vertical NOR flash thin film transistor string

Abstract

A memory structure includes active columns of polysilicon formed over a semiconductor substrate, each active column including one or more vertical NOR strings, where each NOR string has thin film memory transistors sharing local source lines and local bit lines, the local bit line is connected by a segment of the segmented global bit line to a sense amplifier provided in the semiconductor substrate.

Description

[0001] This application is a divisional application of Chinese patent application No. 201980024463.2, whose application date is January 18, 2019 and whose invention name is “Three-dimensional vertical NOR flash thin film transistor string”. Technical Field

[0002] The present invention relates to a high density memory structure. In particular, the present invention relates to a high density memory structure formed by thin film memory elements (such as thin film memory transistors formed in vertical strips) interconnected by horizontal word lines. Background Art

[0003] In the present disclosure, memory circuit structures are described. These structures can be fabricated on a flat semiconductor substrate (e.g., a silicon wafer) using conventional fabrication processes. For ease of clarity of this description, the term "vertical" refers to a direction perpendicular to the surface of a semiconductor substrate, and the term "horizontal" refers to any direction parallel to the surface of a semiconductor substrate.

[0004] In the prior art, many high-density non-volatile memory structures are known, such as "three-dimensional vertical NAND strings". Many of these high-density memory structures are formed using thin-film storage transistors composed of deposited thin films (e.g., polycrystalline silicon films) and organized into arrays of "memory strings". One type of memory string is called a NAND memory string or simply a "NAND string". A NAND string includes many thin-film storage transistors (TFTs) connected in series. Reading or programming the contents of any series TFT requires activating all series TFTs in the string. The conductivity of thin-film NAND transistors is lower than that of NAND transistors formed in single crystal silicon, and therefore, the low read current that needs to be conducted through a long string of NAND TFTs results in a relatively slow read access speed (i.e., a longer delay).

[0005] Another type of high-density memory structure is known as a NOR memory string or "NOR string". A NOR string includes a plurality of memory transistors, each memory transistor being connected to a shared source region and a shared drain region. Thus, the transistors in the NOR string are connected in parallel, so that the read current in the NOR string conducts a much smaller resistance than the read current through the NAND string. To read or program a memory transistor in a NOR string, only the memory transistor needs to be activated (i.e., "turned on" or conducting), and all other memory transistors in the NOR string can remain dormant (i.e., "turned off" or not conducting). Thus, the NOR string allows for faster sensing of the activated memory transistor to be read. Conventional NOR transistors are programmed by channel hot electron injection techniques, in which when an appropriate voltage is applied to the control gate, electrons are accelerated in the channel region by the voltage difference between the source region and the drain region and the electrons are injected into a charge trapping layer between the control gate and the channel region. Channel hot electron injection programming requires a relatively large electron current to flow through the channel region, thereby limiting the number of transistors that can be programmed in parallel. Unlike transistors programmed by hot electron injection, in transistors programmed by Fowler-Nordheim tunneling or by direct tunneling, electrons are injected from the channel region into the charge-trapping layer by a high electric field applied between the control gate and the source and drain regions. The efficiency of Fowler-Nordheim tunneling and direct tunneling is several orders of magnitude higher than that of channel hot electron injection, allowing massive parallel programming; however, such tunneling is more susceptible to program disturb conditions.

[0006] A three-dimensional NOR memory array is disclosed in US Patent 8,630,114 to HT Lue, entitled “Memory Architecture of 3D NOR Array,” filed on March 11, 2011 and issued on January 14, 2014.

[0007] U.S. Patent Application Publication US2016 / 0086970A1 by Haibing Peng, entitled “Three-Dimensional Non-Volatile NOR-type Flash Memory,” filed on September 21, 2015 and published on March 24, 2016, discloses a non-volatile NOR flash memory device comprising an array of basic NOR memory groups in which individual memory cells are stacked in a horizontal direction parallel to a semiconductor substrate, wherein source and drain electrodes are shared by all field effect transistors located on one side or two opposite sides of a conductive channel.

[0008] Three-dimensional vertical memory structures are disclosed, for example, in U.S. Patent 8,878,278 ("Alsmeier"), entitled "Compact Three-Dimensional Vertical NAND and Methods of Making Thereof," filed on January 30, 2013, and issued on November 4, 2014, by Alsmeier et al. Alsmeier discloses various types of high-density NAND memory structures, such as "TB Cell Array Transistor" (TCAT) NAND arrays (FIG. 1A), "Public Bit Cost Scalable" (P-BiCS) flash memory (FIG. 1B), and "Vertical NAND" memory string structures. Similarly, U.S. Pat. No. 7,005,350 (“Walker I”) to Walker et al., entitled “Method for Fabricating Programmable Memory Array Structures Incorporating Series-Connected Transistor Strings,” filed on Dec. 31, 2002 and issued on Feb. 28, 2006, also discloses many three-dimensional high-density NAND memory structures.

[0009] U.S. Patent 7,612,411 to Walker, entitled “Dual-Gate Device and Method,” filed on August 3, 2005 and issued on November 3, 2009 (“Walker II”), discloses a “dual-gate” memory structure in which a common active area is used as separately controlled storage elements in two NAND strings formed on opposite sides of the common active area.

[0010] A three-dimensional NOR memory array is disclosed in US Patent No. 8,630,114 to HT Lue, entitled “Memory Architecture of 3D NOR Array,” filed on March 11, 2011 and issued on January 14, 2014.

[0011] In the document “Multi-layered Verticalgate NAND Flash Overcoming Stacking Limit for Terabit Density Storage” (“Kim”) by W. Kim et al., published in the 2009 VLSI Symposium Technical Papers Digital, pages 188-189, a three-dimensional storage structure is disclosed that includes horizontal NAND strings controlled by vertical polysilicon gates. In the document “A Highly Scalable 8-Layer 3D Vertical-gate (VG) TFT NAND Flash Using Junction-Free Buried Channel BE-SONOS Device” by HTLue et al., published in the 2010 VLSI Symposium Technical Papers Digital, pages 131-132, another three-dimensional storage structure is disclosed that also includes horizontal NAND strings with vertical polysilicon gates.

[0012] Figure 1a Prior art three-dimensional vertical NAND strings 111 and 112 are shown. Figure 1b A basic circuit representation 140 of a prior art three-dimensional vertical NAND string is shown. Specifically, Figure 1a The vertical NAND strings 111 and 112 and their circuit representation 150 are essentially conventional horizontal NAND strings - instead of each having 32 or more transistors in series along the surface of the substrate - they are rotated 90 degrees so as to be perpendicular to the substrate. The vertical NAND strings 111 and 112 are thin film transistors (TFTs) connected in series in a string configuration that rises from the substrate like a skyscraper, where each TFT has a storage element and the control gate is provided by one of the word line conductors in the adjacent stack of word line conductors. Figure 1bAs shown, in the simplest implementation of a vertical NAND string, TFTs 15 and 16 are the first and last memory transistors of the NAND string 150, controlled by separate word lines WL0 and WL31, respectively. The bit line select transistor 11 activated by the signal BLS and the ground select transistor 12 activated by the signal SS are used to connect the addressed TFTs in the vertical NAND string 150 to the corresponding global bit line GBL at the terminal 14 and the global source line (ground) GSL at the terminal 13 during read, program, program inhibit and erase operations. Reading or programming the contents of any one TFT (e.g., TFT 17) requires activating all 32 TFTs in the vertical NAND string 150, which exposes each TFT to read disturb and program disturb conditions. Such conditions limit the number of TFTs that can be provided in the vertical NAND string to no more than 64 or 128 TFTs. Furthermore, the polysilicon film of the vertical NAND string formed thereon has lower channel mobility - and therefore higher resistivity - than a conventional NAND string formed on a single crystal silicon substrate, resulting in a lower read current relative to that of a conventional NAND string.

[0013] U.S. Patent Application Publication 2011 / 0298013 ("Hwang"), entitled "Vertical Structure Semiconductor Memory Devices And Methods of Manufacturing The Same," discloses three-dimensional vertical NAND strings. In FIG. 4D thereof, Hwang shows a block of three-dimensional vertical NAND strings addressed by word lines 150 stacked around them (reproduced herein as Figure 1c ).

[0014] US Patent 5,768,192 to Eitan, entitled "Memory Cell utilizing asymmetrical charge trapping," filed July 23, 1996 and issued June 16, 1998, discloses NROM-type memory transistor operation of the type employed in embodiments of the present invention.

[0015] U.S. Patent 8,026,521, entitled “Semiconductor Device and Structure”, filed on October 11, 2010 and issued on September 27, 2011, by Zvi Or-Bach et al., discloses a first layer and a second layer of layer-transferred single crystal silicon, wherein the first layer and the second layer include horizontally oriented transistors. In the structure, the second layer of horizontally oriented transistors covers the first layer of horizontally oriented transistors, and each group of horizontally oriented transistors has a side gate.

[0016] A transistor having a conventional non-volatile memory transistor structure but a short retention time can be referred to as "quasi-volatile". In this scenario, the data retention time of conventional non-volatile memory exceeds several decades. HC Wann and C. Hu published a document titled "High-Endurance Ultra-Thin Tunnel Oxide in Monos Device Structure for Dynamic Memory Application" in IEEE Electronic Devices Letters, Vol. 16, No. 11, pp. 491-493 in November 1995, which disclosed a planar quasi-volatile memory transistor on a single crystal silicon substrate. A quasi-volatile three-dimensional NOR array with quasi-volatile memory is disclosed in the above-mentioned U.S. Patent 8,630,114 of HT Lue.

[0017] The article "A 768Gb 3b / cell 3D-Floating-Gate NAND Flash Memory" by T. Tanaka et al. published in the Abstracts of Technical Papers of the 2016 IEEE International Solid-State Circuits Conference, pages 142-144, discloses a method of placing CMOS logic circuits underneath a three-dimensional NAND memory array. Summary of the invention

[0018] According to one embodiment of the present invention, a high-density memory structure is referred to as a three-dimensional vertical NOR flash memory string ("multi-gate vertical NOR string", or simply "vertical NOR string"). The vertical NOR string includes a plurality of thin film transistors ("TFTs") connected in parallel, each of which has a shared source region and a shared drain region that extend generally in a vertical direction. In addition, the vertical NOR string includes a plurality of horizontal control gates, each of which controls a corresponding TFT in the vertical NOR string. When the TFTs in the vertical NOR string are connected in parallel, the read current in the vertical NOR string conducts a much smaller resistance than the read current of a NAND string through a large number of TFTs. In order to read or program any one TFT in the vertical NOR string, only the TFT needs to be activated, and all other TFTs in the vertical NOR string can remain non-conductive. Therefore, the vertical NOR string can include more TFTs (e.g., hundreds or more), while allowing faster sensing and minimizing programming disturbance or reading disturbance conditions.

[0019] In one embodiment, the shared drain region of the vertical NOR string is connected to a global bit line (“voltage V bl ”), and the shared source region of the vertical NOR string is connected to the global source line (“voltage V ss ”). Alternatively, in a second embodiment, only the shared drain region is connected to a global bit line biased to a supply voltage, while the shared source region is precharged to a voltage determined by the amount of charge in the shared source region. In order to perform precharging, one or more dedicated TFTs may be provided to precharge the parasitic capacitance C of the shared source region.

[0020] According to one embodiment of the present invention, a multi-gate NOR flash memory thin film transistor string array ("multi-gate NOR string array") is organized as an array of vertical NOR strings, each vertical NOR string extending perpendicular to the surface of a silicon substrate. Each multi-gate NOR string array includes a plurality of vertical active columns arranged in rows, each row extending along a first horizontal direction, wherein each active column has two vertical heavily doped polysilicon regions of a first conductivity, which are separated by one or more vertical polysilicon regions that are undoped or lightly doped to a second conductivity. The heavily doped regions form a shared source or drain region, respectively, and in combination with one or more stacks of horizontal conductors (each stack extending orthogonally to the first horizontal direction), the lightly doped regions each form a multi-channel region. The charge trapping material forms a plurality of storage elements, covering at least the channel region of the TFT in the active column. The horizontal conductive lines in each stack are electrically isolated from each other, and a control gate is formed above the storage element and the channel region of the active column. In this way, the multi-gate NOR string array forms a three-dimensional array of storage TFTs.

[0021] In one embodiment, support circuits are formed in a semiconductor substrate to support multiple multi-gate NOR string arrays formed above the support circuits and the semiconductor substrate. The support circuits may include address encoders, address decoders, sense amplifiers, input / output drivers, shift registers, latches, reference cells, power supply lines, bias voltage and reference voltage generators, inverters, NAND, NOR, XOR and other logic gates, other memory elements, sequencers and state machines, and others. The multi-gate NOR string arrays may be organized as multiple blocks of circuits, each of which has multiple multi-gate NOR string arrays.

[0022] According to embodiments of the present invention, variations in the threshold voltage of TFTs within a vertical NOR string may be compensated for by providing one or more electrically programmable reference vertical NOR strings in the same or another array of multi-gate vertical NOR strings. Background leakage currents inherent to the vertical NOR string may be substantially neutralized during a read operation by comparing the results of the TFT being read with the results of the TFT being read simultaneously on the programmable reference vertical NOR string. In certain embodiments, each TFT of the vertical NOR string is shaped so as to amplify the capacitive coupling between each control gate and its corresponding channel region, thereby enhancing tunneling from the channel region into the charge trapping material (i.e., the memory cell) during programming, and reducing charge injection from the control gate into the charge trapping material during erase. This favorable capacitive coupling is particularly useful for storing more than one bit in each TFT of the vertical NOR string. In another embodiment, the structure of the charge trapping material of each TFT may be modified to provide high write / erase cycle endurance despite the need to refresh the stored data at a lower retention time. However, since the refresh required for the vertical NOR string array is expected to be much less than that in conventional dynamic random access memory (DRAM), the multi-gate NOR string array of the present invention can be operated in certain DRAM applications. This use of vertical NOR strings allows for a substantially lower figure of merit for cost per bit compared to conventional DRAM and substantially shorter read-latency compared to conventional NAND string arrays.

[0023] In another embodiment, the vertical NOR string can be programmed, erased and read as an NROM / mirrored bit TFT string.

[0024] Organizing the TFTs into vertical NOR strings—rather than the prior art vertical NAND strings—results in (i) reduced read latency that can approach that of a dynamic random access memory (DRAM) array, (ii) reduced sensitivity to read disturb and program disturb conditions associated with long NAND flash strings, and (iii) lower cost per bit compared to NAND flash strings.

[0025] According to an alternative embodiment of the present invention, each active column in the memory structure includes one or more vertical NOR strings, wherein each NOR string has thin film storage transistors that share a local source line and a local bit line, and the local bit line is connected to a sense amplifier provided in the semiconductor substrate by a segment of a segmented global bit line. In order to significantly reduce the read latency, multiple shorter global bit line segments are provided instead of global bit lines spanning a larger distance (for example, between half the length and the entire length of the chip). Each such global segment connects one or more adjacent local bit lines to a segment sense amplifier provided in the semiconductor substrate through a segment connector. After the local source line is precharged to a virtual ground voltage (for example, V ss ) embodiment, the parasitic capacitance of the virtual ground is substantially increased by providing a short global source line segment connector that connects a group of adjacent local source lines into one local source line segment. The number of local source lines included in the segment determines the combined parasitic capacitance (C).

[0026] The present invention will be better understood by considering the following detailed description taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1a Prior art three-dimensional vertical NAND strings 111 and 112 are shown.

[0028] Figure 1b A basic circuit representation 140 of a prior art three-dimensional vertical NAND string is shown.

[0029] Figure 1c A three-dimensional representation of a block of three-dimensional vertical NAND strings addressed by surrounding stacked word lines 150 is shown.

[0030] Figure 2 A conceptualized memory structure 100 is shown illustrating a three-dimensional organization of memory cells according to one embodiment of the present invention; the memory cells are provided in vertical NOR strings, wherein the memory cells of each vertical NOR string are each controlled by one of a plurality of horizontal word lines.

[0031] Figure 3aA basic circuit representation of a vertical NOR string 300 formed in an active column according to an embodiment of the present invention is shown in the ZY plane; the vertical NOR string 300 represents a three-dimensional arrangement of non-volatile memory device TFTs, each of which shares a local source line (LSL) 355 and a local bit line (LBL) 354, which are addressed by a global bit line (GBL) 314 and a global source line (GSL) 313, respectively.

[0032] Figure 3b The basic circuit representation of a vertical NOR string 305 formed in an active column according to one embodiment of the present invention is shown in the ZY plane; the vertical NOR string 305 represents a three-dimensional arrangement of non-volatile memory devices TFTs, including a circuit for setting a voltage (“V ss ”), the vertical NOR string 305 has a parasitic capacitance C.

[0033] Figure 3c A basic circuit representation of a dynamic non-volatile storage transistor 317 is shown, having one or more programmed threshold voltages and connected to a parasitic capacitor 360; when the control gate 323p is raised to a voltage exceeding the threshold voltage, the capacitor 360 is pre-charged to temporarily maintain a dummy voltage V on the source terminal 355 ss , so as to allow the threshold voltage of transistor 317 to pass the voltage V ss The discharge is used for dynamic detection.

[0034] Figure 3d Shows Figure 3a A variation of the vertical NOR memory array circuit architecture in an embodiment of the present invention, wherein the global bit line (GBL) 314 is replaced by bit line segments MSBL1, MSBL2, ..., each bit line segment connecting multiple adjacent local vertical bit lines 374-1, 374-2, ...; the segments are in turn connected to regional bit line segments SGBL1, SGBL2, ... through segment selection thin film transistors 586-1, ..., 586-n, each of which is associated with a plurality of bit line segments and isolated from the sense amplifiers and other circuits in the silicon substrate 310 beneath them by dielectrics 393.

[0035] Figure 3e Shows Figure 3d A variation of the circuit architecture in the embodiment of , in which the global source select line 313 accesses a group of adjacent vertical local source lines 375-1, 375-2, ... through source select transistor SLS1, which are associated with source line segment MSSL1.

[0036] Figure 3f Shows Figure 3eA variation of the circuit architecture in an embodiment of the present invention, in which the global source line 313 is eliminated and replaced by a local source line segment MSSL1 connecting vertical local source lines 375-1, 375-2, ..., which are charged and maintained at a virtual ground voltage Vss through a pre-charge transistor (e.g., pre-charge transistor 370).

[0037] Figure 3g Shows Figure 3f A variation of the circuit architecture of the embodiment of the invention, wherein the regional bit line segments SGBL1, SGBL2, ... are merged with the bit line segments MSBL1, MSBL2, ... and connected to the segment selection transistors 315-1, 315-2 ... through the vias 322, the segment selection transistors 315-1, 315-2 ... being located in the substrate (thereby replacing Figure 3d Segment selection thin film transistors 586-1, 586-2).

[0038] Figure 3h Shows Figure 3g The circuit architecture of the embodiment in which two adjacent bit line segments MSBL1, MSBL2 have their local source line segments MSSL1, MSSL2 connected from the substrate through a dedicated active vertical column 381 formed in the space marked BL0 between the two bit line segments.

[0039] Figure 3i and 3i1 (The key to 3i and 3i1) is shown in the XY plane Figure 3h A top view of an embodiment in which each vertical local source line in source segment MSSL1 is maintained at a voltage Vss or Vbl supplied by column 381.

[0040] Figure 4a FIG. 4 is a cross-section of side-by-side active columns 431 and 432 according to an embodiment of the present invention, each of which may form a vertical NOR string having a ZY plane. Figure 3a or Figure 3b The basic circuit representation is shown in the figure.

[0041] Fig.4a1 yes Figure 4a 4. Top view of a vertical NOR string of FIG. 1, wherein the conductivity of a vertical local source or drain line is improved by including a metal material 420 (M) in the core of the pillar of the local source or drain line.

[0042] Figure 4b 4 is a cross-section of active columns 430R, 430L, 431R, and 431L, charge trapping layers 432 and 434, and word lines 423p-L and 423p-R according to an embodiment of the present invention, shown in a ZX plane.

[0043] Figure 4c A basic circuit representation of a pair of perpendicular NOR strings 491 and 492 according to one embodiment of the present invention is shown in the ZX plane.

[0044] Figure 5a FIG. 1 is a diagram showing a vertical NOR string of active columns 531 connected to global bit line 514-1 (GBL1), global source line 507 (GSL1), and common body bias source 506 (V bb ) cross section.

[0045] Figure 5b is a cross-section in the ZY plane showing the connection of the body region 556 (providing the P-channel material) to the conductive pillar 591, which is composed of P + Polysilicon is formed in dielectric layer 592, for example to provide conductors 590 above active columns 581 and extending parallel to the word lines; conductors 590 receive a body bias voltage V from a voltage source 594 in substrate 505 through vias 593 located in openings through dielectric spacers 509. bb .

[0046] Figure 6a FIG. 6 is a diagram showing a TFT 685 (T 685 ) of a vertical NOR string 451 a in a vertical NOR string pair 491 according to an embodiment of the present invention in an XY plane. L ) and the TFT 684 (T R ) cross section, such as combined Figure 4c discussed; Figure 6a , global bit line 614-1 accesses alternate ones of local bit lines LBL-1, and a predetermined curvature 675 of transistor channel 656L amplifies capacitive coupling between each control gate and the corresponding channel during programming.

[0047] Figure 6b FIG. 6 is a diagram showing a TFT 685 (T 685 ) of a vertical NOR string 451 a in a vertical NOR string pair 491 according to an embodiment of the present invention in an XY plane. L ) and the TFT 684 (T R ) share the cross section of the active area, such as the combination Figure 4c discussed; Figure 6b In the embodiment, global bit line 614-1 accesses alternating (odd) local bit lines in local bit line 654 (LBL-1), global bit line 614-2 addresses alternating (even) local bit lines in local bit line 657-2 (LBL-2), and local source lines LSL-1 and LSL-2 are precharged to provide dummy supply voltage V ss .

[0048] Figure 6c is a cross-section in the XY plane showing dedicated word line stacks 623p, each having a word line for a TFT of a respective vertical NOR string surrounding ("wrapping around"), and local vertical pillar bit lines 654 (extending along the Z direction) and local vertical pillar source lines 655 (extending along the Z direction) accessed by global horizontal bit lines 614 and global horizontal source lines 615, respectively, in accordance with one embodiment of the present invention; Figure 6c In FIG. 6 , adjacent word line stacks 623 p are separated by an air gap 610 or another dielectric spacer.

[0049] Figure 6d is a cross section of a vertical NOR string closely grouped in an interleaved manner according to an embodiment of the present invention, similar to Figure 6c , the vertical NOR strings share the word line stack 623p and have their own dummy V ss A parasitic capacitor 660 is pre-charged for supply voltage.

[0050] Figure 6e The XY plane shows the body bias voltage V shared between the body regions 656 (L+R) in adjacent rows of active columns. bb (e.g., via conductors 690-1 and 690-2), using Figure 6b The layout of the embodiment shown in .

[0051] Figure 6f An implementation of a global word line for connecting local word lines on one plane (ie, in a stair-step) in conjunction with the bit line segmentation scheme of the present invention is illustrated.

[0052] Figure 6g An implementation of a vertical NOR string memory array according to an embodiment of the present invention is illustrated that avoids doubling the silicon area occupied by word line staircase steps when the number of layers of memory transistors is doubled in the vertical direction.

[0053] Figure 7a , 7b 7c and 7d are cross-sections of intermediate structures formed during the fabrication of a multi-gate NOR string array according to an embodiment of the present invention.

[0054] Figure 7d-1 The vertical pillars of local source lines or local bit lines are shown in the XY plane to include conductive material 720 (M) at their cores.

[0055] Figure 8a is a schematic representation of a read operation of an embodiment in which the local source line (LSL) of a vertical NOR string is hardwired; Figure 8aIn the example, “WLs” represents the voltage on the selected word line, and all unselected word lines (“WLs”) in the vertical NOR string are NS ”) is set to 0V.

[0056] Figure 8b is a schematic representation of a read operation of an embodiment in which the local source line is floated at a precharged dummy voltage V ss Department; Figure 8b In "WL CHG ” represents the gate voltage on the precharge transistor (e.g. Figure 3c Pre-charge transistor 317 or 370 in. DETAILED DESCRIPTION

[0057] Figure 2 A conceptualized memory structure 100 is shown, which illustrates a three-dimensional organization of memory cells (or storage elements) provided in vertical NOR strings. In the conceptualized memory structure 100, according to one embodiment of the present invention, each vertical NOR string includes memory cells each controlled by a corresponding horizontal word line. In the conceptualized memory structure 100, each memory cell is formed in a deposited thin film provided "vertically" (i.e., in a direction perpendicular to the surface of a substrate layer 101). The substrate layer 101 can be, for example, a conventional silicon wafer familiar to those of ordinary skill in the art for manufacturing integrated circuits. In the detailed description, a Cartesian coordinate system (such as Figure 2 Indications) are only used for the purpose of facilitating discussion. In this coordinate system, the surface of the substrate layer 101 is considered to be a plane parallel to the XY plane. Therefore, as used in this description, the term "horizontal" refers to any direction parallel to the XY plane, and "vertical" refers to the Z direction.

[0058] Figure 2, each vertical column in the Z direction represents a storage element or TFT in a vertical NOR string (e.g., vertical NOR string 121). The vertical NOR strings are arranged in rows in a regular manner, with each row extending along the X direction. (Of course, it can also be understood as an arrangement that is alternatively the same as the arrangement of rows that each extend along the Y direction). The storage elements of the vertical NOR strings share vertical local source lines and vertical local bit lines (not shown). A stack of horizontal word lines (e.g., WL 123) extends along the Y direction, wherein each word line serves as a control gate for a corresponding TFT adjacent to the word line in the vertical NOR string along the Y direction. Global source lines (e.g., GSL 122) and global bit lines (e.g., GBL 124) are provided along the X direction, generally extending below the bottom or on the top of the conceptualized memory structure 100. Alternatively, both signal lines GSL 122 and GBL 124 can be routed underneath the conceptualized memory structure 100 (or routed on top of the memory structure), each of which can be selectively connected by access transistors (not shown) to local source lines and local bit lines of a separate vertical NOR string. Unlike the vertical NAND strings of the prior art, in the vertical NOR strings of the present invention, writing to or reading from any one of its storage elements does not involve activating other storage elements in the vertical NOR string. Figure 2 As shown, for illustration purposes only, the conceptualized memory block 100 is a multi-gate vertical NOR string array including a 4×5 arrangement of vertical NOR strings, each of which typically has 32 or more storage elements and access select transistors. As a conceptualized structure, the memory block 100 only extracts certain salient features of the memory structure of the present invention. Although Figure 2 A 4×5 arrangement of vertical NOR strings is shown, where each vertical NOR string has multiple storage elements, but the memory structure of the present invention can have any number of vertical NOR strings in each row along either the X direction or the Y direction, and any number of storage elements in each vertical NOR string. For example, there can be thousands of vertical NOR strings arranged in rows along both the X direction and the Y direction, where each NOR string has, for example, 2, 4, 8, 16, 32, 64, 128 or more storage elements.

[0059] Figure 2 The number of storage elements in each vertical NOR string (e.g., vertical NOR string 121) corresponds to the number of word lines (e.g., WL 123) that provide control gates to the vertical NOR string. The word lines are formed as narrow and long metal strips that each extend along the Y direction. The word lines are stacked one above the other and are electrically isolated from each other by a dielectric isolation layer therebetween. The number of word lines in each stack can be any number, but is preferably an integer power of 2 (i.e., 2 n, where n is an integer). The selection of a power of 2 for the number of word lines follows conventional practice in conventional memory design. Conventionally, each addressable cell of a memory is accessed by decoding a binary address. This convention is a matter of preference and need not be followed. For example, within the scope of the present invention, the conceptualized memory structure 100 may have M vertical NOR strings along each row in the X and Y directions, where M is not necessarily 2. n (for any integer n). In some embodiments described below, two vertical NOR strings can share a vertical local source line and a vertical local bit line, but their corresponding storage elements are controlled by two separate word line stacks. This effectively doubles the storage density of the vertical NOR string.

[0060] Since only Figure 2 The conceptualized memory structure 100 is shown to illustrate the organization of memory cells and is therefore not drawn to scale in any of the X, Y, and Z directions.

[0061] Figure 3a A basic circuit representation of a vertical NOR string 300 formed in an active column according to one embodiment of the present invention is shown in the ZY plane; the vertical NOR string 300 represents a three-dimensional arrangement of non-volatile memory device TFTs, each of which shares a local source line 355 and a local bit line 354. In this detailed description, the terms "active area", "active column" or "active strip" refer to an area, column or strip of one or more semiconductor materials on which active devices (such as transistors or diodes) can be formed. Figure 3a As shown, the vertical NOR string 300 extends along the Z direction, with TFTs 316 and 317 connected in parallel between a vertical local source line 355 and a vertical local drain or bit line 354. The bit line 354 is spaced apart from the source line 355, with the region therebetween (i.e., body region 356) providing a channel region for the TFTs in the vertical NOR string. A storage element is formed at the intersection between the channel region 356 and each horizontal word line 323p, where p is the index of the word line of the word line stack; in this example, p can take any value between 0 and 31. The word lines extend along the Y direction. The local bit line 354 is connected to a horizontal global bit line (GBL) 314 through a bit line access select transistor 311, which extends along the X direction and connects the local bit line 354 to an access bit line supply voltage V bl The local source line 355 is connected to the source supply voltage V via the horizontal global source line (GSL) 313. ss . Optional source select transistor ( Figure 3a313) may be provided as a connection between the local source line 355 and the GSL 313. The optional source select transistor may be controlled by a source decoding circuit that may be implemented in the substrate (eg, Figure 2 The active column body region 356 may be connected to a substrate bias voltage V at terminal 331. bb。 During the erase operation, for example, a substrate bias voltage V bb。 V bb The supply voltage can be applied to the entire multi-gate vertical NOR string array, or selectively to one or more rows of vertical NOR strings via a decoding mechanism. bb The line supplying the voltage connected to the body region 356 preferably extends in the direction of the word line.

[0062] Figure 3b A basic circuit representation of a vertical NOR string 305 formed in an active column according to one embodiment of the present invention is shown in the ZY plane; the vertical NOR string 305 represents a three-dimensional arrangement of non-volatile storage device TFTs, including an (optional) dedicated pre-charge TFT 370 for temporarily setting a voltage ("Vss") to a shared local source line 355, and has a parasitic capacitance C (represented as capacitor 360). Figure 3a The vertical NOR string 300, vertical NOR string 305 does not implement GSL313, which is replaced by a precharge transistor 370 that precharges the parasitic capacitor 360 to temporarily maintain V ss Under this precharge scheme, the global source line (e.g., Figure 3a The global source line 313) and its decoding circuit do not need to be present, thereby simplifying the manufacturing process and circuit layout, and providing a very tight footprint for each vertical NOR string. Figure 3c The structure of the nonvolatile storage TFT 317 is highlighted, which in addition to its normal storage function can also be used to perform the precharge function of the dedicated precharge transistor 370. The dynamic read operation of the TFT 317 is described below in conjunction with sensing the correct threshold voltage among several threshold voltages programmed into the storage element 334 of the TFT 317.

[0063] Figure 4a FIG. 4 is a cross-section of side-by-side active columns 431 and 432 according to an embodiment of the present invention, each of which may form a vertical NOR string having a ZY plane. Figure 3a or Figure 3b The basic circuit diagram is shown in the figure. Figure 4aAs shown, active columns 431 and 432 each include a vertical N+ doped local source region 455 and a vertical N+ doped local drain or bit line region 454 separated by a lightly P-doped or undoped channel region 456. The P-doped channel region 456, the N+ doped local source region 455, and the N+ doped local drain or bit line region 454 can be biased to a body bias voltage V bb , source supply voltage V ss , and the bit line voltage V bl In some embodiments of the present invention, a body bias voltage V bb is optional, such as when the active strip is thin enough (e.g., 10 nanometers or less). For sufficiently thin active strips, the active region is easily fully depleted under appropriate voltage conditions on the control gate, so that the voltage V bb A solid state supply voltage may not be provided to the channel region of the TFT along the vertical NOR string. Isolation region 436 (which electrically isolates active columns 431 and 432) may be a dielectric insulator or an air gap. Word lines 423p (labeled WL0-WL1, respectively) may be electrically isolated from each other by a dielectric insulator or an air gap. 31 (and optionally WL CHG )) provides control gates to the TFTs in the vertical NOR strings formed in the active columns 431 and 432. The word line stacks 423p are typically formed as long, narrow metal conductors (e.g., tungsten, silicide) extending along the Y direction and electrically isolated from each other by dielectric layers 426, each of which is typically composed of silicon oxide (e.g., SiO2) or an air gap. By providing a charge trapping material (not shown) between the word lines 423p and the P-doped channel regions 456, a non-volatile storage element can be formed at the intersection of each word line 423p and each P-doped channel region 456. For example, Figure 4a The dashed box 416 indicates where nonvolatile storage elements (or storage transistors) T0 to T1 may be formed. 31 The dotted box 470 indicates where a dedicated pre-charge transistor may be formed which, when temporarily turned on, allows all transistors T0 to T1 to be turned on. 31 Charge is transferred from common local bit line region 454 to common local source line region 455 when in their off state.

[0064] Figure 4b FIG. 2 is a cross-section diagram showing active columns 430R, 430L, 431R and 431L, charge trapping layers 432 and 434, and word line stacks 423p-L and 423p-R according to an embodiment of the present invention, taken along a ZX plane. Figure 4a , Figure 4bEach of the vertical word line stacks 423p-L and 423p-R represents a stack of long, narrow conductors, where p is an index that labels a word line in the stack (eg, word lines WL0 through WL1). 31 ).like Figure 4b As shown, each word line serves as a control gate for a nonvolatile TFT in a vertical NOR string formed on adjacent active columns 430-L and 431-R on opposite sides of the word line (within region 490). Figure 4b In the word line stack 423p-R, the word line WL 31 Serves as the control gate for both transistor 416L on active column 430L and transistor 416R on active column 431R. Adjacent word line stacks (e.g., word line stacks 423p-L and 423p-R) are separated by a distance 495, the width of which is the trench formed by etching through the continuous word line layer, as described below. Active columns 430R and 430L, and their corresponding charge trapping layers 432 and 434 are subsequently formed inside the trench etched through the word line layer. Charge trapping layer 434 is provided to be interposed between word line stack 423p-R and vertical active columns 431R and 430L. As explained below, during programming of transistor 416R, charge injected into charge trapping layer 434 is trapped in the portion of charge trapping layer 434 within dashed box 480. The trapped charge modifies the threshold voltage of TFT 416R, which can be detected by measuring the read current flowing between local source region 455 and local drain region 454 on active column 431R (these regions are shown, for example, in an orthogonal cross section of the active column in FIG. 4 ). In some embodiments, a precharged word line 478 (i.e., WL CHG ) as the control gate of the pre-charge TFT 470, which is used to convert the parasitic capacitance C of the local source line 455 (see, Figure 3b The capacitor 360 and Figure 4a The local source line 455) is charged to ground or source supply voltage V ss As a stopgap measure, the charge trapping layer 434 also provides a storage element in the pre-charge transistor 470, which however does not itself function as a memory transistor. The memory transistors T0 to T1 formed on the active column 431R may be used. 31 Any transistor in the local bit line 454 performs precharge instead. One or more of these memory transistors may perform the function of a precharge transistor in addition to their storage function. To perform precharge, the voltage on the word line or control gate is temporarily raised to a few volts above its highest programmable threshold voltage, thereby allowing the voltage V applied to the local bit line 454 to be ss Transfer to local source line 455 ( Figure 4a ). Memory transistors T0 to T 31Having performed the pre-charge function eliminates the need for a separate dedicated pre-charge TFT 470. However, care must be taken to avoid unnecessarily disturbing the threshold voltage of such memory TFT when it performs its pre-charge function.

[0065] Although Figure 4b Active columns 430R and 430L are shown as two discrete active columns separated by an air gap or dielectric isolation 433, but adjacent vertical N+ local source lines can be implemented by a single shared vertical local source line. Similarly, vertical N+ local drains or bit lines can be implemented by a single shared vertical local bit line. Such a configuration provides a "vertical NOR string pair". In that configuration, active columns 430L and 430R can be viewed as two branches (hence a "pair") in one active column. The vertical NOR string pair provides double density storage through charge trapping layers 432 and 434 inserted between active columns 430R and 430L on opposite sides and word line stacks 423p-L and 423p-R. In fact, active columns 430R and 430L can be merged into one active string by eliminating the air gap or dielectric isolation 433, and still achieve a pair of NOR TFT strings implemented at two opposite sides of a single active column. Such a configuration achieves the same double density storage because the TFTs formed in the opposite sides of the active columns are controlled by separate word line stacks and are composed of separate charge trapping layers 434 and 432. Maintaining separate thin active columns 430R and 430L (i.e., instead of merging them into one active column) is advantageous because the TFTs on each active column are thinner than the merged column and can therefore be more easily fully depleted under appropriate control gate voltage conditions, thereby substantially separating the vertical source region 455 from the vertical drain region 454 ( Figure 4a ) between the source-drain subthreshold leakage current. Having ultra-thin (and therefore high-resistance) active columns is possible for even very long vertical NOR strings (e.g., 128 TFTs or longer) because the TFTs in a vertical NAND string are connected in parallel and because only one of many TFTs is turned on at any one time, compared to the TFTs in a high-resistance NAND TFT string that are connected in series and therefore must all be turned on to sense any one TFT in the string. For example, in a 32-TFT vertical NOR string, in order to be able to read transistor T 30 ( Figure 4a ), the channel length of channel region 456 may span only 20 nanometers, whereas the corresponding channel length of the NAND string may be 32 times longer or 640 nanometers.

[0066] Figure 4c The basic circuit representation of the vertical NOR string pair 491 and 492 according to one embodiment of the present invention is shown in the ZX plane. Figure 4c As described above, the vertical NOR strings 451b and 452a share a common word line stack 423p-R in the following manner: Figure 4b 430L and 431R of the vertical NOR string. For their respective commonly connected local bit lines, the vertical NOR string pair 491 and 492 are served by the global bit line 414-1 (GBL1) through the access select transistor 411 and the global bit line 414-2 (GBL2) through the access select transistor 414, respectively. For their respective commonly connected local source lines, the vertical NOR string pair 491 and 492 are served by the global source line 413-1 (GSL1) and the global source line 413-2 (GSL2), respectively (the source line select access transistors may be similarly provided and not in FIG. 1 ). Figure 4c As shown in Figure 4c As shown, the vertical NOR string pair 491 includes vertical NOR strings 451a and 451b, which share a local source line 455, a local bit line 454, and an optional body connection 456. Therefore, the vertical NOR string pair 491 represents Figure 4b The vertical NOR strings formed on the active columns 430R and 430L of FIG. 423p-L and 423p-R (where, in this example, s1≥p≥0) provide control gates for the vertical NOR strings 451a and 451b, respectively. The word lines to the control gates in the stacks are decoded by decoding circuitry formed in the substrate to ensure that the appropriate voltages are applied to the addressed TFTs (i.e., the activated word lines) and to the unaddressed TFTs (i.e., all other inactivated word lines in the string). Figure 4c Picture shows Figure 4b 430L and 431R are served by the same word line stack 423p-R. Therefore, the vertical NOR string 451b of the vertical NOR string pair 491 and the vertical NOR string 452a of the NOR string pair 492 correspond to Figure 4b The memory transistors of vertical NOR string 451a (eg, memory transistor 415R) are served by word line stack 423p-L.

[0067] In another embodiment, Figure 4c The hard-wired global source lines 413-1, 413-2 are eliminated and replaced with parasitic capacitors (e.g., parasitic capacitors are composed of Figure 4c A capacitor of 460 or Figure 3cThe parasitic capacitance is represented by capacitor 360, which is between the shared N+ local source line 455, which is common to both vertical NOR strings 451a and 451b, and its associated word lines 423p-L and 423p-R. In a vertical stack of 32 TFTs, each of the 32 word lines contributes their parasitic capacitance to provide a total parasitic capacitance C that is large enough to temporarily maintain the voltage supplied by the pre-charged TFT 470 to provide a virtual source voltage V during the relatively short duration of a read or program operation. ss . In this embodiment, a dummy source voltage temporarily held on a parasitic capacitor (C) is provided from the global bit line GBL1 to the local source line 455 through the access transistor 411 and the precharge transistor 470. Alternatively, if one or more of the memory TFTs in the vertical NOR string are used in addition to their storage function to precharge the local source line 455 by bringing the word line voltage temporarily higher than its highest programming voltage, the dedicated precharge transistor 470 can be eliminated. Using a storage TFT for this purpose, however, care must be taken to avoid overprogramming the storage TFT. Using a dummy V ss The voltage provides the significant advantage of eliminating hard-wired global source lines (eg, GLS1, GLS2) and their associated decoding circuitry and access transistors, substantially simplifying the process flow and design challenges and resulting in a significantly more compact vertical NOR string.

[0068] Figure 5a The vertical NOR string of active columns 531 according to one embodiment of the present invention is shown in the ZY plane connected to the global bit line 514-1 (GBL1), the global source line 507 (GSL1), and the common body bias source 506 (V bb ) cross section. Figure 5a As shown, the bit line access transistor 511 connects GBL1 to the local bit line 554, and the buried contact 556 connects the P-body region on the active strip to the body bias source 506 (V bb ). Figure 5a In the embodiment, the bit line access select transistor 511 is formed above the active column 531. However, alternatively, the bit line access select transistor 511 may be formed at the bottom of the active column 531 or in the substrate 505 ( Figure 5a not shown). Figure 5a, the bit line access select transistor 511 can be formed, for example, in an isolated island of an N+ / P- / N+ doped polysilicon stack together with an access select word line 585. When a sufficiently large voltage is applied to select word line 585, the P-channel is inverted, thereby connecting the local bit line 554 to GBL1. Word line 585 extends in the same direction (i.e., the Y direction) as word line 523p, which serves as a control gate of a TFT connected to a vertical NOR string. Word line 585 can be formed separately from word line 523p. In one embodiment, GBL1 extends horizontally along the X direction (i.e., a direction perpendicular to the word line), and the bit line access select transistor 511 provides access to a local bit line 554, which is a local bit line of only one vertical NOR string of many vertical NOR strings served by GBL1. To improve read and program operation efficiency in a multi-gate NOR string array, thousands of global bit lines can be used to access thousands of local bit lines of perpendicular NOR strings accessed by word lines 585 in parallel. Figure 5a In FIG. 5 , local source line 555 is connected to global source line 513-1 (GSL1) through contact 557, which can be decoded, for example, by a decoding circuit in substrate 505. Alternatively, as already described, the global source line can be eliminated by providing a dummy source voltage V on local bit line 555. ss And the parasitic capacitor 560 (ie, the parasitic capacitance C) of the local source line 555 is temporarily precharged through the TFT 570 .

[0069] Support circuits formed in substrate 505 may include address encoders, address decoders, sense amplifiers, input / output drivers, shift registers, latches, reference cells, power supply lines, bias voltage and reference voltage generators, inverters, NAND, NOR, XOR and other logic gates, other memory elements, sequencers and state machines, and others. The multi-gate NOR string arrays may be organized as multiple blocks of circuits, with each block having multiple multi-gate NOR string arrays.

[0070] Figure 6a FIG. 6 shows the TFT 685 (T 685 ) of the vertical NOR string 451 a in the vertical NOR string pair 491 in the XY plane. L ) and the TFT 684 (T R ) cross section, such as combined Figure 4c As shown in FIG. 6, TFTs 684 and 685 share an N+ local source region 655 and an N+ local drain or bit line region 654, both of which extend along the Z direction in a long, narrow column. (N+ local source region 655 corresponds to Figure 4a The local source line 455 of N+ local drain region 654 corresponds to Figure 4aIn this embodiment, the P-doped channel regions 656L and 656R form a pair of active strings between the local source column 655 and the local drain column 654 and extend along the Z direction, isolated from each other by the isolation region 640. The charge trapping layer 634 is formed on the word line 623p-L (WL 31-0 ) and 623p-R(WL 31-1 ) and the outside of channel regions 656L and 656R, respectively. Charge trapping layer 634 can be a transistor gate dielectric material (e.g., including a thin film of a tunneling dielectric (e.g., silicon dioxide) followed by a thin layer of charge trapping material (such as silicon nitride or conductive nanodots embedded in a non-conductive dielectric material), or an isolated floating gate, and the charge trapping layer 634 is capped with a layer of a blocking dielectric such as ONO (a triple layer of oxide-nitride-oxide) or a high dielectric constant film such as aluminum oxide or hafnium oxide, or a combination of such dielectrics. Source drain conduction is controlled by word lines 623p-L and 623p-R, respectively, to form a control gate on the outside of charge trapping layer 634. When programming or reading TFT 684 (T R )、TFT 685(T L ) is turned off by maintaining an appropriate inhibit voltage at word line 623p-L. Similarly, when programming or reading TFT 685 (T L )、TFT 684(T R ) is turned off by maintaining an appropriate inhibit voltage at word line 623p-R.

[0071] exist Figure 6a In the embodiment shown in , word lines 623p-L and 623p-R are contoured to improve the tunneling efficiency into TFTs 684 and 685 during programming, while reducing the reverse tunneling efficiency during erasing. Specifically, as known to those skilled in the art, the curvature 675 of the channel region 656R amplifies the electric field at the interface between the active channel polysilicon and the tunneling dielectric during programming, while reducing the electric field at the interface between the word line and the blocking dielectric during erasing. This feature is particularly useful when each TFT transistor stores more than one bit in a multi-level cell (MLC) configuration. Using this technology, 2, 3 or 4 bits or more can be stored in each TFT. In fact, TFTs 684 and 685 can be used as analog storage TFTs with a continuum of storage states. Following the programming sequence (discussed below), electrons are trapped in the charge trapping layer 634, as schematically indicated by the dashed line 680. Figure 6a In FIG. 1 , global bit lines 614-1 and 614-2 extend perpendicular to word lines 623p-R and 623p-L and are configured to be above or below the vertical NOR string, corresponding to Figure 4cAs shown in the above combination Figure 2 As discussed, the word lines may span the entire length of the memory block 100 along the X direction, while the global bit lines span the width of the memory block 100 along the Y direction. Importantly, Figure 6a In FIG. 6 , word line 623p-R is shared by TFTs 684 and 683 of two vertical NOR strings on opposite sides of word line 623p-R. Therefore, to allow TFTs 684 and 683 to be read or programmed individually, global bit line 614-1 (GBL1) contacts local drain or bit line region 657-1 (“odd addresses”), while global bit line 614-2 (GBL2) contacts local drain or bit line region 657-2 (“even addresses”). To achieve this effect, the contacts along global bit lines 614-1 and 614-2 are staggered, with each global bit line contacting every other pair of vertical NOR strings along the X-direction row.

[0072] In a similar manner, the global source line ( Figure 6a (not shown) - which may be located at the bottom or above the multi-gate NOR string array - may extend parallel to the global bit lines and may contact the local source lines of the vertical NOR string pairs according to odd or even addresses. Alternatively, the parasitic capacitance (i.e., capacitor 660) may be temporarily precharged to a dummy source voltage V ss There is no need to provide a global source line, thereby simplifying the decoding scheme and process complexity.

[0073] Figure 6a Only one of several possible embodiments is shown by which a vertical NOR string pair with stacked word lines can be provided. For example, the curvature 675 of the channel region 656R can be further enhanced. Conversely, such a curvature can be as Figure 6b The embodiments shown in FIG. 1 and FIG. 2 are eliminated together (for example, straightened). Figure 6b In the embodiment, Figure 6a The isolation spacer 640 can be reduced or eliminated altogether by merging the channel regions 656L and 656R into a single region 656(L+R), achieving greater area efficiency without sacrificing a dual channel configuration: for example, TFTs 685(T L ) and 684(T R ).exist Figure 6a , 6b In an embodiment of the present invention, vertical NOR strings that share a word line may be arranged in a staggered manner relative to each other (not shown) so that they are closer to each other, thereby reducing the effective footprint of each vertical NOR string. Figure 6a and 6bA direct connection via a contact between global bit line 614-1 and N+ doped local drain bit line pillar 654 (LBL-1) is shown, but such a connection may also be made using a bit line access select transistor (e.g., Figure 5a The bit line access select transistor 511 is crowded Figure 6a and 6b ) to complete.

[0074] exist Figure 6a and 6b In the embodiment of the present invention, the dielectric isolation (corresponding to Figure 4a The isolation regions 436 of the word lines 623p-R and 623p-L can be established, for example, by defining the separation 676 between the word lines 623p-R and 623p-L to be less than the thickness of the two back-to-back charge trapping layers so that the charge trapping layers are merged together during their deposition. The resulting merging of the deposited charge trapping layers creates the desired dielectric isolation. Alternatively, isolation between adjacent active strings can be achieved by using a high aspect ratio etch of the N+ polysilicon to create a gap 676 (an air gap or a filled dielectric, i.e., creating a dielectric gap) that isolates the N+ column 658 of one string from the N+ column 654 of an adjacent string. Figure 4a Gap 436 shown).

[0075] By comparing the vertical NAND strings of the prior art with the vertical NOR strings of the present invention, although both types of devices use thin film transistors with similar word lines as control gates, their transistor orientations are different: in the prior art NAND strings, each vertical active string can have 32, 48 or more TFTs in series. In contrast, each active column of the vertical NOR strings that form the vertical columns of the present invention can have one or two sets of 32, 48 or more TFTs in parallel. In the prior art NAND strings, in some embodiments the word lines typically wrap around the active strips. In some embodiments of the vertical NOR strings of the present invention, separately designated left and right word lines are used for each active strip, thereby achieving doubled (i.e., a pair) storage density for each global bit line, such as Figure 4c , 6a 6a and 6b. The vertical NOR string of the present invention does not suffer from the degradation of program disturb or read disturb, nor does it suffer from the longer waiting time of the prior art NAND string. Therefore, a greater number of TFTs can be provided in a vertical NOR string than in a vertical NAND string. However, the vertical NOR string may be more susceptible to subthreshold or long vertical source and drain diffusions (e.g., Figure 4a Other leakage effects are shown between the local source region 455 and the local drain region 454 accordingly.

[0076] Figure 6c and Figure 6d Two additional embodiments of the vertical NOR string of the present invention are shown in . In these embodiments, all word lines in each word line stack wrap around the vertical active strip.

[0077] Figure 6c In the embodiment of the present invention, a vertical NOR string is formed inside a void formed by etching through a stack of dielectric isolation layers between metal word lines and word lines. The manufacturing process flow is similar to the manufacturing process flow of a prior art vertical NAND string, except that the transistors in the vertical NOR string are arranged parallel to each other, rather than being connected in series in a vertical NAND string. The formation of transistors in the vertical NOR string is facilitated by N+ doped vertical pillars extending to the entire depth of the void, providing a shared local source line 655 (LSL) and a shared local bit line (drain) 654 (LBL) for all TFTs along the vertical NOR string, with an undoped or lightly doped channel region 656 adjacent to both. The charge storage element 634 is positioned between the channel 656 and the word line stack 623p, thereby forming 2, 4, 8, ... 32, 64 or more TFTs (e.g., device 685 (T 10 )) of stacked bodies. Figure 6c In the embodiment of the present invention, the word line stack extends in the Y direction, wherein the individual horizontal strips 623p (WL 31-0 )、623p(WL 31-1 ) are separated from each other by air gaps or dielectric isolation 610. Global bit lines 614 (GBL) and global source lines 615 (GSL) extend horizontally in rows along the X direction perpendicular to the word lines. Each global bit line 614 is connected by an access select transistor ( Figure 5a 511, not shown here) accesses local bit line pillars 654 (LBL) along the rows of vertical strips, and the access selection transistors can be located below or above the memory array. Similarly, each global source line 615 accesses local source line pillars along the row. Although Figure 6a and 6b The structure shown in Figure 6c The single vertical NOR string of the embodiment occupies roughly the same area as the pair of vertical NOR strings, but Figure 6c Each TFT of each vertical NOR string has two parallel conductive channels (ie, channel regions 656a and 656b) and can therefore store more charge and increase or double the read current, thereby enabling more bits to be stored in each TFT.

[0078] Figure 6d FIG. 2 shows a more compact vertical NOR string with surrounding word lines according to one embodiment of the present invention. Figure 6dAs shown, the vertical NOR strings are staggered to be closer together so that the word line stack 623p (WL 31-0 ) can be shared by more vertical NOR strings. The staggered configuration is made possible by using the parasitic capacitors of the local source line pillars 655 (LSL), i.e., parasitic capacitors 660. By precharging capacitor 660 to temporarily hold a dummy voltage V during read and program operations ss , as described below, avoids the need for hardwired global source lines (e.g., Figure 6c Although Figure 6c and 6d The vertical NOR string of FIG. 1 may not provide significant area efficiency by itself, but is comparable to the prior art vertical NAND string (e.g., Figure 1c Such vertical NOR strings achieve longer string lengths than vertical NAND strings. For example, while the vertical NOR strings of the present invention can well support strings of 128 to 512 or more TFTs per stack, such string lengths are not practical for vertical NAND strings due to the severe limitations imposed on the series-connected TFT strings.

[0079] An alternative to long global bit lines that are split into short, segmented bit lines to facilitate fast access to sense amplifiers Example

[0080] The inventors have noted that in the case of sense amplifiers and other supporting circuits provided in a semiconductor substrate, global bit lines are routed using global interconnect conductors provided above or below the memory array to connect to vertical local bit lines (e.g., Figure 5a The global bit line GBL1 connected to the vertical local bit line 554 results in a long RC delay due to the substantial length of leads involved. In addition, it is highly desirable to use the area of ​​the silicon substrate underneath the memory array (as opposed to occupying valuable silicon area next to the array) to form a number of support circuits such as sense amplifiers, decoders, voltage sources and other circuits required for memory operation.

[0081] According to one embodiment of the present invention, a conductor that is otherwise used as a global bit line can be segmented into a large number of relatively short segments (e.g., each segment can be 1 / 100 or less the length of a global bit line). Each segment provides a horizontal line connector to connect groups of adjacent vertical local bit lines. The bit line segments can preferably exist between the substrate and the memory array and be dielectrically isolated from the substrate and the memory array. The bit line segments facilitate connection between adjacent vertical local bit lines in the group and other supporting circuits formed in the semiconductor substrate beneath the array of dedicated sense amplifiers and vertical NOR strings. In this detailed description, the term "bit line segment" can refer to a collection of local bit lines connected by a line connector.

[0082] Similarly, conductors that are otherwise used as global source lines may also be segmented into a large number of relatively short line segments, each of which provides a horizontal line connector to connect groups of adjacent local vertical source lines. The line connectors and their associated local vertical source lines form a common source line that has a parasitic capacitance that is several times the parasitic capacitance of just one local vertical source line. The common source line connector may be connected by a segment select transistor to a global source line that is preferably located at the top of the array. In this detailed description, the term "source line segment" may refer to a collection of local source lines connected by a line connector. Where a source line segment may be further divided into smaller groups of connected local source lines, each such smaller group may be referred to as a "source line sub-segment."

[0083] In another alternative embodiment of the present invention, although no global source line is provided extending from the top or below the memory stack, each source line segment and its associated group of adjacent local vertical source lines are operated as a local common source region. In this configuration, one or more pre-charged transistors are provided in each active column connected to the source line segment to transfer a virtual ground voltage (V ss In a 64-layer vertical NOR memory array, each local source line may have approximately 1 femtofarad (i.e., 1.0×10 -15 Farads), which in some instances provide too little charge to maintain the virtual ground voltage (V ss ). By combining the capacitances of groups of, for example, 64 local source lines, their combined pre-charge capacitance C is increased to approximately 64 femtofarads, which will be more suitable for charge-sharing read operations.

[0084] Figure 3d , 3e , 3f and 3g illustrate some embodiments of the present invention that achieve fast read access and utilize the silicon substrate underneath the array to form supporting circuits such as sense amplifiers, decoders, registers and voltage sources. Figure 3dAs shown, according to one embodiment of the present invention, the vertical NOR string 380 represents a three-dimensional arrangement of non-volatile memory device TFTs, where each TFT shares a local source line 375 and a local bit line 374. The local bit line 374 and the local source line 375 are separated by a body region 356, which provides a channel region for the TFTs in the vertical NOR string 380. The storage element is formed at the intersection between the channel region 356 and each horizontal word line 323p, where p is the index of the word line in the word line stack; in this example, p can take any value between 0 and 31. The word line extends along the Y direction. In this embodiment, the source line supply voltage Vss is provided to the local vertical source line 375 through the global source line (GSL1) 313 shown extending from the substrate 310 on the top of the vertical column through the source select transistor (SLS) 371. Note that the body region 356 providing the transistor channel of the active column can be connected to the substrate bias voltage V at the terminal 331. bb However, electrical connection to the P-doped channel 556 can also be achieved from the top of the vertical NOR string (see below for Figure 5b for discussion).

[0085] Figure 3d 374-n are connected along the word lines WL0 to WL0. 31 The orthogonal X-direction is provided longitudinally. The bit line segments MSBL1, MSBL2, ... are formed on the dielectric insulator 392 and can be relatively short, such as covering from 1 (no segmentation) to 16, 64, 256, 512 or more vertical local bit lines. Each bit line segment can be connected to a longer horizontal conductor through a segment selection transistor (e.g., segment selection transistors 586-1, ..., 586-n, which can be implemented as thin film transistors) to form a regional bit line segment SGBL1, SGBL2 including multiple MSBL1 type bit line segments. The horizontal regional bit line segment SGBL1 can be formed on the insulating layer 393 above the substrate 310 to allow logic elements such as sense amplifiers to be formed in the substrate directly below the regional bit line segment. Preferably, the regional segment is long enough to allow sense amplifiers, decoders, registers, voltage sources, and other circuits formed in the substrate to physically fit under the regional bit line segment.

[0086] In a double density configuration, such as Figure 6eAs shown, each word line serves the active columns on both sides of the word line. In this configuration, two adjacent local bit lines on opposite sides of the word line are respectively associated with bit line segments MSBL1 (L) and MSBL1 (R) and their corresponding segment sense amplifiers and decoders, and the two adjacent local bit lines are closely spaced from each other and extend parallel to each other. The spacing is also the spacing along the Y direction between adjacent vertical active columns in the memory array. It may not be possible to provide dedicated sense amplifiers and other supporting circuits for each of the bit line segments laid out along the Y direction. In such an arrangement, each sense amplifier can serve 1, 2, 4, 8 or more adjacent bit line segments through a segment selection encoder in the substrate. In the X direction, a 1TB three-dimensional vertical NOR flash memory chip can have hundreds of regional bit line segments instead of long global bit lines, thereby significantly reducing bit line RC delays.

[0087] Figure 3e Shows Figure 3d A variation of the circuit architecture in the embodiment of FIG. 1, wherein a group of adjacent vertical local source lines 375-1, 375-2, ... are connected by source line segments MSSL1, MSSL2, ... extending along the same X direction as the bit line segments. This group of local source lines connected by the source line segments reduces the need to provide a source voltage V to each of the vertical NOR strings associated with the source line segments. ss The number of source line selection transistors SLS1, SLS2, ... is increased. In addition, as previously mentioned, the group of vertical local source lines connected by source line segments directly contributes to increasing the accumulated parasitic capacitance (C). The vertical local source lines connected by horizontal source line segments are also closely associated with the vertical local bit lines connected by corresponding horizontal bit line segments. However, the number of vertical local bit lines associated with a bit line segment does not need to be the same as the number of vertical local source lines associated with a source line segment. Therefore, a bit line segment can, for example, be associated with multiple source line segments. For example, bit line segment MSBL1 can be associated with 256 local vertical bit lines 374-1, 374-2, ..., which can be associated with eight source line segments, each of which can be associated with only 32 local source lines 375-1, 375-2, .... Each source line segment can have a voltage V granted to it by its dedicated source line selection transistor (e.g., source line selection transistor SLS1), respectively. ss .

[0088] Figure 3f Shows Figure 3e A variation of the circuit architecture of the embodiment of FIG. 1 in which a global source line (eg, global source line 313) or a source line selection transistor (eg, source selection transistor SLS1) is not provided. Figure 3f In the embodiment, the local vertical source line associated with each source line segment is precharged to a source voltage V by a precharge transistor (e.g., precharge transistor 370).ss , the precharge transistor word line W CHG is turned on by a voltage pulse sufficient to supply the voltage V supplied by the circuit in the substrate 310. bl The number of local vertical bit lines associated with the source line segment is selected to maximize the parasitic capacitance (C) of the source line segment to maintain the virtual ground voltage V during the cell read. ss The optimization is balanced by the need to keep the background leakage current associated with all the "off" transistors in the vertical NOR string associated with the source line segment low enough so as not to interfere with the storage transistors accessed in the read source line segment. Within a bit line segment, any unselected source line sub-segment can be precharged to have its V ss The voltage is associated with the bit line segment voltage V bl equal to eliminate its background leakage current.

[0089] Figure 3g yes Figure 3e Variations of the circuit architecture in the embodiments. Figure 3g In the embodiment, the connectivity between the memory array and the substrate can be further simplified by merging the regional bit line segments SGBL1, SGBL2, ... with their corresponding local bit line segments MSBL1, MSBL2, ... and connecting each bit line segment to the segment selection transistors 315-1, 315-2, ... in the substrate below the bit line segment through corresponding vias or conductors (e.g., buried contacts). In this configuration, the segment selection transistors are provided by high-efficiency transistors in the single crystal substrate 310, rather than providing thin film segment selection transistors (e.g., quartz crystals) above the silicon substrate. Figure 3f The configuration provides reliable access to sense amplifiers, decoders, registers, voltage sources, and other circuits associated with the bit line segments. By eliminating the global source line select transistors SLS1, SLS2, ... by the precharge path, and by eliminating the segment select thin film transistors 586-1, ..., 586-n (or select transistors built with expensive selective epitaxial silicon, as is typically done in conventional three-dimensional NAND arrays), each bit line segment can be positioned close to its segment circuit in the substrate, greatly simplifying the process integration flow.

[0090] Figure 3h and 3i Shows something like Figure 3g Another embodiment of the embodiment of. Figure 3h and 3iIn the embodiment, the voltage on the source line segment connectors MSSL1 and MSSL2, as well as the voltage on the local vertical source line 375 (LSL) within each source line segment, is supplied from the substrate 310 by an active column 381 ("charge column"), which structurally mimics any storage active column of the memory array (e.g., active column 380), but is not used for memory storage. In other words, charge column 381 is dedicated to charging the local source lines in source line segments MSSL1 and MSSL2. (In other embodiments, each charge column can only supply a single source line segment. For example, Figure 3h As shown, the charge column 381 can be formed, for example, in the opening BLO between adjacent bit line segments SEG1 and SEG2. Throughout the read operation (and optionally, any programming, program inhibit, or erase operation), the charge column 381 delivers and maintains the required voltage on the vertical local source lines in the source line segments MSSL1 and MSSL2. (Both source line segments MSSL1 and MSSL2 are served by the charge column 381.) In this regard, for example, the charge column 381 avoids Figure 3e The need for the global source line GSL1 313 of the memory stack is eliminated and the need for the associated source line segment select transistor SLS1 is eliminated. For example, the pre-charge transistor 370 in the memory stack, which requires an additional word line plane WL chg ——demand, such as Figure 3g As shown in the embodiment.

[0091] exist Figure 3h and 3i In the segmented structure, in a read operation of any memory transistor on any memory plane, the source voltage on each local source line of source line segments MSSL1 and MSSL2 is applied by connecting VSL from the vertical source line 375 (LSL) of the charge column 381. ss (eg, 0 volts). From substrate 310 through a decoding selection transistor ( Figure 3h 315X), a bit line mini-segment SSVss, a vertical local bit line 374 (LBL), a voltage V delivered through transistor 371 and a vertical local source line 375 (LSL) ss (The pass transistor 371 is activated and the word line WL 31 The conductive or "on" state is maintained throughout the read operation.) The source voltage to be applied to the source line segments MSSL1 and MSSL2 during any program, program inhibit or erase operation can be similarly provided. The select transistor 315X in the silicon substrate 310 can be a high voltage transistor that is capable of withstanding the high voltage applied to the local bit line 374 (LBL) during the erase operation.

[0092] Figure 3iShown in more detail Figure 3h An XY plane top view of an embodiment of the invention, wherein each vertical local source line in source segment MSSL1 is maintained at a voltage V supplied by column 381 ss or V bl Place. Figure 3i In the example, the memory array is laid out similar to Figure 6b The layout shown in the embodiment. Figure 3i As shown, an array of charge columns is provided between the bit line segments SEG1 and SEG2, wherein each row extends along the X direction having two charge columns and a predetermined number of such rows (e.g., 2048) are arranged along the Y direction. The array of charge columns is provided at two breaks or openings ( Figure 3i In a row of active columns between the two dashed lines, a source line connector extending along the X direction connects the right charged column to the local source line in source line segment MSSL1 in bit line segment SEG1 (i.e., every other active column along the upper dashed line). The same right charged column is connected to the local source line of the active column of source line segment MSSL2 in bit line segment SEG2. A source voltage is provided from the silicon substrate to the bit line connector connected to the local bit line of the right active column. Marked “WL 31 The word line of " activates the pass transistor in the charging column to transfer the source voltage to the local source line marked VSL, which provides the source voltage to the local source lines of source line segments MSSL1 and MSSL2. (This circuit configuration is in Figure 3h ) The left charge column in the row of charge columns between the dashed lines is connected in a similar manner along the lower dashed lines to another pair of source line segments.

[0093] In a three-dimensional vertical NOR string memory array with multiple word line planes, the local word lines of all planes in the stack can be arranged as stair-steps WL at the edge of the array. STC (See, for example, Figure 3i and Figure 6g Each memory plane may require one or more dedicated global word lines (e.g. Figure 3i Marked as "GWL chg ”), to provide a value for each pair of adjacent bit line segments (e.g., Figure 3h The bit line segments SEG1 and SEG2 in FIG. 1 activate the charge column (e.g., charge column 381). Figure 3i As shown in the example (see illustration), marked as GWL chg The global word lines are all connected to the local word lines WL corresponding to the active columns 381. 31All other word lines in bit line segments SEG1 and SEG2 are skipped. In contrast, each global word line (e.g., GWL) of the memory transistors of the memory array is hard wired to multiple local word lines associated with bit line segments SEG1 and SEG2, while skipping the word lines of charge column 381. The global word lines ( Figure 3i All illustrations are marked with "GWL chg ”) can be shorted together at the peripheral circuit (not shown), thereby activating the charging column 381 and the word lines WL0-WL 31 In one embodiment, when the chip is powered up, the pass transistors of all charge columns in a block of connected source line segments can be activated together; however, any source line segment or source line segment pair within a block can be unselected by disconnecting its associated segment select transistor (e.g., segment select transistor 315X) to isolate its corresponding charge column from the silicon substrate.

[0094] Figure 3h and 3i The embodiments eliminate the need for a floating source precharge sequence, such as Figure 3g Eliminating the precharge sequence speeds up the read operation because the source voltage can be set and then held steady at voltage V ss The read operation is then initiated, thereby eliminating the overhead time required for the floating source precharge pulse. In addition, as charge column 381 holds the local source line of source line segment MSSL1 at voltage Vss throughout the read operation (i.e., not just the temporary precharge pulse), the steady current provided by connecting VSL compensates for any source-drain leakage, which, if excessive, could compromise read sensing of the addressed storage transistor.

[0095] In summary, the charging column 381 is used as a local vertical connector to transfer the voltage V ss or V bl Transferred from the silicon substrate to the local source lines in the vertical NOR memory string. Any voltage V on the vertical local source line of the charged column ss or V bl The voltage may be transferred to its associated local bit line via a pass transistor (eg, pass transistor 371), but the local bit line may also be charged directly from bit line connector MSBL1, which may be connected to a voltage source in the silicon substrate via segment select decoder 315-1.

[0096] In a three-dimensional vertical NOR memory stack with 64 or 128 memory planes, the height of the stack, which is also the length of the charge column 381, can exceed 5 microns, which is the length of the charge column 381 ( Figure 3h) of the vertical local source line 375 (LSL) or the local bit line 374 (LBL). The corresponding N+ doped polysilicon pillars 455 and 454 (see, Figure 4a ; It is also shown as Figure 6e The resistance (R; in ohms) of the pillars 655 (N+) LSL-1 and 654 (N+) LBL-1 (and sometimes referred to as the pylons) may become excessive, introducing an RC delay that adversely affects the read path. The resistance R of the pillars may be reduced by an order of magnitude or more by providing a low resistivity metal material in the core of the pillars. For example, in the detailed description below, Fig.4a1 A metal core 420 (M) is shown and Figure 7d-1 A metal core 720 (M) is shown.

[0097] Figure 5b 5 is a cross-section showing the connection of the body region 556 (providing P-channel material) through a conductive pillar 591 according to one embodiment of the present invention in the ZY plane, the conductive pillar 591 being formed of P+ polysilicon in a dielectric layer 592, for example connected to a conductor 590 provided above the active column 581 and extending in a configuration parallel to the word line. The conductor 590 may also be formed of heavily doped polysilicon or silicide or a metal conductor. In this arrangement, the body bias voltage (V bb ) 594 may be provided from substrate 505 through vias 593 in openings in dielectric isolation 509 to conductor 590 to facilitate a bulk erase operation.

[0098] Figure 6e The body bias voltage is shown provided by conductors 690-1 and 690-2 ("body bias conductors"). Figure 6b The layout of the embodiment shown shares the body bias voltage between body regions in adjacent rows of active columns. In this configuration, word line 592 (i.e., word line 623p-L) extends in line with body bias conductor 690-1. The block size of the erase operation is limited to the active columns to the left of each body bias conductor (e.g., conductor 690-1) and the active columns to the right of each body bias conductor. Larger erase blocks can be configured, for example, to bundle clusters of body bias conductors together to match the number of word lines of the addressing bit line segment. A decoder in the substrate provides the appropriate body bias voltage (e.g., erase voltage) to one or more selected erase blocks.

[0099] Reference back Figure 5b After forming the active columns (eg, active column 581), a dielectric layer 592 is formed over the active columns. Thereafter, vias are anisotropically etched from the top of the dielectric layer 592 to the top of the body region 556. + A layer of doped polysilicon is then deposited over dielectric layer 592, filling the vias to form conductor pillars (e.g., conductor pillar 591). +The layer of doped polysilicon is then patterned and etched to form a conductor (e.g., conductor 590) to connect through via 593 to provide a body bias voltage V bb Voltage source 594. Body bias voltage V bb This can be a positive high voltage applied during erase or a low negative substrate bias voltage applied during read to raise the TFT threshold voltage or reduce its sub-threshold leakage. Figure 6e It is shown that the formation of P + Top view of doped polysilicon features 690 - 1 and 690 - 2 .

[0100] exist Figure 5b In the embodiment shown in , conductor 590 is provided above body region 556. However, in other embodiments, conductor 590 may be provided below body region 556 to contact body region 556 from below. In fact, it may be advantageous to provide body bias voltage from above and from below body region 556. In the case where the body bias voltage is provided from below, a conductor similar to conductor 590 may be provided directly from the substrate through a via in the interlayer dielectric, with Figure 5a Similar to that shown.

[0101] Operational modes of segmented local bit line and segmented local source line arrays

[0102] In a memory stack having, for example, 64 planes of word lines for bit line segments, such as described above with respect to embodiments of the present invention, when reading storage transistors on any plane (e.g., plane 25) associated with a selected bit line segment, all word lines at all planes associated with the selected bit line segment are held at their "off" threshold voltages, except for the word line that is addressing the selected storage transistor on the selected plane. When the word line voltage is raised, the storage transistors in the erased state (i.e., the conductive or "on" state) will raise their bit line voltage (V bl ) to its local source line (and its associated source line segment, if applicable), which had previously been charged to a virtual ground potential (V ss ). The bit line voltage V is sensed by the sense amplifier for the bit line segment. b1The rate of discharge. Other storage transistors associated with other bit line segments sharing the same word line in the Y direction on the selected plane (i.e., the 25th plane in this example), or other storage transistors associated with other bit line segments in the X direction addressed by different word lines, can be read simultaneously because each bit line segment has its dedicated sense amplifier. For a read operation, during a precharge operation, the dummy source voltage is first precharged by setting the local bit line to 0V. (Alternatively, the dummy source voltage can be raised to ~1V.) After precharge, the local bit line is charged to the sense amplifier voltage (e.g., ~0.1V to 0.5V above the source voltage), and the substrate is set to a voltage V bb (eg, ~0V to ~-2V) and the word line WL is raised to ~1V-3V above the erase threshold voltage.

[0103] For embodiments where storage transistors on both sides of each word line are Figure 6a and 6e In the embodiment of the present invention, care must be taken to ensure that only one of the two storage transistors is conductive at any time during a read operation. As discussed above, this is achieved by providing discrete bit line segments that extend parallel to each other, but each of which is served by its own sense amplifier, decoder, voltage supply and other supporting circuitry. Figure 6e As shown, the bit line segments are MSBL1 (L) for the left storage transistor and MSBL1 (R) for the right storage transistor.

[0104] To program the memory transistors, all word lines on all planes except the selected plane (the 25th plane in this example) are set to ground potential, while the word line addressing the selected memory transistor (i.e., on the 25th plane) is increased using, for example, a gradual voltage step (e.g., from The voltage on the bit line segment and the associated source line segment are maintained at ground potential during the programming operation.

[0105] In order to inhibit further programming while continuing to program the storage transistors associated with other bit line segments sharing the same word line on the selected plane, the bit line segments and source line segments are raised to a program inhibit voltage (e.g., approximately one-third or one-half of the programming voltage) until the end of the programming sequence, with a read verification cycle between consecutive programming pulses. All programming and program inhibit voltages to local bit lines and local source lines within a bit line or source line segment are provided only through the bit line segment (through a precharge operation of the source line). As with the read operation, storage transistors associated with other bit line segments along the Y direction (i.e., sharing the same word line as the selected storage transistor), and storage transistors associated with other bit line segments along the X direction (i.e., associated with different word lines) can be programmed or inhibited from programming at the same time.

[0106] The erase operation can be accomplished by holding all word lines of the storage transistors associated with the bit line segment, source line segment, or block to be erased at 0 V, while the body bias voltage (V bb ) to (i.e., storage transistors that have never been programmed or erased), and the body bias voltage of the high cycle count storage transistors is raised to as high as 20 V or more. All sense amplifiers associated with the bit line segments can be isolated from their bit lines or bit line segments because the floating N+ vertical local source lines and N+ vertical local bit lines within the erase block follow the positive voltage applied to their p-body regions.

[0107] Reading, programming, program inhibiting, and erasing may be performed by other conditions familiar to those of ordinary skill in the art.

[0108] Low latency split local and global word lines.

[0109] The bit line segmentation in an embodiment of the present invention is used to significantly reduce the RC delay in conventional global bit lines of conventional three-dimensional NAND and three-dimensional NOR memory arrays. Another major cause of long read latency is the long and high capacitive local word line conductors, which are typically almost half or the entire width of the chip orthogonal to the local bit lines. Therefore, the three-dimensional vertical NOR flash memory array of US2017 / 0092371 A1, like the conventional three-dimensional NAND flash memory array, requires at least one layer of local word line conductors for each storage plane. In a 64-plane NAND or NOR memory array, these word line conductors are constructed with high-step steps. Because the local word lines supply high voltages during programming, the decoders of the local word lines require high-voltage transistor circuits, which can occupy a large amount of silicon area for each such step-like step.

[0110] To reduce the associated overhead costs, word lines are typically very long, which results in high RC delays and poor read latency (e.g., in the range of a few microseconds). In conventional three-dimensional NAND memory arrays, global bit lines are also too long and have slow rise or fall times, which essentially masks the problem of long word line latency. In the case of the bit line segments of the present invention, since the bit line response time can be very short (e.g., in the range of 100 nanoseconds), the long word line RC delay becomes a limiting factor for fast read access. According to one embodiment of the present invention, a partial solution makes the three-dimensional NOR memory chip long and narrow (i.e., short along the direction of the word line and long along the direction of the bit line segment). Although such a design does not reduce the silicon area forming the word line decoder, it significantly reduces the length and RC delay of the word line without significantly increasing the RC delay along the bit line segment.

[0111] According to another embodiment of the present invention, the word line delay can be further reduced by dividing the memory array into more blocks with shorter word lines, each block forming a staircase with its repetition. By dividing the memory array by doubling the number of staircases and their word line decoders, the RC delay can be reduced by 4 times.

[0112] Another significant contributor to long read latency is the large RC delay of the global word lines (GWLs) extending in the X direction, which spans the length of the memory array over the stair-stepped steps along the sides of the memory array. Figure 6f An implementation of a global word line for connecting local word lines on one plane (ie, in a stair-step) in conjunction with the bit line segmentation scheme of the present invention is illustrated. Figure 6f In the figure, only the local word lines at one XY plane passing through the stair-like steps along the side of the memory array, the global word lines above the stair-like steps, and their interconnections are shown. For the sake of clarity, all other details (e.g., P - channel material layer and charge trapping layer). Figure 6f As shown, the memory array (eg, corresponding to Figure 6e The word lines WL0, WL1, ... of the memory array of the embodiment shown in the figure extend in the Y direction. The global word lines GWL0, GWL1, ... extend in the X direction above the stair-like steps. The global word lines connect the word lines at each plane of the memory array to their corresponding decoders, voltage sources and other supporting circuits in the substrate 605. Figure 3d , 3e In the architectures of 3f and 3g, each staircase step can accommodate at most n global bit lines, which match the n number of local word lines in the bit line segment. Figure 6fIn the embodiment of FIG. 1 , for example, each bit line segment may include 128 bit lines and each storage transistor at each step is selected by a corresponding word line. Therefore, there are 128 word lines at each step of the bit line segment. Therefore, each global word line is connected to every 128th word line. For example, on each plane, the global word line GWL0 is connected to the global word line GWL0 through vias VIA0, VIA1, VIA2, VIA3, VIA4, VIA5, VIA6, VIA7, VIA8, VIA9, VIA10, VIA11, VIA12, VIA13, VIA14, VIA15, VIA16, VIA17, VIA18, VIA19, VIA20, VIA21, VIA22, VIA23, VIA19, VIA24, VIA25, VIA26, VIA27, VIA28, VIA30, VIA31 127 , ... are connected to word lines WL-0, WL-127, ..., and GWL1 is connected to the substrate decoder and voltage source through vias VIA1, VIA2 in its substrate 605. 128 , ... are connected to word lines WL-1, WL-129, .... This arrangement allows 128 sets of storage transistors on each plane to be read simultaneously by activating a common global word line and its dedicated sense amplifier decoder. i+128 ,…(Generally, WL i+128k , k=0,1,…) can be read or programmed simultaneously by activating the global word line GWLi, while all other global word lines at the same step or at other steps can be at ground potential (i.e., all other storage transistors are disconnected) or floating at ground potential.

[0113] Figure 6f The embodiment illustrated in FIG. 1 may be considered to consume silicon area: if there are 128 word lines and 64 stair steps in each bit line segment, then each of the 64 stair steps requires 128 global word lines (or a total of 8192 global word lines). According to an embodiment of the present invention, the number of global word lines required can be reduced by 2, 4, 8, 16 times or more by having each global word line contact more than one local word line in each bit line segment. For example, global word line GSL1 can contact not only word lines WL1, WL2, but also word lines WL3, WL4, WL5, WL6, WL7, WL8, WL9, WL10, WL11, WL12, WL13, WL14, WL15, WL16, WL17, WL18, WL19, WL20, WL19, WL21, WL12, WL13, WL14, WL15, WL16, WL17, WL18, WL19, WL21, WL19, WL19, WL21, WL1 129 , ..., and can contact the word line WL 33 , WL 65 ,...(Generally, WL 1+32k , k = 0, 1, ...), thereby reducing the number of global word lines required for each step by a factor of four, and reducing the total width of the staircase by a factor of four. Of course, additional decoding circuitry is required in the silicon substrate or four times the number of dedicated sense amplifiers for each bit line segment. (Alternatively, a single sense amplifier for a bit line segment can be time-shared through four consecutive read or program sequences.)

[0114] Because the global word lines are implemented at the top of the memory array above the stair-like steps, low-resistivity copper interconnects can be used to implement the global word lines. The capacitance between adjacent global word lines within a step can be reduced by replacing the air gap between them with a dielectric, as known to those of ordinary skill in the art. The global word line RC delay can be further reduced by connecting a global word line decoder in the silicon substrate under the stair-like steps to a voltage source to access the global word line every half, quarter, or eighth of the global word line length through interruptions along the length of the global word line.

[0115] When going from, for example, a 32-layer stack to a 64-layer stack, the number of word line stair-steps doubles from 32 to 64. Figure 6g An embodiment of a vertical NOR string memory array avoiding such step doubling is shown according to one embodiment of the present invention. Figure 6g , a ZY cross-section of a memory array is shown, wherein the total number of planes in the memory array is provided to be two or more stacks (e.g., STK1 and STK2) formed one above the other in succession. Each stack is provided having its own set of stair-like steps completed, and then the next stack is formed. In a prior art three-dimensional NAND memory array, two stacks of memory cells are formed, each stack consisting of 32 planes. Thereafter, stair-like steps of 64 planes are then formed, respectively, followed by their associated global word lines. In contrast, Figure 6f The stacked bodies STK1 and STK2 (step A, step B) are shown each having only 32 wide stair-shaped steps, each of which is formed by global word lines GWL1, GWL2, ..., GWL 32 (extending in the X direction) connected word lines (extending in the Y direction). Stacks STK1 and STK2 are isolated from each other by isolation layer 617, thereby reducing the total width to half to provide 64 stair-step steps. Under this scheme, local bit lines (e.g., BL 654) and local source lines (e.g., SL 655) in stack STK2 are connected to their corresponding local bit lines and local source lines in stack STK1 by etching through isolation layer 617 to expose openings at the tops of the N+ doped vertical columns, thereby connecting the vertical active columns of the top 32 planes to their corresponding components in the lower 32 planes above substrate 605. Similarly, the P-doped channel regions (e.g., corresponding to the P-doped channel regions) of both stacks STK1 and STK2 are connected to the top 32 planes of the substrate 605. Figure 5b The channel regions 556 and 656 of the embodiment of the present invention are connected together by a P+ doped plug 691, which is formed in the isolation layer 617 before forming STK2.

[0116] The silicon substrate area associated with the global word lines can be reduced by locating the global word line decoders and voltage sources below the staircase steps or on top of the memory array rather than outside the array in the substrate. Figure 3f and 3g The memory array of FIG. 1 provides such placement. In those embodiments, the top surface of the memory array is free of any source line or bit line interconnects. Of course, such word line decoders and voltage sources are implemented using thin film transistors, which must be able to support the relatively high voltages required for the global word lines during programming (e.g., in the range of 12V-20V). Such thin film transistors can be implemented by shallow (excimer) laser annealing to partially recrystallize the deposited polysilicon, or by seeding technology developed for solar panels or LED displays or other applications. The top surface of the memory array can also be used to extend larger or taller global word line interconnects with larger spacing between them to reduce their RC delay without excessively increasing the memory chip area.

[0117] 3D vertical NOR array with segmented bit lines of quasi-volatile NOR strings.

[0118] Non-provisional patent application III, which is incorporated by reference above and now published as US 2017 / 0092371A1 (“the '237 publication”), discloses quasi-volatile NOR strings (see the '237 publication, paragraphs

[0128] -

[0131] ) that are suitable for replacing DRAM in certain memory applications that do not require extremely high cycle durations. To this end, the read access time of the quasi-volatile NOR strings approaches that of DRAM, which is approximately 500 times faster than conventional three-dimensional NAND flash memory at less than 100 nanoseconds. In the three-dimensional vertical NOR strings disclosed in this detailed description, segmented bit lines and their dedicated sense amplifiers located at the bottom of the array, decoders (e.g., Figure 3d , 3e , 3f, and 3g) closely emulate the horizontal strings of non-provisional patent application III and are similarly able to achieve read latencies close to DRAM. The process steps for constructing these quasi-volatile vertical NOR strings are similar to the steps described in paragraph

[0129] of the '237 publication. Because the retention time of quasi-volatile storage transistors is relatively short (e.g., in the range of one hour to several days), they require frequent read refreshes; in this scenario, having the ability to read or reprogram a large number of storage transistors simultaneously (i.e., read and reprogram storage transistors associated with many bit line segments in parallel) is critical to minimizing interruptions to normal reads as chip densities approach 1TB.

[0119] Non-Provisional Patent Application III also discloses pairing two storage transistors in a horizontal NOR string for fast read cache memory (see the '237 publication, paragraphs

[0194] -

[0196] ). As disclosed in this detailed description, segmented bit lines with dedicated segment sense amplifiers in a vertical NOR string are well suited for such fast read cache memory, where a two-transistor pair can be used to program data on one transistor and the inverted data (i.e., erased state) on an adjacent transistor sharing the same word line. For example, Figure 6e , will come from the same word line WL 31-1 The two transistors T in the two adjacent bit line segments MSBL1(L) and MSBL1(R) on both sides of L (683), T R The read output signal of (682) is fed into a differential sense amplifier in the silicon substrate. The differential sense amplifier is shared between two adjacent bit line segments along the Y direction. This dual segment arrangement, while reducing the array bit efficiency by 50%, provides excellent resistance to process variations and string leakage, parameter drift, or device sensitivity on the chip, while providing very fast sensing, higher cycle duration, and omitting the need for a programmable reference string. Because of the isolation between the bit line segments along the X direction (i.e., along the same direction as the global bit lines), it is possible to have blocks of bit line segments on the same chip that are configured with paired transistor differential sensing for cache storage, while other blocks employ conventional sensing with a single transistor at a time for density doubling. This flexibility allows the same chip to be used partially as a cache memory and partially as a storage memory. It also allows files that require multiple pages of storage (e.g. a photo image that requires 4MB of storage takes up 2000 pages of 2KB each) to have their first page or pages written to a segment with fast cache memory and the rest written to non-cached segments on the same chip, and then fetch the image by reading its first page very quickly, while pipelined reads are used for the other pages to enjoy lower read latency for the entire 4MB.

[0120] Although the global bit line segmentation of the present invention into regional bit lines with corresponding segment sense amplifiers and global word line segments (combined with Figure 6f and 6g ), but this can be similarly applied to conventional three-dimensional vertical NAND memory strings.

[0121] Manufacturing process

[0122] Figure 7a , 7b 7c and 7d are cross-sections of intermediate structures formed in a fabrication process of a multi-gate NOR string array according to an embodiment of the present invention.

[0123] Figure 7a The cross section of the semiconductor structure 700 after a low resistivity layer 723p has been formed over the substrate 701 according to one embodiment of the present invention is shown in the ZY plane. In this embodiment, p is an integer between 0 and 31, representing each of the 32 word lines. Figure 7a As shown, semiconductor structure 700 includes low resistivity layers 723-0 to 723-31. Semiconductor substrate 701 represents, for example, a P-doped bulk silicon wafer, on which and in which support circuits for memory structure 700 can be formed prior to forming the vertical NOR string. Such support circuits can include both analog and digital logic circuits. Some examples of such support circuits can include shift registers, latches, sense amplifiers, reference cells, power supply lines, bias and reference voltage generators, inverters, NAND, NOR, XOR and other logic gates, input / output drivers, address decoders including bit line and word line decoders, other memory elements, sequencers and state machines. In order to provide these support circuits, a conventional N-well, P-well, triple well (not shown), N + The diffusion region (eg, region 707-0) and P + Diffusion regions (eg, region 706), isolation regions, low voltage and high voltage transistors, capacitors, resistors, transistors, and interconnects constitute building blocks as known to those skilled in the art.

[0124] After supporting circuits have been formed in and on the semiconductor substrate 701, an insulating layer 708 is provided, which may, for example, be deposited or grown as thick silicon dioxide. In some embodiments, one or more metal interconnect layers may be formed, including a global source line 713-0, which may be provided as a horizontal long and narrow strip extending in a predetermined direction. The global source line 713-0 is connected to the circuit 707 in the substrate 701 through an etched opening 714. For ease of discussion in this detailed description, the global source line is assumed to extend in the X direction. Metal interconnects may be formed by applying photolithographic patterning and etching steps to one or more deposited metal layers. (Alternatively, these metal interconnects may be formed using a conventional damascene process, such as a conventional copper or tungsten damascene process). A thick dielectric layer 709 is then deposited, followed by planarization using conventional chemical mechanical polishing (CMP).

[0125] Conductor layers 723 - 0 to 723 - 31 are then formed successively, each of which is isolated from the layer below and the layer above by an intermediate insulating layer 726 . Figure 7a, although thirty-two conductor layers are indicated, any number of such layers may be provided. In fact, the number of conductor layers that may be provided may depend on the process technology, such as the use of a well-controlled anisotropic etching process that allows cutting through multiple conductor layers and the dielectric isolation layer 726 therebetween. For example, the conductor layer 723p may be formed by first depositing a 1-2 nm thick layer of titanium nitride (TiN), followed by a 10–50 nm thick layer of tungsten (W) or a similar refractory metal or silicide, such as nickel, cobalt or tungsten and other silicides, or self-aligned silicides, followed by a thin layer of etching stop material, such as aluminum oxide (Al2O3). Each conductor layer is etched in block 700 after deposition, or each conductor layer is deposited as a block by a conventional damascene process. In Figure 7a In the embodiment of FIG. 7 , each continuous conductor layer 723p extends in the Y direction by a distance 727 shorter than (i.e., recessed from) the edge of the immediately preceding metal layer, so that all conductor layers can be contacted from the top of the structure 700 in a later step of the process. However, in order to reduce the formation of Figure 7a The number of masking and etching steps required for the stepped conductor stack of block 700 can be reduced by achieving the recessed surface 727 for multiple conductor layers simultaneously using other process techniques known to those skilled in the art that do not require each individual conductor plane to be masked and etched separately to create the exposed recessed surface 727. After the conductor layers are deposited and etched, a corresponding layer of dielectric isolation layer 726 is then deposited. Dielectric isolation layer 726 can be, for example, silicon dioxide having a thickness between 15 and 50 nanometers. Conventional CMP prepares the surface of each dielectric layer for deposition of the next conductor layer. The number of conductor layers in the stack of block 700 corresponds at least to the number of memory TFTs in the vertical NOR string, plus any additional conductor layers that may be used as, for example, pre-charge TFTs (e.g., Figure 5a The control gate of a non-memory TFT (e.g., a precharge TFT 575) or a bit line access selection TFT (e.g., Figure 5a The steps of conductor layer deposition and etching and dielectric layer deposition and CMP processes are repeated until all conductor layers are provided.

[0126] A dielectric isolation layer 710 and a hard mask layer 715 are then deposited. The hard mask 715 is patterned to allow etching of the conductor layer 723p to form long strips that have not yet formed word lines. The word lines extend in length along the Y direction. FIG. 6 shows an example of a mask pattern for word lines 623p-R, 623p-L, which includes features such as extensions toward each other in adjacent word lines by discrete amounts 676, and recesses in each word line for creating a desired curvature 675. Deep trenches are created by anisotropically etching continuous conductor layers 723p and their corresponding intermediate dielectric insulating layers 726 until the dielectric layer 709 at the bottom of the conductor layer 723p is reached. Because a large amount of the conductor layer is etched, the photoresist mask itself is not robust enough to maintain the desired word line pattern through multiple continuous etchings. In order to provide a robust mask, a hard mask layer 715 (e.g., carbon) is preferred, as known to those of ordinary skill in the art. The etching may terminate at the dielectric material 709, at the landing pad 713 on the global source line, or at the substrate 701. An etch stop barrier film (eg, aluminum oxide) may be advantageously provided to protect the landing pad 713 from etching.

[0127] Figure 7b A cross section of semiconductor structure 700 according to one embodiment of the present invention is shown in the ZX plane, with a trench (eg, deep trench 795 ) etched through continuous conductor layer 723 p and corresponding dielectric layer 726 , which contacts down to dielectric layer 709 . Figure 7b In the embodiment of the present invention, the conductor layer 723p is anisotropically etched to form conductor stacks 723p-R and 723p-L, which are separated from each other by deep trenches 795. The anisotropic etching is a high aspect ratio etching. In order to achieve the best results, the etching chemistry may have to alternate between the etching of the conductor material and the etching of the dielectric, because, as known to those skilled in the art, the etching passes through the materials of different layers. The anisotropy of the multi-step etching is important because the undercut of any layer should be avoided so that the word line obtained at the bottom of the stack has approximately the same conductor width and groove spacing as the corresponding width and spacing of the word line at or near the top of the stack. Naturally, the larger the number of conductor layers in the stack, the more challenging it is to maintain a slight pattern tolerance through multiple continuous etchings. In order to alleviate the difficulty associated with etching through, for example, 64 or 128 or more conductor layers, etching can be performed in sections, for example, every 32 layers. The separated etched sections can then be spliced ​​together, as taught, for example, in the Kim reference mentioned above.

[0128] Etching through multiple conductor layers 723p composed of a conductor material (e.g., tungsten or other refractory material) is more difficult and time-consuming than etching the intermediate insulating layer 726. Therefore, an alternative process can be used to eliminate the need for multiple etchings of the conductor layer 723p. The process (known to those skilled in the art) includes first replacing the conductor layer 723p with a sacrificial layer of an easily etched material. Figure 7b For example, the insulating layer 726 may be silicon dioxide and the sacrificial layer (occupying Figure 7b The spaces shown as 723p in the figure can be silicon nitride or other fast etching dielectric materials. Deep trenches can then be anisotropically etched through the alternating dielectric layers of ONON (oxide-nitride-oxide-nitride) to create tall stacks of dual dielectrics. At a later step in the manufacturing process flow (to be described below), these stacks are supported by active vertical strips of polysilicon, allowing the sacrificial layer to be etched away, preferably by selective chemical or isotropic etching. The cavities thus created are then filled by conformal deposition of conductor material, resulting in conductor layers 723p separated by intermediate insulating layers 726.

[0129] In the formation Figure 7b After the structure of FIG. 7 is formed, a charge trapping layer 734 and a polysilicon layer 730 are then successively and conformally deposited on the sidewalls of the etched conductor wordline stack. Figure 7c The cross section of the resulting structure is shown in the ZX plane. Figure 7c As shown, a charge trapping layer 734 is formed, for example, by first depositing a blocking dielectric 732a, which is a dielectric film of 5 to 15 nanometers thick and includes a high dielectric constant (e.g., aluminum oxide, hafnium oxide, or some combination of silicon dioxide and silicon nitride). Thereafter, a charge trapping material 732b is deposited to a thickness of 4 to 10 nanometers. The charge trapping material 732b can be, for example, silicon nitride, silicon-rich oxynitride, conductive nanodots embedded in a dielectric film, or a thin conductive floating gate isolated from adjacent TFTs sharing the same vertical active strip. The charge trap 732b can then be capped with a deposited conformal thin tunneling dielectric film (e.g., a silicon dioxide layer or a silicon oxide-silicon nitride-silicon oxide ("ONO") trilayer) with a thickness ranging from 2 to 10 nanometers. The storage element formed by the charge trapping layer 734 can be any of the following: SONOS, TANOS, nanodot memory, isolated floating gate, or any suitable charge trapping sandwich structure known to those of ordinary skill in the art. The combined thickness of the charge-trapping layer 734 is typically between 15 and 25 nanometers.

[0130] After depositing the charge trapping layer 734, a contact opening is made at the bottom of the trench 795 using a masking step and by anisotropic etching through the charge trapping layer 734 and the dielectric layer 709 at the bottom of the trench 795, and at the source supply voltage Vss (See Figure 7b ) stops at the bottom global source line landing pad 713, or at the global bit line voltage V b1 (not shown) or at the back bias supply voltage V bb The contact stops at the P+ region 706 (see Figure 7c ). In some embodiments, prior to this etching step, an ultra-thin film of polysilicon (e.g., 2 to 5 nanometers thick) is deposited to protect the vertical surfaces of tunneling dielectric layer 732c during the contact opening etching of charge trapping material 734 at the bottom of trench 795. In one embodiment, each global source line is connected only to alternating vertical NOR string pairs in a row of vertical NOR string pairs. For example, in Figure 5a For odd-numbered address word lines, electrical contacts (eg, contact openings 557) are etched to connect N+ doped local source lines (eg, Figure 5a Similarly, for even-numbered address word lines, electrical contacts are etched to connect the N+ doped local source lines in the rows of vertical NOR string pairs to global source line 513-2 ( Figure 5a ). Through the parasitic capacitor C (i.e., Figure 5a The capacitor 560 in the embodiment adopts the virtual V ss In an embodiment, the step of etching through the charge trapping layer 734 at the bottom of the trench 795 can be skipped.

[0131] Thereafter, a polysilicon film 730 is deposited to a thickness ranging from 5 to 10 nanometers. Figure 7c , polysilicon films 730 are shown on opposite sidewalls of trench 795, labeled 730R and 730L, respectively. Polysilicon film 730 is undoped or preferably P-doped with boron, with a doping concentration typically in the range of 1×10 16 / cm 3 Up to 1×10 17 / cm 3 The trench 795 is wide enough to accommodate the charge trapping layer 734 and the polysilicon film 730 on its opposite sidewalls. After the polysilicon 730 is deposited, the sacrificial layer in the stack described above is etched away and the conductor layer 723p ( Figure 7c ) fills the cavity thus formed.

[0132] like Figure 7bAs shown, the trench 795 extends in the Y direction. After forming the isolated word line stacks 723p-L and 723p-R, in one example, the semiconductor structure 700 can have 16,000 or more side-by-side word line stacks or 16,000 TFTs (8,000 TFTs on each side of the stack), each word line stack serving as a control gate for 8,000 or more active columns to be formed along the length of each stack. With 64 word lines in each stack, 16 billion TFTs can eventually be formed in each such multi-gate vertical NOR string array. If each TFT stores two data bits, such a multi-gate vertical NOR string array will store 32GB of data. Approximately 32 such multi-gate vertical NOR string arrays (plus spare arrays) can be formed on a single semiconductor substrate, thereby providing a 1TB integrated circuit chip.

[0133] Figure 7d In one embodiment Figure 7c A cross-sectional view in the XY plane of the top surface of the structure. Nested between word lines 723p-L and 723p-R are two sidewalls 730L and 730R of a vertically deposited P-doped polysilicon structure (i.e., active column). The deep gap 740 between sidewalls 730L and 730R can be filled with a fast-etching insulating dielectric material (e.g., silicon dioxide or liquid glass or carbon-doped silicon oxide). Conventional CMP can then be used to flatten the top surface. A photolithography step then exposes openings 776 and 777, followed by a high aspect ratio selective etch to dig the fast-etching dielectric material in the exposed areas 776 and 777 all the way down to the bottom of trench 795. A hard mask may be required in this etching step to avoid excessive pattern degradation during etching. The excavated gap is then filled with in-situ N+ doped polysilicon. N+ dopants are diffused into the very thin, lightly doped active polysilicon pillars 730L and 730R within the exposed voids to make them N+ doped. Alternatively, the lightly doped polysilicon inside the voids can be etched away by a simple isotropic plasma etch or a selective wet etch before filling the voids with in-situ N+ doped polysilicon. CMP or top surface etching then removes the N+ polysilicon from the top surface, leaving tall N+ polysilicon pylons in regions 754 (N+) and 755 (N+). These N+ pylons form the shared vertical local source lines and shared vertical local bit lines for the TFTs in the resulting vertical NOR string.

[0134] Figure 7d-1The conductivity of the tall vertical source / drain towers is shown to be greatly improved by only partially filling the exposed voids 776 of the vertical towers 754 and 755, for example by first depositing ultra-thin layers 754 (N+) and 755 (N+) of N+ doped polysilicon, each layer being between 5 and 15 nanometers thick (insufficient to fill the voids), and then depositing (e.g., using atomic layer deposition (ALD)) a metallic conductive material (e.g., titanium nitride, tungsten nitride, or tungsten) to fill the remaining voids 720 (M) at the cores of the source / drain towers. See also Fig.4a1 , which shows in the YZ plane the metal conductor 420 (M) occupying the core of the pylon, which is in close contact with the ultra-thin N+ polysilicon 454 (N+). Due to the relatively significantly higher conductivity of the metal material at the core, the N-type doping concentration of the ultra-thin N+ doped polysilicon can be reduced by one to two orders of magnitude, thereby reducing the undesirable thermal diffusion of the N-type dopant into the P-type dopant of the channel. The N+ / metal conductor structure can be applied to one or both of the source and drain pylons. In another embodiment, with the P- doping 756 in the channel region (which can be 2×10 18 / cm 3 The thin P-doped polysilicon in region 757 outside of channel region 756 may first be more heavily doped P+ (e.g., 10 19 / cm 3 or higher). Adding P+ polysilicon in the source tower that contacts the P- polysilicon in the channel can improve erase efficiency when the local source line is raised to a positive high voltage during an erase operation.

[0135] Next, a dielectric isolation layer is deposited and patterned using a photolithography mask and etching steps. The etching step opens the contacts used to connect the vertical local bit lines to the horizontal global bit lines (e.g., contact 657-1 to the string at odd addresses and contact 657-2 to the string at even addresses, as shown in FIG6 ). A low resistivity metal layer (e.g., tungsten) is deposited. The deposited metal is then patterned using photolithography and etching steps to form global bit lines (e.g., global word line 614-1 or GBL1 for the string at odd addresses; global bit line 614-2 (GBL2) for the string at even addresses, as shown in FIG6 ). Alternatively, a conventional copper damascene process can be used to form the global bit lines. As known to those skilled in the art, all global bit lines of the word line stack and all metal layers 723p ( Figure 7a ) are connected to the bit line decoding and sensing circuits and word lines in the substrate through etched vias. Switching and sensing circuits, decoders and reference voltage sources can be provided to the global bit lines and global word lines individually or shared by several bit lines and word lines.

[0136] In some embodiments, as known to those skilled in the art, the bit line access select transistor ( Figure 5a 511 in) and its associated control gate word line (eg, Figure 5a The word lines 585 in FIG. 5A are formed as isolated vertical N+P-N+ transistors to separate odd and even global bit lines (e.g., Figure 6a The bit lines 614-1 and 614-2 in FIG. 1 are selectively connected to vertical NOR strings at alternating odd and even addresses (e.g., Figure 6a 657-1 and 657-2, respectively).

[0137] Read Operation

[0138] Because the TFTs of the vertical NOR strings are connected in parallel, in all embodiments of the present invention, all TFTs in an active column (including the active column on which the vertical NOR string pair is formed) should preferably be in enhancement mode—that is, each TFT should have a positive gate-to-source threshold voltage—in order to provide a positive gate-to-source threshold voltage on the shared local source line and the shared local bit line (e.g. Figure 4c The enhancement mode TFT is formed by a 1×10 16 and 1×10 17 / cm 3 The channel region is doped with boron at a concentration between Figure 7c The P-channel region 756 of the active column is implemented with a target intrinsic TFT threshold voltage of about 1 V. Using such a TFT, all unselected word lines of the vertical NOR string pair of the active column can be held at 0 V. Alternatively, the read operation can be performed on the shared local N+ source line (e.g., Figure 4c The voltage on the local source line 455 of the TFT is raised to about 1.5 V, while the voltage on the shared local N+ drain line (e.g., local bit line 454) is raised to about 2 V, and all unselected local word lines are held at 0 V. Such a configuration is equivalent to setting the word line to -1.5 V relative to the source, thereby suppressing leakage current caused by slight depletion of the threshold voltage of the TFT, such as would occur if the TFT were slightly over-erased.

[0139] After erasing the TFTs of a vertical NOR string, a soft programming operation may be required to move any TFTs in the vertical NOR string that were over-erased (ie, now have a depletion mode threshold voltage) back to the enhancement mode threshold voltage. Figure 5a , an optional connection 556 is shown through which the P-channel is connected to the back bias voltage 506 (V bb )(exist Figure 4c 456). bbA negative voltage can be used to modulate the threshold voltage of the TFTs in each active column to reduce the sub-threshold leakage current between the shared N+ source and the shared N+ drain / local bit line. In some embodiments, a positive V bb The voltage is used to tunnel and erase the TFT whose control gate is kept at 0V.

[0140] To read the data stored in the TFTs of a vertical NOR string pair, all TFTs in both vertical NOR strings of the vertical NOR string pair are initially placed in an "off" state by holding all word lines in the multi-gate NOR string array at 0 V. Addressed vertical NOR strings can share sensing circuits among several vertical NOR strings along a common word line using a decoding circuit. Alternatively, each vertical NOR string can be connected to a global bit line (e.g., Figure 4c In the latter case, one or more vertical NOR strings sharing the same word line plane can be sensed in parallel. Each addressed vertical NOR string has its local source line, which is either connected to the dedicated sense circuit through Figure 8a A hardwired global source line (e.g., Figure 4c GSL1 in is set to or through a precharge transistor (e.g. Figure 4c The precharge transistor 470 in or Figure 3c The transistor 317 in the The precharge transistor will Temporarily transferred to parasitic capacitance C (eg, capacitor 460 or capacitor 360 of floating local source line 455 or 355), such as Figure 8b Shown schematically.

[0141] Immediately after turning off the precharge transistor 470, the bit line access select transistor (eg, Figure 4c The bit line access select transistor 411 or Figure 5a The bit line access select transistor 511 in the embodiment of the present invention is used to select the local bit line (e.g., Figure 4c The local bit line 454) is set to The voltage at the sense amplifier of the vertical NOR string used for addressing is also used. At this time, the addressed word line is raised from 0V to typically about 6V in a small gradual voltage step, while all unselected word lines at the odd address TFTs and even address TFTs of the vertical NOR string pair are kept at 0V. Figure 8a The hardwired V ss In one example, the addressed TFT has been programmed to a threshold voltage of 2.5V, so the voltage V on the local bit line LBL is bl Start by passing the selected TFT to the local source line (Vss ) discharge, as long as its WL S More than 2.5V, so provide a voltage drop ( Figure 8a This voltage drop is detected at the sense amplifier servicing the selected global bit line. Figure 8b Virtual V ss In the embodiment, the precharge transistor word line WL CHG Temporarily turned on to precharge the floating local source line LSL to 0V at the beginning of the read sequence. Then, the selected word line WL S The selected TFT will increase the voltage on its local bit line from V to bl The voltage drops by 2V. Figure 8b The dummy voltage V is detected by a sense amplifier connected to a global bit line of a selected local bit line (shown by a dashed arrow in FIG. 1 ). As known to those skilled in the art, there are other alternatives to correctly read the programmed threshold voltage of the selected TFT. ss In an embodiment, the taller the vertical stack, the larger the capacitance C, and thus the longer the retention time and the larger the read signal presented to the selected sense amplifier. To further increase C, one or more dummy conductors may be added to the vertical string in one embodiment, the primary purpose of which is to increase the capacitance C.

[0142] In the case of an MLC implementation (i.e. a "multi-level cell" implementation, where each TFT stores more than one bit), the addressed TFTs can already be programmed to one of several voltages (e.g. 1V (erased state), 2.5V, 4V or 5.5V). S The voltage is increased in gradual steps until conduction in the TFT is detected at the sense amplifier. Alternatively, a single word line voltage (e.g. volts), and the local bit line LBL (V bl ) is compared to the discharge rates of several programmable reference voltages representing the voltage states of the stored multiple bits. This approach can be extended to a continuum of states to effectively provide analog storage. The programmable reference voltages can be stored in a dedicated reference vertical NOR string located within the multi-gate vertical NOR string array, so that the characteristics during reading, programming, and background leakage are closely tracked. In a vertical NOR string pair, only the TFTs on one of the two vertical NOR strings can be read in each read cycle; the TFTs on the other vertical NOR string are placed in the "off" state (i.e., all word lines are 0V). During the read cycle, since only one TFT in the vertical NOR string is exposed to the read voltage, there is essentially no read disturb condition.

[0143] In one example of an embodiment of the present invention, 64 TFTs and one or more pre-charge TFTs may be provided on each vertical NOR string of a vertical NOR string pair. Each word line forms a capacitor at the intersection with a local vertical N+ source line column (see, e.g. Figure 6a The capacitance 660 of such a capacitor may be, for example, 1×10 -18 Farad. Including all the capacitors in the two vertical NOR strings of the vertical NOR string pair, the total distributed capacitance C is about 1×10 -16 Farads, which is sufficient to keep the local source line at the precharged source voltage (V ss ), which is typically completed in less than one microsecond directly after the precharge operation. The charging time through the bit line access select transistor 411 and the precharge TFT 470 is on the order of a few nanoseconds, so the charging time does not significantly add to the read latency. Reading from the TFTs in the vertical NOR string is fast because the read operation involves conduction in only one TFT in the vertical NOR string, unlike the read operation on the NAND string, where multiple TFTs in series need to be conducted.

[0144] There are two main factors that affect the read latency of the vertical NOR string of the present invention: (a) the resistance R bl and capacitor C bl The associated RC time delay (e.g. Figure 6a (b) when the addressed TFT begins to conduct, the sense amplifier senses the voltage drop V on the local bit line (e.g., LBL-1) bl The RC time delay associated with servicing a global bit line of, for example, 16,000 vertical NOR strings is on the order of tens of nanoseconds. Figure 1b The read latency of the TFT of a NAND string) is determined by the current flowing through 32 or more TFTs in series and the discharge capacitance C of the global bit line selection transistor. bl In contrast, in the vertical NOR string of the present invention, only one addressing transistor (e.g., Figure 4a The transistor 416L) provides the read current discharge C bl , resulting in a faster discharge of the local bit line voltage (V bl ). As a result, much lower latency is achieved.

[0145] exist Figure 4c, when one TFT (e.g., TFT 416L in vertical NOR string 451b) is read at a time, all other TFTs in vertical NOR string 451a or 451b of vertical NOR string pair 491 remain in the "off" state, with their word lines maintained at 0 V. Even though TFT 416R in vertical NOR string 452a of vertical NOR string pair 492 shares word line W31 with TFT 416L, TFT 416R can still be read simultaneously with TFT 416L because vertical NOR string 452a is served by global bit line 414-2, while vertical NOR string 451b is served by global bit line 414-1. ( Figure 6a and 6b Illustrated is how global bit lines 614-1 and 614-2 serve adjacent vertical NOR strings).

[0146] In one embodiment, the wordline stack includes 32 or more wordlines provided in 32 planes. In a multi-gate vertical NOR string array, each plane may include 8,000 wordlines controlling 16,000 TFTs, each of which can be read in parallel via 16,000 global bitlines, as long as each bitline is connected to a dedicated sense amplifier. Alternatively, if several global bitlines share sense amplifiers via a decoding circuit, 16,000 TFTs will be read in several consecutive read cycles. Reading a large number of discharged TFTs in parallel will cause a large drop in the ground power supply (V ss ), which may cause a voltage bounce in the local source line (i.e., providing a dummy source voltage (V ss The embodiment using the pre-charged parasitic capacitor C in )) has a particular advantage because such ground voltage bounce is eliminated. This is because the dummy source voltage in the vertical NOR string is independent and not connected to the ground supply of the chip.

[0147] Program (write) and program inhibit operations.

[0148] Programming of the addressed TFT can be achieved by: when a selected word line (eg, word line 423p-R) is aligned with an active channel region (eg, Figure 4a When a high programming voltage is applied between the active channel region 456 in the TFT, electrons are pulled from the channel region of the TFT (e.g., Figure 4bThe TFTs are programmed to a charge trapping layer (e.g., charge trapping layer 434) by tunneling - either directly or by Fowler-Nordheim tunneling - through the channel region 430L shown. Since tunneling is efficient, very little current is required to program the TFTs, and thus parallel programming of tens of thousands of TFTs can be achieved with low power consumption. Programming by tunneling may require, for example, 20V, 100 microsecond pulses. Preferably, programming is achieved by successive, shorter duration step voltage pulses starting at about 14V and up to about 20V. The step voltage pulses reduce the electrical stress on the TFTs and avoid overshooting the intended programmed threshold voltage.

[0149] After each high voltage pulse of programming, the addressed transistor is read to verify whether it has reached its target threshold voltage. If the target threshold voltage has not been reached, the next programming pulse applied to the selected word line is typically stepped up by a few hundred millivolts. This program verification sequence is repeatedly applied to the active columns (e.g., Figure 4b 430L) has an addressed word line (ie, control gate) that has access to local bit lines (eg, Figure 4a 454). At these programmed high word line voltages, the channel region of TFT 416L is inverted and held at 0V, causing electrons to tunnel into the charge storage layer of TFT 416L. When the read sense indicates that the addressed TFT has reached its target threshold voltage, the addressed TFT must be inhibited from further programming, while other TFTs sharing the same word line can continue to be programmed to their higher target threshold voltages. For example, when programming TFT 416L in vertical NOR string 451b, programming of all other TFTs in vertical NOR strings 451b and 451a must be inhibited by holding all word lines of all other TFTs at 0V.

[0150] To inhibit further programming of TFT 416L, a half-select voltage (i.e., approximately 10V) is applied to local bit line 454 once it reaches the target threshold voltage. With 10V set in the channel region and 20V set on the control gate, only a net 10V voltage is applied to the charge trapping layer, so the Fowler-Nordheim tunneling current is negligible, and no meaningful further programming occurs on TFT 416L during the remaining sequence of step pulse voltages up to 20V. By raising local bit line 454 to 10V while continuing to ramp up the programming voltage pulses on word line WL31, all TFTs on the vertical NOR string sharing the same selected word line are correctly programmed to their higher target threshold voltages. The sequence of "program-read-program inhibit" is essential in order to correctly program tens of thousands of parallel TFTs to their various target threshold voltage states in multi-level cell storage. If there is no such program inhibition to over-program individual TFTs, it may result in an over-limit or merged threshold voltage with the next higher target threshold voltage state. Although TFT 416R and TFT 416L share the same word line, they belong to different vertical NOR string pairs 452 and 451. TFT 416L and TFT 416R can be programmed with the same programming pulse voltage sequence because their corresponding bit line voltages are supplied by GBL1 and GBL2 and are independently controlled. For example, TFT 416L can continue to be programmed, while TFT 416R can be prohibited from further programming at any time. These programming and programming inhibition voltage conditions can be met because the vertical NOR strings 451a and 451b of the vertical NOR string pair 491 are controlled by separate word lines 423p-L and 423p-R, respectively, and the voltage on each local bit line can be set independently of all other vertical NOR string pairs. During programming, any unselected word line in an addressed word line stack or in an unaddressed word line stack can be set to 0V, half-select 10 volts, or floating. In the process of selecting the transistor ( Figure 4c ) to access the global source line (e.g., Figure 4c In the embodiment of GSL1), the access select transistor is turned off during programming, causing the voltage on the local source line 455 to follow the voltage on the local bit line 454 during programming and program inhibit. The same applies to Figure 4c The capacitor 460 in FIG. 4 represents an embodiment of a parasitic capacitance C providing a voltage on a local source line. Figure 4c In an embodiment with a global source line but no source access select transistors, the voltage applied to the global source line 413-1 of the addressed string should preferably track the voltage of the addressed global bit line 414-1 during programming and inhibiting programming.

[0151] Each progressively higher voltage programming pulse is followed by a read cycle to determine whether TFTs 416L and 416R have reached their respective target threshold voltages. If so, the drain, source, and body voltages are raised to 10V (alternatively, these voltages are floated to near 10V) to inhibit further programming, while word line WL31 continues to program other addressed TFTs on the same plane that have not yet reached their target threshold voltages. The sequence terminates when all addressed TFTs have been read and verified to be correctly programmed. In the case of MLC, programming one of multiple threshold voltage states can be accelerated by setting each addressed global bit line to one of several predetermined voltages (e.g., 0V, 1.5V, 3.0V, or 4.5V, representing four different states of 2-bit data to be stored), and then applying step programming pulses (up to about 20V) to word line WL31. In this way, the addressed TFT receives a predetermined one of the effective tunneling voltages (i.e., 20, 18.5, 17, and 15.5 volts), resulting in one of the predetermined threshold voltages being programmed into the TFT in a single programming sequence. Fine programming pulses can then be provided at the individual TFT level.

[0152] Accelerate full-plane parallel programming

[0153] Due to the inherent parasitic capacitance C of each local source line in the multi-gate vertical NOR string array, all local source lines in the multi-gate vertical NOR string array can have 0V (for programming) or 10V (for inhibiting), which is temporarily placed on all vertical NOR strings (e.g., by the global bit line GBL1 and the bit line access string select transistor 411 and the pre-charge transistor 470) before applying the high voltage pulse sequence. This process can be implemented by addressing the word line planes one by one. For each addressed word line plane, a programming pulse sequence can be applied to many or all word lines on the addressed word line plane, while all word lines on other word line planes are kept at 0V, so that a large number of TFTs on the addressed plane are programmed in parallel, and then individually read-verified and, if necessary, the local source lines of the appropriately programmed TFTs are reset to the program inhibit voltage. This method provides a significant advantage because the programming time is relatively long (i.e., about 100 microseconds), while the speed of precharging all local source line capacitors or reading and verifying all TFTs sharing the addressed word line plane is more than 1000 times faster. Therefore, it is desirable to program as many TFTs as possible in parallel in each word line plane.This accelerated programming feature provides a greater advantage in MLC programming, which is much slower than single bit programming.

[0154] Erase Operation

[0155] For some charge trapping materials, the erase operation performed by reverse tunneling of the trapped charge can be quite slow, sometimes requiring pulses of 20V or more for tens of milliseconds. Therefore, the erase operation can usually be implemented at the vertical NOR string array level ("block erase") performed in the background. A typical vertical NOR string array can have 64 word line planes, each of which controls, for example, 16384×16384 TFTs, for a total of about 17 billion TFTs. Therefore, if two bits of data are stored on each TFT, then a TB chip can include about 30 such vertical NOR string arrays. In some embodiments, block erase can be implemented by applying about 20V to the P-channel shared by all TFTs in the vertical NOR string (for example, Figure 4c The body connection 456 and Figure 5a The erase pulse is then erased to a contact 556 in the block while keeping all word lines in the block at 0V. The duration of the erase pulse should be such that most of the TFTs in the block are erased to a slightly enhancement mode threshold voltage, i.e., between zero and one volt. Some TFTs will overshoot and be erased to depletion mode (i.e., slightly negative threshold voltage). As part of the erase command, after the erase pulse is terminated, soft programming may be required to return the over-erased TFTs to the slightly enhancement mode threshold voltage. A vertical NOR string that may contain one depletion mode TFT among multiple depletion mode TFTs that cannot be programmed to enhancement mode may have to be disabled to be replaced with a spare string.

[0156] Alternatively, in addition to providing an erase pulse to the bulk (ie, the P-layer), the local source lines and local bit lines (eg, Figure 4c The local source lines 455 and local bit lines 454 in the vertical NOR string are raised to about 20V while all word lines on all word line planes are held at 0V for the duration of the erase pulse. This scheme requires the global source line and global bit line select decoders to employ high voltage transistors that can withstand 20V at their junctions. Alternatively, all TFTs sharing an addressed word line plane can be erased together by applying a -20V pulse to all word lines on the addressed plane while holding word lines on all other planes at 0V. All other voltages in the vertical NOR string pair are held at 0V. This will erase only the X-Y slice of all TFTs contacted by one addressed plane of word lines.

[0157] Semi-nonvolatile NOR TFT string

[0158] Some charge-trapping materials suitable for use in perpendicular NOR strings (e.g., oxide-nitride-oxide or "ONO") have long data retention times (typically on the order of many years), but low endurance (i.e., performance degrades after a certain number of write-erase cycles, typically on the order of tens of thousands or less). However, in some embodiments, a charge-trapping material may be selected that retains the stored charge for a greatly reduced time but has greatly increased endurance (e.g., retention times on the order of minutes or hours, and endurance on the order of tens of millions of write-erase cycles). For example, in Figure 7c In an embodiment, the thickness of the tunneling dielectric layer 732c, which is typically a 6-8 nanometer SiO2 layer, can be reduced to about 2 nanometers, or replaced with another dielectric material of similar thickness (e.g., SiN). The thinner dielectric layer can use a moderate voltage to introduce electrons into the charge trapping layer through direct tunneling (which is different from Fowler-Nordheim tunneling that requires a higher voltage), and the electrons will be trapped from a few minutes to a few hours or days. The charge trapping layer 732b can be silicon nitride, conductive nanodots dispersed in a thin dielectric film, or other combinations including charge trapping films that isolate thin floating gates. The blocking layer 732a can be silicon dioxide, aluminum oxide, hafnium oxide, silicon nitride, a high dielectric constant dielectric, or any combination thereof. The blocking layer 732a blocks the electrons in the charge trapping layer 732b from escaping to the control gate word line. The trapped electrons will eventually leak back into the active region 730R due to the breakdown of the ultra-thin tunneling dielectric layer or by reverse direct tunneling. However, such loss of trapped electrons is relatively slow. Other combinations of charge storage materials can also be used, resulting in high endurance but low retention "semi-volatile" storage TFTs that require periodic write or read refresh operations to replenish the lost charge. Because the vertical NOR strings of the present invention have relatively fast read access (i.e., low latency), they can be used in certain applications that currently require the use of dynamic random access memory (DRAM). The significant advantages of the vertical NOR strings of the present invention over DRAM are: lower cost per bit, because DRAM cannot be built in a three-dimensional stack; and much lower power consumption, because the refresh cycle only needs to be run once every few minutes or hours, compared to every few milliseconds required to refresh DRAM. The three-dimensional semi-volatile storage TFT of the present invention is achieved by selecting appropriate materials for the charge trapping material, such as the materials discussed above, and by appropriately adjusting the program / read / inhibit program / erase conditions and combining periodic data refresh.

[0159] NROM / Mirror Bit NOR TFT String

[0160] In another embodiment of the present invention, the vertical NOR string can be programmed using a channel hot electron injection method similar to the injection method used in two-dimensional NROM / mirror bit transistors known to those skilled in the art. Figure 4a Taking the embodiment of as an example, the programming conditions for channel hot electron injection can be: 8V on the control gate 423p, 0V on the local source line 455, and 5V on the local drain line 454. The charge representing one bit is stored in the charge storage layer at one end of the channel region 456 next to the intersection with the local bit line 454. By reversing the polarity of the local source line 455 and the local bit line 454, the charge representing the second bit is programmed and stored in the charge storage layer, which is located at the opposite end of the channel region 456 next to the intersection with the local bit line 454. Reading the two bits requires reading in the opposite programming order, as is known to those skilled in the art. The efficiency of channel hot electron programming is much lower than the efficiency of programming by direct tunneling or Fowler-Nordheim tunneling, and therefore, it is not suitable for massive parallel programming using tunneling. However, each TFT has twice the bit density, making it attractive for applications such as archive memory. Erasing of the NROM TFT embodiment can be achieved by employing a conventional NROM erase mechanism, which is to neutralize the charge of trapped electrons by hot hole injection induced by band to band tunneling: -5V is applied to the word line, 0V is applied to the local source line 455, and 5V is applied to the local bit line 454. Alternatively, the high positive substrate voltage V bb is applied to the body region 456 to erase the NROM TFT. Due to the high programming current associated with channel hot electron injection programming, all embodiments of vertical NROM TFT strings must employ hard-wired local source lines and local bit lines, such as Figure 3a and 6c In the embodiment of .

[0161] The above detailed description is provided to illustrate specific embodiments of the present invention and is not intended to limit the present invention. Various variations and modifications are possible within the scope of the present invention. The present invention is set forth in the appended claims.

Claims

1. An array of thin film NOR memory strings formed in a semiconductor structure above a planar surface of a semiconductor substrate, wherein each NOR memory string comprises a plurality of memory transistors, and wherein the semiconductor substrate comprises circuitry formed therein or thereon for supporting memory circuit operation, and wherein each thin film NOR memory string comprises: a common source region and a common drain region, each region extending longitudinally along a first direction substantially perpendicular to the planar surface; a plurality of channel regions, each channel region being provided between and in contact with both the common drain region and the common source region; a plurality of regions of data storage material, each region being associated with and in contact with a respective one of the channel regions; a plurality of gate electrodes spaced apart and insulated from each other by a dielectric material, each gate electrode being positioned adjacent to one of the channel regions and separated from the channel region by an associated region of the data storage material, each gate electrode extending longitudinally along a second direction substantially parallel to the planar surface, wherein each memory transistor of the NOR memory string is formed by one of the gate electrodes, the common source region, the common drain region, a portion of the channel region adjacent to the gate electrode, and a region of the data storage material associated with the channel region.

2. The array of thin film NOR memory strings of claim 1, wherein: The semiconductor structure further includes: a source line selection transistor electrically coupled to the common source region and configured to receive a control signal that switches the source line selection transistor between a conducting state and a non-conducting state; and An interconnect conductor extends along a third direction substantially orthogonal to the first direction and the second direction, the interconnect conductor electrically connecting the circuit for supporting memory operation to the source line selection transistor, so that when the source line selection transistor is in the on state, the common source region is electrically coupled to the circuit for memory operation through the interconnect conductor.

3. The array of thin film NOR memory strings of claim 2, wherein: The source line selection transistor includes a source region, a channel region, and a drain region stacked along the first direction.

4. The array of thin film NOR memory strings of claim 1 further comprising: (i) a first conductor segment, a second conductor segment, and a third conductor segment associated with a first thin film NOR memory string, a second thin film NOR memory string, and a third thin film NOR memory string of the thin film NOR memory strings, wherein (a) the first conductor segment electrically connects both common drain regions of the first thin film NOR memory string and the second thin film NOR memory string, (b) the second conductor segment electrically connects the common drain region of the third thin film NOR memory string, and (c) the third conductor segment electrically connects circuitry for supporting memory operations; and (ii) a first bit line select transistor and a second bit line select transistor, each of which is configured to receive a control signal that causes the bit line select transistor to switch between a conductive state and a non-conductive state, wherein (a) when the first bit line select transistor is biased to its conductive state, the first bit line select transistor connects the first conductor segment to the third conductor segment, and (b) when the second bit line select transistor is biased to its conductive state, the second bit line select transistor connects the second conductor segment to the third conductor segment.

5. The array of thin film NOR memory strings of claim 4, wherein: Each of the conductor segments is provided between the semiconductor substrate and a planar surface of the semiconductor substrate.

6. The array of thin film NOR memory strings of claim 4, wherein: The first bit line selection transistor and the second bit line selection transistor are both formed in the semiconductor substrate.

7. The array of thin film NOR memory strings of claim 4, wherein: Each of the first conductor segment, the second conductor segment, and the third conductor segment is provided over the semiconductor substrate.

8. The array of thin film NOR memory strings of claim 4, wherein: Each of the first bit line selection transistor and the second bit line selection transistor includes a source region, a channel region, and a drain region stacked along the first direction.

9. The array of thin film NOR memory strings of claim 4, wherein: The first conductor segment and the second conductor segment are formed in an interconnect layer formed substantially parallel to the planar surface.

10. The array of thin film NOR memory strings of claim 1, wherein: The thin film NOR memory strings are isolated from each other by an isolating dielectric material or by an air gap.

11. The array of thin film NOR memory strings of claim 1 , wherein: Each thin film NOR memory string also includes one or more stepped structures, so that each gate electrode of the thin film NOR memory string terminates at one of the stepped structures, and wherein each gate electrode is electrically coupled to a circuit for supporting memory operation through a conductor-filled through-hole at its stepped structure.

12. The array of thin film NOR memory strings of claim 1, wherein: The circuit for supporting memory operation includes a body bias voltage source, wherein the channel regions of the thin film NOR memory string are each electrically connected to the body bias voltage source.

13. The array of thin film NOR memory strings of claim 1, further comprising metal towers each embedded in a common source region or a common drain region, each metal tower comprising one or more of titanium nitride, tungsten nitride or tungsten.

14. The array of thin film NOR memory strings of claim 1, wherein: Each channel region is substantially semi-annular, and wherein each region of the data storage material forms an annular ring surrounding the channel region.

15. The array of thin film NOR memory strings of claim 1, wherein: The common source region and the common drain region are formed of heavily doped semiconductor material.

16. The array of thin film NOR memory strings of claim 15, wherein: The NOR memory strings are organized into a two-dimensional array extending along the second direction and a third direction, the third direction being parallel to the planar surface.

17. The array of thin film NOR memory strings of claim 16, wherein: The semiconductor structure also includes a set of interconnect conductors, each interconnect conductor extending longitudinally along the second direction above or below the gate electrode, wherein the common drain region and the common source region of the NOR memory string can be selectively connected to an associated one of the set of interconnect conductors.

18. The array of thin film NOR memory strings of claim 17, wherein: The set of interconnect conductors includes a plurality of bit line segments, each bit line segment being associated with a predetermined number of common drain regions arranged along the second direction, and wherein each bit line segment is selectively electrically isolated from the other bit line segments.

19. The array of thin film NOR memory strings of claim 18, wherein: The circuit in the semiconductor substrate includes at least a plurality of sense amplifiers and a plurality of segment selection transistors distributed over the entire planar surface of the semiconductor substrate, each sense amplifier being connected to a corresponding bit line segment through a different group of one or more of the segment selection transistors.

20. The array of thin film NOR memory strings of claim 18, wherein: The set of interconnect conductors also includes a plurality of regional bit line segments, each regional bit line segment being selectably connectable to the plurality of bit line segments.

21. The array of thin film NOR memory strings of claim 1, further comprising a pre-charge transistor associated with each common source region, the pre-charge transistor configured to charge the common source region to a predetermined voltage.

22. The array of thin film NOR memory strings of claim 21, wherein: During a read, program, program inhibit, or erase operation, a parasitic capacitor in each common source region capacitively maintains the predetermined voltage.

Images