Spinning logic device, spinning logic memory device and preparation method
The spin logic device addresses complexity and inefficiency in existing magnetoelectric coupling devices by employing a simplified structure with spin-orbit coupling layers to regulate ferroelectric polarization, enabling efficient and reconfigurable logic and memory functions.
Patent Information
- Application Number
- CN202411179057.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-27
- Publication Date
- 2024-12-13
AI Technical Summary
Current magnetoelectric coupling devices for spin logic are complex in structure and inefficient in energy consumption, with existing technologies requiring complex membrane stacks and high energy consumption for regulating output current direction.
A spin logic device with a simplified structure comprising an oxide layer, multiferroic layer, spin-orbit coupling layers, and electrodes, where spin currents are injected and regulated through symmetrically distributed spin-orbit coupling units to achieve different logic gates by flipping ferroelectric polarization configurations.
The device enables efficient and reconfigurable logic operations with reduced energy consumption by utilizing spin waves and non-volatile gate control, supporting various logic gates and memory functions with a simple and easy-to-manufacture design.
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Figure CN119136643A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of logic storage technology, and in particular to a spin logic device, a spin logic storage device, and a preparation method thereof. Background Art
[0002] Magnetoelectric coupling devices have attracted widespread attention due to their ultra-low energy consumption and miniaturization. However, the current structure of magnetoelectric coupling devices is relatively complex, and experimental implementation is challenging. For example, US20220076868 patent discloses a magnetoelectric coupling spin logic device. It injects spin current into the two-dimensional electron gas through the ferromagnetic layer plan, which is inefficient. The output current is generated by the inverse spin Hall effect. The membrane stack and device structure are more complex; US11785783B2 patent discloses a magnetoelectric coupling spin logic device. It injects spin current into the two-dimensional electron gas through the polarization of the ferromagnetic layer, which is inefficient. The output current is generated by the inverse spin Hall effect. The output current direction is regulated by flipping the ferromagnetic layer through magnetoelectric coupling, and the energy consumption is high. The membrane stack and device structure are more complex; US11502188B2 patent discloses a magnetoelectric coupling device. It enhances the efficiency of spin current injection through a ferromagnetic layer and a filter layer. Its logic operation also requires flipping the ferromagnetic layer through magnetoelectric coupling to regulate the output current direction, which consumes a lot of energy. The membrane stack and device structure are more complex. Summary of the invention
[0003] In view of this, in order to at least partially solve at least one of the above-mentioned technical problems, the present disclosure provides a spin logic device, a spin logic memory device and a preparation method.
[0004] In order to achieve the above purpose, the technical solution of the present invention is as follows:
[0005] According to an embodiment of one aspect of the present disclosure, a spin logic device is provided, comprising: an oxide layer; a multiferroic layer, located on the oxide layer and forming a two-dimensional electron gas as a transmission layer between the oxide layer, transmitting spin current in the form of spin waves; a spin-orbit coupling layer, comprising a first spin-orbit coupling unit and a second spin-orbit coupling unit, the first spin-orbit coupling unit and the second spin-orbit coupling unit are not connected to each other and are symmetrically distributed on the multiferroic layer; a top electrode, comprising a first top electrode respectively connected to the first spin-orbit coupling unit and a second top electrode connected to the second spin-orbit coupling unit; and a bottom electrode, comprising a first bottom electrode and a second bottom electrode respectively connected to both sides of the oxide layer.
[0006] According to the embodiment of the present disclosure, the first spin-orbit coupling unit and the second spin-orbit coupling unit are used to respectively adjust the polarization direction of the multiferroic layer region therebelow and to respectively inject spin currents into the multiferroic layer.
[0007] According to an embodiment of the present disclosure, voltages are applied between the first top electrode and the first bottom electrode, and between the second top electrode and the second bottom electrode, respectively, to flip the local multiferroic layer between the first top electrode and the first bottom electrode, and the local multiferroic layer between the second top electrode and the second bottom electrode to different ferroelectric polarization configurations, thereby realizing different logic gates.
[0008] According to the embodiment of the present disclosure, when the ferroelectric polarization directions of the local multiferroic layer between the first top electrode and the first bottom electrode and the local multiferroic layer between the second top electrode and the second bottom electrode are the same, OR logic or XNOR logic is implemented.
[0009] According to the embodiment of the present disclosure, when the ferroelectric polarization directions of the local multiferroic layer between the first top electrode and the first bottom electrode and the local multiferroic layer between the second top electrode and the second bottom electrode are opposite, XOR logic is implemented.
[0010] According to an embodiment of another aspect of the present disclosure, a spin logic memory device is provided, comprising: the spin logic device described above; and a gate dielectric layer, adjacent to the oxide layer and between the regions of the vertical projection of the plane where an unconnected gap between a first spin-orbit coupling unit and a second spin-orbit coupling unit is located.
[0011] According to the embodiments of the present disclosure, by applying a gate voltage to the gate dielectric layer, the two-dimensional electron gas conductive channel can be non-volatilely controlled; by applying a gate voltage to the gate dielectric layer, the two-dimensional electron gas below the gate dielectric layer is depleted and the conductive channel is turned off; the heterojunctions on the left and right sides of the gate are independently controlled and read to realize the function of a binary storage unit; when the two-dimensional electron gas is enhanced and the conductive channel is turned on, the function of a spin logic device can be realized.
[0012] According to the disclosed embodiment, the spin-orbit coupling layer is made of a material selected from topological materials, heavy metals, and semi-metals; the multiferroic layer is made of a material selected from BiFeO 3 、ErFeO 3 ScFeO 3 、HoFeO 3 、YFeO 3 、SrTiO 3 、BiTiO 3 , KTaO 3 ; The material for preparing the oxide layer is selected from SrTiO 3 、LaAlO 3 、EuO、AlO x , topological materials, heavy metals, semi-metals; preparation materials for gate dielectrics BiFeO 3 、Pb(Zr 0.2 Ti 0.8 ) 3 、TaO x , HfO x, GdO x 、HfZrO.
[0013] According to an embodiment of another aspect of the present disclosure, a method for preparing the spin logic device described above is provided, comprising: S1: sequentially growing an oxide layer, a multiferroic layer, and a SOC layer on a wafer with designed interconnections; S2: processing the separated SOC layers through photolithography and ion beam etching to obtain a spin-orbit coupling layer; S3: in-situ growing an insulating medium on the wafer after etching to insulate the device; S4: performing a second photolithography and ion beam etching, and the etching is stopped on the oxide layer; S5: in-situ growing an insulating medium on the wafer after etching to insulate the device; S5: performing a third photolithography and ion beam etching to open a bottom electrode through hole; S6: preparing a bottom electrode on the etched wafer; S7: performing a fourth photolithography and ion beam etching to open a top electrode through hole; S8: preparing a top electrode on the etched wafer.
[0014] According to another embodiment of the present disclosure, a method for preparing the spin logic memory device described above is provided, comprising: S10: growing a gate dielectric layer on a wafer with designed interconnections, and processing a gate pattern by photolithography and ion beam etching, and in-situ growing an insulating dielectric on the wafer after etching to insulate the device; S20: performing chemical mechanical polishing on the wafer after the insulating dielectric is grown; S30: sequentially growing an oxide layer, a multiferroic layer, and a SOC layer on the polished wafer; S40: performing a second photolithography and ion beam etching to etch out the SOC layers on both sides; S 50: After etching, an insulating dielectric is grown in situ on the wafer to insulate and protect the device, and a third photolithography and ion beam etching are performed, with the etching stopped on the oxide layer; S60: an insulating dielectric is grown in situ to insulate and protect the device; S70: a fourth photolithography and ion beam etching are performed to open the bottom electrode through hole and prepare the bottom electrode on the etched wafer; S80: a fifth photolithography and ion beam etching are performed to open the top electrode through hole and prepare the top electrode on the etched wafer; S90: a sixth photolithography and ion beam etching are performed to open the gate electrode through hole and prepare the gate electrode on the etched wafer. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] The above and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:
[0016] Figure 1 A schematic diagram showing the structure of a spin logic device and the implementation principle of an OR gate and an XNOR gate according to an embodiment of the present disclosure is shown;
[0017] Figure 2 A schematic diagram showing the structure of a spin logic device and an XOR gate implementation principle of an embodiment of the present disclosure is shown;
[0018] Figure 3A schematic diagram showing the physical mechanism of a spin logic device according to an embodiment of the present disclosure is shown;
[0019] Figure 4 A process flow chart of a specific method for preparing a spin logic device according to an embodiment of the present disclosure is shown;
[0020] Figure 5 A schematic diagram showing the structure and working mode of a spin logic memory device according to an embodiment of the present disclosure is shown.
[0021] Figure 6 A process flow chart of a method for preparing a spin logic memory device according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION
[0022] The present invention provides a spin logic device, a spin logic storage device and a preparation method with a simple structure and easy preparation, wherein the switching of spin logic and storage functions can be realized by controlling the opening and closing of the 2DEG (two-dimensional electron gas) conductive channel by non-volatile gate voltage. When used as a spin logic device, the multifunctional and reconfigurable logic gate function can be realized by regulating the different configurations of ferroelectric polarization in the multiferroic layer.
[0023] In order to make the objectives, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.
[0024] In the embodiments of the present disclosure, Figure 1 and Figure 2 As shown, a spin logic device is provided, comprising: an oxide layer (denoted by Oxide in the figure); a multiferroic layer (denoted by FE in the figure), which is located on the oxide layer and forms a two-dimensional electron gas (denoted by 2DEG in the figure) as a transmission layer between the oxide layer and the oxide layer, and transmits spin current in the form of spin waves; a spin-orbit coupling layer (denoted by Electrode in the figure), comprising a first spin-orbit coupling unit (left side) and a second spin-orbit coupling unit (right side), wherein the first spin-orbit coupling unit and the second spin-orbit coupling unit are not connected to each other and are symmetrically distributed on the multiferroic layer; a top electrode, comprising a first top electrode (E 1 ) and a second top electrode (E 2 ); and a bottom electrode, comprising a first bottom electrode (E) connected to both sides of the oxide layer respectively. 1 ') and the second bottom electrode (E 2 ').
[0025] It can be seen that the multiferroic layer is formed on the side of the oxide layer away from the substrate, and is used to form a two-dimensional electron gas at the interface with the oxide, and acts as a transmission layer to transmit spin current in the form of spin waves; the two spin-orbit coupling layers are formed on the side of the multiferroic layer away from the oxide layer, and are not connected to each other, and are used to respectively regulate the polarization direction of the multiferroic layer region below them, and respectively inject spin current into the multiferroic layer. During initialization, voltages are applied between the first top electrode and the first bottom electrode on the left, and the second top electrode and the second bottom electrode on the right, respectively, to flip the local multiferroic layer under the left top electrode and the local multiferroic layer under the right top electrode to different ferroelectric polarization configurations. Figure 1 As shown, when the ferroelectric polarization directions of the multiferroic layers on the left and right sides are the same (such as in Figure 1 The arrows representing the polarization direction are all pointing upwards), and OR and XNOR logic can be realized. When the logic input is mapped to the input current being present or absent, and the logic output is mapped to the total loop current I Total =(I Out1 +I Out2 ),As long as any input (I in1 , I in2 ) is not 0, the output current I Total When the logic input is mapped to the input forward or reverse, and the logic output is mapped to the total loop current (I Out1 +I Out2 ), when the two inputs are reversed (10 or 01), I Out1 , I Out2 The amplitudes are equal but the directions are opposite. At this time, the total current in the circuit (I Out1 +I Out2 ) is 0. Only when the input is in the same direction (11 or 00), I Out1 , I Out2 The amplitudes are equal and the directions are the same. At this time, the total circuit current (I Out1 +I Out2 ) is 1, corresponding to the logical XNOR gate. Figure 2 As shown in the figure, when the polarization directions of the multi-ferroic layers corresponding to the top and bottom electrodes on the left and right sides are opposite, XOR logic can be realized. When the logic input is mapped to the presence or absence of input, and the logic output is mapped to the total loop current (I Out1 +I Out2 ), when the two inputs are in the same direction (11 or 00), I Out1 , I Out2 The amplitudes are equal but the directions are opposite. At this time, the total circuit current (I Out1 +I Out2 ) is 0. Only when the two input directions are opposite (10 or 01), I Out1 , I Out2 The amplitude is equal and the direction is the same, the total circuit current (I Out1 +IOut2 ) is 1, realizing logical XOR gate operation.
[0026] Figure 3 The physical mechanism of the spin logic device described in the present disclosure is described. Intrinsic, a two-dimensional electron gas (2DEG) with a strong Rashba effect is formed at the interface between the multiferroic layer and the oxide layer. The Rashba effect causes the spin band splitting in the 2DEG, and the spin and momentum are locked to each other (Spin-momentum locking). The polarity of the Rashba effect is determined by the polarity of the interface electric field (E). When the input current J in Flowing through the SOC layer along the x direction, due to the strong spin-orbit coupling effect of the SOC layer, a spin current polarized along the y direction is generated (J S ), the spin current is injected into the multiferroic layer along the z direction and is transmitted in the multiferroic layer in the form of magnon (J M ). When an unbalanced spin current is injected into the 2DEG, the Fermi surface in the k-space shifts Δk along the kx direction. Due to the translation of the Fermi surface, an output current (J) along the x-direction is generated. out ), resulting in the Inverse Rashba-Edelstein effect. Since the polarity of the Rashba effect is determined by the interface electric field, the direction of the output current will also be reversed when the direction of the interface electric field is changed. Therefore, when the direction of the ferroelectric polarization (P) of the multiferroic layer is flipped, the direction of the interface electric field will be reversed, and the corresponding output current will also be reversed under the same input.
[0027] According to another embodiment of the present disclosure, Figure 4 As shown, a method for preparing the above spin logic device is provided, comprising operations S1-S9:
[0028] S1: Thin film growth: an oxide layer (Oxide), a multiferroic layer (FE), and a spin-orbit coupling layer (SOC) are sequentially grown on the designed interconnected wafer. In practice, a cap layer (not shown) is also added on the SOC layer to prevent oxidation of the SOC layer, etc.;
[0029] S2: The SOC layers on both sides are processed by photolithography and ion beam etching (i.e., the first spin-orbit coupling unit on the left and the second spin-orbit coupling unit on the right in the figure); S3: After etching, the insulating dielectric is grown in situ on the wafer to insulate the device;
[0030] S4: performing a second photolithography and ion beam etching, with the etching being stopped on the oxide layer;
[0031] S5: After etching, the wafer is in-situ grown with insulating dielectric to provide insulation protection for the device;
[0032] S6: performing a third photolithography and ion beam etching to open a bottom electrode through hole; S7: forming a bottom electrode (a first bottom electrode E1 and a second bottom electrode E2) on the etched wafer by sputtering / evaporation and stripping;
[0033] S8: performing the fourth photolithography and ion beam etching to open the top electrode through hole;
[0034] S9: forming top electrodes (first top electrode E1' and second top electrode E2') on the etched wafer by sputtering / evaporation and stripping, wherein two first top electrodes E1' are respectively prepared on both sides of the first spin-orbit coupling unit, and two second top electrodes E2' are respectively prepared on both sides of the second spin-orbit coupling unit).
[0035] In the embodiments of the present disclosure, Figure 5 As shown, a spin logic memory device is provided, comprising: the spin logic device described above; and a gate dielectric layer (represented by Dielectric in the figure), which is located on the oxide layer and between the areas of the vertical projection of the plane where the gap between the first spin-orbit coupling unit and the second spin-orbit coupling unit is not connected.
[0036] like Figure 5 The device structure and different working modes of the spin logic memory device are shown. The spin logic memory device includes two spin-orbit coupling layers (SOC), a multiferroic layer (FE), an oxide layer (Oxide), and a gate dielectric layer (Dielectric). The two spin-orbit coupling layers are formed on the substrate and are not connected to each other. They are used to respectively regulate the polarization direction of the multiferroic layer above them and inject spin currents into the multiferroic layers respectively; the multiferroic layer is formed on the side of the spin-orbit coupling layer away from the substrate, and acts as a transmission layer to transmit the spin current in the form of spin waves; the oxide layer is formed on the side of the multiferroic layer away from the spin-orbit coupling layer, and forms a two-dimensional electron gas (2DEG) at the interface with the multiferroic layer; the gate dielectric layer is formed on the side of the oxide layer away from the multiferroic layer, and is located between the vertical projection areas of the two spin-orbit coupling layers on the plane. By applying a gate voltage V to the gate dielectric layer G , the 2DEG conductive channel at the interface can be non-volatilely controlled. Initially, the channel is turned on, and the spin logic memory device is implemented as follows Figure 1 and Figure 2 The reconfigurable logic functions of the spin logic device shown (such as Figure 5 As shown on the left). After the gate voltage is applied, the 2DEG under the gate is depleted, the channel is turned off, and the heterojunctions on the left and right sides of the gate are independently regulated and read. At this time, the spin logic memory device realizes the function of a binary storage unit (such as Figure 5 shown on the left).
[0037] According to another embodiment of the present disclosure, a method for preparing the spin logic memory device described above is also provided, comprising S10-S90:
[0038] S10: growing a gate dielectric layer on the wafer with designed interconnections, and processing a gate pattern through photolithography and ion beam etching. After etching, an insulating dielectric is grown in situ on the wafer to insulate and protect the device;
[0039] S20: The wafer after the insulating medium is grown is processed by chemical mechanical polishing;
[0040] S30: sequentially growing an oxide layer, a multiferroic layer, and a SOC layer on the polished wafer;
[0041] S40: performing a second photolithography and ion beam etching to etch out the SOC layers on both sides;
[0042] S50: After etching, an insulating dielectric is grown in situ on the wafer to insulate the device, and a third photolithography and ion beam etching are performed, with the etching being terminated on the oxide layer;
[0043] S60: In-situ growth of insulating dielectric for device insulation protection;
[0044] S70: fourth photolithography and ion beam etching to open bottom electrode through holes and prepare bottom electrodes (first bottom electrode E1 and second bottom electrode E2) on the etched wafer;
[0045] S80: performing the fifth photolithography and ion beam etching to open the top electrode through hole and prepare the top electrode (the first top electrode E1' and the second top electrode E2') on the etched wafer;
[0046] S90: Perform the sixth photolithography and ion beam etching to open the gate electrode through hole and prepare the gate electrode G on the etched wafer.
[0047] In the above spin logic device and spin logic memory device, the spin-orbit coupling layer is one, multiple or related combinations of topological materials, heavy metals, semi-metals, etc.; the multiferroic layer is BiFeO 3 、ErFeO 3 ScFeO 3 、HoFeO 3 、YFeO 3 ,SrTiO 3 ,BiTiO 3 ,KTaO 3 One or more of the above; the oxide layer is SrTiO 3 ,LaAlO 3 ,EuO,AlO x , one or more of topological materials, heavy metals, semi-metals, etc.; the gate dielectric layer is BiFeO3 ,Pb(Zr 0.2 Ti 0.8 ) 3 (PZT), TaO x , HfO x , GdO x , HfZrO, etc.
[0048] So far, the embodiments of the present disclosure have been described in detail in conjunction with the accompanying drawings. It should be noted that the implementation methods not shown or described in the drawings or the main body of the specification are all forms known to ordinary technicians in the relevant technical field and are not described in detail. In addition, the above definitions of each element and method are not limited to the various specific structures, shapes or methods mentioned in the embodiments, and ordinary technicians in this field can simply change or replace them. For example: (1) The stacking order of the membrane stack; (2) cascading of multiple devices and expansion of functions; (3) Simple changes in the shape, size, and relative position of the device; (4) Material replacement.
[0049] According to the above description, those skilled in the art should have a clear understanding of the spin logic device, spin logic memory device and preparation method disclosed in the present invention.
[0050] In summary, the present disclosure provides a spin logic device, a spin logic memory device and a preparation method, which have the advantages of multi-function, reconfigurability, high energy efficiency, simple structure and easy preparation. That is, a hybrid device that integrates topological spin electronics logic and storage functions, based on structures such as programmable logic arrays or programmable logic gate arrays, realizes various combinational logic and sequential logic functions through programming configuration; at the same time, the integrated memory module can be used for data storage, program storage, etc. The logic function and the storage function can be independently programmed and configured, and can be reconstructed and modified according to requirements. It can be widely used in embedded systems, digital signal processing, control systems, communication equipment, etc. The logic memory device proposed in the present disclosure has both logical flexibility and storage function, which helps to reduce system complexity and shorten the development cycle. It is a very practical hybrid electronic device.
[0051] It should be noted that, in this document, unless otherwise specified, “a” element is not limited to a single element, but may include one or more elements.
[0052] In addition, in this document, unless otherwise specified, ordinal numbers such as "first" and "second" are only used to distinguish multiple components with the same name, and do not indicate that there is a hierarchy, level, execution order, or process order between them. A "first" component and a "second" component may appear together in the same component, or appear in different components. The presence of a component with a larger ordinal number does not necessarily indicate the presence of another component with a smaller ordinal number.
[0053] In this document, unless otherwise specified, the so-called feature A "or" or "and / or" (and / or) feature B means that A exists alone, B exists alone, or A and B exist at the same time; the so-called feature A "and" (and) or "and" (and) or "and" (and) feature B means that A and B exist at the same time; the so-called "include", "comprise", "have" and "contain" mean including but not limited to these.
[0054] In addition, in this document, the terms "upper", "lower", "left", "right", "front", "back", or "between" are only used to describe the relative positions between multiple elements, and can be extended to include translation, rotation, or mirroring. In addition, in this document, unless otherwise specified, "an element is on another element" or similar descriptions do not necessarily mean that the element contacts the other element.
[0055] In addition, unless the steps are specifically described or must occur in sequence, the order of the above steps is not limited to the above list, and can be changed or rearranged according to the required design. And the above embodiments can be mixed and matched with each other or with other embodiments based on design and reliability considerations, that is, the technical features in different embodiments can be freely combined to form more embodiments.
[0056] The specific embodiments described above further illustrate the purpose, technical solutions and beneficial effects of the present disclosure. It should be understood that the above description is only a specific embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure should be included in the protection scope of the present disclosure.
Claims
1. A spin logic device, comprising: Oxide layer; A multiferroic layer, located on the oxide layer and forming a two-dimensional electron gas as a transmission layer between the multiferroic layer and the oxide layer, transmitting a spin current in the form of a spin wave; A spin-orbit coupling layer, comprising a first spin-orbit coupling unit and a second spin-orbit coupling unit, wherein the first spin-orbit coupling unit and the second spin-orbit coupling unit are not connected to each other and are symmetrically distributed on the multiferroic layer; A top electrode, comprising a first top electrode connected to the first spin-orbit coupling unit and a second top electrode connected to the second spin-orbit coupling unit; as well as The bottom electrode comprises a first bottom electrode and a second bottom electrode respectively connected to two sides of the oxide layer.
2. According to the spin logic device according to claim 1, the first spin-orbit coupling unit and the second spin-orbit coupling unit are used to respectively adjust the polarization direction of the multiferroic layer region therebelow and respectively inject spin currents into the multiferroic layer.
3. According to the spin logic device of claim 1, voltage is applied between the first top electrode and the first bottom electrode, and between the second top electrode and the second bottom electrode, respectively, so as to flip the local multiferroic layer between the first top electrode and the first bottom electrode, and the local multiferroic layer between the second top electrode and the second bottom electrode to different ferroelectric polarization configurations, thereby realizing different logic gates.
4. The spin logic device according to claim 3 realizes OR logic or XNOR logic when the ferroelectric polarization directions of the local multiferroic layer between the first top electrode and the first bottom electrode and the local multiferroic layer between the second top electrode and the second bottom electrode are the same.
5. The spin logic device according to claim 3 implements XOR logic when the ferroelectric polarization directions of the local multiferroic layer between the first top electrode and the first bottom electrode and the local multiferroic layer between the second top electrode and the second bottom electrode are opposite.
6. A spin logic memory device, comprising: The spin logic device according to any one of claims 1 to 5; as well as The gate dielectric layer is adjacent to the oxide layer and is located between the areas of the vertical projection of the unconnected gap between the first spin-orbit coupling unit and the second spin-orbit coupling unit on the plane.
7. The spin logic memory device according to claim 6, wherein the two-dimensional electron gas conductive channel can be non-volatilely controlled by applying a gate voltage to the gate dielectric layer; If a positive gate voltage is applied to the gate dielectric layer, the two-dimensional electron gas under the gate dielectric layer will be depleted and the conductive channel will be turned off; the heterojunctions on the left and right sides of the gate are independently regulated and read to realize the function of a binary storage unit; conversely, if a negative gate voltage is applied to the gate dielectric layer, the two-dimensional electron gas will be enhanced and the conductive channel will be turned on, which can realize the function of a spin logic device.
8. The spin logic memory device according to claim 1 or 6, The spin-orbit coupling layer is prepared from a material selected from topological materials, heavy metals, and semimetals; The preparation material of the multi-iron layer is selected from BiFeO3, ErFeO3, ScFeO3, HoFeO3, YFeO3, SrTiO3, BiTiO3, KTaO3; The material for preparing the oxide layer is selected from SrTiO3, LaAlO3, EuO, AlO x , topological materials, heavy metals, and semimetals; Gate dielectric materials BiFeO3, Pb(Zr 0.2 Ti 0.8 )O3、TaO x , HfO x , GdO x 、HfZrO.
9. A method for preparing a spin logic device according to any one of claims 1 to 5 and 8, comprising: S1: growing an oxide layer, a multiferroic layer, and a SOC layer in sequence on the wafer with designed interconnections; S2: Separate SOC layers are processed by photolithography and ion beam etching to obtain a spin-orbit coupling layer; S3: After etching, the wafer is in-situ grown with insulating dielectric to provide insulation protection for the device; S4: performing a second photolithography and ion beam etching, with the etching being stopped on the oxide layer; S5: After etching, the wafer is in-situ grown with insulating dielectric to provide insulation protection for the device; S5: performing a third photolithography and ion beam etching to open a bottom electrode through hole; S6: preparing a bottom electrode on the etched wafer; S7: performing the fourth photolithography and ion beam etching to open the top electrode through hole; S8: preparing a top electrode on the etched wafer.
10. A method for preparing a spin logic memory device according to any one of claims 6 to 8, comprising: S10: growing a gate dielectric layer on the wafer with designed interconnections, and processing a gate pattern through photolithography and ion beam etching. After etching, an insulating dielectric is grown in situ on the wafer to insulate and protect the device; S20: treating the wafer after the insulating medium is grown by chemical mechanical polishing; S30: sequentially growing an oxide layer, a multiferroic layer, and a SOC layer on the polished wafer; S40: performing a second photolithography and ion beam etching to etch out the SOC layers on both sides; S50: After etching, an insulating dielectric is grown in situ on the wafer to insulate the device, and a third photolithography and ion beam etching are performed, with the etching being terminated on the oxide layer; S60: In-situ growth of insulating dielectric for device insulation protection; S70: fourth photolithography and ion beam etching to open a bottom electrode through hole and prepare a bottom electrode on the etched wafer; S80: performing the fifth photolithography and ion beam etching to open the top electrode through hole and prepare the top electrode on the etched wafer; S90: Perform the sixth photolithography and ion beam etching to open the gate electrode through hole and prepare the gate electrode on the etched wafer.