Digital end driving system and method of micro light emitting diode display wafer panel

Abstract

The invention relates to a digital end driving system (1) and a method of a micro light emitting diode display wafer panel. The digital end driving system (1) comprises an external chip (11), a register array (12) and a display area (13). The external chip (11) is used for providing configuration information and frame pixel data; the register array (12) comprises a plurality of register modules (121), and the configuration message comprises a plurality of module configuration messages which are stored by the corresponding register modules (121); the display control register (122) is a subset of the register array (12) and is used for storing all module configuration messages; the display area (13) is used for receiving the total module configuration information and the frame pixel data to generate a PWM modulation signal and controlling the display brightness and the gray scale according to the PWM modulation signal. The digital end driving system (1) adopts a separate storage configuration mode and is configured when scanning of each frame is started, and it is ensured that the picture of each frame is displayed completely.

Description

Digital end driving system and method for micro-LED display chip panel Technical Field

[0001] The present invention relates to a digital end driving system and method, and in particular to a digital end driving system and method for a micro-LED display chip panel. Background Art

[0002] Micro-LED (micro-LED) display technology uses self-luminous micron-sized light-emitting diodes (LEDs) as pixel units, assembled onto a driver panel to form a high-density LED array. Due to their small chip size, high sensitivity, and self-luminescence, micro-LEDs offer significant advantages over liquid crystal displays (LCDs) and organic light-emitting diodes (OLEDs) in terms of brightness, resolution, contrast, energy consumption, lifespan, response speed, and thermal stability.

[0003] The technical principles and circuit structures for digital-side drive of displays in prior art primarily fall into two categories. The first type involves digital drive circuits in the LCD and OLED display fields. Due to the different display principles employed by these displays, a detailed comparison of the technical details regarding the drive principles will not be discussed here. The second type involves the digital drive principles of micro LED display technology. Please refer to Figure 1, which is a block diagram of a digital-side drive system P1 based on prior art. As shown in Figure 1, the prior art digital-side drive system P1 comprises three components: an external chip P11, a register array P12, and a display area P13. Figure 1 shows that the existing micro LED drive method utilizes real-time configuration modification and data loading, with the display area P13 receiving real-time configuration information directly from the register array P12. Please refer to Figure 2, which is a schematic diagram of a subframe timing cycle based on prior art. As shown in Figure 2, the digital-side drive system is driven based on the Sync signal (S signal) and Configuration signal (C signal) within the subframe timing cycle. During the frame scanning process of the digital end driving system according to the sub-frame timing cycle, the position of the S signal and the C signal are set at the middle position of the sub-frame timing cycle, and the specific position is determined by the external chip P11 (i.e., the host computer) and changes in real time.

[0004] In actual use, the aforementioned prior art drive methods require real-time configuration and data loading, which can lead to instability in the display drive control process and image tearing, affecting the viewing experience. Therefore, addressing the display instability and image tearing caused by current digital-side drive methods for micro-LED display chip panels is a key research topic and direction.

[0005] Summary of the Invention

[0006] In view of this, the purpose of the present invention is to provide a digital end driving system and method for a micro-LED display chip panel, which can solve the problems of the previous technology and solve the technical problem of unstable driving caused by real-time configuration modification of the host computer. The image display is more stable, the picture display is guaranteed, and the technical problems of display instability and image tearing are effectively solved.

[0007] To achieve the above-mentioned object, the present invention discloses a digital end driving system for a micro-LED display chip panel, which is characterized by comprising:

[0008] An external chip, used to provide a configuration message and a frame of pixel data;

[0009] a register array coupled to the external chip, the register array comprising a plurality of register modules, the configuration information comprising a plurality of module configuration information, each register module being used to store corresponding module configuration information; and

[0010] a display control register electrically connected to the register array, which is a subset of the register array and is used to store a total module configuration message including the module configuration messages; and

[0011] a display area coupled to the external chip and the display control register, for receiving the master module configuration information and the frame pixel data to generate a PWM modulation signal, and controlling display brightness and grayscale according to the PWM modulation signal;

[0012] Among them, the digital end driving system of the micro-light-emitting diode display chip panel displays brightness and grayscale according to a sub-frame timing cycle. The sub-frame timing cycle includes at least one C signal and at least one S signal. Under the C signal, the display control register stores the total module configuration information in the register array, and places the C signal in the sub-frame timing cycle at the initial position in the sub-frame timing cycle, and connects the S signal after the C signal; under the S signal, the display area receives the total module configuration information and the frame pixel data to generate the PWM modulation signal, and controls the display brightness and grayscale according to the PWM modulation signal.

[0013] The display area is used to receive the total module configuration information to generate an SFx signal, combine the frame pixel data and the SFx signal to generate an SFMX signal, and superimpose the SFMX signal to generate the PWM modulation signal.

[0014] The display area further includes:

[0015] a scan driving circuit coupled to the display control register and configured to receive the master module configuration information stored in the display control register to generate the SFx signal;

[0016] a column data transmission control circuit coupled to the external chip and the display control register for receiving the frame pixel data; and

[0017] A pixel array includes a plurality of pixels, each of which includes:

[0018] a pixel driving circuit comprising a memory, a modulator, and a control circuit; the memory is coupled to the column data transmission control circuit and is configured to receive and store the frame pixel data; the modulator is coupled to the memory and the scan driving circuit and is configured to receive the SFx signal and the frame pixel data, combine the SFx signal and the frame pixel data to generate the SFMX signal, and superimpose the SFMX signal to generate the PWM modulation signal; the control circuit is coupled to the modulator; and

[0019] a light-emitting diode, disposed in the control circuit, electrically connected to the control circuit, and having a light-emitting function;

[0020] The control circuit receives the PWM modulation signal and controls the brightness and grayscale of the light emitting diode according to the PWM modulation signal.

[0021] The modulator is used to place the S signal at an initial position in the sub-frame timing cycle and at a continuous position after the C signal.

[0022] The data transmission control circuit further includes:

[0023] a frame buffer coupled to the external chip for receiving and storing the frame pixel data; and

[0024] A column data transmission control circuit body is coupled to the frame buffer and electrically connected to the display control register for receiving and transmitting the frame pixel data.

[0025] Also disclosed is a digital end driving method for a micro-LED display chip panel, which is characterized by comprising the following steps:

[0026] An external chip provides a configuration message and a frame of pixel data;

[0027] a register array comprising a plurality of register modules, wherein the configuration information comprises a plurality of module configuration information, and each register module stores corresponding module configuration information;

[0028] Under a C signal in a sub-frame timing period, the display control register stores a total module configuration information including the module configuration information in the register array;

[0029] Under the C signal in the sub-frame timing period, placing the C signal in the sub-frame timing period at an initial position in the sub-frame timing period, and connecting the S signal after the C signal;

[0030] Under an S signal in a sub-frame timing period, a display area receives the overall module configuration information and the frame pixel data to generate the PWM modulation signal; and

[0031] The display brightness and grayscale of the display area are controlled according to the PWM modulation signal.

[0032] The step of receiving the master module configuration information and the frame pixel data in the display area to generate the PWM modulation signal under the S signal in the sub-frame timing period further includes the following sub-steps:

[0033] A scan driving circuit in the display area receives the master module configuration information to generate an SFx signal;

[0034] A frame buffer in the display area transmits the frame pixel data;

[0035] A column of data transmission control circuit bodies in the display area transmits the frame of pixel data from the frame buffer;

[0036] A memory in the display area transmits and stores the frame pixel data from the row data transmission control circuit body; and

[0037] A modulator in the display area receives the SFx signal and the frame pixel data from the memory to generate the PWM modulation signal.

[0038] The step of the modulator in the display area receiving the SFx signal and the frame pixel data to generate the PWM modulation signal further includes the following sub-steps:

[0039] The modulator receives and combines the SFx signal and the frame pixel data to generate a SFMX signal;

[0040] The modulator superimposes the SFMX signal to generate the PWM modulation signal; and

[0041] Under the S signal, the modulator places the S signal at an initial position in the sub-frame timing period.

[0042] The step of placing the C signal in the sub-frame timing period at an initial position in the sub-frame timing period and connecting the S signal to the C signal further includes the following sub-steps:

[0043] The display control register places the C signal at an initial position in the sub-frame timing cycle; and

[0044] A modulator in the display area places the S signal at an initial position in the sub-frame timing period and at a continuous position after the C signal.

[0045] The step of controlling the display brightness and grayscale of the display area according to the PWM modulation signal further includes the following sub-steps:

[0046] A control circuit in the display area receives the PWM modulation signal; and

[0047] The control circuit controls the brightness and grayscale of a light emitting diode in the display area according to the PWM modulation signal.

[0048] Therefore, compared with the digital end driving system mentioned in the prior art, the register array in the digital end driving system of the present invention further includes a display control register as a subset. The display control register places the C signal at the initial position of the sub-frame period and connects the S signal after the C signal. Because the display control register stores the total module configuration information for the display area, the sub-frame period is automatically adjusted to the order of C, S, SFX..., and the configuration information can be read directly from the display control register, so that the display area can operate stably. On the other hand, because the prior art does not have a display control register, it does not have the function of automatically adjusting the sub-frame period. It is necessary to read the configuration information from the external chip when the C signal appears, and to read the frame pixel data from the external chip when the S signal appears, which causes the display area to operate unsmoothly, resulting in the problem of image tearing. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] FIG. 1 is a block diagram of a digital end driving system according to the prior art.

[0050] FIG. 2 is a schematic diagram of a subframe timing cycle according to the prior art.

[0051] FIG3 is a block diagram of a digital-side driving system for a micro-LED display chip panel according to an embodiment of the present invention.

[0052] FIG. 4 is a block diagram of a digital-side driving system of a further micro-LED display wafer panel according to FIG. 3 .

[0053] FIG. 5 is a structural diagram of a digital end driving system of the micro-LED display wafer panel according to FIG. 4 .

[0054] FIG6 is a diagram of a pixel driving circuit according to FIG4 .

[0055] FIG. 7 is a flow chart of a digital-side driving method for a micro-LED display chip panel according to a specific embodiment of the present invention.

[0056] FIG. 8 is a further flow chart of the digital end driving method of the micro-LED display wafer panel according to FIG. 7 .

[0057] FIG. 9 is a flow chart of a digital end driving method of the micro-LED display chip panel according to FIG. 8 under an S signal.

[0058] FIG. 10 is a further flow chart of the digital end driving method of the micro-LED display wafer panel according to FIG. 7 .

[0059] FIG. 11 is a further flow chart of a digital-side driving method for the micro-LED display wafer panel according to FIG. 7 .

[0060] FIG. 12 is a schematic diagram of a sub-frame timing cycle of a digital-end driving method for a micro-LED display chip panel according to a specific embodiment of the present invention.

[0061] FIG. 13 is a schematic diagram of SFx signals when Gray Value=0xC5 according to a digital-side driving method of a micro-LED display chip panel according to an embodiment of the present invention.

[0062] FIG. 14 is a PWM iteration diagram according to FIG. 13 . DETAILED DESCRIPTION

[0063] To make the advantages, spirit, and features of the present invention more easily and clearly understood, the following detailed description and discussion will be provided using examples and with reference to the accompanying drawings. It should be noted that these examples are merely representative of the present invention. However, the present invention may be implemented in many different forms and is not limited to the examples described in this specification. Rather, these examples are provided to provide a more thorough and comprehensive disclosure of the present invention.

[0064] The terms used in the various embodiments disclosed in the present invention are only used for the purpose of describing specific embodiments and are not used to limit the various embodiments disclosed in the present invention. As used herein, the singular form also includes the plural form, unless the context clearly indicates otherwise. Unless otherwise specified, all terms used in this specification (including technical terms and scientific terms) have the same meanings as those commonly understood by ordinary technicians in the field of the various embodiments disclosed in the present invention. The above terms (such as those defined in generally used dictionaries) will be interpreted as having the same meaning as the contextual meaning in the same technical field, and will not be interpreted as having idealized meanings or overly formal meanings, unless clearly defined in the various embodiments disclosed in the present invention.

[0065] Please refer to Figure 3, which is a block diagram of a digital-side driver system 1 for a micro-LED display chip panel according to a specific embodiment of the present invention. As shown in Figure 3, the digital-side driver system 1 for a micro-LED display chip panel of the present invention includes an external chip 11, a register array 12, and a display area 13. The external chip 11 is used to provide configuration information and frame pixel data. Frame pixel data is the source data of an image. Configuration information refers to control parameters used to organize the image source data into a continuous video stream, such as frame data, brightness / grayscale data, etc. The register array 12 is coupled to the external chip 11. The register array 12 includes multiple register modules 121. The register array 12 is structured as a register array 12 composed of multiple register modules 121 that store configuration information for different modules. The primary function of the register array 12 is to store all configuration information for the display device, including the configuration information for the display area 13. The configuration information includes multiple module configuration information, and each register module 121 is used to store the corresponding module configuration information. The display control register 122 is electrically connected to the register array 12, which is a subset of the register array 12 and is used to store the total module configuration information including all module configuration information. In other words, the display control register 122 is a register in the register array 12 specifically used to store the configuration information in the display area 13. The configuration information for the display area 13 stored in the display control register 122 includes row and column display control configuration information, that is, all configuration information that controls the display state of the image. The configuration information includes but is not limited to the scanning time t and the format of the data, etc. The display area 13 is coupled to the external chip 11 and the display control register 122 to receive the total module configuration information and frame pixel data to generate a PWM modulation signal, and control the display brightness and grayscale according to the PWM modulation signal. Among them, the digital end driving system 1 of the micro-light-emitting diode display chip panel displays brightness and grayscale according to the sub-frame timing period. The sub-frame timing period includes at least one C signal and at least one S signal. Under the C signal, the display control register 122 stores the master module configuration information in the register array 12 and places the C signal at the initial position within the sub-frame timing cycle. The S signal is then connected to the C signal. Under the S signal, the display area 13 receives the master module configuration information and frame pixel data to generate a PWM modulation signal, and controls the display brightness and grayscale according to the PWM modulation signal.

[0066] It should be noted that the display control registers 122 are a subset of the register array 12. The multiple register modules 121 in the register array 12 store different configuration information. Of course, each register module 121 may also have its own subset. The function of each subset corresponds to the module position displayed in the display area where it resides. The number of display control registers 122 can correspond to the number of register modules 121, or one display control register 122 can be assigned to multiple register modules 121, but this is not a limitation.

[0067] Please refer to Figures 4, 5, and 6. Figure 4 is a block diagram of a digital-side driving system 1 for a micro-LED display chip panel further according to Figure 3. Figure 5 is a schematic structural diagram of the digital-side driving system 1 for a micro-LED display chip panel according to Figure 4. Figure 6 is a pixel driving circuit diagram according to Figure 4. As shown in Figures 4, 5, and 6, the column data transmission control circuit 132 further includes a frame buffer 1321 and a column data transmission control circuit body 1322. The frame buffer 1321 is coupled to the external chip 11 to receive and store frame pixel data. The column data transmission control circuit body 1322 is coupled to the frame buffer 1321 and electrically connected to the display control register 122 to receive and transmit frame pixel data. The display area 13 further includes a scan driver circuit 131, a column data transmission control circuit 132, and a pixel array 133. The scan driver circuit 131 is coupled to the display control register 122 to receive the overall module configuration information stored in the display control register 122 to generate an SFx signal (or SFX signal). The column data transmission control circuit 132 is coupled to the external chip 11 and the display control register 122 to receive frame pixel data. The pixel array 133 is composed of individual pixels 1331. Each pixel 1331 includes a pixel driver circuit 1332 and a light-emitting diode 1336. The pixel driver circuit 1332 includes a memory 1333, a modulator 1334, and a control circuit 1335. The memory 1333 is coupled to the column data transmission control circuit 132 to receive and store the frame pixel data. The modulator 1334 is coupled to the memory 1333 and the scan driver circuit 131 to receive the SFx signal and the frame pixel data, combine the SFx signal and the frame pixel data to generate an SFMX signal, and superimpose the SFMX signal to generate a PWM modulated signal. The control circuit 1335 is coupled to the modulator 1334. The light-emitting diode 1336 is disposed within and electrically connected to the control circuit 1335 and provides light emission. The control circuit 1335 receives the PWM modulation signal and controls the brightness and grayscale of the light-emitting diode 1336 according to the PWM modulation signal, thereby controlling the PMOS gate in the control circuit 1335. The modulator 1334 is used to place the S signal at the initial position in the subframe timing cycle and at a continuous position after the C signal.

[0068] Specifically, the scan driver circuit 131 is the row control element. Therefore, the configuration information in the display control register 3 represents the row and column control elements, and is represented to the scan driver circuit 131 and the column data transfer control circuit body 1322. Since the column data transfer control circuit body 1322 assumes the function of inputting source data, it is therefore named column data transfer control circuit body 1322.

[0069] Please refer to Figure 7, which is a flow chart of a digital-side driving method for a micro-LED display chip panel according to one embodiment of the present invention. As shown in Figure 7, the digital-side driving method for a micro-LED display chip panel according to the present invention includes the following steps: Step S1: an external chip provides configuration information and frame pixel data; Step S2: a register array includes multiple register modules, the configuration information includes multiple module configuration information, and each register module stores corresponding module configuration information; Step S3: under the C signal in a sub-frame timing cycle, the display control register stores the total module configuration information containing these module configuration information in the register array; Step S4: under the C signal in the sub-frame timing cycle, the C signal in the sub-frame timing cycle is placed at the initial position in the sub-frame timing cycle, and the S signal is connected after the C signal; Step S5: under the S signal in the sub-frame timing cycle, the display area receives the total module configuration information and frame pixel data to generate a PWM modulation signal; and Step S6: the display area controls the display brightness and grayscale of the display area according to the PWM modulation signal.

[0070] Please refer to Figure 8, which is a further flow chart of the digital-side driving method for the micro-LED display chip panel according to Figure 7. As shown in Figure 8, step S5 (under the S signal) further includes the following sub-steps: Sub-step S51: the scan driver circuit receives the master module configuration information to generate the SFx signal; Sub-step S52: the frame buffer transmits the frame pixel data; Sub-step S53: the column data transmission control circuit body transmits the frame pixel data from the frame buffer; Sub-step S54: the memory transmits and stores the frame pixel data from the column data transmission control circuit body; and Sub-step S55: the modulator receives the SFx signal and the frame pixel data from the memory to generate a PWM modulation signal.

[0071] Please refer to Figure 9, which is a flowchart of the digital-side driving method for the micro-LED display chip panel according to Figure 8 under the S signal. As shown in Figure 9, sub-step S55 further includes the following sub-steps: Sub-step S551: The modulator receives and combines the SFx signal ("X" ranges from 0 to "x", where "x" determines the number of bits based on the grayscale value of the pixel, e.g., 8 bits, x = 7) and the frame pixel data to generate the SFMX signal; Sub-step S552: The modulator superimposes the SFMX signal to generate a PWM modulation signal; and Sub-step S553: ​​Under the S signal, the modulator places the S signal at the initial position in the sub-frame timing period.

[0072] Please refer to Figure 10, which is a further flow chart of the digital-side driving method for the micro-LED display chip panel according to Figure 7. As shown in Figure 10, step S4 further includes the following sub-steps: Sub-step S41: the display control register places the C signal at the initial position in the sub-frame timing cycle; and Sub-step S42: the modulator in the display area places the S signal at the initial position in the sub-frame timing cycle, and at a subsequent position after the C signal.

[0073] Please refer to Figure 11, which is a further flowchart of the digital-side driving method for the micro-LED display chip panel according to Figure 7. As shown in Figure 11, step S6 further includes the following sub-steps: Sub-step S61: the control circuit in the display area receives a PWM modulation signal; and Sub-step S62: the control circuit controls the brightness and grayscale of the LEDs in the display area based on the PWM modulation signal.

[0074] Please refer to Figure 12, which illustrates a subframe timing cycle diagram of a digital-side driving method for a micro-LED display chip panel according to one embodiment of the present invention. In Figure 12, the S signal is the sync signal, which controls the transmission of frame source data. The C signal is the configuration signal, which controls the transmission of configuration information. Within the subframe timing cycle, S and C represent instructions for controlling data transmission, respectively. The remaining positions represent the time occupied by the image display process (i.e., the display process of the frame pixel data). The subframe timing cycle in Figure 12 represents the panel-side driving timing. First, "C" represents the configuration, which reads the relevant driving configuration from the register array. This configuration controls the scanning time, data format, and other aspects. The frame pixel data in the frame buffer is then loaded into the pixel memory. Combined with the scanning signal (SFx), a PWM output is generated to control the on and off time of the micro-LEDs. This drives the micro-LEDs to achieve the set grayscale and brightness.

[0075] Please refer to Figures 13 and 14. Figure 13 illustrates the SFx signal when Gray Value = 0xC5 for a digital-side driving method for a micro-LED display chip panel according to one embodiment of the present invention. Figure 14 illustrates the PWM iteration diagram based on Figure 13. The timing of the SFx-related signals is as follows, taking 8-bit grayscale driving as an example, as shown in Figure 13. The driving method of the present invention ensures frame integrity, and full-screen driving results in better display consistency and higher driving efficiency. As shown in Figure 14, for example, when Gray Value = 0xC5, only bits 7, 6, 2, and 0 are high, indicating that SF7, SF6, SF2, and SF0 appear in the PWM, while the others do not. Furthermore, because the PMOS transistor is being controlled, the signal needs to be inverted. The PWM waveform is shown in Figure 14. The SFMx signal in the figure is an internal signal in the modulator, carrying the grayscale information stored in the register and undergoing a signal inversion operation. PWM is the modulator output signal, directly controlling the PMOS transistor to control the on / off of the micro-LED.

[0076] Compared to the prior art, the drive system of the present invention includes a display control register that places the C signal at the initial position of the sub-frame period and connects the S signal after the C signal. Moreover, because the display control register stores the configuration information for the display area, the sub-frame period is automatically adjusted to C→S→SFX.... This allows the drive system of the present invention to directly read the configuration information from the display control register, allowing the display area 4 to operate stably. In contrast, because the prior art did not have a display control register, it did not have the function of automatically adjusting the sub-frame period. It was necessary to read the configuration information from the external chip when the C signal appeared, and to read the frame pixel data from the external chip when the S signal appeared, which resulted in the display area operating unsmoothly and causing the problem of image tearing.

[0077] In summary, the digital end driving system and method of the micro-LED display chip panel of the present invention are characterized in that the configuration information transmitted by the main host computer (external chip and register array) is separated from the configuration information actually used (display control register and storage), and the host computer configuration information is only loaded into the actual use configuration at the start position of the frame scan (C and S), solving the technical problem of unstable driving caused by the host computer modifying the configuration in real time. In other words, the driving method of the present invention adopts a method of storing the configuration separately, and performs configuration at the beginning of each frame scan. Preloading data and pre-configuration are performed at the initial position of each frame display, so that there is no need to load data and load configuration information in real time during the frame display process, making the image display more stable. It is not only convenient for the host computer to configure the registers, but also does not affect the display of the panel. Therefore, the overall driving system can be efficiently adjusted and displayed, and the complete picture display of each frame is guaranteed. It effectively solves the technical problems of unstable display and image tearing.

[0078] The above detailed description of the specific embodiments is intended to more clearly illustrate the features and spirit of the present invention, and is not intended to limit the scope of the present invention by the specific embodiments disclosed above. On the contrary, its purpose is to cover various modifications and equivalent arrangements within the scope of the patent application of the present invention.

Claims

1. A digital end driving system for a micro-LED display chip panel, characterized in that Include: An external chip, used to provide a configuration message and a frame of pixel data; a register array coupled to the external chip, the register array comprising a plurality of register modules, the configuration information comprising a plurality of module configuration information, each register module being used to store corresponding module configuration information; as well as a display control register electrically connected to the register array, which is a subset of the register array and is used to store a total module configuration information including the module configuration information; as well as a display area coupled to the external chip and the display control register, for receiving the master module configuration information and the frame pixel data to generate a PWM modulation signal, and controlling display brightness and grayscale according to the PWM modulation signal; Among them, the digital end driving system of the micro-light-emitting diode display chip panel displays brightness and grayscale according to a sub-frame timing cycle. The sub-frame timing cycle includes at least one C signal and at least one S signal. Under the C signal, the display control register stores the total module configuration information in the register array, and places the C signal in the sub-frame timing cycle at the initial position in the sub-frame timing cycle, and connects the S signal after the C signal; under the S signal, the display area receives the total module configuration information and the frame pixel data to generate the PWM modulation signal, and controls the display brightness and grayscale according to the PWM modulation signal.

2. The digital end driving system of the micro-LED display chip panel according to claim 1, wherein: The display area is used to receive the overall module configuration information to generate an SFx signal, combine the frame pixel data and the SFx signal to generate an SFMX signal, and superimpose the SFMX signal to generate the PWM modulation signal.

3. The digital end driving system of the micro-LED display chip panel according to claim 2, wherein: The display area also includes: a scan driving circuit coupled to the display control register and configured to receive the master module configuration information stored in the display control register to generate the SFx signal; a column data transmission control circuit coupled to the external chip and the display control register for receiving the frame pixel data; and A pixel array includes a plurality of pixels, each of which includes: a pixel driving circuit comprising a memory, a modulator and a control circuit, wherein the memory is coupled to the row data transmission control circuit and is used to receive and store the frame pixel data; The modulator is coupled to the storage and the scan driving circuit, and is used to receive the SFx signal and the frame pixel data, combine the SFx signal and the frame pixel data to generate the SFMX signal, and superimpose the SFMX signal to generate the PWM modulation signal; The control circuit is coupled to the modulator; as well as a light-emitting diode, disposed in the control circuit, electrically connected to the control circuit, and having a light-emitting function; The control circuit receives the PWM modulation signal and controls the brightness and grayscale of the light emitting diode according to the PWM modulation signal.

4. The digital end driving system of the micro-LED display chip panel according to claim 3, characterized in that: The modulator is used for placing the S signal at an initial position in the sub-frame timing period and at a continuous position after the C signal.

5. The digital end driving system of the micro-LED display chip panel according to claim 3, wherein: The column data transmission control circuit further includes: a frame buffer coupled to the external chip for receiving and storing the frame pixel data; and A column data transmission control circuit body is coupled to the frame buffer and electrically connected to the display control register for receiving and transmitting the frame pixel data.

6. A digital end driving method for a micro-LED display chip panel, characterized in that The following steps are involved: An external chip provides a configuration message and a frame of pixel data; a register array comprising a plurality of register modules, wherein the configuration information comprises a plurality of module configuration information, and each register module stores corresponding module configuration information; Under a C signal in a sub-frame timing period, the display control register stores a total module configuration information including the module configuration information in the register array; Under the C signal in the sub-frame timing period, placing the C signal in the sub-frame timing period at an initial position in the sub-frame timing period, and connecting the S signal after the C signal; Under an S signal in a sub-frame timing period, a display area receives the overall module configuration information and the frame pixel data to generate the PWM modulation signal; and The display brightness and grayscale of the display area are controlled according to the PWM modulation signal.

7. The digital end driving method of the micro-LED display chip panel according to claim 6, wherein: The step of the display area receiving the master module configuration information and the frame pixel data to generate the PWM modulation signal under the S signal in the sub-frame timing period further includes the following sub-steps: A scan driving circuit in the display area receives the master module configuration information to generate an SFx signal; A frame buffer in the display area transmits the frame pixel data; A column of data transmission control circuit bodies in the display area transmits the frame of pixel data from the frame buffer; A memory in the display area transmits and stores the frame pixel data from the row data transmission control circuit body; as well as A modulator in the display area receives the SFx signal and the frame pixel data from the memory to generate the PWM modulation signal.

8. The digital end driving method of the micro-LED display chip panel according to claim 7, wherein: The step of the modulator in the display area receiving the SFx signal and the frame pixel data to generate the PWM modulation signal further includes the following sub-steps: The modulator receives and combines the SFx signal and the frame pixel data to generate a SFMX signal; The modulator superimposes the SFMX signal to generate the PWM modulation signal; as well as Under the S signal, the modulator places the S signal at an initial position in the sub-frame timing period.

9. The digital end driving method of a micro-LED display chip panel according to claim 6, wherein: Under the C signal in the sub-frame timing period, placing the C signal in the sub-frame timing period at an initial position in the sub-frame timing period and connecting the S signal to the C signal further includes the following sub-steps: The display control register places the C signal at an initial position in the sub-frame timing cycle; and A modulator in the display area places the S signal at an initial position in the sub-frame timing period and at a continuous position after the C signal.

10. The digital end driving method of a micro-LED display chip panel according to claim 6, wherein: The step of controlling the display brightness and grayscale of the display area according to the PWM modulation signal further includes the following sub-steps: A control circuit in the display area receives the PWM modulation signal; and The control circuit controls the brightness and grayscale of a light emitting diode in the display area according to the PWM modulation signal.

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